Integrated MEMS inertial device and manufacturing method thereof

Abstract

The invention relates to a manufacturing method of an integrated MEMS inertial device and the MEMS inertial device manufactured based on the manufacturing method, and the manufacturing method comprises the steps: bonding a blank wafer on an ASIC wafer, thinning the blank wafer, carrying out photoetching alignment based on an alignment mark on the ASIC wafer, and then etching the blank wafer into a device layer wafer to obtain a first bonding body; bonding a cap wafer on the first bonding body, and thinning the ASIC wafer and the cap wafer to obtain a second bonding body; and scribing the second bonding body to obtain a single MEMS inertial device, and performing signal leading-out operation on the MEMS inertial device. According to the manufacturing method, the blank wafer is bonded on the ASIC wafer firstly, then the blank wafer is manufactured into the device layer wafer, pattern deviation caused by alignment and bonding operation of the two wafers can be avoided, the alignment mark is manufactured on the ASIC wafer in advance, the alignment precision between the device layer wafer and the ASIC wafer can be guaranteed based on the precision of photoetching alignment, and therefore the alignment precision of the device layer wafer and the ASIC wafer is improved. And the product quality and performance of the MEMS inertial device are ensured.

Description

TECHNICAL FIELD

[0001] The application relates to a manufacturing method of an integrated MEMS inertial device and the integrated MEMS inertial device prepared based on the manufacturing method. BACKGROUND

[0002] The MEMS inertial sensor comprises an accelerometer, a gyroscope or a combination thereof, wherein the accelerometer is used for measuring acceleration of an object, the gyroscope is used for measuring angular velocity of the object, and comprehensive measurement of the acceleration and the angular velocity can be used for describing a motion state of the object.

[0003] The existing MEMS inertial sensor is packaged in a tube shell through wire bonding by combining a discrete MEMS sensing chip and an ASIC signal processing chip. The existing MEMS inertial sensing chip is generally sealed in a micro cavity by a multilayer wafer bonding mode (specifically, a substrate wafer, a device wafer and a cap wafer are bonded in multiple layers), and due to the pattern alignment deviation between wafers caused by the bonding process, the support anchor point position of the movable device structure is deviated, thereby generating unnecessary internal stress and affecting the performance stability of the device.

[0004] Then, the MEMS inertial sensing chip and the ASIC signal processing chip are packaged in a tube shell through wire bonding, and no matter whether the two chips are tiled or stacked, the final sensor size is large, the manufacturing process is complex, the cost is high, the signal is transmitted between the chips through the wire, the transmission distance is long, the efficiency is low, and the noise is large. SUMMARY

[0005] The application relates to a manufacturing method of an integrated MEMS inertial device and the integrated MEMS inertial device prepared based on the manufacturing method, and at least part of the defects of the prior art can be solved.

[0006] The application relates to a manufacturing method of an integrated MEMS inertial device, which comprises the following steps.

[0007] S1, providing an ASIC wafer;

[0008] S2, bonding a blank wafer to the ASIC wafer, thinning the blank wafer, performing photoetching alignment based on alignment marks on the ASIC wafer, and then etching the blank wafer into a device layer wafer to obtain a first bonding body containing the ASIC wafer and the device layer wafer;

[0009] S3, bonding a cap wafer to the first bonding body, thinning the ASIC wafer and the cap wafer to obtain a second bonding body;

[0010] S4, dicing the second bonding body to obtain a single MEMS inertial device, and performing a signal leading operation on the MEMS inertial device.

[0011] As one of the embodiments, the photolithography alignment based on the alignment mark on the ASIC wafer specifically comprises:

[0012] Based on the long-wave infrared emitted by the alignment mark on the ASIC wafer, a long-wave infrared lens is used for detection, so as to perform photolithography alignment.

[0013] As one of the embodiments, the photolithography alignment based on the alignment mark on the ASIC wafer specifically comprises:

[0014] Etching the corresponding region of the blank wafer to expose the alignment mark on the ASIC wafer, and then performing photolithography alignment.

[0015] As one of the embodiments, in S1, the ASIC wafer is provided with a conducting part and a bonding connection part; in S2, the bonding of the ASIC wafer and the blank wafer is realized based on the bonding connection part, and the electrical conduction between the device layer wafer and the ASIC wafer is realized based on the conducting part.

[0016] As one of the embodiments, the pre-preparation of the conducting part and the bonding connection part on the ASIC wafer specifically comprises:

[0017] A passivation layer is grown on the ASIC wafer, and an electrical connection hole and a bonding anchor column are prepared on the ASIC wafer through photolithography, etching and cleaning processes;

[0018] A conducting metal is grown in the electrical connection hole, a bonding metal is grown on the bonding anchor column, and patterning is performed.

[0019] As one of the embodiments, in S1, an electrical interface and a sensing signal interface are prepared on the ASIC wafer in advance, and then the conducting part and the bonding connection part are prepared, the electrical interface is used for signal leading, and the conducting part is prepared on the sensing signal interface.

[0020] As one of the embodiments, a metal wiring layer is grown on the ASIC wafer, and the metal wiring layer is patterned to form a sensing signal interface and an electrical interface on the surface of the ASIC wafer.

[0021] As one of the embodiments, in S1, a TSV structure is prepared inside the ASIC wafer; in S3, when the ASIC wafer is thinned, the ASIC wafer is thinned to the end of the TSV structure and a solder joint is prepared at the end of the TSV structure, and in S4, a signal leading structure is connected by soldering at the solder joint.

[0022] As one of the embodiments, the ASIC wafer is bonded with the blank wafer by means of eutectic bonding; and the cap wafer is bonded with the first bonding body by means of eutectic bonding or fusion sealing bonding.

[0023] The application also relates to an integrated MEMS inertial device prepared by the preparation method.

[0024] The application has at least the following beneficial effects:

[0025] In the application, the blank wafer is bonded on the ASIC wafer first, and then the blank wafer is made into a device layer wafer, so that the pattern deviation caused by the double wafer alignment and bonding operation can be avoided, the alignment precision between the device layer wafer and the ASIC wafer is ensured, and thus the product quality of the MEMS inertial device is ensured and the performance of the MEMS inertial device is improved.

[0026] In the application, the alignment mark is made on the ASIC wafer in advance, and based on the precision of photolithography alignment, the alignment precision between the device layer wafer and the ASIC wafer, including but not limited to the alignment precision between the pattern on the device layer wafer and the anchor point on the ASIC wafer, can be ensured, so that the product quality of the MEMS inertial device is ensured and the performance of the MEMS inertial device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0028] Figure 1 A schematic diagram for pre-treating the ASIC wafer;

[0029] Figure 2 A schematic diagram for integrating the ASIC wafer and the device layer wafer;

[0030] Figure 3 A flowchart of the preparation method of the electrical interface in the TSV structure (the intermediate steps are omitted). DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0032] Embodiment one: as Figure 1 and Figure 2 The embodiment of the present application provides a manufacturing method of an integrated MEMS inertial device 200, comprising the following steps:

[0033] S1, providing an ASIC wafer 1;

[0034] S2, bonding a blank wafer 2 to the ASIC wafer 1, manufacturing the blank wafer 2 into a device layer wafer 20, and obtaining a first bonding body;

[0035] S3, bonding a cap wafer 3 to the first bonding body, thinning the ASIC wafer 1 and the cap wafer 3, and obtaining a second bonding body 100;

[0036] S4, dicing the second bonding body 100, obtaining a single MEMS inertial device 200, and performing a signal leading operation on the MEMS inertial device 200.

[0037] The blank wafer 2 is a wafer without patterns.

[0038] The eutectic bonding is preferably adopted between the blank wafer 2 and the ASIC wafer 1, and since the blank wafer 2, the pattern deviation caused by the double wafer alignment and eutectic bonding can be avoided in the process.

[0039] In one of the embodiments, S2 specifically comprises the following steps:

[0040] Thinning the blank wafer 2,

[0041] Performing photoetching alignment based on the alignment mark on the ASIC wafer 1, and then etching the blank wafer 2 to obtain the device layer wafer 20.

[0042] Optionally, when the blank wafer 2 is thinned, the thickness of the blank wafer 2 is thinned to a range of 5-80 μm, which is beneficial to the manufacturing of the device layer wafer 20.

[0043] By manufacturing the alignment mark on the ASIC wafer 1 in advance, the alignment precision between the device layer wafer 20 and the ASIC wafer 1 can be ensured based on the precision of the photoetching alignment, including but not limited to the alignment precision between the patterns on the device layer wafer 20 and the anchor points on the ASIC wafer 1, so that the product quality of the MEMS inertial device 200 is ensured and the performance of the MEMS inertial device 200 is improved.

[0044] In one of the embodiments, the lithography alignment based on the alignment marks on the ASIC wafer 1 specifically comprises: using a long-wave infrared lens to detect the long-wave infrared (which can penetrate silicon material) emitted by the alignment marks on the ASIC wafer 1, so as to perform lithography alignment. This alignment mode can ensure the alignment accuracy between the device layer wafer 20 and the ASIC wafer 1.

[0045] In another embodiment, the lithography alignment based on the alignment marks on the ASIC wafer 1 specifically comprises: etching the corresponding area of the blank wafer 2 to expose the alignment marks on the ASIC wafer 1, and then performing lithography alignment. This mode can use a conventional visible light lens to perform lithography alignment, which is convenient and reliable. In this mode, the alignment accuracy is mainly determined by the performance of the lithography machine, and the pattern shift can be generally controlled within 100 nm.

[0046] It can be understood that the etching of the blank wafer 2 is a lithography method, and the inertial sensitive structure is formed in the device layer wafer 20.

[0047] The ASIC wafer 1 and the blank wafer 2 are preferably bonded by eutectic bonding.

[0048] In one of the embodiments, as shown in Figure 1 and Figure 2 , a bonding connection part is made in advance on the ASIC wafer 1, and the bonding of the ASIC wafer 1 and the blank wafer 2 is realized based on the bonding connection part, which can improve the bonding efficiency and quality between the ASIC wafer 1 and the blank wafer 2.

[0049] Optionally, as shown in Figure 1 , the making of the bonding connection part on the ASIC wafer 1 specifically comprises:

[0050] a passivation layer 13 is grown on the ASIC wafer 1, and a bonding anchor column is made on the ASIC wafer 1 through lithography, etching and cleaning processes;

[0051] a bonding metal is grown on the bonding anchor column and is patterned.

[0052] When the ASIC wafer 1 and the blank wafer 2 are bonded, the blank wafer 2 is connected with the above-mentioned bonding anchor column.

[0053] In one of the embodiments, as shown in Figure 1 , a through part is made in advance on the ASIC wafer 1, and electrical conduction between the device layer wafer 20 and the ASIC wafer 1 is realized based on the through part, which can ensure the reliability of signal transmission between the device layer wafer 20 and the ASIC wafer 1.

[0054] Optionally, as shown inFigure 1 The making of the conducting part on the ASIC wafer 1 specifically includes:

[0055] A passivation layer 13 is grown on the ASIC wafer 1, and an electrical connection hole 14 is made on the ASIC wafer 1 through photolithography, etching and cleaning processes;

[0056] A conducting metal 15 is grown in the electrical connection hole 14, and is patterned.

[0057] The above-mentioned conducting part realizes the electrical conduction and signal transmission between the device layer wafer 20 and the ASIC wafer 1, which not only has a short transmission distance and high efficiency, but also can improve the quality of signal transmission and reduce noise, and the electrical connection has high reliability.

[0058] Preferably, the conducting part and the bonding connection part are made at the same time, for example, after the passivation layer 13 is grown on the ASIC wafer 1, the electrical connection hole 14 and the bonding anchor column are made on the ASIC wafer 1 through photolithography, etching and cleaning processes; the conducting metal 15 is grown in the electrical connection hole 14, and the bonding metal is grown on the bonding anchor column and is patterned. Figure 1 The conducting part and the bonding connection part can have the same structure, which can further simplify the process.

[0059] Optionally, the thickness of the passivation layer 13 is in the range of 1-10 μm, which can be silicon oxide, silicon nitride or undoped polysilicon; the thickness of the conducting metal and the bonding metal is preferably controlled in the range of 1-5 μm, and the conducting metal can be titanium, tungsten or aluminum, etc., and the bonding metal can be aluminum germanium or gold, etc.

[0060] In one embodiment, S1, a sensing signal interface 12 is made on the ASIC wafer 1 in advance, which is used for electrical communication with the device layer wafer 20. When the above-mentioned conducting part is made, the conducting part is electrically connected with the sensing signal interface 12, for example, the conducting part is made on the sensing signal interface 12. Optionally, Figure 1 A metal wiring layer is grown on the ASIC wafer 1, and the metal wiring layer is patterned, so as to form the sensing signal interface 12 on the surface of the ASIC wafer 1.

[0061] In one embodiment, S1, an electrical interface 11 is made on the ASIC wafer 1 in advance, which is used for signal lead-out. As an optional way, Figure 1 A metal wiring layer is grown on the ASIC wafer 1, and the metal wiring layer is patterned, so as to form the electrical interface 11 on the surface of the ASIC wafer 1; preferably, Figure 2In step S4, the electrical interface 11 for signal extraction is located outside the projection range of the cap wafer 3 on the ASIC wafer 1. Signal extraction can be performed based on this electrical interface 11, which is convenient to operate. The electrical interface 11 can be fabricated simultaneously with the aforementioned sensing signal interface 12. Specifically, after growing a metal wiring layer on the ASIC wafer 1, the metal wiring layer is patterned to form the sensing signal interface 12 and the electrical interface 11 on the surface of the ASIC wafer 1.

[0062] The aforementioned metal wiring layer can be made of metals such as titanium, tungsten, gold, or aluminum, and its thickness is preferably in the range of 100~1000nm; the patterning of the metal wiring layer can be achieved by etching or stripping processes.

[0063] As another alternative, such as Figure 3 In step S3, a TSV structure 110 is prefabricated inside the ASIC wafer 1. In step S4, when thinning the ASIC wafer 1, it is thinned to the end of the TSV structure 110, thus exposing one end of the TSV structure 110. A solder joint 111 is fabricated at the end of the TSV structure 110. In step S5, based on the solder joint 111, signal leads are made using pressure bonding, specifically by bonding signal lead-out structures (including but not limited to signal connection lines) at the solder joint 111. Preferably, the TSV structure 110 is fabricated during ASIC design and wafer fabrication.

[0064] The cap wafer 3 can be bonded to the device layer wafer 20 or to the ASIC wafer 1. The bonding method can be eutectic bonding, and correspondingly, metals such as aluminum germanium / gold can be grown in the bonding area (which can be on the cap wafer 3 and / or on the first bond body), with a thickness preferably of 500~1000um; or a fusion bonding method can be used, and correspondingly, glass paste is printed in the bonding area, with a thickness preferably of 1~10μm.

[0065] Optionally, the cavity depth of the cap wafer 3 is in the range of 5~20μm.

[0066] Optionally, after the ASIC wafer 1 and the cap wafer 3 are thinned, the total wafer thickness of the resulting second bond 100 is in the range of 300~600μm.

[0067] Example 2: This embodiment of the invention provides an integrated MEMS inertial device 200, which is fabricated using the same method as the integrated MEMS inertial device 200 described in Example 1.

[0068] The above merely provides the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of fabricating an integrated MEMS inertial device, comprising: The method comprises the following steps: S1, providing an ASIC wafer; S2, bonding a blank wafer to the ASIC wafer, thinning the blank wafer, performing photolithography alignment based on alignment marks on the ASIC wafer, and then etching the blank wafer into a device layer wafer to obtain a first bonded body comprising the ASIC wafer and the device layer wafer; S3, bonding a cap wafer to the first bonded body, and thinning the ASIC wafer and the cap wafer to obtain a second bonded body; S4, dicing the second bonded body to obtain a single MEMS inertial device, and performing signal lead-out operation on the MEMS inertial device.

2. The method of claim 1, wherein The photolithography alignment based on the alignment marks on the ASIC wafer specifically comprises: Performing detection by using a long-wave infrared lens based on long-wave infrared emitted by the alignment marks on the ASIC wafer, so as to perform photolithography alignment.

3. The method of claim 1, wherein the integrated MEMS inertial device is a microelectromechanical system (MEMS) accelerometer. The photolithography alignment based on the alignment marks on the ASIC wafer specifically comprises: Exposing the alignment marks on the ASIC wafer by etching a corresponding region of the blank wafer, and then performing photolithography alignment.

4. The method of claim 1, wherein In S1, the ASIC wafer is provided with a through-connection part and a bonding connection part; In S2, the bonding connection part is used to bond the ASIC wafer and the blank wafer, and the through-connection part is used to electrically connect the device layer wafer and the ASIC wafer.

5. The method of claim 4, wherein the integrated MEMS inertial device is a microelectromechanical system (MEMS) accelerometer. The through-connection part and the bonding connection part are pre-prepared on the ASIC wafer, which specifically comprises: A passivation layer is grown on the ASIC wafer, and an electrical connection hole and a bonding anchor column are prepared on the ASIC wafer by photolithography, etching and cleaning processes; A through metal is grown in the electrical connection hole, and a bonding metal is grown on the bonding anchor column and is patterned.

6. The method of fabricating an integrated MEMS inertial device of claim 4, wherein, In S1, an electrical interface and a sensing signal interface are pre-prepared on the ASIC wafer, and then the through-connection part and the bonding connection part are prepared, the electrical interface is used for signal lead-out, and the through-connection part is prepared on the sensing signal interface.

7. The method of fabricating an integrated MEMS inertial device of claim 6, wherein, A metal wiring layer is grown on the ASIC wafer, and the metal wiring layer is patterned to form the sensing signal interface and the electrical interface on the surface of the ASIC wafer.

8. The method of claim 1, wherein In S1, a TSV structure is prepared inside the ASIC wafer; In S3, the ASIC wafer is thinned to the end of the TSV structure and a solder joint is prepared at the end of the TSV structure when the ASIC wafer is thinned, In S4, a signal lead-out structure is connected by soldering at the solder joint.

9. The method of claim 1, wherein The ASIC wafer and the blank wafer are bonded by eutectic bonding, and the cap wafer is bonded to the first bonded body by eutectic bonding or fusion sealing bonding.

10. An integrated MEMS inertial device, characterized by, The integrated MEMS inertial device is prepared by the method of any one of claims 1 to 9.

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