Infrared detector column processing circuit

Abstract

The invention discloses an infrared detector column processing circuit, and relates to the technical field of infrared detectors. The average value calculation circuit is composed of a column-level operational amplifier, a filtering module and a sampling noise reduction module, and the sampling noise reduction module further comprises a switch-capacitor network (S-C network) and a ping-pong sampling module. Average value calculation of multiple times of sampling of analog signals is effectively realized; the influence of noise on the signal can be reduced, so that a more stable signal value is output; the circuit is realized in a pure simulation mode, so that a complicated digital processing process is avoided, the circuit structure is relatively simple, and the cost is relatively low; meanwhile, the circuit is easy to expand due to the modular design, the sampling frequency and the average level can be adjusted according to actual requirements, and certain flexibility and practicability are achieved.

Description

Technical Field

[0001] This invention relates to the field of infrared detector technology, and in particular to an infrared detector array processing circuit. Background Technology

[0002] In low-background applications, such as sky imaging, infrared detectors often need to stretch the image gain to highlight imaging details. However, if there is noise in the operational amplifier during this process, the noise will be amplified accordingly, causing the human eye to see obvious column stripes or flash lines when observing the image. This noise phenomenon has a certain impact on image quality and is difficult to solve through subsequent correction methods.

[0003] Operational amplifier noise mainly includes thermal noise and flicker noise. Noise can be reduced to some extent by adjusting parameters such as the channel size of the MOSFET, the gate oxide thickness, and increasing the filter capacitor. However, the effectiveness of these methods is limited and they are often restricted by process and design.

[0004] In addition, other patents have proposed other noise reduction methods. For example, the patent with publication number CN119325041A reduces noise by sampling and integrating m times to amplify the signal by m times. This method improves the noise reduction effect to a certain extent, but it is accompanied by an increase in circuit complexity and cost.

[0005] Traditional methods for reducing column noise mainly include using large-size MOSFETs and increasing filter capacitors. Using large-size MOSFETs can reduce noise, but the size of the MOSFET cannot be increased indefinitely due to the limitation of detector area. In addition, while increasing filter capacitors helps to filter out high-frequency noise, it also increases the row transition time, which places higher demands on the driving capability of the operational amplifier and leads to increased power consumption.

[0006] Traditional methods for reducing column noise have certain limitations in practical applications and cannot meet the high image quality requirements of infrared detectors in low-background applications. Therefore, a more effective method for reducing column operational amplifier noise is needed to improve the quality of infrared imaging. Summary of the Invention

[0007] The purpose of this invention is to provide an infrared detector column processing circuit with column-level operational amplifiers, filter capacitors, and a sampling noise reduction module. This circuit structure solves the problem of column-direction noise affecting image quality when infrared detectors are used in low-background applications through innovative sampling noise reduction technology design, reduces thermal noise and flicker noise generated by the column operational amplifier, and improves the clarity and detail of infrared imaging in low-background applications.

[0008] The technical solution proposed in this invention is implemented as follows: An infrared detector column processing circuit includes a column-level operational amplifier, a filtering module, and a sampling noise reduction module; the column-level operational amplifier has its positive input terminal connected to a pixel circuit to receive pixel signals, and its negative input terminal connected to its output terminal to form a unity-gain negative feedback structure; the filtering module includes a filtering capacitor C connected between the output terminal of the column-level operational amplifier and ground; the sampling noise reduction module includes a switch-capacitor network (SC network) and a ping-pong sampling module; the switch-capacitor network (SC network) is composed of N cascaded switch-capacitor units, the first stage SC network includes a switch S1 and a capacitor C1, the second stage includes a switch S2 and a capacitor C2, and the Nth stage includes a switch SN and a capacitor CN; the units from the first stage to the Nth stage are connected in series through switches (S1-SN), and the positive terminals of capacitors (C1-CN) are connected to switches (S1-SN). The series nodes of N) are connected, and the negative terminals of all capacitors are grounded; the ping-pong sampling module includes an additional unit connected in parallel with the first-stage switch-capacitor unit. The additional unit consists of a series switch S1' and a capacitor C1', and satisfies C1=C2=...=CN=C1'; the column processing circuit has: an input terminal connected to the positive input terminal of the column-level operational amplifier and connected to the pixel; a first output terminal connected to the positive terminal of capacitor C1 of the first stage of the switch-capacitor network; and a second output terminal connected to the positive terminal of capacitor C1' of the ping-pong sampling structure; the capacitance value of the filter capacitor C is significantly larger than the capacitance values ​​of each sampling capacitor C1-CN and C1'; the column-level operational amplifier adopts a folded common-source common-gate structure and has a voltage gain of 80dB-100dB; the switch-capacitor network achieves 2 by controlling the timing of the switch chain. N-1 The signal is sampled multiple times, and the sampled values ​​are arithmetically averaged. The number of stages N in the switch-capacitor network is ≥3. The capacitance of the filter capacitor C is greater than 10 times the sum of the values ​​of all sampling capacitors. The switches (S1-SN, S1') are implemented using CMOS transmission gates.

[0009] The theoretical basis of the circuit noise reduction in this invention is as follows: The noise reduction theory of this invention lies in using multiple sampling averaging techniques to reduce the disturbance of random noise. Its core idea is briefly described as follows: In a single sampling process, due to the superposition of various types of random noise, the obtained sampled value often deviates from the actual signal value. To overcome this problem, this invention adopts a multiple sampling averaging strategy. This strategy reduces the interference of random noise by performing multiple independent samplings of the same signal and calculating the arithmetic mean of these sampled values. Because the positive and negative effects of random noise in multiple samplings cancel each other out, the average value is closer to the true signal value.

[0010] Furthermore, in the extreme case where the number of column-level samples approaches infinity, the sampled value of each column will infinitely approach its true value. According to the infrared focal plane array parameter testing method, the noise calculation formula is: ; ; in Vi: The value of the i-th sample.

[0011] F: Number of samples.

[0012] V: The average value of F samples.

[0013] Under this limiting condition, as Vi approaches V, (V−Vi)² will approach 0, causing the output of the entire noise calculation formula to also approach 0. This means that the column-level noise will approach zero.

[0014] The noise reduction method of this invention improves the accuracy of sampled values ​​and reduces column noise levels through a column-level multiple sampling averaging strategy. Under the extreme condition that the number of column-level samplings approaches infinity, the column-level noise will approach zero. The selection of the actual number of samplings should also consider comprehensive factors such as frame rate and occupied area.

[0015] The infrared detector column processing circuit proposed in this invention features a column-level operational amplifier, filtering capacitors, and a sampling noise reduction module. It employs an averaging circuit based on an SC network, effectively calculating the average value of multiple samples of the analog signal through precise control of a multi-stage switched capacitor network. This design reduces the impact of noise on the signal, resulting in a more stable output signal value. It solves the problem of column-direction noise affecting image quality in low-background applications of infrared detectors, reduces thermal and flicker noise generated by the column operational amplifier, and improves the clarity and detail of infrared imaging in low-background conditions. Furthermore, the circuit is implemented purely analog, avoiding complex digital processing, resulting in a relatively simple circuit structure and lower cost. Its modular design also makes the circuit easily expandable, allowing adjustment of the sampling number and averaging level according to actual needs, providing flexibility and practicality. Attached Figure Description

[0016] Figure 1 The present invention provides a block diagram of the readout circuit array processing circuit.

[0017] Figure 2 The present invention provides a circuit diagram of the readout circuit array processing circuit.

[0018] Figure 3 The present invention provides an algorithm for calculating the average circuit of the sampling and noise reduction module.

[0019] Figure 4 Example circuit structure of a 4-level switch-capacitor network invention.

[0020] Figure 5 : Switch waveform diagram of the present invention.

[0021] The technical solution and advantages of the present invention will be further described below with reference to the accompanying drawings and embodiments. The sampling averaging principle in this circuit design is as follows: Figure 3 As shown, a pairwise averaging method was used. The example in the figure illustrates the process of 16 samplings, where the voltage value sampled each time is labeled Vi (i=1, 2, …, 16). After these sampled values ​​are averaged pairwise, the average value is recorded as V1_x (x=1,2, …, 8); then, the value of V1_x is averaged pairwise again to obtain V2_x (x=1,2, …, 4); and so on, the value of V2_x is averaged pairwise again to obtain V3_x (x=1, 2), and finally the average value of V3_1 and V3_2 is recorded as V4_1.

[0022] The specific steps are explained below: Initial sampling and pairwise averaging: 1) The first and second sampled values ​​are averaged to obtain v1_1.

[0023] 2) The 3rd and 4th sample values ​​are averaged to obtain v1_2.

[0024] 3) Next, average v1_1 and v1_2 to obtain the average value v2_1 of the first 4 samples.

[0025] Continue sampling, pairwise averaging, and combination: 1) The 5th and 6th sample values ​​are averaged to obtain v1_3.

[0026] 2) The 7th and 8th sample values ​​are averaged to obtain v1_4.

[0027] 3) Average v1_3 and v1_4 to obtain the average value v2_2 of the 5th to 8th samples.

[0028] 4) At this point, average v2_1 (the average of the first 4 times) with v2_2 (the average of the 5th to 8th times) to obtain the average of the first 8 samples, v3_1.

[0029] Expand to more sampling times: 1) Following the steps above, continue to average the subsequent sampled values ​​pairwise. For example, average the sampled values ​​from the 9th to the 12th times to obtain v1_5 and v1_6 respectively, and then average these two values ​​to obtain the average value v2_3 from the 9th to the 12th times.

[0030] 2) Similarly, the sampling values ​​from the 13th to the 16th times are v1_7 and v1_8, and then the average value from the 13th to the 16th times is v2_4.

[0031] 3) Average v2_3 (average of the 9th to 12th times) with v2_4 (average of the 13th to 16th times) to get v3_2 (average of the 9th to 16th times).

[0032] Iteration and final average: 1) Average v3_1 (the average of the first 8 samples) with v3_2 (the average of the 9th to 16th samples) to obtain the final average of the first 16 samples, V4_1. Due to the multiple pairwise averaging, the random noise is significantly smoothed.

[0033] 2) When the SC network is of level N, the above strategy of pairwise averaging and combination can be used to gradually obtain 2 N-1 The average of all samples. Each level represents a larger range of average values ​​from all previous samples, thus effectively suppressing noise.

[0034] The core of this algorithm lies in pairwise averaging and combination. By adjusting the number of levels N in the SC network, it can flexibly adapt to different numbers of sampled values ​​and different levels of noise suppression requirements. Furthermore, this algorithm is easily extended to larger sample sets and more complex averaging strategies, providing an effective solution for noise suppression in circuit design.

[0035] Timing design for circuit averaging: such as Figure 2 As shown, in a switched-capacitor (SC) network, through precise timing control and the coordinated operation of capacitors and switches, it is possible to perform multiple samplings and calculate the average value. The following section uses a 3-level SC network as an example to elaborate on its timing design process and demonstrates how to extend it to more levels to achieve averaging with more samples.

[0036] Timing design for a Level 3 SC network: (1) Circuit composition and initial state: 1) The circuit contains three capacitors C1, C2, and C3, and three switches S1, S2, and S3.

[0037] 2) C1 is connected to C2 through S1, C2 is connected to C3 through S2, and C3 is connected to the output terminal of the column operational amplifier and the filter capacitor C through S3.

[0038] 3) In the initial state, all switches are closed to ensure that the voltage of all capacitors is the same and equal to the output of the column operational amplifier. After the column operational amplifier stabilizes, it is ready to enter the sampling and noise reduction mode.

[0039] (2) Sampling and average value calculation steps: 1) First sampling: Disconnect S1, sample C1, and store the voltage V1 in C1; keep S2 and S3 closed.

[0040] 2) Second sampling: Disconnect S2, sample C2, and store the voltage V2 in C2; keep S1 open and S3 closed.

[0041] 3) Calculate the average value of the first and second samplings: Close S1, C1 and C2 share the charge, and the voltage V2_1 = (V1 + V2) / 2 is obtained; after stabilization, open S1 and store V2_1 in C1.

[0042] 4) Reset C2: Close S2.

[0043] 5) Third sampling: Disconnect S2, sample C2, and store voltage V3 in C2; keep S1 open and S3 closed.

[0044] 6) Fourth sampling: Disconnect S3, sample C3, and store voltage V4 in C3; keep S1 and S2 disconnected.

[0045] 7) Calculate the 3rd and 4th times and the overall average: a) When S2 is closed, C2 and C3 share the charge, resulting in a voltage V2_2 = (V3 + V4) / 2; after stabilization, S2 is opened, and V2_2 is stored in C2.

[0046] b) Close S1 again, and C1 (stores V2_1) and C2 (stores V2_2) share the charge, resulting in a voltage V3_1 = (V2_1 + V2_2) / 2 = (V1 + V2 + V3 + V4) / 4; after stabilization, open S1, and V3_1 is stored in C1.

[0047] Expand to more SC network levels: (1) Access to Level 4 SC network: a) Introduce a new capacitor C4 and a switch S4.

[0048] b) C4 is connected to C3 via S4 and then connected to the output of the column operational amplifier.

[0049] c) Repeated sampling and average calculation steps: C4, C3, and C2 are used to sample the values ​​from the 5th to the 8th time and then average them. C1 remains disconnected.

[0050] d) Store the average value of 5-8 samples into C2.

[0051] (2) Calculate the average of the first 8 samples: a) Turn on S1 (C1 stores the average value of 1-4 times), and share the charge of C2 (stores the average value of 5-8 times) with C1.

[0052] b) After disconnecting S1, the voltage on C1 is the average value of 1-8 samples.

[0053] (3) Continue to expand to more levels: a) Introduce more capacitors and switches, expanding step by step.

[0054] b) The number of sampling times doubles for each level increase (e.g., from 8 to 16).

[0055] c) By switching operations and charge sharing, the newly sampled average value is combined with the previous average value.

[0056] d) After each round, store the final average value in C1.

[0057] (4) Loop operation: a) Repeat the steps, continuously adding new levels, and performing more sampling and average calculations.

[0058] b) When the SC network is of level N, 2 can be calculated. N-1 Average value of each sample.

[0059] c) After each round, the average value is stored in C1 via a switch operation.

[0060] Replacing S1 and C1 in the above description with S1' and C1' will enable the switching to ping-pong mode.

[0061] Through the above design, the SC network can efficiently perform multiple samplings and calculate the average value, effectively suppressing noise and improving circuit performance.

[0062] Invention Embodiment: A 4-level sampling noise reduction infrared detector array processing circuit based on SC network The circuit structure is shown in the attached figure. Figure 4 The timeline is as follows. Figure 5 As shown.

[0063] Circuit parameters: 1) Capacitors C1=C2=C3=C4=100fF, C=5pF 2) SC network levels: 4 levels 3) Number of samplings: Calculate the average of 8 samples. Timing and Operation Procedures: Initial state: 1) Switches S1 to S4 are in the closed state to initialize the charging of capacitors C1 to C4.

[0064] 2) Switch S1' is in the off state, preparing for ping-pong sampling.

[0065] Sampling and averaging process: 1) First sampling: Disconnect switch S1, capacitor C1 samples the signal, and record the pixel voltage signal V1 at this time.

[0066] 2) Second sampling: Disconnect switch S2, capacitor C2 samples the signal, and record the pixel voltage signal V2 at this time.

[0067] 3) First calculation of the average: a) Close switch S1 to redistribute the charge of capacitors C1 and C2, and calculate the average value V1_1=(V1+V2) / 2.

[0068] b) Disconnect switch S1 and store the calculated average voltage into capacitor C1. c) Keep switch S2 closed to prepare for the next sampling.

[0069] 4) Third sampling: Disconnect switch S2 and record the pixel voltage signal as V3 at this time.

[0070] 5) Fourth sampling: Disconnect switch S3 and record the pixel voltage signal as V4 at this time.

[0071] 6) Calculate the average for the second time: a) Close switch S2 and calculate the average value V1_2=(V3+V4) / 2.

[0072] b) Disconnect switch S2 and store the average voltage in capacitor C2.

[0073] c) Close switch S3 (to prepare for the next averaging), while keeping switch S3 closed.

[0074] 7) Calculate the average for the third time: a) Close switch S1 and calculate the cumulative average value: V2_1=(V1_1+V1_2) / 2=(V1+V2+V3+V4) / 4.

[0075] b) Disconnect switch S1 and store the accumulated average voltage in capacitor C1.

[0076] c) Keep switches S2 and S3 closed to prepare for the next sampling.

[0077] 8) Sampling from the 5th to the 8th time and averaging: a) Repeat the above process, sequentially disconnect switches S2, S3, and S4 to sample, and calculate the average values ​​V1_3=(V5+V6) / 2 and V1_4=(V7+V8) / 2.

[0078] b) By closing S2, calculate the average of 5-8 iterations: (V5+V6+V7+V8) / 4 c) By closing S1, calculate the average value from 1 to 8 times and save the value C1. d)V3_1=(V2_1+V2_2) / 2=(V1+V2+V3+V4+V5+V6+V7+V8) / 8 Ping-pong sampling and output mode: 1) After sampling the current row 8 times and calculating the average value, prepare to sample the next row.

[0079] 2) At this time, switch S1' is closed, and capacitor C1' begins to sample the voltage signal of the first pixel in the next row.

[0080] 3) At the same time, switch S1 is opened, capacitor C1 (the capacitor that stores the final average value of 8 times) is connected to the output operational amplifier, and the output mode is entered, outputting the calculated average voltage.

[0081] 4) This process is repeated to achieve continuous sampling, noise reduction, and output of the infrared detector array signals.

Claims

1. An infrared detector array processing circuit, characterized in that: Includes column-level operational amplifiers, filtering modules, and sampling noise reduction modules; The column-level operational amplifier has its positive input terminal connected to the pixel circuit to receive the pixel signal, and its negative input terminal connected to the output terminal to form a unity-gain negative feedback structure. The filtering module includes a filtering capacitor C connected between the output terminal of the column-stage operational amplifier and ground; The sampling and noise reduction module includes a switched-capacitor network (SC network) and a ping-pong sampling module; The switch-capacitor network (SC network) consists of N cascaded switch-capacitor units. The first-stage SC network includes switch S1 and capacitor C1, the second-stage includes switch S2 and capacitor C2, and the Nth-stage includes switch SN and capacitor CN. The units from the first stage to the Nth stage are connected in series through switches (S1-SN), the positive terminals of capacitors (C1-CN) are connected to the series junction of switches (S1-SN), and the negative terminals of all capacitors are grounded. The ping-pong sampling module includes an additional unit connected in parallel with the first-stage switch-capacitor unit. The additional unit consists of a switch S1' and a capacitor C1' connected in series, and satisfies C1=C2=...=CN=C1'. The column processing circuit is equipped with: The input terminal is connected to the positive input terminal of the column operational amplifier and is connected to the cell. The first output terminal is connected to the positive terminal of capacitor C1 in the first stage of the switched-capacitor network. The second output terminal is connected to the positive terminal of capacitor C1' in the ping-pong sampling structure; The capacitance value of the filter capacitor C is significantly greater than the capacitance values ​​of each sampling capacitor C1-CN and C1'; The column-level operational amplifier adopts a folded cascode structure and has a voltage gain of 80dB-100dB. The switched-capacitor network achieves 2 by controlling the timing of the switching chain. N-1 The signal is sampled once, and the sampled values ​​are then arithmetically averaged.

2. The infrared detector array processing circuit according to claim 1, characterized in that: The number of stages N in the switch-capacitor network is greater than or equal to 3.

3. The infrared detector array processing circuit according to claim 1, characterized in that: The capacitance of the filter capacitor C is greater than 10 times the sum of the capacitances of all sampling capacitors.

4. The infrared detector array processing circuit according to claim 1, characterized in that: The switches (S1-SN, S1') are implemented using CMOS transmission gates.

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