A method for estimating capacitance of a semiconductor device and an optimal design method
By designing multiple test structures and fitting curves, the parasitic capacitance between the gate and the conductive contact was separated, solving the problem of the difficulty in measuring the gate-to-conductive contact capacitance in semiconductor devices, and realizing accurate capacitance measurement and optimized design.
Patent Information
- Application Number
- CN202511486664.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-17
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2045-10-17
AI Technical Summary
In semiconductor devices, the parasitic capacitance Cco from the gate to the conductive contact is difficult to measure separately, and existing technologies struggle to effectively separate and accurately measure this capacitance.
By designing multiple test structures and using conductive contacts and gates with different spacings, capacitance data is obtained. Parasitic capacitance is separated using the fitting curve. A shallow trench isolation structure is set to shield other capacitances, and a parasitic capacitance fitting curve between the gate and the conductive contact is obtained.
It enables accurate measurement and separation of parasitic capacitance between the gate and conductive contact, improving the accuracy of capacitance measurement and optimizing device design based on the fitted curve.
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Figure CN120971821B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a method for estimating capacitance of a semiconductor device and a method for optimizing design. BACKGROUND
[0002] With the increasing scale of integrated circuits, the device size is getting smaller and smaller, and the distance between devices is getting closer and closer. The influence of the parasitic capacitance of MOSFET devices on the overall performance of the circuit is also increasing. In order to improve the performance of the circuit, it is necessary to accurately measure the parasitic capacitance of MOSFET, especially the capacitance Cco from the gate to the conductive contact (CT), the capacitance Cpm from the gate to the interconnection layer (Metal), and the like.
[0003] The capacitance Cov from the gate to the active region and the capacitance Cgg from the gate to the body region Pwell in the MOSFET device can be measured separately, but the capacitance Cco from the gate to the conductive contact (CT) is inevitably included in the measurement, and it is difficult to separate it out. SUMMARY
[0004] In view of the above problems, the purpose of the present application is to provide a method for estimating the capacitance of a semiconductor device and a method for optimizing design to measure the parasitic capacitance between the gate and the conductive contact.
[0005] One aspect of the present application provides a method for estimating the capacitance of a semiconductor device, comprising:
[0006] providing a plurality of first test structures, the first test structures comprising a first gate, a conductive contact, and a first wiring layer, and in different first test structures, the adjacent conductive contacts have different spacings;
[0007] obtaining a first capacitance of a plurality of first test structures;
[0008] providing at least one second test structure, the second test structure comprising a second gate and a second wiring layer;
[0009] obtaining a second capacitance of the second test structure;
[0010] subtracting the plurality of first capacitances from the second capacitance respectively to obtain a plurality of target parasitic capacitances;
[0011] obtaining a fitting curve of the target parasitic capacitance and the spacing of the adjacent conductive contacts; and
[0012] calculating the parasitic capacitance of the semiconductor device according to the fitting curve;
[0013] The target parasitic capacitance is a capacitance between the first gate and the conductive contact, and the fitting curve includes a rising stage of the target parasitic capacitance with an increase of a spacing of adjacent conductive contacts and a saturation stage close to a saturation value.
[0014] The fitting curve is:
[0015] Cco=Co*(1+fac*(-1.0+tanh((Space-dds) / slope)))
[0016] wherein Cco is the target parasitic capacitance, Co, fac, dds, and slope are fitting parameters, and Space is the spacing of adjacent conductive contacts.
[0017] Optionally, the target parasitic capacitance includes:
[0018] a front-side parasitic capacitance of the conductive contact and the first gate; and
[0019] a side-side parasitic capacitance of the conductive contact and the first gate.
[0020] Optionally, the side-side parasitic capacitance changes with a change of the spacing of adjacent conductive contacts.
[0021] Optionally, an intercept of an ordinate of the fitting curve is the front-side parasitic capacitance of the conductive contact and the first gate.
[0022] Optionally, the first test structure includes:
[0023] a first semiconductor layer;
[0024] a first shallow trench isolation structure in the first semiconductor layer;
[0025] the first gate is on the first shallow trench isolation structure, and the conductive contact is on the first shallow trench isolation structure and couples the first wiring layer to the first shallow trench isolation structure.
[0026] The second test structure includes:
[0027] a second semiconductor layer, which is substantially the same as the first semiconductor layer;
[0028] a second shallow trench isolation structure in the second semiconductor layer, which is substantially the same as the first shallow trench isolation structure;
[0029] the second gate is on the second shallow trench isolation structure, and the second gate is substantially the same as the first gate; and the second wiring layer is substantially the same as the first wiring layer.
[0030] Another aspect of the present application provides a method for optimizing design of a semiconductor device, comprising:
[0031] providing a plurality of first test structures, the first test structures comprising a first gate, a conductive contact, and a first wiring layer, and in different first test structures, the conductive contacts have different distances between adjacent conductive contacts;
[0032] obtaining a plurality of first capacitances of the first test structures;
[0033] providing at least one second test structure, the second test structure comprising a second gate and a second wiring layer;
[0034] obtaining a second capacitance of the second test structure;
[0035] subtracting the plurality of first capacitances from the second capacitance respectively to obtain a plurality of target parasitic capacitances;
[0036] obtaining a fitting curve between the target parasitic capacitances and the distances between adjacent conductive contacts; and
[0037] setting the distance between adjacent conductive contacts of the semiconductor device according to an expected value of the target parasitic capacitance of the semiconductor device;
[0038] wherein the target parasitic capacitance is a capacitance between the first gate and the conductive contact, and the fitting curve comprises a rising stage of the target parasitic capacitance with an increase of the distance between adjacent conductive contacts and a saturation stage approaching a saturation value;
[0039] the fitting curve is:
[0040] Cco=Co*(1+fac*(-1.0+tanh((Space-dds) / slope)))
[0041] wherein Cco is the target parasitic capacitance, Co, fac, dds, and slope are fitting parameters, and Space is the distance between adjacent conductive contacts.
[0042] Optionally, the target parasitic capacitance comprises:
[0043] a front surface parasitic capacitance of the conductive contact and the first gate; and
[0044] a side surface parasitic capacitance of the conductive contact and the first gate.
[0045] Optionally, the side surface parasitic capacitance changes with a change of the distance between the conductive contacts in the first test structure.
[0046] Optionally, an intercept of an ordinate of the fitting curve is the front surface parasitic capacitance of the conductive contact and the first gate.
[0047] Optionally, the first test structure comprises:
[0048] a first semiconductor layer;
[0049] a first shallow trench isolation structure in the first semiconductor layer;
[0050] the first gate is on the first shallow trench isolation structure, the conductive contact is on the first shallow trench isolation structure, and the first wiring layer is coupled to the first shallow trench isolation structure;
[0051] the second test structure comprises:
[0052] a second semiconductor layer, substantially the same as the first semiconductor layer;
[0053] a second shallow trench isolation structure in the second semiconductor layer, substantially the same as the first shallow trench isolation structure;
[0054] the second gate is on the second shallow trench isolation structure, substantially the same as the first gate; and the second wiring layer is substantially the same as the first wiring layer.
[0055] The unexpected technical effect of the present application is:
[0056] The present application obtains a fitting curve of the parasitic capacitance Cco between the gate and the conductive contact and the distance Space between the conductive contacts, according to which the parasitic capacitance between the gate and the conductive contact can be obtained by measuring the distance between the conductive contacts of the semiconductor device.
[0057] The present application obtains a fitting curve of the parasitic capacitance Cco between the gate and the conductive contact and the distance Space between the conductive contacts, according to which the relationship between the parasitic capacitance of the gate and the conductive contact and the distance between the conductive contact and the gate, and the relationship between the parasitic capacitance of the gate and the conductive contact and the distance between the conductive contacts can be studied.
[0058] The present application obtains a fitting curve of the parasitic capacitance Cco between the gate and the conductive contact and the distance Space between the conductive contacts, according to which, based on the expected value of the parasitic capacitance of the semiconductor device, the distance between the conductive contacts is obtained based on the above fitting curve as a guide, and the semiconductor device is optimized based on the distance.
[0059] Further, the present application improves the accuracy of capacitance measurement by setting a shallow trench isolation structure in the test structure to shield the parasitic capacitance of the gate semiconductor layer.
[0060] Furthermore, this application designs a first test structure and a second test structure to isolate the parasitic capacitance between the gate and the conductive contact. Attached Figure Description
[0061] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0062] Figure 1 A schematic cross-sectional view of a semiconductor device is shown:
[0063] Figure 2 A flowchart of the capacitance estimation method for a semiconductor device according to the first embodiment of this application is shown;
[0064] Figure 3a A cross-sectional view of a first test structure according to a first embodiment of this application is shown;
[0065] Figure 3b It shows Figure 3a The diagram shows a top view of the layout of the first test structure.
[0066] Figure 4a A cross-sectional view of the second test structure according to the first embodiment of this application is shown;
[0067] Figure 4b It shows Figure 4a The diagram shows a top view of the layout of the second test structure.
[0068] Figure 5 A fitted curve is shown between the parasitic capacitance of multiple test samples and the spacing of the conductive contact in one embodiment;
[0069] Figure 6a A partially enlarged view of the first test structure is shown;
[0070] Figure 6b A partially enlarged view of the nth first test structure is shown;
[0071] Figure 7 A flowchart illustrating the optimization design method of a semiconductor device according to a second embodiment of this application is shown. Detailed Implementation
[0072] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.
[0073] This application may be presented in various forms, some of which will be described below.
[0074] Figure 1 A schematic cross-sectional view of a semiconductor device is shown. The semiconductor device 100 is, for example, a MOSFET (i.e., a metal-oxide-semiconductor field-effect transistor), but is not limited thereto. In one embodiment, the semiconductor device is, for example, an N-type MOSFET. As shown, the semiconductor device 100 includes a semiconductor layer 101, a source region 102, a drain region 103, a gate stack, a conductive contact 107, and an interconnect layer 108. Figure 1
[0075] The semiconductor layer 101 can be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. In this application, the semiconductor layer 101 includes a semiconductor substrate P-sub, a well region DWN in the semiconductor substrate P-sub, and a body region Pwell in the well region DWN. The source region 102 and the drain region 103 are in the semiconductor layer 101, and the gate stack is on the semiconductor layer 101 and between the source region 102 and the drain region 103. The source region 102 and the drain region 103 are doped regions in the semiconductor layer 101. For example, for an N-type MOSFET, the source region 102 and the drain region 103 are N-type doped; for a P-type MOSFET, the source region 102 and the drain region 103 are P-type doped. The gate stack of the semiconductor device 100 includes a gate dielectric layer 104, a gate electrode 105, and a sidewall 106, wherein the gate dielectric layer 104 is sandwiched between the semiconductor layer 101 and the gate electrode 105. The conductive contact 107 couples the wiring layer 108 to the source region 102 and the drain region 103, respectively.
[0076] In the above structure, the parasitic capacitances include a capacitance Cco of the gate electrode 105 to the conductive contact 107, a capacitance Cpm of the gate electrode 105 to the wiring layer 108, a capacitance Cov of the gate electrode 105 to the active region (the source region 102 and the drain region 103), a capacitance Cgg of the gate electrode 105 to the body region Pwell, etc.
[0077] The capacitance Cov of the gate electrode 105 to the active region (the source region 102 and the drain region 103) and the capacitance Cgg of the gate electrode 105 to the body region Pwell in the MOSFET device can be measured separately, while the capacitance Cco of the gate electrode 105 to the conductive contact (CT) 107 is difficult to separate from the capacitance Cpm of the gate electrode 105 to the interconnect layer 108, the capacitance Cov of the gate electrode 105 to the active region (the source region 102 and the drain region 103), and the capacitance Cgg of the gate electrode to the body region Pwell during the measurement.
[0078] Figure 2 A flowchart of a method for estimating capacitances of a semiconductor device according to a first embodiment of the present application is shown, as shown in FIG. 1. The method for estimating capacitances of a semiconductor device includes: Figure 2
[0079] S110: providing a plurality of first test structures, the first test structures comprising a first gate, a conductive contact, and a first wiring layer, and in different first test structures, the conductive contacts have different intervals between adjacent conductive contacts;
[0080] S120: obtaining a first capacitance of the plurality of first test structures;
[0081] S130: providing at least one second test structure, the second test structure comprising a second gate and a second wiring layer;
[0082] S140: obtaining a second capacitance of the second test structure;
[0083] S150: subtracting the second capacitance from the plurality of first capacitances respectively to obtain a plurality of target parasitic capacitances;
[0084] S160: obtaining a fitting curve of the target parasitic capacitance and the interval of the adjacent conductive contacts; and
[0085] S170: calculating a parasitic capacitance of a semiconductor device according to the fitting curve;
[0086] The target parasitic capacitance is a capacitance between the first gate and the conductive contact, and the target parasitic capacitance is related to the interval of the adjacent conductive contacts.
[0087] Specifically, in step S110, a plurality of first test structures are provided. Figure 3a A cross-sectional view of the first test structure 200 of the first embodiment of the present application is shown, Figure 3b A top view layout of the first test structure 200 is shown. Figure 3a As shown in the first test structure 200, Figure 3a And Figure 3b As shown, the first test structure 200 comprises a first semiconductor layer 201, a first shallow trench isolation structure 209 located in the first semiconductor layer 201, a first gate stack located above the first semiconductor layer 201, a first conductive contact 207, and a first interconnection layer 208.
[0088] The first semiconductor layer 201 can be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. In this application, the first semiconductor layer 201 includes a semiconductor substrate P-sub, a well region DWN in the semiconductor substrate P-sub, and a body region Pwell in the well region DWN. The first shallow trench isolation structure 209 is in the first semiconductor layer 201, specifically in the body region Pwell. The first gate stack is on the first semiconductor layer 201, specifically on the first shallow trench isolation structure 209. The first gate stack of the first test structure 200 includes a first gate dielectric layer 204, a first gate electrode 205, and a first sidewall 206, wherein the first gate dielectric layer 204 is sandwiched between the first shallow trench isolation structure 209 and the first gate electrode 205. The first conductive contact 207 is on the first shallow trench isolation structure 209 and is separated from the first gate electrode 205. The first conductive contact 207 couples the first wiring layer 208 to the first shallow trench isolation structure 209.
[0089] The plurality of first test structures are substantially the same except that the spacing between the first conductive contacts 207 in the plurality of first test structures is different. As shown in FIG. 2, the plurality of first test structures 200 include, for example, a first first test structure 2001, a second first test structure 2002, and an nth first test structure 200n. The first conductive contacts 207 in the first first test structure 2001 have a first spacing Space1, the first conductive contacts 207 in the second first test structure 2002 have a second spacing Space2, and the first conductive contacts 207 in the nth first test structure 200n have an nth spacing Spacen. Figure 3b
[0090] In step S120, the first capacitance of each of the plurality of first test structures 200 is obtained. In the plurality of first test structures 200, the first shallow trench isolation structure 209 is disposed in the body region Pwell, and the first gate electrode 205 and the first conductive contact 207 are both disposed on the first shallow trench isolation structure 209. The first shallow trench isolation structure 209 isolates the first gate electrode 205 and the body region Pwell, and the first conductive contact 207 and the body region Pwell, shields the capacitance between the first gate electrode 205 and the body region Pwell and the capacitance between the first conductive contact 207 and the body region Pwell, and further makes the parasitic capacitance in the first test structure 200 include the capacitance Cco between the first gate electrode 205 and the first conductive contact 207 and the capacitance Cpm between the first gate electrode 205 and the first wiring layer 208, i.e., C1=Cco+Cpm.
[0091] The first capacitance of the first test structure 2001 is C11=Cco1+Cpm1, the first capacitance of the second test structure 2002 is C12=Cco2+Cpm2, and the first capacitance of the nth test structure 200n is C1n=Ccon+Cpmn. Cco1 is the capacitance between the first gate 205 and the first conductive contact 207 in the first test structure 2001, Cpm1 is the capacitance between the first gate 205 and the first wiring layer 208 in the first test structure 2001, Cco2 is the capacitance between the first gate 205 and the first conductive contact 207 in the second test structure 2002, Cpm1 is the capacitance between the first gate 205 and the first wiring layer 208 in the second test structure 2002, Ccon is the capacitance between the first gate 205 and the first conductive contact 207 in the nth test structure 200n, and Cpmn is the capacitance between the first gate 205 and the first wiring layer 208 in the nth test structure 200n.
[0092] Since the first gates 205 of the plurality of first test structures are substantially the same, the first wiring layers 208 of the plurality of first test structures are substantially the same, and the distance between the first gate 205 and the first wiring layer 208 is the same, Cpm1=Cpm2=…=Cpmn=Cpm0, that is, the first capacitance of the first test structure is C11=Cco1+Cpm0, the first capacitance of the second test structure is C12=Cco2+Cpm0, and the first capacitance of the nth test structure is C1n=Ccon+Cpm0. Further, the distances between the first conductive contacts 207 of the plurality of first test structures are different, so the capacitance between the first gate 205 and the first conductive contact 207 in different first test structures is different.
[0093] In step S130, at least one second test structure is provided. Figure 4a A cross-sectional view of the second test structure 300 of the first embodiment of the present application is shown, Figure 4b A top view of the second test structure 300 is shown. Figure 4a As shown in the top view of the second test structure 300, Figure 4a And Figure 4b As shown, the second test structure 300 includes a second semiconductor layer 301, a second shallow trench isolation structure 309 in the second semiconductor layer 301, a second gate stack above the second semiconductor layer 301, and a second interconnection layer 308.
[0094] The second semiconductor layer 301 can be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. In this application, the second semiconductor layer 301 includes a semiconductor substrate P-sub, a well region DWN in the semiconductor substrate P-sub, and a body region Pwell in the well region DWN. The second shallow trench isolation structure 309 is in the second semiconductor layer 301, specifically in the body region Pwell. The second gate stack is on the second semiconductor layer 301, specifically on the second shallow trench isolation structure 309. The second gate stack of the second test structure 300 includes a second gate dielectric layer 304, a second gate electrode 305, and a second sidewall 306, wherein the second gate dielectric layer 304 is sandwiched between the second shallow trench isolation structure 309 and the second gate electrode 305.
[0095] Further, the second semiconductor layer 301 of the second test structure 300 is substantially the same as the first semiconductor layer 201 of the first test structure 200, and the second gate stack of the second test structure 300 is substantially the same as the first gate stack of the first test structure 200, for example, the second gate electrode 305 is substantially the same as the first gate electrode 205, the second gate dielectric layer 304 is substantially the same as the first gate dielectric layer 204, and the second sidewall 306 is substantially the same as the first sidewall 206. The second wiring layer 308 of the second test structure 300 is substantially the same as the first wiring layer 208 of the first test structure 200. Substantially the same includes that all parameters such as size and material are the same.
[0096] In step S140, a second capacitance of the second test structure 300 is obtained. The body region Pwell of the second test structure 300 is provided with the second shallow trench isolation structure 309, and the second gate electrode 305 is arranged on the second shallow trench isolation structure 309. The second shallow trench isolation structure 309 isolates the second gate electrode 305 and the body region Pwell, and shields the capacitance between the second gate electrode 305 and the body region Pwell, so that the parasitic capacitance in the second test structure 300 only includes the capacitance Cpm between the second gate electrode 305 and the second wiring layer 308, i.e. C2=Cpm.
[0097] Further, in addition to the first conductive contact 207, the second test structure 300 is substantially the same as the first test structure 200, and the capacitance Cpm between the second gate electrode 305 and the second wiring layer 308 is Cpmo, i.e. C2=Cpmo.
[0098] In step S150, a plurality of first capacitances are subtracted from the second capacitance respectively to obtain a plurality of target parasitic capacitances, wherein the target parasitic capacitance is the parasitic capacitance between the gate electrode and the conductive contact.
[0099] Specifically,
[0100] C11 - C2= Cco1 + Cpmo - Cpmo = Cco1 ;
[0101] C12 - C2= Cco2 + Cpmo - Cpmo = Cco2 ;
[0102] ...
[0103] C1n - C2= Ccon + Cpmo - Cpmo = Ccon.
[0104] The multiple target parasitic capacitances, i.e. the parasitic capacitances Cco1, Cco2,..., Ccon between the gate and the conductive contacts, are obtained via the above steps.
[0105] Further, in step S160, a fitting curve between the multiple target parasitic capacitances and the spacing of the conductive contacts is obtained.
[0106] Figure 5 A fitting curve between the multiple target parasitic capacitances and the spacing of the conductive contacts in one embodiment is shown. As shown, the fitting curve is: Figure 5
[0107] Cco = Co * (1 + fac * (-1.0 + tanh((Space - dds) / slope)))
[0108] where Cco is the parasitic capacitance between the gate and the conductive contact, i.e. the target parasitic capacitance, Co, fac, dds, slope are fitting parameters, in one embodiment, Co = 3.02E -10 , fac = 0.23, dds = 0.12, slope = 0.2, and Space is the spacing (ct to ct space) between the adjacent first conductive contacts 207.
[0109] From the above curve, it can be seen that the fitting curve includes a rising stage where the target parasitic capacitance increases with the spacing of the conductive contacts and a saturation stage where the target parasitic capacitance approaches a saturation value. When the spacing ds between the first conductive contacts 207 is 0, Cco = 1.9524098.
[0110] Figure 6a A partial enlarged view of the first first test structure 2001 is shown, Figure 6b A partial enlarged view of the nth first test structure 200n is shown. In the first first test structure 2001, the spacing between the first conductive contacts 207 is, for example, Space1, which is, for example, 0.2 microns, corresponding to the rising stage of the fitting curve. Figure 5 In the nth first test structure 200n, the spacing between the first conductive contacts 207 is, for example, Spacen, which is, for example, 0.8 microns. Corresponding to the saturation stage of the fitting curve.Figure 5 The saturation stage of the fitted curve.
[0111] like Figure 6a As shown, in the first test structure 2001, the parasitic capacitance Cco1 between the first gate 205 and the first conductive contact 207 includes a first parasitic capacitance Ca and a second parasitic capacitance Cb1. The first parasitic capacitance Ca is the front parasitic capacitance (CT face polycap) between the first gate 205 and the first conductive contact 207, and the second parasitic capacitance Cb1 is the side parasitic capacitance (CT edge to polycap) between the first gate 205 and the first conductive contact 207. Figure 6b As shown, in the nth first test structure 200n, the parasitic capacitance Ccon between the first gate 205 and the first conductive contact 207 includes a first parasitic capacitance Ca and a second parasitic capacitance Cb2. The first parasitic capacitance Ca is the front parasitic capacitance (CT face poly cap) between the first gate 205 and the first conductive contact 207, and the second parasitic capacitance Cbn is the side parasitic capacitance (CT edge to poly cap) between the first gate 205 and the first conductive contact 207.
[0112] Continue reading Figure 5 The fitted curve shows that when the spacing Space between the first conductive contacts 207 is 0, the target parasitic capacitance Cco = Ca = 1.9524098. Figure 5 The intercept in the curve. When the distance Space between the first conductive contacts 207 gradually increases, the first parasitic capacitance Ca remains unchanged, while the second parasitic capacitance Cb gradually increases, which is the rising stage of the fitted curve. When the distance Space between the first conductive contacts 207 increases to a certain distance, the second parasitic capacitance Cb no longer changes and gradually tends to flatten out, which is the saturation stage of the fitted curve approaching the saturation value.
[0113] This application obtains a fitting curve of the parasitic capacitance Cco between the gate and the conductive contact and the spacing Space between the conductive contacts. According to the fitting curve, the parasitic capacitance between the gate and the conductive contact is related not only to the distance between the conductive contact and the gate (e.g., the Y-intercept of the fitting curve), but also to the spacing between adjacent conductive contacts.
[0114] In step S170, the target parasitic capacitance of the semiconductor device is calculated based on the fitted curve.
[0115] Based on the fitted curve, the distance between the conductive contact and the gate, as well as the spacing between the conductive contacts, in the target semiconductor device can be directly measured, thereby realizing the parasitic capacitance Cco between the gate and the conductive contact in the target semiconductor device.
[0116] The second embodiment of the present application provides an optimization design method of a semiconductor device, Figure 7 A flow chart of the optimization design method of the semiconductor device of the second embodiment of the present application is shown in FIG. 2. Figure 7 As shown in FIG. 2, the optimization design method of the semiconductor device comprises the following steps.
[0117] S210: providing a plurality of first test structures, the first test structures comprising a first gate, a conductive contact and a first wiring layer, and the distances between adjacent conductive contacts in different first test structures being different;
[0118] S220: obtaining first capacitances of the plurality of first test structures;
[0119] S230: providing at least one second test structure, the second test structure comprising a second gate and a second wiring layer;
[0120] S240: obtaining a second capacitance of the second test structure;
[0121] S250: subtracting the second capacitance from each of the first capacitances to obtain a plurality of target parasitic capacitances;
[0122] S260: obtaining a fitting curve of the target parasitic capacitances and the distances between adjacent conductive contacts; and
[0123] S270: setting the distance between adjacent conductive contacts of the semiconductor device according to an expected value of the target parasitic capacitance of the semiconductor device.
[0124] The target parasitic capacitance is the capacitance between the first gate and the conductive contact, and the target parasitic capacitance is related to the distance between adjacent conductive contacts
[0125] In this embodiment, the fitting curve between the parasitic capacitances and the distances between conductive contacts of a plurality of test samples is obtained according to the method in the first embodiment, and the design of the semiconductor device is optimized according to the fitting curve. According to the expected value of the parasitic capacitance of the semiconductor device, the distance between the conductive contacts is obtained by using the above fitting curve as a guide, and the semiconductor device is optimized with the distance.
[0126] The present application has the following unexpected technical effects:
[0127] The present application obtains the fitting curve of the parasitic capacitance Cco between the gate and the conductive contact and the distance Space between the conductive contacts, and according to the fitting curve, the parasitic capacitance between the gate and the conductive contact can be obtained by measuring the distance between the conductive contacts of the semiconductor device.
[0128] The application obtains a fitting curve of the parasitic capacitance Cco between the gate and the conductive contact and the space Space between the conductive contacts, and according to the fitting curve, studies the relationship between the parasitic capacitance of the gate and the conductive contact and the distance between the conductive contact and the gate, and the relationship between the parasitic capacitance of the gate and the conductive contact and the space between the conductive contacts.
[0129] The application obtains a fitting curve of the parasitic capacitance Cco between the gate and the conductive contact and the space Space between the conductive contacts, and according to the fitting curve, based on the expected value of the parasitic capacitance of the semiconductor device, obtains the space of the conductive contacts based on the above fitting curve as a guide, and optimizes the semiconductor device with the space.
[0130] Further, the application shields the parasitic capacitance of the gate semiconductor layer by setting the shallow trench isolation structure in the test structure, to improve the accuracy of the capacitance measurement.
[0131] Further, the application separates out the parasitic capacitance between the gate and the conductive contact by designing the first test structure and the second test structure.
[0132] According to the embodiments of the application as described above, these embodiments do not describe all the details, and do not limit the application to the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made. The description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that those skilled in the art can well utilize the application and make modifications and uses on the basis of the application. The application is limited only by the claims and their full scope and equivalents.
Claims
1. A method for estimating capacitance of a semiconductor device, comprising: providing a plurality of first test structures, each of the first test structures comprising a first gate, a conductive contact, and a first wiring layer, wherein different first test structures have different distances between adjacent conductive contacts; obtaining first capacitances of the plurality of first test structures; providing at least one second test structure, the second test structure comprising a second gate and a second wiring layer; obtaining a second capacitance of the second test structure; subtracting the second capacitance from each of the first capacitances to obtain a plurality of target parasitic capacitances; obtaining a fitting curve of the target parasitic capacitances versus the distances between adjacent conductive contacts; and calculating a parasitic capacitance of the semiconductor device according to the fitting curve; wherein the target parasitic capacitance is a capacitance between the first gate and the conductive contact, the fitting curve comprises a rising stage of the target parasitic capacitance increasing with the distance between adjacent conductive contacts and a saturation stage of the target parasitic capacitance approaching a saturation value; the fitting curve is: Cco = Co * (1 + fac * (-1.0 + tanh((Space - dds) / slope))) wherein Cco is the target parasitic capacitance, Co, fac, dds, and slope are fitting parameters, and Space is the distance between adjacent conductive contacts; the target parasitic capacitance comprises: a front-side parasitic capacitance between the conductive contact and the first gate; and a side-side parasitic capacitance between the conductive contact and the first gate; the side-side parasitic capacitance varies with the distance between adjacent conductive contacts; an intercept of an ordinate of the fitting curve is the front-side parasitic capacitance between the conductive contact and the first gate; the first test structure comprises: a first semiconductor layer; a first shallow trench isolation structure in the first semiconductor layer; the first gate is on the first shallow trench isolation structure, the conductive contact is on the first shallow trench isolation structure, and the first wiring layer is coupled to the first shallow trench isolation structure; the second test structure comprises: a second semiconductor layer substantially identical to the first semiconductor layer; a second shallow trench isolation structure in the second semiconductor layer, the second shallow trench isolation structure being substantially identical to the first shallow trench isolation structure; the second gate is on the second shallow trench isolation structure, the second gate being substantially identical to the first gate; and the second wiring layer is substantially identical to the first wiring layer. 6.A method for optimizing design of a semiconductor device, comprising: providing a plurality of first test structures, each of the first test structures comprising a first gate, a conductive contact, and a first wiring layer, wherein different first test structures have different distances between adjacent conductive contacts; obtaining first capacitances of the plurality of first test structures; providing at least one second test structure, the second test structure comprising a second gate and a second wiring layer; obtaining a second capacitance of the second test structure; subtracting the second capacitance from each of the first capacitances to obtain a plurality of target parasitic capacitances; obtaining a fitting curve of the target parasitic capacitances versus the distances between adjacent conductive contacts; and calculating a parasitic capacitance of the semiconductor device according to the fitting curve. 2. The method of capacitance estimation of a semiconductor device according to claim 1, wherein, 3. The method of capacitance estimation of a semiconductor device according to claim 2, wherein, 4. The method of capacitance estimation of a semiconductor device according to claim 1, wherein, 5. The method of capacitance estimation of a semiconductor device according to claim 1, wherein, a pitch of adjacent conductive contacts of the semiconductor device is set according to an expected value of a target parasitic capacitance of the semiconductor device; wherein the target parasitic capacitance is a capacitance between the first gate and a conductive contact, and the fitting curve comprises a rising stage of the target parasitic capacitance increasing with the pitch of adjacent conductive contacts and a saturation stage approaching a saturation value. The fitting curve is: Cco=Co*(1+fac*(-1.0+tanh((Space-dds) / slope))) wherein Cco is the target parasitic capacitance, Co, fac, dds, and slope are fitting parameters, and Space is the pitch of adjacent conductive contacts.
7. The method of optimizing a design of a semiconductor device according to claim 6, wherein, The target parasitic capacitance comprises: a front-side parasitic capacitance of the conductive contact and the first gate; and a side-side parasitic capacitance of the conductive contact and the first gate.
8. The method of optimizing a design of a semiconductor device according to claim 7, wherein, The side-side parasitic capacitance varies with the pitch of the conductive contacts in the first test structure.
9. The method of optimizing a design of a semiconductor device according to claim 6, wherein, An intercept of an ordinate of the fitting curve is the front-side parasitic capacitance of the conductive contact and the first gate.
10. The method of optimizing a design of a semiconductor device according to claim 6, wherein, The first test structure comprises: a first semiconductor layer; a first shallow trench isolation structure in the first semiconductor layer; the first gate is on the first shallow trench isolation structure, and the conductive contact is on the first shallow trench isolation structure and couples the first wiring layer to the first shallow trench isolation structure. The second test structure comprises: a second semiconductor layer, which is substantially identical to the first semiconductor layer; a second shallow trench isolation structure in the second semiconductor layer, which is substantially identical to the first shallow trench isolation structure; the second gate is on the second shallow trench isolation structure, and the second gate is substantially identical to the first gate; and the second wiring layer is substantially identical to the first wiring layer.
Citation Information
Patent Citations
Radio frequency test pad and radio frequency test structure
CN120933272A