Electric energy quality tester

Abstract

The invention relates to the technical field of electric power test and measurement, discloses an electric energy quality tester, and aims to solve the technical problems of passive measurement, insufficient common-mode error capture and limited dynamic interaction analysis in the prior art. The electric energy quality tester comprises at least two three-phase test interfaces, a switching selection module, a test circuit array group and a controllable power supply, the test circuit array group comprises a mimicry load test circuit, an out-of-order test circuit, a deviation test circuit and a condition simulation test circuit. Through adoption of the technical scheme, deep diagnosis and dynamic response characteristic analysis of a power grid operation state can be realized, various hidden and complex power quality problems including common-mode errors are effectively identified and quantified, and dynamic interaction among system components is disclosed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power quality testing, and more particularly to a power quality tester. BACKGROUND

[0002] As the core driving force of modern social development, the quality of electric power is directly related to the efficiency of industrial production, the stable operation of civil facilities, and the reliability of various precision electronic equipment. As a key device for monitoring and evaluating the operating state of the power system, the power quality tester plays an indispensable role in ensuring the safety of the power grid, diagnosing faults, and optimizing system operation. With the transformation of global energy structure and the rapid development of smart grids, the increasing popularity of distributed power sources, high-power-density power electronic devices, and complex nonlinear loads has made the operating environment of the power grid more complex than ever before, and has raised more stringent and detailed requirements for the evaluation of power quality.

[0003] The traditional power quality tester has relatively intuitive and simplified test logic. Such devices usually access the power source to be tested through multiple terminals, use built-in loads and high-precision detection sensors to obtain voltage and current waveforms in real time or periodically, and then evaluate common power quality indicators such as harmonic distortion, voltage sag, voltage swell, short interruptions, and frequency deviation by performing basic Fourier analysis, effective value calculation, and frequency tracking on the collected voltage and current waveforms. Whether it is single-phase testing or three-phase testing, the core principle revolves around passive monitoring and recording of the electrical parameters of the measured power grid under a given operating state. This "observation-based" testing method has shown its effectiveness and practicality in dealing with explicit power quality problems in traditional and relatively stable power systems. For a considerable period of time, such testers have effectively supported the diagnosis and handling of routine power quality problems by power system operation and maintenance personnel.

[0004] However, with the increasingly stringent operation requirements and the continuous improvement of complexity of modern power systems, the above traditional test methods gradually reveal their inherent limitations in principle, especially in diagnosing some deep and non-obvious power quality problems. The main reason is that the measurement paradigm of traditional test instruments relies too much on the capture of differential mode signals, i.e., mainly focusing on the voltage and current differences between the phase conductors or between the phase lines and the neutral line. This measurement method can effectively reflect most power quality problems, but for some specific types of deviations or waveform characteristics, especially those carrying common mode errors, it is difficult to effectively obtain and analyze them through simple differential mode measurement. Common mode errors, usually manifested as the same or similar voltage / current components exhibited by all phase lines (and the neutral line) relative to a common reference point (such as the ground). Such errors can be caused by poor system grounding, electromagnetic interference coupling, leakage current, common mode voltage generated by unbalanced nonlinear loads acting on the neutral line, or common mode noise generated by specific power electronic devices during switching. Since traditional test methods often lack independent, high-impedance common mode measurement paths, or their measurement circuit structures inherently suppress common mode signals, these hidden common mode disturbances are inadvertently ignored.

[0005] Furthermore, relying solely on passive observation makes it difficult for traditional test instruments to reveal dynamic and interactive power quality problems between components in complex power systems. For example, when a new load is connected to the grid, its internal nonlinear characteristics may interact with the impedance characteristics of the grid, resulting in unpredictable harmonic or transient phenomena. For another example, in a complex topology with multiple power sources connected in parallel, phase inconsistencies, frequency drifts, or uneven power distribution between different power sources can cause serious circulating currents or abnormal oscillations in the system under certain operating conditions. Traditional test instruments only record the waveforms at that moment, but they cannot actively simulate different load conditions, power source switching sequences, or apply specific disturbances to induce and capture these deep dynamic responses and interactions. This limitation makes it difficult to analyze the root cause of the problem, not to mention providing accurate diagnostic evidence for system optimization design or fault elimination. In other words, in the face of evolving grid complexity and diverse power quality challenges, existing technologies only provide a static "snapshot", but fail to present the "behavior patterns" of power systems under dynamic interaction, which to some extent limits their diagnostic depth and predictive ability.

[0006] Therefore, how to develop a kind of active, multi-dimensional interactive test capability, which can break through the traditional passive measurement paradigm, and effectively identify and quantify various hidden, complex power quality problems including common mode error, and can reveal the dynamic response and interaction characteristics of system, has become the key challenge and technical problem to be solved for the technical personnel in the field. SUMMARY

[0007] Therefore, the present application aims to provide a kind of power quality detector.

[0008] In order to solve the above technical problems, the technical scheme of the present application is: a kind of power quality test instrument, it is characterized in that, including at least two three-phase test interface, for coupling external three-phase power supply to be measured, still include switching selection module, test circuit array group, controllable power supply;

[0009] The switching selection module one end is coupled to the three-phase test interface, the other end is coupled to the test circuit array group, and the switching selection module is used to connect the power supply end of the three-phase test interface to different test circuits;

[0010] The test circuit array group includes a quasi-state load test circuit, a disorder test circuit, a deviation test circuit and a condition simulation test circuit, and each test circuit is configured with an electronic load and a current capture unit;

[0011] The quasi-state load test circuit is coupled to the power supply terminals of two different phases and belonging to one three-phase test interface, the electronic load is controlled according to the quasi-state test task to configure the load state of the circuit, and the quasi-state test data is generated by the information generated during the test according to the preset quasi-state capture strategy;

[0012] The disorder test circuit is coupled to the power supply terminals of the test ends of two different phases and not belonging to the same three-phase test interface, the disorder test task is generated according to the quasi-state test data, and the electronic load is controlled according to the disorder test task to configure the load state of the circuit, and the disorder test data is generated by the information generated during the test according to the preset disorder capture strategy;

[0013] The deviation test circuit is coupled to the power supply terminals of the test ends of two same phases and not belonging to the same three-phase test interface, the deviation test task is generated according to the quasi-state test data, and the electronic load is controlled according to the deviation test task to configure the load state of the circuit, and the deviation test data is generated by the information generated during the test according to the preset deviation capture strategy;

[0014] The condition simulation test circuit is coupled with a controllable power supply at one input end and a power terminal of a three-phase test interface at the other input end, generates a condition simulation test task according to the out-of-order test data, and generates a power control instruction according to the deviation test data, configures a corresponding electronic load through the condition simulation test task, controls the corresponding controllable power supply through the power control instruction to control the loop to work, and generates simulation test data through the information generated by the test under the preset condition simulation strategy.

[0015] Further, the switching selection module includes a switching transition unit, an instruction execution unit, and a relay sorting group, the switching transition unit includes a current protector, a voltage protector, and a disturbance filter, the instruction execution unit is configured to receive switching control information to generate switching control instructions, and the relay sorting group includes a plurality of relays, which work according to the switching control instructions to connect an external three-phase power supply to be tested to different test units.

[0016] Further, the mimic load circuit includes a mimic controller, which is coupled with an electronic load and a current capture unit, and is configured with a mimic control strategy, which includes

[0017] Step A1, according to the test input information, a corresponding test task sequence is retrieved from a preset mimic test table, and the test task sequence includes sequentially arranged impedance simulation instructions;

[0018] Step A2, the test current waveform is obtained through the current capture unit;

[0019] Step A3, the mimic abnormal value of the current waveform is calculated through a preset static feedback algorithm, a correction parameter is generated according to the mimic abnormal value to adjust the impedance simulation instruction of the next sequence, and the process returns to step A2 until all the impedance simulation instructions are completed.

[0020] Further, the mimic capture strategy includes

[0021] Step a1, an abnormal waveform feature library is configured, the abnormal waveform feature library stores a plurality of abnormal waveform features, and the obtained current waveform is compared with the abnormal waveform feature library to extract the corresponding mimic waveform feature;

[0022] Step a2, the corresponding state abnormal value is marked in the mimic waveform feature and brought into a preset mimic correlation model to obtain an abnormal pointing data set, the abnormal pointing data set includes an abnormal pointing item and a corresponding abnormal reliable value, and the abnormal pointing item reflects the abnormal type of the target phase current waveform;

[0023] Step a3, the abnormal pointing data set is split into an out-of-order pointing data set and a deviation pointing data set to generate the mimic test data.

[0024] Further, the disorder test circuit includes a disorder controller, the deviation test circuit is configured with a deviation controller and a waveform delay sub-circuit, the disorder controller is configured with a disorder test strategy, the disorder test strategy includes

[0025] Step B1, according to the current test of the disorder pointing data set, the corresponding reliable test task is called from the preset reliability analysis database, the reliable test task includes impedance test instruction and reliable acquisition window, and the reliable acquisition window is used to configure the acquisition window of the current acquisition unit to obtain the reliable window current waveform;

[0026] Step B2, the reliable abnormal items of the reliable window current waveform are analyzed by the reliable abnormal analysis algorithm to obtain the reliable sub-proportion of the corresponding to-be-tested terminal, and the reliable abnormal value corresponding to each abnormal type is calculated by the reliable sub-proportion, and the reliable abnormal value reflects the correlation between the to-be-tested terminal and the abnormal type;

[0027] Step B3, a plurality of reliable abnormal quantization ranges are configured, each abnormal type is marked according to the reliable abnormal quantization range into which the reliable abnormal value falls, and the to-be-tested terminal is recombined according to the preset combination difference condition to generate new switching control information;

[0028] Step B4, according to the abnormal type, the corresponding disorder test task is called from the preset disorder test database, the disorder test task includes impedance test instruction and disorder comparison sub-algorithm, the corresponding disorder comparison sub-algorithm is configured by the reliable abnormal value, and the current waveform is processed according to the disorder comparison sub-algorithm to generate the disorder test characteristics of the to-be-tested terminal;

[0029] Further, the deviation controller is configured with a deviation test strategy, and the deviation test strategy includes

[0030] Step C1, according to the current test of the deviation pointing data set, the delay test task is obtained from the preset delay analysis database, and the delay test task includes impedance test instruction and delay fitting algorithm;

[0031] Step C2, the delay deviation of the two-phase to-be-tested power supply is calculated by the delay fitting algorithm, and the delay correction instruction is generated according to the delay deviation to configure the corresponding waveform delay sub-circuit so that the waveforms of the two to-be-tested power supplies have the same phase;

[0032] Step C3, according to the abnormal type, the corresponding deviation test task is called from the preset deviation test database, the deviation test task includes impedance test instruction, and the impedance deviation characteristics of the to-be-tested terminal are generated by respectively collecting the current signals of the to-be-tested terminal under different types of impedance.

[0033] Further, the disorderly capture strategy is configured with a disorderly capture network, the disorderly capture network includes a plurality of disorderly feature nodes, disorderly feature nodes are configured with disorderly feature connections between them and form disorderly capture paths with preset combinations of disorderly feature nodes, each disorderly feature node is configured with a corresponding activation function, the corresponding disorderly activation value is calculated through the activation function, when the disorderly activation value exceeds the corresponding activation function threshold, the disorderly feature node is activated, when all disorderly feature nodes of a certain disorderly capture path are activated, the corresponding disorderly test data is generated according to the disorderly capture path, the activation function includes a reliability factor, an activation attenuation factor, a feature matching factor and an association gain factor, the reliability factor reflects the matching degree of the disorderly test feature and the to-be-tested end, the activation attenuation factor reflects the number of disorderly feature nodes of the to-be-tested end activated by the disorderly test feature, the feature matching factor reflects the matching degree of the disorderly feature node and the disorderly test feature, and the association gain factor reflects the number of other disorderly feature nodes having an association relationship with the disorderly feature node activated.

[0034] Further, the bias capture strategy includes

[0035] Step c1, acquiring an impedance test instruction of an impedance type of resistive impedance and performing a test to obtain a corresponding bias impedance feature, and calculating a resistive bias value through a resistive bias test algorithm;

[0036] Step c2, acquiring an impedance test instruction of an impedance type of capacitive impedance and performing a test to obtain a corresponding bias impedance feature, and calculating a capacitive bias value through a capacitive bias test algorithm, parameters in the capacitive bias test algorithm being generated according to the resistive bias value;

[0037] Step c3, acquiring an impedance test instruction of an impedance type of inductive impedance and performing a test to obtain a corresponding bias impedance feature, and calculating an inductive bias value through an inductive bias test algorithm, parameters of the inductive bias test algorithm being generated according to the inductive bias value;

[0038] Step c4, generating a composite impedance parameter through the resistive bias value, the capacitive bias value and the inductive bias value, acquiring a corresponding impedance test instruction according to the load impedance parameter, and calculating a composite impedance bias value through a composite impedance bias test algorithm;

[0039] Step c5, generating the bias test data according to the resistive bias value, the capacitive bias value, the inductive bias value and the composite impedance bias value.

[0040] Further, the conditional simulation test circuit comprises a simulation controller, the simulation controller is configured with a normal fitting database and a power supply control strategy, the normal fitting database stores power supply control instructions, the power supply control instructions are indexed by test fitting vectors, the power supply control strategy generates the test fitting vectors through chaotic test data, out-of-order test data and bias test data, and obtains corresponding power supply control instructions from the preset normal fitting database according to the test fitting vectors.

[0041] Further, the conditional simulation strategy comprises

[0042] Step d1, calibrate the output time of the controllable power supply through the calibration constraint condition to make the output of the controllable power supply and the to-be-tested end have the same phase;

[0043] Step d2, calculate the envelope area of the captured current waveform through a preset current integral algorithm to generate an envelope difference waveform;

[0044] Step d3, divide the envelope difference waveform into a plurality of envelope difference sub-waves of different types according to a preset envelope feature classification library;

[0045] Step d4, cluster analyze the obtained envelope difference sub-waves through a clustering analysis algorithm according to the phase range to obtain envelope abnormal difference clusters under different phase ranges;

[0046] Step d5, retrieve corresponding simulation abnormal sub-data according to the envelope abnormal difference clusters to generate simulation test data.

[0047] The technical effects of the present application mainly embody in the following aspects: compared with the traditional power quality analyzer, the power quality tester provided by the present application exhibits significant superiority in the depth, breadth, precision and initiative of power quality diagnosis. It can not only be passively monitored, but also actively induce, simulate and quantify complex power quality problems, thereby providing deep diagnostic information that cannot be obtained by traditional methods, and greatly improving the ability of power quality fault diagnosis and optimization. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 , the structure schematic diagram of the power quality tester of the present application;

[0049] Figure 2 , the structure schematic diagram of the switching selection module;

[0050] Figure 3 , the structure schematic diagram of the chaotic load test circuit;

[0051] Figure 4 , the flowchart of the chaotic capture strategy;

[0052] Figure 5 The flowchart of the out-of-order test strategy of the present application;

[0053] Figure 6 The flowchart of the deviation test strategy of the present application;

[0054] Figure 7 The flowchart of the conditional simulation strategy of the present application.

[0055] Reference signs: 100, three-phase test interface; 200, switching selection module; 210, switching transition unit; 220, instruction execution unit; 230, relay sorting group; 300, test circuit array group; 301, electronic load; 302, current capture unit; 310, analog load test circuit; 311, analog controller; 320, out-of-order test circuit; 321, out-of-order controller; 330, deviation test circuit; 331, deviation controller; 332, waveform delay sub-circuit; 340, conditional simulation test circuit; 341, simulation controller; 400, controllable power supply. DETAILED DESCRIPTION

[0056] The specific embodiments of the present application are further described in detail below with reference to the accompanying drawings, so that the technical solutions of the present application are easier to understand and master.

[0057] An electric energy quality tester is designed to solve the technical problems of passive measurement, insufficient common-mode error capture, and limited dynamic interaction analysis of the electric energy quality tester in the prior art. The present application realizes deep diagnosis and dynamic response characteristic analysis of the power grid operating state by introducing the architecture of active switching, multi-dimensional test circuit array, and controllable power supply synergy, thereby effectively identifying and quantifying various hidden and complex electric energy quality problems including common-mode error, and revealing the dynamic interaction between system components.

[0058] REFERENCE Figure 1The structural schematic diagram shows that the power quality tester comprises at least two three-phase test interfaces 100, a switching selection module 200, a test circuit array group 300 and a controllable power supply 400. The at least two three-phase test interfaces 100 are arranged on the external connection surface of the power quality tester, and the core function thereof is to realize safe and reliable electrical coupling with the external three-phase power source to be tested through a high-voltage test cable. Each three-phase test interface 100 is independently configured with dedicated phase input terminals, such as L1, L2 and L3, and a neutral input terminal N. In addition, in order to ensure the integrity of the test process and the safety of the operator, each interface can be reliably connected to the system ground reference potential through an independent grounding terminal. The switching selection module 200 serves as the entrance hub of the entire tester, the input end of which is electrically coupled with the output end of the three-phase test interface 100, and the output end thereof is further electrically coupled with the input end of the test circuit array group 300. The core function of the switching selection module 200 is to accurately direct and efficiently access the power source signal to be tested received from the three-phase test interface 100 to a specific test circuit unit inside the test circuit array group 300 according to the pre-set test task sequence or the real-time received control instruction. This flexible signal routing capability is the basis for multi-dimensional and dynamic testing.

[0059] The test circuit array group 300 is the core functional module of the application for realizing deep power quality analysis, which is internally integrated with various special test circuits, specifically including quasi-state load test circuit 310, disorder test circuit 320, deviation test circuit 330, and condition simulation test circuit 340. Each of the above-mentioned test circuits, i.e., quasi-state load test circuit 310, disorder test circuit 320, deviation test circuit 330, and condition simulation test circuit 340, is independently configured with a high-precision electronic load 301 and a wide-frequency-response current capture unit 302. The electronic load 301 is not a fixed impedance load in the traditional sense, but an advanced electronic load module with programmable and wide bandwidth characteristics. This module can work in multiple modes, such as constant current mode, constant voltage mode, constant resistance mode, and constant power mode. More importantly, it supports high-speed dynamic load switching and transient response simulation functions to accurately simulate the complex and variable load behavior in the actual power grid. To achieve high power density and fine control, the electronic load 301 is composed of multiple high-power-density insulated gate bipolar transistors or metal oxide semiconductor field effect transistor arrays in parallel, and is precisely regulated at the millisecond level by a precise current / voltage control loop driven by a high-speed digital analog converter. In actual application, the load adjustment resolution of the electronic load can be better than 0.1%, and the response time is less than 10 microseconds, thereby ensuring the ultimate fine simulation capability of the load change of the power grid. For example, a current sensor based on the Hall effect or flux gate principle is used to achieve electrical isolation from the measured power supply, with a measurement accuracy of 0.1% FS, a bandwidth covering DC to several megahertz, and coupled with a high-resolution, high-speed analog-to-digital converter, such as a 16-bit resolution, 10MSPS sampling rate synchronous sampling ADC, to ensure accurate digital capture of the current waveform. The current capture unit 302 also includes a configurable anti-aliasing filter with a cutoff frequency dynamically adjusted according to the sampling rate to prevent signal aliasing. The current capture unit 302 is composed of high-precision, wide-frequency-response current sensors, for example, current sensors based on the Hall effect principle or the flux gate principle can be used to achieve electrical isolation from the measured power supply, thereby effectively avoiding the influence of ground potential difference on measurement accuracy and improving system safety. The measurement accuracy of these sensors can reach 0.1% FS, with a bandwidth covering a wide frequency range from DC to several megahertz, ensuring accurate capture of current waveforms of various frequency components.

[0060] The pseudo-state load test circuit 310 is specifically designed to simulate the profound impact of a specific type of non-linear or dynamic load on the power grid. The input terminals of this circuit are electrically coupled in a unique way to two different phase terminals of the same three-phase test interface, such as the L1 and L2 phase terminals, in the three-phase test interface 100, to simulate inter-phase load characteristics. The pseudo-state load test circuit 310 precisely controls its built-in electronic load 301 according to a pre-set pseudo-state test task sequence, thereby configuring the load state of the circuit and inducing specific load responses on the power source under test. The pseudo-state test task sequence can be a complex time sequence containing a series of sequentially set impedance simulation instructions, such as gradual simulation from pure resistive load to pure capacitive load to pure inductive load, or simulation of loads with impact, pulse or harmonic source characteristics. Throughout the test process, the pseudo-state load test circuit 310 captures and processes the current waveform information generated by its internal current capture unit 302 in real time through a pre-set pseudo-state capture strategy, thereby generating detailed pseudo-state test data.

[0061] The out-of-order test circuit 320 is designed to analyze in-depth the potential dynamic interactions and abnormal patterns between multiple different three-phase power sources or different phases. The input terminals of this circuit are electrically coupled in a non-standard connection manner to power terminals of two different phases and not belonging to the same three-phase test interface, such as connecting the L1 phase terminal from the first three-phase test interface with the L2 phase terminal from the second three-phase test interface, or connecting the L1 phase terminal of the first three-phase test interface with the neutral terminal of the second three-phase test interface. This flexible connection method enables the out-of-order test circuit 320 to simulate and capture complex interactions across power sources and across phases. The out-of-order test circuit 320 receives an out-of-order test task generated by the analysis of pseudo-state test data, which indicates the specific interaction pattern to be simulated. According to the out-of-order test task, the out-of-order test circuit 320 precisely controls its built-in electronic load 301 to configure the load state of the circuit, thereby establishing a pre-set interaction pattern or injecting a specific disturbance between two different sources of power. Through a pre-set out-of-order capture strategy, the circuit captures current waveform information generated during the test in real time and generates out-of-order test data, providing a basis for subsequent interaction anomaly analysis.

[0062] The construction of the deviation test circuit 330 aims to accurately quantify the voltage or current deviation that may exist between the same phase lines of different test interfaces, with particular attention to subtle differences closely related to common-mode components. The input terminals of this circuit are ingeniously electrically coupled to the power supply terminals of the test terminals of two same-phase lines that do not belong to the same three-phase test interface, for example, connecting the L1 phase line terminal from the first three-phase test interface and the L1 phase line terminal from the second three-phase test interface. The deviation test circuit 330 receives a deviation test task generated by the quasi-state test data analysis, which defines in detail the type of deviation that needs to be induced or amplified. According to the deviation test task, the deviation test circuit 330 controls its built-in electronic load 301 to configure the load state of the circuit, thereby inducing or amplifying the expected deviation signal between the power input terminals of the two same-phase lines. Throughout the test process, the circuit captures the current waveform information generated by its current capture unit 302 in real time through a preset deviation capture strategy, and generates deviation test data to provide a basis for identifying and quantifying common-mode errors and imbalance problems.

[0063] The condition simulation test circuit 340 is the most core active test unit in the power quality tester proposed by the present application, which has the ability to actively inject specific disturbances or simulate specific power conditions to the power grid under test. This circuit is configured with at least two input terminals, one of which is crucially electrically coupled to the output terminal of the controllable power supply 400, and the other is electrically coupled to the power supply terminal of the three-phase test interface 100, such as L1, L2, L3 or neutral terminal. The controllable power supply 400 is designed as a high-precision, programmable AC power supply or a high-performance four-quadrant power amplifier. Its output voltage range can reach 0-600Vrms, and its output current range can reach 0-100Arms, which can accurately generate standard sine waves, waveforms containing specific harmonic superposition, transient pulses or any custom waveforms, and has excellent high dynamic response characteristics and extremely low output impedance to ensure that the injected disturbance can effectively act on the power grid. Its control interface uses an industrial Ethernet protocol, such as EtherCAT or a high-speed digital communication bus, to realize real-time synchronization and sub-microsecond accurate waveform control with the system main controller. The condition simulation test circuit 340 receives a condition simulation test task generated by the out-of-order test data analysis, and cooperatively controls the corresponding electronic load 301 and controllable power supply 400 according to the power control instructions generated by the deviation test data analysis, so that the entire test loop works under the simulated specific conditions. Through a preset condition simulation strategy, the circuit captures and processes the current waveform information generated during active testing, and finally generates simulation test data, thereby comprehensively evaluating the performance of the power grid under various extreme or abnormal conditions.

[0064] As a preferred embodiment of the present application, the specific structure of the switching selection module 200 is as follows: Figure 2As shown, the interface includes a switching transition unit 210, an instruction execution unit 220, and a relay sorting group 230. The input of the switching transition unit 210 is directly electrically coupled to the phase lines and neutral line terminals of the three-phase test interface 100, while its output is electrically coupled to the instruction execution unit 220. The switching transition unit 210 internally integrates a current protector, a voltage protector, and a disturbance filter. The current protector consists of a high-efficiency fast-acting fuse and a fast-responding overcurrent protection relay, designed to quickly disconnect the circuit within microseconds in the event of an overload or short-circuit fault, effectively protecting downstream sensitive test circuits from damage. The voltage protector consists of a high-performance transient suppression diode array and a precise overvoltage protection circuit, used to absorb transient overvoltage pulses at the nanosecond level and prevent high-voltage pulses from causing irreversible damage to precision electronic components. The disturbance filter is a multi-stage LC filter network designed to efficiently attenuate common-mode and differential-mode high-frequency noise from the power supply under test, ensuring the purity of the input signal. Its cutoff frequency can be dynamically configured and optimized according to current test requirements to adapt to noise suppression in different frequency ranges.

[0065] The instruction execution unit 220, as the intelligent core of the switching selection module 200, is configured to receive switching control information from the host computer or main controller and generate switching control commands conforming to the relay drive protocol based on this information. The instruction execution unit 220 consists of a high-performance microcontroller or field-programmable gate array (FPGA), which implements complex logic judgments and instruction generation through internal firmware to ensure the timeliness and accuracy of the commands. The relay sorting group 230 consists of several high-voltage, high-current solid-state relays or electromagnetic relays, carefully arranged in a matrix to achieve flexible connection of any input and output ports. The relay sorting group 230 operates precisely according to the switching control commands issued by the instruction execution unit 220, thereby enabling the connection of a specific phase or neutral line of an external three-phase power supply under test to a specific input terminal of a different test unit in the test circuit array group 300 within milliseconds. The contact carrying capacity of the relays is designed to be 1.5 times the rated current to ensure reliability and stability under long-term high-intensity operating conditions.

[0066] In a preferred embodiment of the present invention, the mimicry load test circuit 310, as shown in... Figure 3As shown, the mimic controller 311 is electrically coupled with the control port of the electronic load 301 and the data output port of the current capture unit 302 through a high-speed digital communication interface, such as SPI or I2C bus, thereby realizing real-time control of the load and synchronous acquisition of the current data. The mimic controller 311 is internally configured with a mimic control strategy, which is efficiently run in the processing unit of the mimic controller 311 in the form of firmware or software. The mimic control strategy includes the following detailed steps:

[0067] Step A1, according to the test input information received through the three-phase test interface 100, such as the voltage level of the power to be tested, the system frequency or the known impedance characteristics of the power grid, the corresponding test task sequence is accurately retrieved from the preset mimic test table. The mimic test table is stored in the form of two-dimensional array or structure in the non-volatile memory, each entry contains a unique test task ID and a series of sequentially set impedance simulation instruction list. The impedance simulation instruction specifically includes detailed impedance type, accurate impedance value, and the duration of the impedance state and other key parameters.

[0068] Step A2, the test current waveform data flowing through the mimic load circuit 310 is acquired in real time and synchronously by the current capture unit 302. The current waveform data is a high sampling rate digitized time series, and is subjected to strict calibration and unit conversion processing to ensure the accuracy and consistency of the data.

[0069] Step A3, the mimic abnormal value of the current waveform is calculated by a preset static feedback algorithm, such as a real-time impedance parameter estimation algorithm based on least squares method. The mimic abnormal value quantifies the deviation between the actual current waveform and the ideal current waveform expected according to the current impedance simulation instruction. According to the calculated mimic abnormal value, a correction parameter is dynamically generated, which is used to accurately adjust the impedance simulation instruction of the next sequence in the test task sequence. This correction process may involve fine adjustment of the impedance value, intelligent switching of the impedance type or optimization of the instruction duration, in order to better simulate the actual load characteristics or the power grid response. Steps A2 and A3 constitute a highly closed-loop feedback iteration process, which will continue to run until all impedance simulation instructions are completed or the preset convergence condition is reached, thereby realizing accurate mimic of complex power grid dynamic behavior.

[0070] As a preferred embodiment of the present application, the execution process of the mimic capture strategy includes the following specific steps: Figure 4 As shown, the mimic controller 311 is electrically coupled with the control port of the electronic load 301 and the data output port of the current capture unit 302 through a high-speed digital communication interface, such as SPI or I2C bus, thereby realizing real-time control of the load and synchronous acquisition of the current data. The mimic controller 311 is internally configured with a mimic control strategy, which is efficiently run in the processing unit of the mimic controller 311 in the form of firmware or software. The mimic control strategy includes the following detailed steps:

[0071] The anomaly waveform feature library is stored in the memory of the parastatic controller 311 in a tree structure or hash table form, and a plurality of strictly trained and classified abnormal waveform feature templates are pre-stored in it, such as Fourier coefficients, wavelet transform coefficients or time domain statistical features of specific harmonic distortion, voltage sag / rise, transient spike or high-frequency noise. According to the test current waveform obtained in real time by the current capture unit 302, the advanced pattern recognition algorithm such as the lightweight implementation of support vector machine is used to efficiently compare with the abnormal waveform feature library, so as to extract the most matched or most significant parastatic waveform feature from the current current waveform. This step aims to preliminarily identify the hidden power quality problem in the power grid.

[0072] Step a2, the corresponding state abnormal value calculated in step A3 is accurately marked on the extracted quasi-state waveform feature, and the marked feature is brought into the preset quasi-state correlation model. The quasi-state correlation model is an expert system based on rule-based reasoning or fuzzy logic, and its core function is to deeply analyze the internal relationship and causal relationship between the quasi-state waveform feature and the state abnormal value, and then obtain the abnormal pointing data set. The abnormal pointing data set is stored in a structured data format, which includes abnormal pointing items and corresponding abnormal reliable values. The abnormal pointing items reflect the specific abnormal types of the target phase current waveform, such as "high third harmonic", "voltage drop", "high frequency noise interference", and the abnormal reliable values quantify the probability of the existence of the abnormal type or its severity, the numerical range is usually between 0 and 1, 0 means no existence, and 1 means complete confirmation. The quasi-state correlation model is an expert system based on rule-based reasoning or fuzzy logic. In terms of rule-based reasoning, a rule base is first established, which contains a series of condition-conclusion rules. For example, rule 1: if quasi-state waveform feature F_1 meets condition C_1 and state abnormal value E_1 meets condition C_2, then abnormal pointing data set D_1 is obtained. The quasi-state waveform feature is obtained by a certain feature extraction algorithm, such as extracting the amplitude, frequency, phase and other features of the waveform. The state abnormal value is compared with the preset threshold to determine whether it meets the condition. In the reasoning process, the quasi-state waveform feature and the state abnormal value obtained in real time are matched with the rules in the rule base, if the conditions of a certain rule are met, the corresponding conclusion is obtained, that is, the abnormal pointing data set is obtained. In terms of fuzzy logic, the quasi-state waveform feature and the state abnormal value are first fuzzified. For example, the amplitude of the quasi-state waveform feature is divided into "high", "medium", "low" fuzzy sets, and the state abnormal value is divided into "serious", "general", "slight" fuzzy sets. The membership degree in each fuzzy set is determined by the membership function. Then, a fuzzy rule base is established, such as rule 2: if the amplitude of the quasi-state waveform feature is "high" and the state abnormal value is "serious", the abnormal pointing data set is "high risk". Through fuzzy reasoning algorithm, such as Mamdani reasoning algorithm, the fuzzy output is obtained according to the fuzzified input and the fuzzy rule base, and finally the specific abnormal pointing data set is obtained through defuzzification.

[0073] Step a3, the abnormality pointing data set is intelligently split according to a preset allocation rule, thereby forming a disorderly pointing data set and a deviation pointing data set. For example, the abnormality pointing items closely related to multi-phase interaction, cross-power interference or phase deviation are accurately allocated to the disorderly pointing data set. At the same time, the problems related to single-phase internal load characteristics, common mode characteristics or grounding systems, such as "single-phase overload", "neutral line current anomaly" or "common mode voltage drift", are allocated to the deviation pointing data set. The split disorderly pointing data set and deviation pointing data set jointly constitute the paratransient test data, which will be the accurate input of the subsequent disorderly test circuit 320 and deviation test circuit 330, and provide direction for further in-depth analysis.

[0074] As a preferred embodiment of the present application, the disorderly test circuit 320 includes a disorderly controller 321, and the deviation test circuit 330 is configured with a deviation controller 331 and a waveform delay sub-circuit 332. The disorderly controller 321 and the deviation controller 331 are realized by high-performance embedded processors or FPGAs, have high-speed data processing and real-time control capabilities, and can process complex signal processing algorithms. The waveform delay sub-circuit 332 is composed of a programmable digital delay line or an FPGA-based digital signal processor module, and its core function is to perform microsecond-level precision time delay adjustment on the input analog or digital waveform signals, to ensure the phase synchronization between multiple input signals or to achieve a preset accurate phase difference, which is crucial for accurate phase correlation analysis. The disorderly controller 321 is internally configured with a disorderly test strategy, and the execution process of the disorderly test strategy includes the following specific steps, as shown in Figure 5

[0075] Step B1, according to the disorderly pointing data set obtained by the current test, the corresponding reliable test task is accurately retrieved from the preset reliability analysis database. The reliability analysis database is stored in the form of key-value pair, where the key is the disorderly pointing item, and the value is the corresponding reliable test task. The reliable test task is a test sequence designed by optimization, which contains detailed impedance test instructions and configuration parameters of reliable acquisition window. The reliable acquisition window is used to accurately configure the acquisition window of the current acquisition unit 302, such as setting the starting time, duration and sampling rate of acquisition, to ensure that the most reliable window current waveform is obtained at the key moment of power grid dynamic response, thereby avoiding the interference of irrelevant data.

[0076] ​Step B2, the reliable abnormal items of the acquired reliable window current waveform are deeply analyzed by a reliable abnormal analysis algorithm, such as an algorithm based on spectrum analysis combined with statistical regression, to obtain the reliable sub-proportion of the corresponding to-be-tested terminal. The reliable sub-proportion quantifies the deviation degree of the specific abnormal type in the specific time window relative to the normal waveform, and the numerical range is usually between 0 and 1. Through the reliable sub-proportion, the reliable abnormal value corresponding to each abnormal type is calculated in combination with a preset weight coefficient. The reliable abnormal value is a comprehensive index reflecting the correlation strength between the to-be-tested terminal and the abnormal type, and the larger the value, the stronger the correlation, indicating the significance of the abnormality in multi-source or multi-phase interaction. The operation process of the reliable abnormal analysis algorithm is as follows: first, the reliable window current waveform is subjected to fast Fourier transform to convert the time domain signal into a frequency domain signal to obtain its frequency spectrum distribution. Let the current waveform signal be i(t), and the frequency domain signal I(f) is obtained after FFT transformation. Then, based on the statistical regression method, each frequency component in the frequency spectrum is analyzed. The components in a specific frequency range are selected, denoted as f1 to f2, and the linear regression analysis of the spectrum amplitude |I(f)| in this range is performed to establish a linear model y=ax+b of the amplitude and the frequency, where x is the frequency f and y is the amplitude |I(f)|. The coefficients a and b are determined by the least square method, and thus the feature description of the reliable abnormal item is obtained. Finally, the reliable sub-proportion is calculated according to the features, for example, if the feature amplitude of the reliable abnormal item accounts for a proportion p of the total spectrum amplitude, then the reliable sub-proportion can be represented as

[0077]

[0078] , and then the reliable abnormal value is calculated according to a preset formula.

[0079] Step B3, the disordered controller 321 is internally configured with multiple reliable abnormal quantization ranges, such as “slight abnormality”, “moderate abnormality”, “serious abnormality”, and the like discrete intervals. According to the reliable abnormal value calculated in step B2, the corresponding abnormal type is marked, for example, marked as “L1 phase moderate harmonic interaction abnormality”. On this basis, based on a preset combination difference condition, for example, the difference between the reliable abnormal values of the phase lines or the neutral line exceeds a specific threshold, the to-be-tested terminal is intelligently combined again. For example, if the reliable abnormal value difference between L1 phase and L2 phase is significant, they are marked as a potential interaction abnormality pair, and new switching control information is generated, which will be sent to the switching selection module 200 to dynamically adjust the phase line combination of the subsequent test, so as to focus on the most prominent phase-to-phase or cross-power interaction.

[0080] Step B4, according to the abnormal type identified in step B3, such as "L1-L2 interphase transient coupling abnormality", retrieve the corresponding out-of-order test task from the preset out-of-order test database. The out-of-order test database is indexed by specific abnormal types and stores multiple predefined test tasks. The out-of-order test task not only includes specific impedance test instructions, such as injecting complex impedance at a specific phase difference, but also contains an out-of-order comparison sub-algorithm. By taking the reliable abnormal value obtained in step B2 as an input parameter, the corresponding out-of-order comparison sub-algorithm is accurately configured. The out-of-order comparison sub-algorithm can be a time-domain or frequency-domain signal processing algorithm, such as an algorithm based on cross-correlation analysis or phase spectrum analysis, used to finely compare the waveform similarity, phase consistency or amplitude difference between different phase lines or different power sources. Finally, the real-time captured current waveform is deeply processed by the out-of-order comparison sub-algorithm to generate the out-of-order test features of the tested end, which quantifies the abnormality degree of waveform interaction between different test points, such as coupling coefficient, phase deviation jitter value or common-mode current imbalance. The out-of-order comparison sub-algorithm is also implemented based on cross-correlation analysis or phase spectrum analysis. In terms of cross-correlation analysis, let the waveforms between different phase lines or power sources be x(t) and y(t), respectively, and the cross-correlation function is defined as By calculating the cross-correlation function value under different delays τ, find the maximum value of the cross-correlation function, denoted as R xy (τ max ). According to the properties of the cross-correlation function, the larger R xy (τ max ), the more similar the two waveforms are. For example, when R xy (τ max ) exceeds a certain preset threshold, it is considered that the two waveforms have high similarity. In terms of phase spectrum analysis, first perform Fourier transform on the two waveforms to obtain their frequency spectra X(f) and Y(f). The phase spectra are ∠X(f) and ∠Y(f). Calculate the difference between the two phase spectra, for example, use the phase difference By integrating or statistically analyzing the phase difference within a certain frequency range, a comprehensive phase difference index is obtained. Let the frequency range be f1 to f2, and the phase difference index be According to the phase difference index, the similarity of the two waveforms is judged. The smaller the P value, the closer the two waveforms are in phase, and the higher the similarity.

[0081] As a preferred embodiment of the present application, the deviation controller 331 is internally configured with a deviation test strategy. The execution process of the deviation test strategy, as shown in Figure 6 , includes the following specific steps:

[0082] Step C1: Based on the deviation pointer dataset obtained from the current test, such as items indicating common-mode voltage deviation or neutral line current anomalies, retrieve a delay test task from a pre-defined delay analysis database. The delay analysis database stores test sequences for analyzing phase or time synchronization problems; these sequences typically involve introducing known or unknown delays between different test points. The delay test task includes detailed impedance test instructions, such as injecting a specific resistive load to observe the transient response, and a delay fitting algorithm.

[0083] Step C2: Accurately calculate the delay deviation between the two coupled identical phase power supplies under test using the delay fitting algorithm, such as a phase difference estimation algorithm based on Fast Fourier Transform (FFT) or a cross-correlation peak detection algorithm. Specifically, the delay fitting algorithm is implemented based on a phase difference estimation algorithm based on FFT or a cross-correlation peak detection algorithm. Regarding the phase difference estimation based on FFT, let the voltage waveforms of the two phase power supplies under test be u1(t) and u2(t). First, perform a Fast Fourier Transform on u1(t) and u2(t) to obtain their spectra U1(f) and U2(f). Calculate the phase spectra ∠U1(f) and ∠U2(f) based on the spectra. At a specific frequency f0, calculate the phase difference. Based on the relationship between phase difference and delay

[0084]

[0085] The delay deviation is calculated. Regarding the cross-correlation peak detection algorithm, the cross-correlation function of the two-phase power supply voltage waveforms is calculated. Find the peak position τ of the cross-correlation function peak The τ corresponding to this peak position peak This refers to the delay between the two waveforms. The calculated delay is compared with the standard delay to obtain the delay deviation. For example, if the standard delay is Δt0 and the calculated delay is Δt, then the delay deviation Δδ = |Δt - Δt0|.

[0086] The delay deviation can manifest as a phase difference between voltage or current waveforms, or a small time offset. Based on the calculated delay deviation, a delay correction command is generated and sent to the corresponding waveform delay sub-circuit 332. The waveform delay sub-circuit 332, according to this command, precisely delays or advances the waveform signal of one of the power supplies under test, typically at the microsecond or nanosecond level, thereby ensuring that the waveforms of the two power supplies under test have nearly identical phase at the dominant frequency or a specific harmonic frequency. This provides a unified and stable reference for subsequent precise deviation measurements, greatly improving the accuracy of the measurement results.

[0087] Step C3, based on the steady state of ensuring that the two-phase power waveforms under test have the same phase, the corresponding deviation test task is retrieved from the preset deviation test database according to the identified abnormal type, such as "neutral line drift", "ground current anomaly" or "phase-to-phase voltage imbalance". The deviation test task includes specific impedance test instructions. By executing these impedance test instructions respectively, the load impedance of the terminal under test is accurately changed, and the current signal of the terminal under test is collected by the current capture unit 302 under each load condition. According to the current signals under different loads, the impedance deviation characteristics of the terminal under test are generated. The impedance deviation characteristics can include detailed parameters of differential mode impedance and common mode impedance under different frequencies and load conditions, such as frequency response curve of common mode impedance or phase angle of differential mode impedance.

[0088] As a preferred embodiment of the present application, the core of the disorder capture strategy is a disorder capture network. The disorder capture network is a multi-layer feedforward neural network or a graph neural network, and its topology is composed of a plurality of disorder feature nodes. Disorder feature nodes are configured with disorder feature connections between them, which represent the interaction or information flow path between features, for example, a connection may represent the correlation between L1 phase current and L2 phase voltage. The preset combination of disorder feature nodes constitutes a disorder capture path, and each path aims to identify a specific disorder power quality anomaly pattern, such as "harmonic coupling caused by cross-phase voltage sag". Each disorder feature node is configured with a corresponding activation function, which is a nonlinear mapping used to calculate the corresponding disorder activation value. When the disorder activation value exceeds the corresponding activation function threshold, the disorder feature node is activated, indicating that the feature it represents has been detected. When all disorder feature nodes in a certain disorder capture path are activated, the corresponding disorder test data is generated according to the specific anomaly pattern represented by the disorder capture path, for example, explicitly indicating "L1 and L3 phase transient coupling, coupling strength 0.7".

[0089] The activation function is a composite function whose inputs include a reliability factor, an activation decay factor, a feature matching factor, and a correlation gain factor. The reliability factor reflects the degree of matching between the current out-of-order test feature and the out-of-order feature node; a higher value indicates a better match, calculated using methods such as cosine similarity or Euclidean distance. The activation decay factor reflects the number of out-of-order test features activated by other out-of-order feature nodes in the test context. Its function is to suppress widespread or non-specific anomalies and highlight anomalies from specific sources or regions. It may be calculated by dividing 1 by the square root of the number of activated nodes to achieve non-linear decay. The feature matching factor reflects the fine-grained matching between the out-of-order feature node and the current out-of-order test feature, possibly calculated using more complex feature space projection or kernel functions. The correlation gain factor reflects the number of other out-of-order feature nodes associated with the out-of-order feature node that are activated. Its function is to enhance the identification ability of anomaly patterns with synergistic effects; for example, if "neutral line drift" and "multiphase imbalance" are activated simultaneously, their correlation gain factors will mutually enhance each other. Through this sophisticated network structure and dynamic activation mechanism, the present invention can accurately identify power quality problems caused by multi-point interaction or cross-phase interference from complex out-of-order test characteristics, providing in-depth fault diagnosis capabilities.

[0090] In a preferred embodiment of the present invention, the deviation capture strategy includes the following specific steps:

[0091] Step c1: First, obtain an impedance test command with a purely resistive impedance type, for example, configure the electronic load 301 as a 10Ω purely resistive load. Then, perform a test using the deviation test circuit 330 to obtain the corresponding deviation impedance characteristics, such as the voltage-current phasor relationship and its difference between two identical phase power supplies under a purely resistive load. Based on this, calculate the resistive deviation value of the current test terminal using a resistive deviation test algorithm, such as an algorithm based on Ohm's law and least squares fitting. This resistive deviation value quantifies the common-mode or differential-mode deviation existing under purely resistive conditions, for example, the resistive component of the common-mode voltage. First, apply a known stable voltage U to the circuit under test and measure the current I through the resistor. Let the measured multiple sets of voltage and current data be (U1, I1), (U2, I2), ..., (U... n ,I n To improve measurement accuracy, the least squares fitting method is used. Let the estimated resistance be... The objective function is then

[0092] Solving this equation yields a least-squares estimate of the resistance.

[0093]

[0094] The calculated resistance value is then compared with the standard resistance value R0, and a resistive deviation value is calculated, for example, a resistive deviation value

[0095] Step c2, secondly, impedance test instructions of the impedance type of pure capacitive impedance are obtained, for example, the electronic load 301 is configured as a pure capacitive load with an equivalent capacitive impedance of 20 Ω. Subsequently, a test is performed by the deviation test circuit 330 to obtain the corresponding deviation impedance characteristics, for example, the transient current response under the pure capacitive load. On this basis, a capacitive deviation value is calculated by a capacitive deviation test algorithm. The specific parameters in the capacitive deviation test algorithm, for example, the initial value of the equivalent capacitive model or the convergence threshold of the iterative algorithm, are dynamically generated according to the resistive deviation value obtained in step c1. For example, if the resistive deviation value indicates that there is a significant neutral line grounding resistance, the capacitive deviation algorithm will take this resistance into account and correct its influence on the capacitive response, so as to ensure that the capacitive deviation analysis is performed in the context of the known resistive deviation, greatly improving the accuracy and consistency of the analysis. The capacitive deviation test algorithm uses some parameters in the resistive deviation value generation algorithm to calculate the capacitive deviation value. First, based on the basic formula of capacitance

[0096]

[0097] In an alternating current circuit, the capacitive reactance of a capacitor is

[0098]

[0099] where f is the frequency of the alternating current signal and C is the capacitance value. By measuring the voltage U across the capacitor and the current I through the capacitor, the capacitive reactance Xc can be calculated as

[0100]

[0101] Some parameters obtained by the resistive deviation test algorithm are used, such as the signal frequency f (which remains unchanged during the test), and other known parameters related to the circuit. Let the frequency-related parameter obtained by the resistive deviation test algorithm be k (for example, in some circuit models, k may be related to the characteristics of the signal source), then the capacitance value C can be calculated according to the formula

[0102]

[0103] where Xc is the capacitive reactance C The calculated capacitance value is then compared with the standard capacitance value C0, and a capacitive deviation value is calculated, for example, a capacitive deviation value ΔC = |C - C0|. In the specific calculation process, it may be necessary to filter the measurement data to remove noise interference and improve the accuracy of the calculation.

[0104] Step c3, again, obtain the impedance test instruction of the impedance type of pure inductive impedance, for example, configure the electronic load 301 as a pure inductive load with an equivalent inductive reactance of 30 Ω. Then, test through the deviation test circuit 330 to obtain the corresponding deviation impedance characteristics, for example, the current rate of change under the pure inductive load. On this basis, calculate the inductive deviation value through the inductive deviation test algorithm. The specific parameters in the inductive deviation test algorithm, such as the initial value of the equivalent inductance model or the adjustment factor of the resonance frequency, are dynamically generated according to the inductive deviation value obtained in step c3. For example, if it is known that there is an inductive resonance at a certain frequency, the algorithm can adjust its measurement window or injection frequency, which ensures that the inductive deviation analysis is carried out in the background of the known inductive deviation, further optimizing the accuracy of the analysis. The inductive deviation test algorithm generates algorithm parameters according to the inductive deviation value to calculate the inductive deviation value. In an inductive circuit, the inductive reactance X L of the inductor is X L = 2πfL, where L is the inductance value. First, an alternating voltage U is applied across the inductor, and the current I passing through the inductor is measured, thereby obtaining the inductive reactance

[0105]

[0106] For the determination of the initial value of the equivalent inductance model and the adjustment factor of the resonance frequency, the following method can be used: assuming that the initial estimated value L0 of the inductor is known, the inductance value is adjusted by measuring the response of the circuit at different frequencies using the resonance characteristics. Let the resonance frequency of the circuit be f0, and according to the resonance condition X C (in a series resonance circuit), that is,

[0107]

[0108] , the relationship between the inductance and the capacitance, the resonance frequency can be obtained. By changing the capacitance value or measuring different resonance frequencies, combined with the known capacitance value C, the inductance value

[0109]

[0110] In actual calculation, it may be necessary to consider factors such as parasitic parameters in the circuit to correct the calculation result. For example, introduce a correction coefficient α, then the final inductance value L′ = αL. Then, compare the calculated inductance value with the standard inductance value L std , and calculate the inductive deviation value, such as the inductive deviation value ΔL = |L′-L std |.

[0111] Step c4, generate a complex impedance parameter by comprehensive analysis of the calculated resistive deviation value, capacitive deviation value and inductive deviation value in steps c1, c2 and c3. The complex impedance parameter can be a vector containing equivalent impedance modulus, phase angle and harmonic impedance characteristics at different harmonic frequencies. According to the complex impedance parameter, intelligently configure the corresponding impedance test instruction, which aims to simulate more complex actual complex load conditions, for example, RLC combination load containing nonlinearity, impact or dynamic change. Then, execute the complex impedance test instruction through the deviation test circuit 330, and calculate the complex impedance deviation value through the complex impedance deviation test algorithm, such as the algorithm based on nonlinear system identification or frequency domain parameter estimation, which comprehensively reflects the power quality deviation under complex load conditions, especially various problems sensitive to system impedance changes. The complex impedance deviation test algorithm is realized based on nonlinear system identification or frequency domain parameter estimation. In terms of nonlinear system identification, first, establish a nonlinear model of the circuit, for example, for a circuit containing nonlinear elements (such as diodes, thyristors, etc.), segmented linearization or neural network can be used for modeling. Taking segmented linearization as an example, the characteristic curve of the nonlinear element is divided into several segments, and each segment is approximated by a linear model. Let the input of the circuit be the voltage u(t) and the output be the current i(t), by measuring multiple sets of input and output data (u1(t), i1(t)), (u2(t), i2(t)), …, (u n (t),i n (t)) of the circuit, the model parameters are identified by using least squares method, etc. In terms of frequency domain parameter estimation, different frequency sinusoidal excitation signals are applied to the circuit, and the response is measured. Let the excitation signal be u(t) = A sin(2πft), and the measured response current be i(t). By Fourier transform, the time domain signal is converted into frequency domain signal, and the voltage frequency domain signal U(f) and the current frequency domain signal I(f) are obtained. Then the complex impedance

[0112]

[0113] By analyzing the complex impedance at different frequencies, the parameters of the circuit, such as resistance, inductance, capacitance, etc. are estimated. Compare the estimated parameters with the standard values, and calculate the complex impedance deviation value. For example, let the standard complex impedance be Z std (f), and the calculated complex impedance be Z(f), then the complex impedance deviation value can be represented as ΔZ(f) = |Z(f)-Z std (f)|.

[0114] Step c5, finally, the resistive deviation value, the capacitive deviation value, the inductive deviation value and the complex impedance deviation value obtained in steps c1, c2, c3 and c4 are integrated to generate the deviation test data. The deviation test data is a multi-dimensional vector or matrix, which comprehensively describes the power quality deviation of the power supply under different impedance characteristics, especially the influence of common-mode interference, unbalance phenomenon and high-frequency noise on the system impedance, and provides a comprehensive and accurate quantitative basis for power grid diagnosis.

[0115] As a preferred embodiment of the present application, the core of the condition simulation test circuit 340 is an analog controller 341. The analog controller 341 is internally configured with a normal fitting database and a power supply control strategy. The implementation process of the power supply control strategy is as follows: first, the pseudo-state test data, the disorder test data and the deviation test data are preprocessed. For example, the waveform data in the pseudo-state test data is denoised, and methods such as wavelet transform can be used to remove noise interference. Let the pseudo-state test data be D mimic , the disorder test data be D shuffle , and the deviation test data be D bias . Then, the preprocessed data is fused to generate a test fitting vector. Assuming that the weighted average method is used for fusion, let the weights be w1, w2 and w3, then the test fitting vector V = w1D mimic +w2D shuffle +w3D bias . The power supply control instruction is obtained from the normal fitting database according to the test fitting vector. The normal fitting database pre-stores the corresponding relationship between different test fitting vectors and power supply control instructions, and the corresponding power supply control instruction is obtained by looking up the matching vector. For example, the database stores the records (V1, C1), (V2, C2), …, (V n , C n ). By comparing the similarity of the test fitting vector V and V i , the most matched V j is found, and the corresponding power supply control instruction is C jThe normal fitting database is stored in a high-speed memory in the form of a high-dimensional lookup table or a multi-dimensional array, and a large number of carefully optimized and calibrated power control instructions are stored in the internal storage. Each instruction is indexed by a unique test fitting vector. The power control instructions include precise voltage amplitude, frequency, phase, waveform shape, and duration, etc. Key parameters for millisecond-level accurate control of the output of the controllable power supply 400. The power control strategy is a highly complex decision-making algorithm that generates the test fitting vector by comprehensively analyzing and intelligently processing the normal test data, the random test data, and the deviation test data. The test fitting vector is a condensed representation of the characteristics of the three types of test data, and its dimension and value range are strictly standardized to facilitate indexing and matching. Once the test fitting vector is generated, the power control strategy uses the vector as an index to quickly obtain the corresponding power control instructions from the pre-set normal fitting database, thereby achieving intelligent and dynamic control of the controllable power supply 400, enabling it to accurately simulate or compensate for various complex power quality problems in the power grid, such as actively injecting compensation harmonics or simulating voltage sags.

[0116] As a preferred embodiment of the present application, the execution process of the condition simulation strategy includes the following specific steps as shown in the following table: Figure 7

[0117] Step d1, by calibrating the constraint conditions, such as based on high-precision phase-locked loop or advanced digital phase-locked loop technology, the output time of the controllable power supply 400 is calibrated to sub-microsecond level, so that the output waveform of the controllable power supply 400 has the same phase as the waveform of the power supply to be tested received by the three-phase test interface 100. This step ensures the absolute synchronization of the controllable power supply 400 with the power grid when actively injecting disturbances, effectively avoiding the introduction of additional phase errors, thereby ensuring the accuracy and controllability of active testing. The calibration accuracy can reach sub-degree level.

[0118] Step d2, by a pre-set current integral algorithm, such as a high-precision numerical integral algorithm based on Simpson's rule or trapezoidal rule, the envelope area of the current waveform captured by the condition simulation test circuit 340 is calculated. The envelope area refers to the instantaneous absolute value integral of the current waveform with respect to its zero axis or average value, which reflects the instantaneous change of waveform energy. By comparing the envelope areas of different time periods, an envelope difference waveform is generated, which accurately reflects the fluctuation or abnormality of the current waveform amplitude or energy in a certain time domain, such as the current instantaneous increase caused by load impact.

[0119] ​Step d3, according to the preset envelope feature classification library, the classification library stores various pre-defined envelope anomaly pattern feature templates, such as pulse type, sudden drop type, intermittent type or oscillation type envelope, and their typical features in the frequency domain and time domain. The envelope difference waveform obtained in step d2 is divided into several different types of envelope difference sub-waves. The classification process can use pattern recognition techniques such as cluster analysis, principal component analysis or lightweight neural networks to identify representative abnormal envelope features, such as distinguishing envelope mutations caused by starting current from envelope periodic fluctuations caused by motor oscillation.

[0120] Step d4, according to the preset phase range, such as 0-90 degrees, 90-180 degrees, 180-270 degrees, 270-360 degrees, etc., the envelope difference sub-waves obtained in step d3 are subjected to fine cluster analysis by cluster analysis algorithms such as KK-means or DBSCAN algorithm. This step aims to obtain envelope anomaly difference clusters in different phase ranges, thereby revealing the regularity or concentration of power quality anomalies occurring at specific phase points. Each cluster represents a group of abnormal events with similar envelope features within a specific phase range, for example, a cluster may represent transient spikes occurring near the voltage zero point.

[0121] Step d5, according to the envelope anomaly difference clusters obtained in step d4, the corresponding simulation anomaly sub-data is retrieved from the preset simulation anomaly sub-database. The simulation anomaly sub-database stores typical power quality problem models related to different envelope anomaly clusters, for example, a three-phase short circuit model or a heavy load start model may be associated with a "voltage sudden drop cluster". These simulation anomaly sub-data are intelligently integrated and assembled to finally generate the simulation test data. The simulation test data is a complete quantitative description of the dynamic behavior of power quality problems under specific phase and load conditions, which can be used for subsequent fault diagnosis, system optimization, device compatibility evaluation or system immunity testing, providing quantitative basis for power grid performance improvement.

[0122] Embodiment, in a specific embodiment, the power quality tester proposed in the present application is used to perform in-depth power quality diagnosis on two independent three-phase power supply feeders in an industrial park, the goal is to identify and quantify common mode noise and cross-feeder harmonic interaction problems caused by non-linear loads and frequent start / stop devices.

[0123] First, connect the two three-phase test interfaces 100 of the power quality tester to the L1, L2, L3 phases and N line of feeder A and feeder B respectively. The test process is started according to the preset test task sequence.

[0124] Phase one: analog load test

[0125] The switching selection module 200 first connects the L1 and L2 phase lines of feeder A to the pseudo-state load test circuit 310. The pseudo-state controller 311 dynamically adjusts the electronic load 301 according to the pseudo-state test task sequence. The task sequence includes:

[0126] Pure resistive simulation: The electronic load simulates a 100Ω pure resistor for 100ms. The current capture unit 302 collects the current waveform, and the pseudo-state controller 311 calculates the pseudo-state abnormal value, finding that the current waveform contains slight 3rd and 5th harmonic distortion.

[0127] Pure inductive simulation: The electronic load simulates a 200mH pure inductor for 100ms. The waveform is collected again, and the pseudo-state abnormal value shows that the current lags the voltage by about 80 degrees, and the high harmonic content increases.

[0128] Nonlinear simulation: The electronic load simulates a typical rectifier load for 500ms. At this time, the pseudo-state abnormal value increases significantly, the current waveform distortion rate reaches 25%, and obvious current spikes and voltage sags are found. The pseudo-state controller dynamically adjusts the subsequent simulation parameters, such as increasing the peak current of the simulated load to be closer to the actual value.

[0129] During the execution of the pseudo-state capture strategy:

[0130] Step a1: The pseudo-state controller 311 compares the collected nonlinear load current waveform with the abnormal waveform feature library, and identifies pseudo-state waveform features such as "current spikes", "voltage sags", and "harmonic distortion".

[0131] Step a2: Mark the state abnormal values such as THDi=25% and voltage sag amplitude 10% on the above features, and perform pseudo-state correlation modeling. Generate an abnormal pointing data set containing "there is a serious nonlinear harmonic source between the L1-L2 phases of feeder A" and "there is a risk of transient voltage sag in feeder A".

[0132] Step a3: Split the abnormal pointing data set. Since "nonlinear harmonic source" may be related to cross-phase or cross-feeder interaction, part of the data is assigned to the disorderly pointing data set. While "transient voltage sag" may be more related to the load characteristics within a single feeder, part of the data is assigned to the bias pointing data set.

[0133] Phase two: disorderly test

[0134] The switching selection module 200 connects the L1 phase line of feeder A and the L2 phase line of feeder B to the disorderly test circuit 320 according to the indication of the disorderly pointing data set.

[0135] Step Bl: The out-of-order controller 321 retrieves reliability test tasks from the reliability analysis database according to the out-of-order pointing dataset, including injecting a preset intermittent composite load between two feeders and configuring the reliability collection window to 10 ms, focusing on the load switching moment.

[0136] Step B2: The out-of-order controller 321 obtains the reliability window current waveform by injecting the load. Through the reliability anomaly analysis algorithm, it is found that there is a significant current amplitude and phase difference between feeder A L1 phase and feeder B L2 phase at a certain transient moment, and the reliability sub-ratio is calculated, and the reliability anomaly value is calculated. For example, it is found that the 7th harmonic of feeder A L1 phase has a reliability anomaly value of 0.6 with feeder B L2 phase on the harmonic spectrum, indicating strong correlation.

[0137] Step B3: According to the reliability anomaly value, it is identified that "there is moderate harmonic interaction between feeder A L1 phase and feeder B L2 phase". New switching control information is generated, indicating that the subsequent test needs to focus on the interaction of the two phases.

[0138] Step B4: According to the identified anomaly type, the out-of-order test task is retrieved from the out-of-order test database, and the out-of-order comparison sub-algorithm is configured to calculate the out-of-order test features of the two phases. The result shows that the current cross-correlation coefficient of the two phases is 0.88 and the phase difference is 15 degrees at the 7th harmonic frequency, confirming the significant harmonic coupling.

[0139] Phase three: deviation test

[0140] The switching selection module 200 connects the L1 phase line of feeder A and the L1 phase line of feeder B to the deviation test circuit 330, and focuses on the common mode voltage.

[0141] Step Cl: The deviation controller 331 obtains the delay test task from the delay analysis database according to the delay pointing dataset.

[0142] Step C2: Through the delay fitting algorithm, the delay deviation between feeder A L1 and feeder B L1 is calculated. For example, it is found that feeder B L1 has a phase lag of 50 microseconds relative to feeder A L1. The delay correction instruction is sent to the waveform delay sub-circuit 332, and one of the waveform signals is advanced by 50 microseconds to ensure that the two phases are in phase during measurement.

[0143] Step C3: On the basis of phase synchronization, resistive, capacitive, and inductive load tests are performed in turn, and current signals are collected.

[0144] Pure resistive load: the common mode voltage is measured to be 0.5 Vrms, and the common mode current is 50 mArms. The resistive deviation value is 0.02.

[0145] Pure capacitive load: measured common-mode voltage at 0.8 Vrms, common-mode current at 80 mA rms. Capacitive deviation value is 0.035.

[0146] Pure inductive load: measured common-mode voltage at 0.7 Vrms, common-mode current at 70 mA rms. Inductive deviation value is 0.03.

[0147] Step C4: integrating all the deviation values, composite impedance parameters are calculated, and it is found that the common-mode impedance at 50 Hz is 10 Ω, but rises to 50 Ω at the 3rd harmonic frequency. According to this parameter, a composite impedance test is performed, injecting an impedance simulating a nonlinear rectifier load, and the composite impedance deviation value is measured to be 0.045, indicating that the common-mode problem is more significant under complex loads.

[0148] Step C5: integrating all the deviation values, deviation test data is generated, and the amplitude, frequency characteristics of the common-mode voltage between the two feeders, and the response under different loads are quantified, indicating that the main source of the common-mode problem is high-frequency noise and load imbalance.

[0149] Of course, the above is only a typical example of the present application, and in addition, the present application can have many other specific embodiments, and any technical solutions formed by equivalent substitution or equivalent transformation fall within the scope of the present application.

Claims

1. A power quality tester, characterized in that, It includes at least two three-phase test interfaces for coupling to an external three-phase power supply under test, and also includes a switching selection module, a test circuit array group, and a controllable power supply; The switching selection module is coupled to the three-phase test interface at one end and to the test circuit array group at the other end. The switching selection module is used to connect the power supply terminal of the three-phase test interface to different test circuits. The test circuit array group includes a mimic load test circuit, an out-of-order test circuit, a deviation test circuit, and a condition simulation test circuit. Each test circuit is equipped with an electronic load and a current capture unit. The mimic load test circuit is coupled to two power terminals of different phases that belong to the same three-phase test interface. It controls the electronic load according to the mimic test task to configure the load state of the circuit, and the preset mimic capture strategy generates mimic test data through the information generated during the test. The out-of-order test circuit is coupled to the power terminals of two different phases that do not belong to the same three-phase test interface. It generates out-of-order test tasks based on the mimicry test data, and controls the electronic load to configure the load state of the circuit based on the out-of-order test tasks. It generates out-of-order test data based on the information generated during the test using a preset out-of-order capture strategy. The deviation test circuit is coupled to the power supply terminals of two test terminals of the same phase but not belonging to the same three-phase test interface. It generates a deviation test task based on the mimicry test data, and controls the electronic load to configure the load state of the circuit according to the deviation test task. It generates deviation test data based on the information generated during the test using a preset deviation capture strategy. The conditional simulation test circuit has one input terminal coupled to a controllable power supply and another input terminal coupled to the power supply terminal of a three-phase test interface. It generates conditional simulation test tasks based on out-of-order test data and generates power control commands based on deviation test data. It configures the corresponding electronic load through the conditional simulation test tasks and controls the corresponding controllable power supply through the power control commands to control the circuit operation. It generates simulation test data based on the information generated during the test using a preset conditional simulation strategy.

2. The power quality tester as described in claim 1, characterized in that: The switching selection module includes a switching transition unit, an instruction execution unit, and a relay sorting group. The switching transition unit includes a current protector, a voltage protector, and a disturbance filter. The instruction execution unit is configured to receive switching control information to generate switching control instructions. The relay sorting group includes several relays, which operate according to the switching control instructions to connect external three-phase power supplies under test to different test units.

3. The power quality tester as described in claim 1, characterized in that: The mimicry load circuit includes a mimicry controller, which is coupled to an electronic load and a current capture unit. The mimicry controller is configured with a mimicry control strategy, which includes... Step A1: Retrieve the corresponding test task sequence from the preset mimicry test table according to the test input information. The test task sequence includes impedance simulation instructions set in sequence. Step A2: Obtain the test current waveform through the current capture unit; Step A3: Calculate the mimicry anomaly value of the current waveform using a preset static feedback algorithm, generate correction parameters based on the mimicry anomaly value to adjust the impedance simulation instructions of the next sequence, and return to step A2 until all impedance simulation instructions have been completed.

4. The power quality tester as described in claim 3, characterized in that: The mimicry capture strategy includes Step a1: An abnormal waveform feature library is configured, which stores several abnormal waveform features. The obtained current waveform is compared with the abnormal waveform feature library to extract the corresponding mimicry waveform features. Step a2: Mark the corresponding abnormal state values ​​on the mimicry waveform features and input them into the preset mimicry association model to obtain the abnormality pointing dataset. The abnormality pointing dataset includes abnormality pointing items and corresponding abnormality reliability values. The abnormality pointing items reflect the abnormality type of the target phase current waveform. Step a3: Split the abnormal pointing dataset into an out-of-order pointing dataset and a deviation pointing dataset to generate the mimicry test data.

5. A power quality tester as described in claim 4, characterized in that: The out-of-order test circuit includes an out-of-order controller, and the deviation test circuit is configured with a deviation controller and a waveform delay sub-circuit. The out-of-order controller is configured with an out-of-order test strategy, and the out-of-order test strategy includes... Step B1: Retrieve the corresponding reliable test task from the preset reliability analysis database according to the disordered dataset of the current test. The reliable test task includes an impedance test command and a reliable acquisition window. The reliable acquisition window is used to configure the acquisition window of the current acquisition unit to obtain the reliable window current waveform. Step B2: Analyze the reliable anomaly items of the reliable window current waveform using a reliable anomaly analysis algorithm to obtain the corresponding reliable sub-proportion of the test terminal, and calculate the reliable anomaly value corresponding to each anomaly type using the reliable sub-proportion. The reliable anomaly value reflects the correlation between the test terminal and the anomaly type. Step B3: Multiple reliable anomaly quantization ranges are configured. For each anomaly type, the reliable anomaly value is marked according to the reliable anomaly quantization range it falls into. The test end is then recombined according to the preset combination difference conditions to generate new switching control information. Step B4: Retrieve the corresponding out-of-order test task from the preset out-of-order test database according to the anomaly type. The out-of-order test task includes impedance test instructions and out-of-order comparison sub-algorithms. Configure the corresponding out-of-order comparison sub-algorithms through reliable outlier values, and process the current waveform according to the out-of-order comparison sub-algorithms to generate out-of-order test characteristics of the terminal under test.

6. The power quality tester as described in claim 5, characterized in that: The deviation controller is configured with a deviation testing strategy, which includes: Step C1: Obtain a delay test task from a preset delay analysis database based on the deviation of the current test dataset. The delay test task includes an impedance test instruction and a delay fitting algorithm. Step C2: Calculate the delay deviation between the two phases of the power supply under test using a delay fitting algorithm, and generate a delay correction command based on the delay deviation to configure the corresponding waveform delay sub-circuit so that the waveforms of the two power supplies under test have the same phase. Step C3: Retrieve the corresponding deviation test task from the preset deviation test database according to the anomaly type. The deviation test task includes an impedance test instruction, and generates the impedance deviation characteristics of the test terminal by collecting the current signal of the test terminal under different types of impedance.

7. A power quality tester as described in claim 6, characterized in that: The out-of-order capture strategy is configured with an out-of-order capture network, which includes several out-of-order feature nodes. These nodes are connected by out-of-order feature lines and form out-of-order capture paths using preset combinations. Each out-of-order feature node is configured with a corresponding activation function. The activation function calculates a corresponding out-of-order activation value. When the out-of-order activation value exceeds the corresponding activation function threshold, the out-of-order feature node is activated. When all out-of-order feature nodes in a certain out-of-order capture path are activated, corresponding out-of-order test data is generated based on the out-of-order capture path. The activation function includes a reliability factor, an activation decay factor, a feature matching factor, and a correlation gain factor. The reliability factor reflects the degree of matching between the out-of-order test feature and the test device. The activation decay factor reflects the number of out-of-order test features activated by other out-of-order feature nodes in the test device. The feature matching factor reflects the degree of matching between the out-of-order feature node and the out-of-order test feature. The correlation gain factor reflects the number of other out-of-order feature nodes associated with the out-of-order feature node that are activated.

8. A power quality tester as described in claim 7, characterized in that: The deviation capture strategy includes Step c1: Obtain the impedance test command with the impedance type of resistive impedance and perform the test to obtain the corresponding deviation impedance characteristics, and calculate the resistive deviation value through the resistive deviation test algorithm. Step c2: Obtain an impedance test command with capacitive impedance type and perform the test to obtain the corresponding deviation impedance characteristics, and calculate the capacitive deviation value through the capacitive deviation test algorithm. The parameters in the capacitive deviation test algorithm are generated based on the resistive deviation value. Step c3: Obtain an impedance test command with inductive impedance type and perform the test to obtain the corresponding deviation impedance characteristics, and calculate the inductive deviation value through the inductive deviation test algorithm. The parameters of the inductive deviation test algorithm are generated based on the inductive deviation value. Step c4: Generate composite impedance parameters using resistive deviation, capacitive deviation, and inductive deviation values; configure corresponding impedance test commands based on load impedance parameters; and calculate composite impedance deviation values ​​using the composite impedance deviation test algorithm. Step c5: Generate the deviation test data based on the resistive deviation value, capacitive deviation value, inductive deviation value, and composite impedance deviation value.

9. A power quality tester as described in claim 8, characterized in that: The conditional simulation test circuit includes an analog controller, which is configured with a normal fitting database and a power control strategy. The normal fitting database stores power control instructions, which are indexed by a test fitting vector. The power control strategy generates the test fitting vector using mimicry test data, disordered test data, and deviation test data, and retrieves the corresponding power control instructions from the preset normal fitting database based on the test fitting vector.

10. A power quality tester as described in claim 9, characterized in that: The conditional simulation strategy includes Step d1: Calibrate the output time of the controllable power supply by calibrating the constraint conditions to ensure that the output of the controllable power supply and the terminal under test have the same phase; Step d2: Calculate the envelope area of ​​the captured current waveform using a preset current integration algorithm to generate an envelope difference waveform; Step d3: Divide the envelope difference waveform into several different types of envelope difference sub-wavelengths according to the preset envelope feature classification library; Step d4: Based on the phase range, perform cluster analysis on the obtained envelope difference wavelet using a cluster analysis algorithm to obtain envelope anomaly difference clusters under different phase ranges; Step d5: Retrieve the corresponding simulated anomaly sub-data based on the envelope anomaly difference cluster to generate simulated test data.

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