A semiconductor device capacitance voltage testing system and method

Abstract

The application belongs to the technical field of electronic measurement, and discloses a semiconductor device capacitance voltage test system and method. The power supply circuit based on the combination of high-frequency PWM voltage increase and symmetrical topology voltage multiplier chain is used to solve the bottleneck problem that the existing portable device is difficult to efficiently generate a wide range of symmetrical bipolar high-voltage bias in a compact volume. The differential pulse width modulation measurement circuit based on AC / DC isolation is used to inject measurement pulses with opposite phases and perform differential sampling, so as to solve the problem that the existing single-ended measurement method is extremely sensitive to common-mode noise and ground line interference, resulting in low reliability in the field environment, and improve the measurement accuracy and stability. The software timing control method based on dynamic output baseline correction is proposed, and the intelligent sequence of stabilization-evaluation output baseline-measurement-compensation is used at each bias point to solve the slow response phenomenon existing in the existing method.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic measurement, and particularly relates to a semiconductor device capacitance-voltage (CV) test system and method, which is suitable for characterizing the electrical properties of semiconductor devices and materials. BACKGROUND

[0002] Capacitance-voltage (CV) test is a basic and extremely important analysis method in the characterization of physical properties of semiconductor devices and materials. By accurately measuring how the capacitance value of a device (such as a MOS capacitor or a transistor structure) changes with the DC bias voltage applied across it, a series of key physical and electrical parameters such as semiconductor doping type and concentration distribution, oxide layer thickness, flat band voltage, threshold voltage, and semiconductor-insulator interface trap state density can be non-destructively extracted. Therefore, CV test plays an indispensable role in semiconductor process development and monitoring, device reliability evaluation and failure analysis, and research on new electronic materials, and has been highly valued by academia and industry for a long time.

[0003] At present, high-precision CV test tasks are still largely limited to professional laboratory environments and are heavily dependent on large and complex benchtop semiconductor parameter analyzers produced by international leading instrument manufacturers such as Keysight (Agilent), Keithley (Keithley), etc. Although such equipment has excellent performance, its large size, high price and complex operation make it difficult to meet the growing demand for portability, such as rapid process control and quality monitoring (In-situ Process Control) on semiconductor production lines, or timely fault diagnosis and failure analysis on site. Therefore, developing a truly portable CV test system that integrates a wide range of high-voltage bias sources and high-precision capacitance measurement functions has become a technical direction that needs to be solved and has important application value in the field.

[0004] Although there have been academic explorations and prototype designs for portable CV systems in recent years, there are still no mature commercial products that can fully meet the needs of industrial applications. In order to break through the limitations of traditional AC LCR bridges in terms of integration and cost, some advanced technical solutions have begun to shift to measurement methods based on pulse charging timing. The core principle is to apply a small voltage step pulse to the measured capacitor based on a known DC bias voltage, and by accurately measuring the time required for the capacitor to charge from the step start voltage to a certain preset threshold voltage, the capacitance value is then inferred. However, to fully and reliably implement this technical path in a portable system, there are still three interrelated core technical challenges:

[0005] Firstly, the generation of high voltage bias and its symmetry are key challenges. The full characterization of a device often requires bipolar bias voltage as high as tens of volts or even hundreds of volts (e.g. ±90V) to explore its full characteristics in depletion, inversion and accumulation regions. In portable devices with strict limitations on volume and power consumption, traditional power frequency transformers are excluded due to their inherent bulkiness and inefficiency. While the conventional DC boost circuit can efficiently generate a positive high voltage, it usually requires a separate and complex circuit to generate a negative high voltage that is strictly symmetrical and performance-matched to the positive high voltage, greatly increasing the complexity, cost and volume of the design, making it difficult for existing solutions to economically and efficiently cover a wide range of bipolar bias requirements under small size conditions.

[0006] Secondly, the anti-interference ability of the measurement method is poor. The device inevitably works in a complex electromagnetic environment in factories, fields and other places. The traditional single-ended pulse timing scheme directly references the system ground, so it is extremely sensitive to power supply noise, ground potential fluctuations and external coupled common-mode interference. Even microvolt-level noise disturbances can be amplified during the charging timing process, causing significant deviations in the measurement results, which restricts its reliability and repeatability in real industrial environments.

[0007] Finally, there is still a lack of accurate characterization means for slow physical processes. Many key degradation mechanisms in semiconductor devices, such as slow trap effects in insulating layers and capture and release processes of semiconductor-insulator interface charges, have response time constants usually falling within the time scale of milliseconds to seconds. If fixed hardware timing is used to pursue measurement speed, the pulse charging timing method is essentially a fast measurement, with a measurement time window (usually in the order of microseconds) much smaller than the response time of these slow processes, so it cannot provide sufficient response and equilibrium time, resulting in an inability to accurately capture the real impact of these effects on the device capacitance.

[0008] Overall, the pulse charging timing method provides a new technical direction for breaking through the limitations of traditional AC measurement methods, but existing designs are mostly based on simple single-ended injection comparator timing circuits. While such schemes are simple in structure, they have systematic shortcomings in high voltage power generation, measurement anti-interference ability and slow response process characterization in the three core aspects. These challenges together have resulted in the fact that a truly functional and complete portable high voltage CV test system has not yet matured. SUMMARY

[0009] The application aims to provide a semiconductor device capacitance voltage test system, which solves the bottleneck problem of traditional schemes in generating a wide range of symmetrical bipolar bias in a portable volume by providing a Boost-voltage multiplication power supply circuit based on high-frequency switching conversion and symmetrical topology voltage multiplication chain, efficiently and compactly converting low-voltage DC input into symmetrical ±90V high-voltage rails, and solving the problem of low reliability and easy interference of existing single-ended measurement methods in the field environment by constructing a differential pulse width modulation measurement circuit, converting the measured capacitance value into the pulse width of a differential square wave signal, and finally demodulating it into an analog voltage, thereby suppressing common-mode noise and ground interference from the hardware architecture.

[0010] In order to achieve the above-mentioned purpose, the application adopts the following technical solutions:

[0011] A semiconductor device capacitance voltage test system comprises a low-voltage power supply circuit, a Boost-voltage multiplication power supply circuit, an MCU, a high-voltage bias control circuit, an AC / DC isolation circuit, and a differential pulse width modulation measurement circuit.

[0012] The low-voltage power supply circuit provides an initial low-voltage power supply for the entire system.

[0013] The Boost-voltage multiplication power supply circuit is used to receive the low-voltage DC input of the low-voltage power supply circuit and generate a pair of stable, symmetrical, and isolated high-voltage bipolar power rails as the power rails of the high-voltage operational amplifier circuit.

[0014] The high-voltage bias control circuit comprises a signal processing circuit and a high-voltage operational amplifier circuit.

[0015] The MCU outputs a low-voltage control signal according to a preset scanning program through its built-in dual-channel DAC.

[0016] After the low-voltage control signal is subjected to polarity conversion and buffering by the signal processing circuit, it is linearly amplified by the high-voltage operational amplifier circuit and applied to the DUT in the form of differential DC bias voltage from -90V to +90V through the AC / DC isolation circuit.

[0017] At each stable DC bias point, an AC measurement pulse is coupled to the DUT, and the capacitance response of the DUT is captured by the differential pulse width modulation measurement circuit and converted into a signal whose pulse width is monotonically related to the capacitance value.

[0018] The signal is finally fed back to the input end of the MCU, and the real capacitance value is calculated by the MCU.

[0019] The real capacitance value obtained by calculation is paired with the current DC bias voltage to generate a CV curve point by point.

[0020] In addition, based on the above system, the application further provides a software timing control method based on dynamic output baseline correction, aiming at solving the contradiction between slow response and effective leakage current suppression in the existing measurement method.

[0021] The method is realized by an intelligent sequence of "stabilization, evaluation of output baseline, measurement and compensation" at each bias point.

[0022] A semiconductor device capacitance voltage test method, the method comprising the following steps:

[0023] Step 1. Bias application and system stabilization;

[0024] A target DC bias voltage is applied to the capacitor DUT to be tested through a high-voltage bias control circuit, wherein the DC bias voltage is applied to the DUT only through an AC-DC isolation circuit; after applying the DC bias voltage, the MCU waits for a preset time to allow the slow physical process inside the DUT to fully respond and reach quasi-static equilibrium;

[0025] Step 2. Baseline error evaluation and measurement signal acquisition;

[0026] The MCU acquires the DC analog voltage signal U_adc output by the analog signal conditioning front-end circuit AFE after the waiting is over; the MCU analyzes the U_adc signal to evaluate the equivalent baseline offset U_offset_measured caused by slow response contained therein;

[0027] U_offset_measured represents the DC offset in the AFE output caused by slow response non-ideal factors;

[0028] The MCU further acquires the U_adc signal to obtain the raw ADC sampling value ADC_measured_raw;

[0029] Wherein, ADC_measured_raw represents the uncorrected raw ADC sampling value, and ADC_measured_raw contains the output generated jointly by the capacitance information and the equivalent baseline offset U_offset_measured;

[0030] Step 3. Software algorithm compensation;

[0031] The MCU calculates a correction factor K_adc_compensated, which represents a correction factor for compensating the ADC sampling value; wherein K_adc_compensated is proportional to the equivalent baseline offset U_offset_measured;

[0032] MCU uses K_adc_compensated to correct ADC_measured_raw, and obtains the real ADC sampling value excluding the influence of non-ideal factors: ADC_true = ADC_measured_raw - K_adc_compensated;

[0033] Wherein, ADC_true represents the ADC sampling value after correction, reflecting the DUT capacitance information;

[0034] Step 4. Capacitance calculation of the measured capacitor:

[0035] MCU inverses the theoretical DC voltage U0_compensated output by the DPWM core according to the transfer function U_adc = M × U0 + N of the AFE, and obtains ADC_true: U0_compensated = (ADC_true - N) / M;

[0036] Wherein, U0_compensated represents the compensated DPWM core output voltage obtained by AFE inversion; N represents the bias constant of AFE, and M represents the gain coefficient of AFE; U0 represents the compensated voltage.

[0037] MCU substitutes U0_compensated into the theoretical model of the DPWM core, and the formula is as follows:

[0038] U0 = U_high ×( (Cdut - C_ref) / (Cdut + C_ref) );

[0039] Wherein, U_high represents the charging high level of the DPWM core; Cdut represents the capacitance value of the DUT, and C_ref represents the known calibration value of the fixed reference capacitor C2, and the capacitance value Cdut of the DUT is calculated according to the above formula;

[0040] MCU calculates the normalized intermediate variable X:

[0041] X = U0_compensated / U_high;

[0042] Wherein, X represents the normalized ratio of U0_compensated to U_high;

[0043] MCU obtains the capacitance value of the DUT through algebraic operation, and the formula is as follows:

[0044] Cdut = C_ref× (1 + X) / (1 - X);

[0045] Step 5. Data storage and iteration;

[0046] The MCU stores the Cdut value paired with the current target DC bias voltage, and iteratively performs the above steps 1-5 to complete the C-V characteristic curve measurement within the preset bias range.

[0047] The present application has the following advantages:

[0048] As described above, the present application relates to a semiconductor device capacitance voltage test system and method. In terms of system composition, the present application proposes a high voltage generation circuit based on Boost conversion and symmetrical voltage multiplier chain (i.e. Boost-voltage multiplier power supply circuit), which is a power supply circuit combined by two sets of symmetrical topology Cockcroft-Walton voltage multiplier chain driven by high-frequency boost type switch converter U23 (ADP1612ARMZ-R7). The circuit uses U23 and energy storage inductor L1 to convert low voltage DC into high-frequency square wave energy, and then performs synchronous and symmetrical charge pumping through the positive voltage multiplier chain (composed of diodes U25-U33, U12, etc.) and the negative voltage multiplier chain (composed of diodes U13-U22, etc.). This scheme solves the problem of difficulty in generating a wide range (±90V in this embodiment) of symmetrical bipolar high voltage bias in a compact volume in existing portable devices, providing a stable and reliable power supply basis for the high voltage operational amplifier U9 in the high voltage operational amplifier circuit. In addition, the present application also proposes a differential pulse width modulation measurement circuit resistant to common mode interference, which is mainly a differential pulse width modulation measurement front end composed of D-type flip-flop U3 (SN74LS74N) and dual comparator U1 (LM393N). The circuit injects phase-opposed charging current into the measured total capacitance (reference capacitor C2+ DUT to be measured) through the complementary output positive modulation pulse output pin (1Q) and the reverse modulation pulse output pin (1Q#) of U3, via charging resistors R3 and R4, and converts the capacitance value into a change in pulse width. The subsequent signal conditioning circuit composed of operational amplifier U2 (LM358DR2G) processes the differential signal. This differential drive and processing hardware architecture fundamentally suppresses common mode noise and ground line interference, solving the problem of extremely sensitive single-ended measurement methods that result in low reliability in field environments, significantly improving measurement accuracy and stability. In addition, the present application also designs a symmetrical bipolar high voltage bias control circuit based on dual single-polarity DAC, which adopts a "low voltage precision synthesis, high voltage linear amplification" design, uses two independent single-polarity DAC outputs (DAC1, DAC2) of MCU (such as STM32 single-chip microcomputer), and cooperates with the analog operation circuit composed of general operational amplifiers U10 and U11 to synthesize a high-precision bipolar reference signal in the low voltage domain. The bipolar reference signal is then linearly amplified by high-voltage operational amplifier U9 (OPA462IDDAR) at a high rate. This scheme solves the problem of how to achieve high linearity, symmetry, and seamless zero-crossing bipolar high voltage scanning function at extremely low cost and hardware complexity, significantly reducing the cost and design complexity of the system. Finally, the present application also proposes a software compensation and differential measurement method combined with dynamic output baseline correction. This method is a software measurement method implemented in MCU.At each DC bias point, the method effectively solves the characterization of slow response problems in existing measurement techniques through the intelligent timing sequence of "stabilization-evaluation output baseline-measurement-compensation". BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 The high-voltage capacitor voltage (CV) test system in the embodiment of the application is composed of and a work flow chart;

[0050] Figure 2 The structure diagram of the Boost-voltage supply circuit in the embodiment of the application is shown in the figure;

[0051] Figure 3 The structure diagram of the high-voltage bias control circuit in the embodiment of the application is shown in the figure;

[0052] Figure 4 The structure diagram of the differential pulse width modulation measurement circuit in the embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0053] The application will be further described in detail below in combination with the drawings and specific embodiments:

[0054] EMBODIMENT

[0055] At present, the measurement method based on pulse charging timing has low signal-to-noise ratio when detecting pF-level weak capacitor changes, is easily affected by parasitic parameters and electromagnetic interference, and leads to unstable measurement results. At the same time, a portable system needs to efficiently generate a wide range of symmetric bipolar high-voltage bias (such as ±90V) in a compact space, and the traditional scheme is difficult to balance volume, efficiency and symmetry. In addition, the characterization of slow response processes such as semiconductor interface traps requires a long enough bias stabilization time, but this will introduce the accumulation of device leakage current, interfere with the voltage measurement reference, and cause measurement errors. The existing technology is in a dilemma: prolonging the stabilization time will increase the leakage error, and shortening the time will not be able to accurately capture the slow response process. In order to solve the technical bottlenecks of existing portable CV test equipment in high-voltage power generation, measurement anti-interference ability and slow response process characterization, the application provides a portable high-voltage CV test system and method which integrates a high-voltage power supply, a differential measurement front end and intelligent timing control software.

[0056] Specifically, the application adopts a hardware and software collaborative design scheme. The hardware part designs a Boost-voltage doubling circuit based on high-frequency switching conversion and symmetric voltage doubling topology, which can efficiently convert low-voltage direct current input into symmetric ±90V high-voltage rails, overcoming the bottleneck of high-voltage generation in portable devices. The measurement part adopts a differential pulse width modulation circuit to convert the capacitance value into a differential square wave pulse width, and then demodulates it into an analog voltage. Through the differential architecture, common-mode noise and ground line interference are suppressed, and the anti-interference ability is improved. On the software level, intelligent timing control and algorithm compensation are realized in the MCU. By executing the loop sequence of "stabilization-baseline measurement-compensation" at each bias point, the system provides sufficient stabilization time for slow response processes while actively measuring and compensating for baseline errors caused by leakage current, thereby fundamentally solving the contradiction between slow response characterization and leakage current suppression.

[0057] As shown in Figure 1 The semiconductor device capacitance voltage test system in the embodiment includes a low-voltage power supply circuit, a Boost-voltage doubling power supply circuit, an MCU, a high-voltage bias control circuit, an AC-DC isolation circuit, and a differential pulse width modulation measurement circuit.

[0058] The low-voltage power supply circuit provides initial low-voltage power supply for the entire system.

[0059] One of the low-voltage power supply circuits is sent to the STM32 single-chip microcomputer and other low-voltage analog circuits, and the other is sent to the Boost-voltage doubling power supply circuit, which generates symmetric ±90V high voltage as the power rail of the high-voltage operational amplifier circuit.

[0060] The Boost-voltage doubling power supply circuit is used to receive the low-voltage direct current input of the low-voltage power supply circuit and generate a pair of stable, symmetric, and isolated high-voltage bipolar power rails as the power rail of the high-voltage operational amplifier circuit.

[0061] The high-voltage bias control circuit includes a signal processing circuit and a high-voltage operational amplifier circuit.

[0062] The STM32 single-chip microcomputer outputs a low-voltage control signal through its built-in dual-channel DAC according to a preset scan program. After the low-voltage control signal is transformed in polarity and buffered by the signal processing circuit, it drives the high-voltage operational amplifier circuit.

[0063] The high-voltage operational amplifier circuit is used to linearly amplify the low-voltage control signal and apply the -90V to +90V direct current bias voltage generated by the Boost-voltage doubling power supply circuit to the device under test (DUT) through the AC-DC isolation circuit in differential form.

[0064] At each stable direct current bias point, an alternating current measurement pulse is coupled to the DUT, and the capacitance response of the DUT is captured by the differential pulse width modulation measurement circuit and converted into a signal whose pulse width is monotonically related to the capacitance value.

[0065] The signal is finally returned to the ADC input terminal of the STM32 single-chip microcomputer, and the STM32 single-chip microcomputer calculates the real capacitance value and pairs it with the current DC bias voltage to generate a CV curve point by point.

[0066] The Boost-voltage supply circuit is the power source of the entire system, which is used to generate a pair of stable, symmetrical and isolated high-voltage bipolar power rails (+90V and -90V in the embodiment) from a single low-voltage DC input (such as +3.3V).

[0067] The high-voltage bias control circuit is used to receive the low-voltage, unipolar control signal (output by the DAC) sent by the MCU and accurately and linearly convert it into a wide range (-90V to +90V) and continuously scanned bipolar high voltage.

[0068] The high voltage is applied to the DUT as the DC bias voltage V_bias in the CV test.

[0069] The function of the differential pulse width modulation measurement circuit is to linearly convert the capacitance value of the DUT into an analog signal that can be easily captured by the hardware ADC of the MCU (such as an STM32 single-chip microcomputer) with high precision.

[0070] The Boost-voltage supply circuit is used to provide the high-voltage power supply necessary for the normal operation of the high-voltage operational amplifier U9. Without stable and clean ±90V power supply, U9 will not be able to output the required high-voltage bias.

[0071] Among them, the high-voltage operational amplifier U9 is the core element in the high-voltage bias control circuit.

[0072] As shown in Figure 2 The Boost-voltage supply circuit in the embodiment includes the following two circuits:

[0073] The high-frequency Boost-voltage circuit is used to preliminarily boost the +3.3V DC input voltage received by the low-voltage power supply circuit and convert it from a DC form to a high-frequency energy source required by the voltage doubler circuit;

[0074] And the Cockcroft-Walton voltage doubler circuit with symmetrical topology is used to receive the high-frequency energy source output by the high-frequency Boost-voltage circuit and amplify its voltage amplitude to the target value ±90V through multiple stages of passive charge pumping.

[0075] The high-frequency Boost-voltage circuit includes a high-frequency boost-type switching converter U23 and an energy storage inductor L1.

[0076] U23 preferably adopts ADP1612 ARMZ-R7 device. The +3.3V DC input voltage is applied to the VIN (pin 6) and the enable control pin EN (pin 3) of U23; connecting EN directly to VIN can ensure that the chip starts working as soon as it is powered on.

[0077] L1 is connected between the input pin VIN of U23 and the internal power switch output pin SW (pin 5).

[0078] After the high-frequency boost switching converter U23 is powered on, its internal oscillator starts working to drive the internal MOSFET power switch at an extremely high frequency (MHz level) to perform high-speed on-off.

[0079] When the internal switch tube of the SW pin is turned on to ground, a low-resistance path is formed from VIN to ground through the energy storage inductor L1, and the current quickly flows through the inductor L1. According to the inductance characteristics, the current increases linearly, and the input electrical energy is stored in L1 in the form of a magnetic field.

[0080] When the internal switch tube of the SW pin is suddenly turned off, the current path through the energy storage inductor L1 is cut off, and the magnetic field energy stored in L1 is instantaneously converted into electrical energy due to the inductance current cannot be abruptly changed.

[0081] At this time, the SW pin outputs a series of high-peak, high-frequency square wave pulses (voltage spikes).

[0082] The amplitude of this voltage spike is much higher than the input +3.3V, achieving voltage boosting; a series of high-peak, high-frequency square wave pulses are output on the SW pin, which is the high-frequency energy source for the subsequent voltage doubling circuit.

[0083] The high-frequency boost circuit also includes a closed-loop feedback network for sampling from the internal power switch output pin SW; the closed-loop feedback network is composed of two voltage dividing resistors R30, R31, a Schottky diode U24 and a capacitor C39.

[0084] The Schottky diode U24 and the capacitor C39 constitute a peak detector for capturing the peak voltage of the pulses output by the internal power switch output pin SW, and the two voltage dividing resistors R30, R31 divide the peak voltage.

[0085] The voltage after voltage division is sent to the feedback input pin FB of the high-frequency boost switching converter U23; the high-frequency boost switching converter U23 internally compares the voltage of the feedback input pin FB with the target voltage.

[0086] If the voltage of the feedback input pin FB is higher than the target voltage, the on-time of the internal switch tube will be reduced, i.e. the duty cycle will be reduced; otherwise, if the voltage of the feedback input pin FB is not higher than the target voltage, the on-time of the internal switch tube will be increased, i.e. the duty cycle will be increased.

[0087] Through this negative feedback mechanism, the pulse peak voltage outputted from the SW pin of the high-frequency boost switching converter U23 is precisely stabilized at the target value set by the proportional resistors R30 and R31.

[0088] In addition, the high-frequency boost circuit further comprises a loop compensation network (i.e. RC compensation network) for adjusting the frequency response characteristics of the feedback loop, ensuring that the loop can work stably under various load conditions, preventing oscillation or slow response.

[0089] The loop compensation network comprises a compensation resistor R29 and a compensation capacitor C1. The R29 and C1 are connected in series and connected between the compensation pin COMP (pin 1) of the U23 and the ground.

[0090] As shown in Figure 2 The voltage doubling circuit is composed of two sets of five-stage CW voltage doubling chains which are completely mirrored and have the same topology; the input ends of the two voltage doubling chains are connected to the SW pin of the internal power switch output and share the same high-frequency energy source.

[0091] The two five-stage CW voltage doubling chains are a positive +90V voltage doubling chain and a negative -90V voltage doubling chain, respectively.

[0092] The positive +90V voltage doubling chain adopts a five-stage pumping structure, which includes:

[0093] A plurality of coupling capacitors C3, C40, C42, C44, C46 (respectively in each stage of pumping structure), wherein one end of the coupling capacitor C3 is connected to the SW excitation source of the high-frequency boost circuit, for transferring energy in the alternating cycle of square wave.

[0094] A plurality of energy storage and filtering capacitors C4, C41, C43, C45, C47 (respectively in each stage of pumping structure), for storing the charge pumped up by each stage of pumping structure and gradually lifting the DC voltage.

[0095] And a plurality of rectifier diodes U25, U26, U27, U28, U29, U30, U31, U32, U33, U12 (every two rectifier diodes are in one stage of pumping structure, for example, U25 and U26 are in the first stage of pumping structure).

[0096] They constitute a one-way charge transmission path, ensuring that the charge can only be pumped up step by step from low potential to high potential.

[0097] Each pumping structure consists of a coupling capacitor, two rectifier diodes and an energy storage and filter capacitor. For example, the first pumping structure consists of coupling capacitor C3, rectifier diodes U25 and U26, and energy storage and filter capacitor C4.

[0098] SW pin is connected to one end of C3 and the anode of U25, and the other end of C3 is connected to the cathode of U26. The cathode of U25 is connected to the anode of U26, and to one end of C4, and the other end of the energy storage and filter capacitor C4 is grounded.

[0099] This "coupling capacitor-diode pair-energy storage and filter capacitor" "ladder" structure is cascaded in turn. For example, the second pumping structure consists of coupling capacitor C40, rectifier diodes U27 and U28, and energy storage and filter capacitor C41.

[0100] The cathode of U26 is also connected to one end of C40 and the anode of U27. The other end of C40 is connected to the cathode of U28. The cathode of U27 and the anode of U28 are adjacent and connected to one end of C41. The other end of the energy storage and filter capacitor C41 is grounded.

[0101] The second "coupling capacitor-diode pair-energy storage and filter capacitor" structure consists of coupling capacitor C40, diodes U27 and U28, and energy storage and filter capacitor C41, and so on, as shown in Figure 2 .

[0102] This structure is repeated for five levels, and the last level takes the cathode of diode U12 as the +90V high voltage output terminal.

[0103] Similarly, the negative +90V voltage doubler chain adopts a five-level pumping structure, which includes:

[0104] A plurality of coupling capacitors C22, C20, C18, C16, C14 (in each pumping structure, respectively), wherein one end of C22 is connected to the SW excitation source of the high-frequency Boost circuit, for transferring energy in the alternating cycle of the square wave.

[0105] A plurality of energy storage and filter capacitors C23, C21, C19, C17, C15 are respectively in each pumping structure, for storing the charge pumped up by each pumping structure and gradually raising the DC voltage.

[0106] and a plurality of rectifier diodes U13, U14, U15, U16, U17, U18, U19, U20, U21, U22 (every two rectifier diodes are in a pumping structure, for example, U13 and U14 are in the first pumping structure).

[0107] They constitute unidirectional charge transport paths, ensuring that charges can only be pumped step by step from low potential to high potential.

[0108] Each pumping structure is composed of a coupling capacitor, two rectifier diodes and an energy storage and filtering capacitor; for example, the coupling capacitor C22, the rectifier diodes U22, U21 and the energy storage and filtering capacitor C23 constitute the fifth pumping structure.

[0109] As shown in Figure 2 , the SW pin is connected to one end of C22 and the cathode of U22, and the other end of C22 is connected to the anode of U21. The anode of U22 and the cathode of U21 are connected and connected to one end of C23, and the other end of C23 is grounded.

[0110] This "ladder" structure of "coupling capacitor-diode pair-energy storage and filtering capacitor" is cascaded in turn. For example, the coupling capacitor C20, the rectifier diodes U20, U19 and the energy storage and filtering capacitor C21 constitute the fourth pumping structure.

[0111] The anode of U21 is also connected to one end of the energy storage capacitor C20 in the previous pumping structure. This negative chain structure is a mirror image of the positive chain topology, and all diodes are reversed. After five levels of cascading, the anode of diode U13 serves as a -90V high voltage output terminal.

[0112] The Boost-voltage supply circuit is based on charge pumping, driven by the high-frequency square wave energy source output by the SW pin.

[0113] Since the positive and negative voltage doubling chain topologies are completely symmetrical and share the same excitation source, their charge pumping processes are synchronized and mirror-image alternately performed in the two half cycles of the SW pin, thereby efficiently generating a symmetrical bipolar high voltage output.

[0114] The positive +90V charge pumping process (step-by-step lifting of positive charges), which can be divided into two alternating stages:

[0115] First half cycle: charging phase, SW pin voltage is 0V.

[0116] For each level of the positive chain, its corresponding coupling capacitor (for example, C3 of the first level) is connected to the system reference potential (ground) through the forward conduction of the diode connected to it (for example, U25). At this time, C3 is charged, and its right end potential is clamped at about +0.7V (diode forward voltage drop), making charge reserves for the next half cycle of voltage lifting.

[0117] Second half cycle: pumping / lifting phase, the SW pin voltage jumps from 0V to the peak voltage Vp in an instant.

[0118] According to the physical characteristic that the voltage of a capacitor cannot change abruptly, the voltage difference across C3 must remain the same at the instant of the jump. Since the left end of C3 is forced to rise by Vp, the right end of C3 must also rise by Vp, to about Vp + 0.7V.

[0119] At this moment, the high voltage at the right end of C3 causes the diode (e.g. U26) in the following stage to conduct in the forward direction, while the diode U25 in the preceding stage is reverse-biased and non-conducting because its anode is at 0V. Thus, the charge stored in C3 and endowed with higher potential energy is "pumped" through U26 to the first energy storage and filtering capacitor (e.g. C4), charging it.

[0120] The voltage across C4 will gradually build up and stabilize at about Vp. At this point, the first stage of charge pumping is complete, successfully boosting the DC voltage from 0V to about Vp. This cycle of "charging-pumping" is repeated iteratively in the subsequent four stages.

[0121] Each stage takes the DC voltage established by the previous stage as its "ground" potential, and boosts it by about Vp again. The flow of charge is unidirectional along the "potential ladder" formed by U25 to U12, with each stage being higher than the previous one.

[0122] Finally, the positive high voltage output is formed at the +90V output terminal.

[0123] Negative -90V charge pumping process (step-by-step extraction of positive charge) The working principle of the negative chain is a mirror image of the positive chain, and can be understood as a step-by-step "extraction" of positive charge, thus forming a negative potential at the output terminal.

[0124] First half cycle: preparation phase In this phase, the SW pin voltage is high at Vp. For each stage of the negative chain, its corresponding coupling capacitor (e.g. C22 for the first stage) is connected to the SW terminal through its preceding diode (e.g. U22).

[0125] Second half cycle: pumping / down phase In this phase, the SW pin voltage drops instantaneously from Vp to 0V. The left end of C22 is forced to drop by Vp, causing the right end of C22 to be "pulled down" to a very low negative potential (about -Vp).

[0126] At this moment, this very low negative potential causes the diode (e.g. U21) in the following stage to conduct in the forward direction, while the diode U22 in the preceding stage is reverse-biased and non-conducting. Thus, the very low potential of C22 "extracts" positive charge (equivalent to injecting electrons) from the energy storage and filtering capacitor (e.g. C23). C23 gradually loses positive charge and its potential relative to the system ground gradually decreases, and eventually stabilizes at about -Vp. At this point, the fifth stage of negative pumping is complete, successfully "pulling down" the DC voltage from 0V to about -Vp.

[0127] This process is repeated iteratively in subsequent stages, and the positive charges are extracted from the final -90V output end, and flow down along the "ladder" composed of U13 to U22, and finally into the system.

[0128] Finally, the -90V output end forms a stable negative high voltage due to the continuous loss of positive charges.

[0129] The Boost-voltage supply circuit is a symmetrical bipolar high-voltage generation circuit, which is beneficial to solve the power bottleneck problem that it is difficult to efficiently generate a wide range of symmetrical bipolar high-voltage bias in a compact volume in existing portable devices.

[0130] The high-voltage bias control circuit is used to accurately convert the low-voltage, digital control intention generated by the STM32 single-chip microcomputer into an analog DC high-voltage with high linearity and a wide dynamic range (-90V to +90V) applied to the element to be tested.

[0131] This voltage is called the DC bias voltage V_bias in the CV test, and is the basis for scanning the capacitance characteristics.

[0132] In order to ensure extremely high precision and linearity while maximizing the use of general-purpose, low-cost components, the high-voltage bias control circuit of the embodiment adopts a two-stage cascading design strategy of "low-voltage precision control synthesis and high-voltage linear amplification".

[0133] The high-voltage bias control circuit converts the low-voltage instructions output by the STM32 single-chip microcomputer into a high-linearity, symmetrical, and seamless zero-crossing bipolar high-voltage bias, which is composed of a signal processing circuit and a high-voltage operational amplifier circuit.

[0134] The signal processing circuit is responsible for combining the two independent, unipolar DAC signals built into the STM32 single-chip microcomputer into an accurate bipolar low-voltage reference signal, which mainly includes a negative signal generation path and a signal merging path.

[0135] The input nodes of the signal processing circuit are DAC1 and DAC2. These two nodes are directly connected to the two DAC output pins of the MCU. The MCU can accurately control the output of these two pins to be any voltage between 0V and +3.3V.

[0136] The negative signal generation path includes the first operational amplifier U10, the input resistor R1, and the feedback resistor R20; wherein the input resistor R1 and the feedback resistor R20 constitute an inverting amplifier.

[0137] The first operational amplifier U10 is for example a dual operational amplifier (using one channel of a dual operational amplifier), the second digital-to-analog conversion output node DAC2 of the MCU is connected to one end of the input resistor R1, and the DAC2 outputs a voltage signal of 0 to 3.3V.

[0138] The other end of the input resistor R1 is connected to the inverting input terminal 1IN- of the U10; the feedback resistor R20 is connected across the output terminal 1OUT and the inverting input terminal 1IN- of the first operational amplifier U10; the non-inverting input terminal 1IN+ of the U10 is directly grounded.

[0139] The output terminal 1OUT (pin 1) of the first operational amplifier U10 outputs a voltage of -3.3V to 0.

[0140] When the DAC2 outputs a unipolar voltage signal of 0V to +3.3V, the inverting amplifier (configured as a unity gain, i.e. R1=R20) converts it accurately into a negative voltage signal of -3.3V to 0V and outputs it from the output terminal 1OUT.

[0141] The signal merging path comprises a second operational amplifier U11, two input resistors R21, R22, and a non-inverting adder formed by a feedback network. In the embodiment, the second operational amplifier U11 is for example a dual operational amplifier.

[0142] Similarly, the U11 is also only using one channel of a dual operational amplifier.

[0143] The output terminal 1OUT of the first operational amplifier U10 is connected to one end of an input resistor R21; the first digital-to-analog conversion output node DAC1 of the MCU is connected to one end of another input resistor R22.

[0144] The other ends of the input resistors R21, R22 are commonly connected to the non-inverting input terminal 1IN+ of the second operational amplifier U11.

[0145] The output terminal 1OUT of the U11 is connected to its inverting input terminal 1IN- through a feedback network formed by two feedback resistors R23 and R24, which is configured as a voltage follower or a non-inverting amplifier with a specific gain.

[0146] The non-inverting adder superimposes the positive signal from the DAC1 of the MCU and the negative signal from the U10.

[0147] Since the DAC1 and the DAC2 are driven in time division, only one of the two inputs is non-zero at any time. Therefore, the output terminal of the U11 can generate a continuous, seamless zero-crossing, low-voltage bipolar reference signal ranging from -3.3V to +3.3V.

[0148] The U10 and U11 in this embodiment are LM358DR2G devices, for example.

[0149] The high-voltage operational amplifier U9 is responsible for amplifying the bipolar low-voltage reference signal synthesized by the previous signal processing circuit to a high-voltage bias required by the DUT.

[0150] The two power supply pins V+ and V- of U9 are connected to the +90V and -90V high-voltage power supply rails generated by the Boost-voltage supply circuit, respectively.

[0151] The high-voltage operational amplifier U9 is used to receive the bipolar low-voltage reference signal output by the second operational amplifier U11.

[0152] The high-voltage output OUT of U9 is fed back to its non-inverting input -IN through a closed-loop feedback network composed of two feedback resistors R26 and R27.

[0153] The high-voltage operational amplifier U9 and its closed-loop feedback network constitute a high-voltage in-phase amplifier. The closed-loop gain G is accurately set by the ratio of the feedback resistors R26 and R27 in the closed-loop feedback network, specifically, G = 1+ R26 / R27.

[0154] The U9 amplifier linearly amplifies the input low-voltage reference signal of -3.3V to +3.3V by a factor of G, thereby generating a continuous high-voltage bias of -90V to +90V synchronized with the DAC digital command at its output and applying it to the DUT.

[0155] The Boost-voltage supply circuit and the high-voltage bias control circuit are used to provide a stable working environment for the DUT.

[0156] After the system provides a stable high-voltage bias working environment for the DUT, the differential pulse-width modulation (DPWM) technique is used to convert the capacitance value Cdut of the DUT into a single-ended analog voltage signal that can be accurately collected by the MCU's ADC.

[0157] The DPWM technique is an ideal choice for high-precision capacitance measurement due to its excellent linearity and anti-interference ability.

[0158] To achieve this goal, the differential pulse width modulation measurement circuit adopts a cascade architecture, whose conversion chain is: capacitor → pulse width → differential square wave → single-ended analog signal. The differential pulse width modulation measurement circuit includes:

[0159] The differential pulse width modulation capacitor detection circuit is used to linearly convert the capacitance value of the measured element DUT into a differential square wave signal, and the pulse width, i.e. the duty cycle, is proportional to the capacitance value.

[0160] The analog signal conditioning front-end circuit is used to perform low-pass filtering on the differential square wave signal, and demodulate and convert it into an analog signal with a voltage range matching the voltage range of the ADC of the MCU through subtraction and level lifting operations.

[0161] The differential pulse width modulation capacitor detection circuit is composed of a logic and drive unit U3, a dual-channel comparator U1, and a differential RC network including a measured arm R3, a DUT, and a reference arm R4, C2.

[0162] The differential pulse width modulation capacitor detection circuit linearly converts the measured capacitance value into a differential square wave signal with a pulse width proportional to the capacitance value through self-oscillation, and the formula is expressed as follows: u_AB = u_A - u_B.

[0163] As shown in Figure 4 , the differential pulse width modulation core circuit includes:

[0164] The logic and drive unit U3 adopts a D-type flip-flop, and the positive modulation pulse output pin 1Q and the reverse modulation pulse output pin 1Q# of the D-type flip-flop complementarily output signals as differential driving sources, which are denoted as u_A and u_B, respectively;

[0165] The dual-channel comparator U1 is used to sense the RC charging process and trigger the state inversion of U3.

[0166] The differential RC network is composed of an upper arm charging path including a charging resistor R3 and a DUT, and a lower arm charging path including a charging resistor R4 and a reference capacitor C2, as well as two reset diodes D1 and D2.

[0167] The 1Q# pin of U3 is connected to the cathode of the reset diode D1 and one end of the charging resistor R3; the anode of D1 and the other end of the charging resistor R3 are connected, and are connected to the DUT through an isolation capacitor C48.

[0168] The 1Q pin of U3 is connected to the cathode of the reset diode D2 and one end of the charging resistor R4; the anode of D2 and the other end of 4 are connected, and are connected to one end of C2, and the other end of C2 is connected to the DUT through an isolation capacitor C49.

[0169] 5V voltage signal through the voltage dividing resistor U5 and R2 voltage dividing reference voltage, access to the comparator 1 of the dual comparator U1 positive input pin IN1+ and the comparator 2 positive input pin IN2+ as reference voltage.

[0170] The pull-up resistor U6 and U7 are connected to 5V at one end and the OUT pin at the other end for output pull-up.

[0171] U6 and U7 are essential pull-up resistors to compensate for the characteristics of the LM393 comparator open collector output that cannot generate high level by itself, ensuring a stable and complete digital signal for the subsequent digital logic chip U3.

[0172] The positive input pin IN1+ of comparator 1 of dual comparator U1 and IN2- of comparator 2 of dual comparator U1 are connected to the anode of reset diode D1, D2 respectively, for accepting input signal for comparison with reference voltage.

[0173] OUT1 output pin connects the 1CP clock input end pin of U3, and OUT2 pin connects the asynchronous clear pin 1RD# of U3.

[0174] The difference signal u_AB = u_A - u_B of u_A and u_B constitutes the core signal carrying modulation information, i.e. the differential square wave signal.

[0175] In this embodiment, U3 uses SN74LS74N device, and U1 uses LM393N device.

[0176] The analog signal conditioning front-end circuit performs demodulation and conversion, which is based on a core operational amplifier U2 and provides reference voltage by a precise 1.6V reference source U8.

[0177] In this embodiment, U2 uses LM358DR2G device, and U8 uses LP3993-16B3F device.

[0178] The analog signal conditioning front-end circuit performs low-pass filtering on the input differential square wave signal to extract the DC component, and performs subtraction and level lifting operation, finally generating a pure and stable single-ended analog voltage signal at the output node H1.

[0179] The voltage range of the single-ended analog voltage signal is completely matched with the ADC of MCU (such as STM32 single-chip microcomputer).

[0180] According to the basic physical law of RC circuit charging, when the capacitor starts charging from 0V to threshold voltage Ur, and the final charging voltage is U_high, the expression of charging time T is:

[0181] T = R × C × ln( U_high / (U_high - Ur) );

[0182] where R represents the voltage, and C represents the capacitance.

[0183] Applying this theory to two half cycles of the present circuit, the pulse widths T_A and T_B are accurately derived as:

[0184] T_A = R3_ref × (Cdut) × ln( U_high / (U_high - Ur) )。

[0185] T_B = R4_ref × C_ref × ln( U_high / (U_high - Ur) )。

[0186] where U_high is the output high level of U3 (about +5V), Ur is the threshold voltage of U1. R3_ref is the resistance of R3, and R4_ref is the resistance of R4.

[0187] In the oscillation core, u_A and u_B are rectangular waves with a period of T = T_A + T_B. u_A is U_high during T_A and 0V during T_B. u_B is U_high during T_B and 0V during T_A.

[0188] According to the theory of the differential pulse width modulation circuit, the difference signal u_AB = u_A - u_B is filtered through a low-pass filter, and the resulting DC voltage U0 is the average value of u_AB in one period.

[0189] The expression of U0 is:

[0190] U0 = (1 / (T_A + T_B)) × [ (U_high × T_A) + (-U_high × T_B) ].

[0191] After rearranging, we get:

[0192] U0 = U_high × ( (T_A - T_B) / (T_A + T_B) )。

[0193] where U_A_dc = U_high × (T_A / (T_A + T_B)) is the DC component of the u_A rectangular pulse, and U_B_dc = U_high × (T_B / (T_A + T_B)) is the DC component of the u_B rectangular pulse.

[0194] T_A = R3_ref x Cdut x Const_ln; T_B = R4_ref x C_ref x Const_ln.

[0195] Let Const_ln = ln(U_high / (U_high - Ur)) be a constant under certain circuit parameters.

[0196] Substitute the expressions of T_A and T_B into the formula of U0, we get:

[0197] U0 = U_high x ((R3_ref x Cdut x Const_ln - R4_ref x C_ref x Const_ln) / (R3_ref x Cdut x Const_ln + R4_ref x C_ref x Const_ln)).

[0198] From the above formula, the constant term Const_ln is completely removed:

[0199] U0 = U_high x ((R3_ref x Cdut - R4_ref x C_ref) / (R3_ref x Cdut + R4_ref x C_ref)).

[0200] In the circuit design, high-precision matching resistance is selected, so that R3_ref = R4_ref = R, and the resistance R can also be removed, that is:

[0201] U0 = U_high x ((Cdut - C_ref) / (Cdut + C_ref));

[0202] Where Cdut is the capacitance value of the element to be measured.

[0203] As can be seen, the direct current voltage U0 obtained after low-pass filtering is proportional to the ratio of the difference and the sum of the two capacitances (the element to be measured and the reference capacitance), which is a highly linear relationship, and can realize accurate capacitance measurement.

[0204] The analog signal conditioning front-end circuit includes a precision reference source U8, an operational amplifier U2, a differential subtractor, a level-lifted adder, and an output filter, such as PZ254V-11-02P.

[0205] The core operational amplifier U2 of the analog signal conditioning front-end circuit adopts LM358DR2G (a dual-channel operational amplifier) to constitute a low-pass filter, a subtraction circuit and a level lifting circuit. The precision reference source U8 adopts LP3993-16B3F to provide a 1.6V reference.

[0206] The analog signal conditioning front-end circuit is connected to the ADC of the STM32 single-chip microcomputer through the interface H1.

[0207] The final output of the analog signal conditioning front-end circuit is a direct-current analog voltage signal U_adc, which is connected to the ADC of the MCU through the final output node interface H1, so as to realize the accurate conversion of the capacitance value into an analog voltage signal that can be collected by the microcontroller.

[0208] The analog signal conditioning front-end circuit is used for receiving the complementary output of the D-type flip-flop U3 and outputting a single-ended analog voltage linearly related to the capacitance value through a series of analog operations.

[0209] The first-stage operational amplifier of the operational amplifier U2, the input resistors R7 and R8, the pull-down resistor R9 and the feedback resistor R10 constitute a subtractor circuit for obtaining a difference signal u_AB by subtracting the divided u_A and u_B signals and outputting the difference signal.

[0210] Wherein u_AB = u_A - u_B.

[0211] The forward modulation pulse output pin 1Q of the logic and driving unit U3 is connected to one end of the input resistor R8 through two voltage dividing resistors R6 and R5, and the other end of the input resistor R8 is connected to the reverse input end 1IN- of the first-stage operational amplifier.

[0212] One end of the input resistor R7 is connected between the two voltage dividing resistors R6 and R5, and the other end is connected to the forward input end 1IN+ of the first-stage operational amplifier; one end of the pull-down resistor R9 is connected between the forward input end 1IN+ of the first-stage operational amplifier and the input resistor R7, and the other end is grounded; the feedback resistor R10 is arranged between the output end 1OUT of the first-stage operational amplifier and the first reverse input end 1IN-.

[0213] The reverse modulation pulse output pin 1Q# of the logic and driving unit U3 is connected to the reverse input end 1IN- of the first-stage operational amplifier of the operational amplifier U2 through the input resistor R8; the output end 1OUT of the first-stage operational amplifier outputs the difference signal u_AB and inputs it as an output to the adder circuit composed of the second-stage operational amplifier of the operational amplifier U2, two input resistors R11 and R12, and two feedback resistors R13 and R14.

[0214] The output terminal 1OUT of the first-stage operational amplifier is connected to the positive input pin 2IN+ of the second-stage operational amplifier through an input resistor R11; a 5V voltage generates a 1.6V reference voltage after passing through a precision reference source U8, and then is connected to the positive input pin 2IN+ of the second-stage operational amplifier through an input resistor R12.

[0215] One feedback resistor R14 is connected between the positive input pin 2IN+ and the output terminal 2OUT of the second-stage operational amplifier, and the other feedback resistor R13 is connected to the positive input pin 2IN+ at one end and grounded at the other end.

[0216] The output terminal 2OUT of the second-stage operational amplifier outputs a direct-current analog voltage signal U_adc, and the spike signal in the output signal is filtered out through an output filter and finally output through an H1 port, which is connected to an ADC of an MCU.

[0217] The interface H1 of the output filter is connected to one end of a resistor R19, the other end of the resistor R19 is connected to the 2OUT pin of U2, and a capacitor C13 is connected between H1 and ground, and the resistor R19 and the capacitor C13 constitute an RC filter circuit for filtering out noise. The spike signal in the output signal of the output terminal 2OUT of the second-stage operational amplifier is filtered out through the filter and finally output through the H1 port.

[0218] The filter capacitors C11 and C12 are used to filter out noise; the feedback resistors R13 and R14 constitute a feedback loop of the adder circuit.

[0219] The working process of the analog signal conditioning front-end circuit is a cascaded signal processing flow:

[0220] First, the subtracter circuit receives the original high-frequency square wave signals u_A and u_B from U3. The subtracter of the circuit utilizes the limited bandwidth of U2 itself to naturally realize low-pass filtering effect while performing differential subtraction operation, thereby effectively filtering out high-frequency harmonics and directly extracting the direct-current component carrying the capacitance information to generate a direct-current voltage with 0V as the center potential. Subsequently, the direct-current voltage signal is sent to the adder circuit.

[0221] The adder circuit with the level lifting function sums the output signal of the subtracter circuit with a stable bias voltage provided by the precision reference source U8, and accurately translates the entire dynamic range of the signal from the bipolar domain with 0V as the center to the unipolar voltage domain with 1.6V as the center and completely matching the input range of the STM32 single-chip microcomputer ADC.

[0222] Finally, this voltage, before being output to the interface H1, will flow through a passive RC low-pass filter composed of resistor R19 and capacitor C13, which performs a final "purification" of the signal, further filtering any residual high-frequency noise that may exist, ensuring that the analog signal U_adc sent to the MCU is an extremely stable, pure DC voltage.

[0223] The application further proposes a method of realizing differential measurement at the functional level through software scheduling and algorithm processing of the MCU (STM32 single-chip microcomputer), thereby significantly improving the measurement accuracy and long-term stability of the system. The method time-division multiplexes the same physical measurement channel, and the core idea and execution steps are as follows.

[0224] The semiconductor device capacitance voltage test method in the embodiment includes the following steps:

[0225] Step 1. Bias application and system stabilization

[0226] Through the high-voltage bias control circuit, a preset target DC bias voltage is accurately applied to the DUT. After the bias voltage is applied, the MCU executes a preset stabilization waiting period (Soak Time) to ensure that the slow charge state caused by interface traps and other factors inside the DUT fully responds and reaches a quasi-static equilibrium.

[0227] Step 2. Baseline error evaluation and signal acquisition.

[0228] After the stabilization waiting period ends, the controller performs the following operations:

[0229] 2.1. Baseline offset evaluation.

[0230] The MCU first acquires and analyzes the DC analog voltage signal U_adc output by the analog signal conditioning front end AFE to quantify the equivalent baseline offset introduced by non-ideal factors such as slow response processes, denoted as U_offset_measured.

[0231] 2.2. Raw signal acquisition.

[0232] The MCU then performs formal signal acquisition to obtain the uncorrected raw ADC sample value ADC_measured_raw. This raw value is the superimposed result of the DUT true capacitance information and U_offset_measured.

[0233] Step 3. Software compensation based on baseline offset.

[0234] To eliminate the influence of non-ideal factors on measurement accuracy, the controller performs a software compensation algorithm:

[0235] Step 3.1. Correction factor calculation:

[0236] MCU calculates an ADC correction factor K_adc_compensated proportional to the measured equivalent baseline offset U_offset_measured, which represents the correction factor for compensating the ADC sampling value.

[0237] K_adc_compensated is proportional to U_offset_measured.

[0238] Step 3.2. Sampling value correction:

[0239] MCU uses the correction factor K_adc_compensated to correct the original ADC sampling value ADC_measured_raw to eliminate the influence of the baseline offset, obtaining the ADC sampling value ADC_true that truly reflects the DUT capacitance information, and obtaining the true ADC sampling value that excludes the influence of non-ideal factors. The correction process follows the following relationship:

[0240] ADC_true = ADC_measured_raw - K_adc_compensated.

[0241] Where ADC_true represents the corrected ADC sampling value reflecting the DUT capacitance information.

[0242] Step 4. Accurate calculation of the measured capacitance Cdut.

[0243] MCU uses the compensated true ADC sampling value ADC_true to accurately calculate the capacitance value of the DUT through two-stage inverse operation.

[0244] Step 4.1. Inverse operation of the analog front-end transfer function:

[0245] MCU performs inverse operation on ADC_true according to the pre-calibrated AFE gain coefficient (M) and bias constant (N), and inversely obtains the compensated DC voltage U0_compensated theoretically output by the DPWM core circuit:

[0246] U0_compensated = (ADC_true - N) / M.

[0247] Where U0_compensated represents the AFE-inverted compensated DPWM core output voltage.

[0248] Step 4.2. Inverse operation of DPWM core model and capacitance value calculation:

[0249] The MCU substitutes U0_compensated into the theoretical model of the DPWM core circuit, and calculates the to-be-measured capacitance value Cdut through the following algebraic operation: U0 = U_high * ((Cdut - C_ref) / (Cdut + C_ref)).

[0250] Wherein U_high represents the charging high level of the DPWM core; Cdut represents the capacitance value of the DUT, and C_ref represents the known calibrated value of the fixed reference capacitance C2. The capacitance value Cdut of the DUT is calculated according to the above formula.

[0251] Firstly, the normalized intermediate variable X is calculated, and the formula is expressed as follows:

[0252] X = U0_compensated / U_high.

[0253] Wherein U_high is the known charging high level of the DPWM core circuit. X represents the normalized ratio of U0_compensated to U_high. Then, the final capacitance value Cdut is obtained through the analytical inverse function of the model:

[0254] Cdut = C_ref * ((1 + X) / (1 - X)).

[0255] Step 5. Data storage and iterative scanning.

[0256] The MCU pairs the finally calculated capacitance value Cdut with the currently applied target direct current bias voltage value, and stores it as an effective data point (V, C).

[0257] Subsequently, the MCU steps the target direct current bias voltage to the next preset value, and repeatedly executes the above steps 1 to 5 until the scanning in the entire preset bias range is completed, and finally generates a complete C-V characteristic curve.

[0258] Finally, a complete CV characteristic curve is accurately measured.

[0259] The software timing control method based on dynamic baseline correction provided by the present application solves the fundamental contradiction existing in the representation of slow response (long stabilization time is required) in the existing measurement method through the intelligent sequence of "stabilization-evaluation output baseline-measurement-compensation" at each bias point, so that accurate quasi-static CV testing becomes possible. Through the method provided by the present application, active compensation of the inherent non-ideal effects of the device is realized, the measurement accuracy is improved, and the interference problem of slow physical processes is solved.

[0260] The application achieves one or more of the following remarkable beneficial effects compared with the prior art. These effects work together to make it possible to realize high-precision capacitance characterization of complex semiconductor devices on a portable and low-cost platform.

[0261] The high precision, high stability and low cost are realized through the differential measurement of the combination of software and hardware, which is specifically embodied in: the system common-mode error is eliminated, the harsh requirements for the precision of hardware components are reduced, and the cost is reduced. It is not necessary to use extremely expensive and ultra-high precision resistors and voltage reference chips. The precision of the system is mainly ensured by the accuracy of the reference capacitor C_2 and the precision of the capture time of the STM32 single-chip microcomputer. The former is obtained through one-time accurate calibration, and the latter is provided by the high-speed hardware timer built-in the modern STM32 single-chip microcomputer. This design idea shifts the focus of precision guarantee from expensive analog hardware to flexible software algorithm and one-time calibration, significantly reducing the bill of materials (BOM) of the system.

[0262] In addition, the application also realizes the high integration, miniaturization and flexibility of the system, which is specifically embodied in: the Boost-voltage boosting power supply circuit adopts the topology structure of high-frequency Boost voltage boosting + CW voltage boosting chain. High-frequency operation (MHz level) makes the energy storage inductor L1 and all voltage boosting capacitors can be selected as small SMD components, completely abandoning the traditional high-voltage power supply with bulky and inefficient power frequency transformer. The generation of high voltage is also based on integrated operational amplifier and SMD components. The entire system can be integrated on a very small printed circuit board (PCB), which is very suitable for portable devices and space-limited application scenarios. The Boost-voltage boosting power supply circuit adopts high-efficiency switching power supply and passive charge pump technology, and the energy conversion efficiency is much higher than that of the traditional linear voltage stabilizer or transformer scheme, thereby reducing the system power consumption and heat, especially suitable for battery-powered applications. The complex measurement timing control, scan waveform generation (such as scan rate, step size, voltage range), error compensation algorithm, etc. are all realized by the software (firmware) of the STM32 single-chip microcomputer. This soft and hard decoupling design brings great flexibility. Users can change test parameters, optimize compensation algorithms, and even add new test functions (such as pulse C-t test) through simple firmware upgrade, without any modification to the hardware, making the system have strong scalability and life cycle.

[0263] The application provides a complete, end-to-end high-precision capacitance measurement solution, fundamentally solves the core technical pain point when measuring slow response, trap-containing and other non-ideal devices, and achieves significant comprehensive advantages in system precision, stability, cost, volume and flexibility and other dimensions, provides a new type of powerful and easy-to-popularize test tool for the fields of semiconductor material research, device characterization, failure analysis and the like, realizes high-precision, high-anti-interference portable CV testing, and can complete complete electrical characterization from a rapid pulse to quasi-static in a field environment, and is free from dependence on expensive bench equipment.

[0264] Of course, the above description is only for the preferred embodiments of the application, and the application is not limited to the above-described embodiments. It should be noted that any person skilled in the art can make all equivalent replacements and obvious modifications under the teaching of the present application, and all the replacements and modifications fall within the scope of the present application, and should be protected by the present application.

Claims

1. A semiconductor device capacitance-voltage testing system, characterized in that, The low-voltage power supply circuit, the Boost-voltage power supply circuit, the MCU, the high-voltage bias control circuit, the AC-DC isolation circuit and the differential pulse width modulation measurement circuit are included. The low-voltage power supply circuit provides an initial low-voltage power supply for the whole system. The Boost-voltage power supply circuit is used for receiving a low-voltage DC input of the low-voltage power supply circuit and generating a pair of stable, symmetrical and isolated high-voltage bipolar power supply rails as power supply rails of a high-voltage operational amplifier circuit. The high-voltage bias control circuit includes a signal processing circuit and a high-voltage operational amplifier circuit. The MCU outputs a low-voltage control signal through a built-in two-way DAC according to a preset scanning program. The low-voltage control signal is subjected to polarity conversion and buffering by the signal processing circuit, linearly amplified by the high-voltage operational amplifier circuit, and applied to a device under test (DUT) in a differential form through the AC-DC isolation circuit. At each stable DC bias point, an AC measurement pulse is coupled to the DUT, the capacitive response of the DUT is captured by the differential pulse width modulation measurement circuit, and converted into a signal whose pulse width is monotonically related to the capacitive value. The signal is finally fed back to the input end of the MCU, and the real capacitive value is calculated by the MCU. The real capacitive value calculated is paired with the current DC bias voltage to generate a CV curve point by point. The Boost-voltage power supply circuit includes: The high-frequency Boost voltage circuit is used for preliminarily boosting the received +3.3V DC input voltage of the low-voltage power supply circuit and converting it from a DC form into a high-frequency energy source required by the voltage doubling circuit. The Cockcroft-Walton voltage doubling circuit with a symmetrical topology is used for receiving the high-frequency energy source output by the high-frequency Boost voltage circuit and amplifying the voltage amplitude to a target value of ±90V step by step through a multi-stage passive charge pump. The high-frequency Boost voltage circuit includes a high-frequency boost-type switching converter U23 and an energy storage inductor L1. The DC input voltage is applied to the input pin VIN and the enable pin EN of U23. The energy storage inductor L1 is connected between the input pin VIN of U23 and the internal power switch output pin SW of U23. When the switch tube inside the internal power switch output pin SW is turned on to ground, a low-resistance path from the input pin VIN to the ground through the energy storage inductor L1 is formed; when the switch tube inside the internal power switch output pin SW is suddenly turned off, the current path through the energy storage inductor L1 is cut off, and the magnetic field energy stored in the energy storage inductor L1 is instantaneously converted into electric energy, and the internal power switch output pin SW outputs a square wave pulse as a high-frequency energy source of the voltage doubling circuit. The high-frequency Boost voltage circuit further includes a closed-loop feedback network for sampling from the internal power switch output pin SW; the closed-loop feedback network is composed of two voltage dividing resistors R30 and R31, a Schottky diode U24 and a capacitor C39. The Schottky diode U24 and the capacitor C39 constitute a peak detector for capturing the peak voltage of the pulse output from the internal power switch output pin SW, and the two voltage dividing resistors R30 and R31 divide the peak voltage; the voltage after voltage division is sent to the feedback input pin FB of U23; the voltage at the feedback input pin FB is compared with the target voltage inside U23; if the voltage at the feedback input pin FB is higher than the target voltage, the on-time of the internal switch tube is reduced, i.e. the duty cycle is reduced; if the voltage at the feedback input pin FB is not higher than the target voltage, the on-time of the internal switch tube is increased, i.e. the duty cycle is increased; The voltage doubling circuit is composed of two sets of five-stage CW voltage doubling chains which are completely mirrored and have the same topology; the input ends of the two voltage doubling chains are connected to the internal power switch output pin SW and share the same high-frequency energy source; The two five-stage CW voltage doubling chains are a positive +90V voltage doubling chain and a negative -90V voltage doubling chain respectively; The positive +90V voltage doubling chain adopts a five-stage pumping structure, which includes: A plurality of coupling capacitors C3, C40, C42, C44 and C46, wherein one end of the coupling capacitor C3 is connected to the SW excitation source of the high-frequency Boost circuit for transferring energy in the alternating cycle of the square wave; A plurality of energy storage and filtering capacitors C4, C41, C43, C45 and C47 for storing the charge pumped by each pumping structure and gradually increasing the direct current voltage; And a plurality of rectifier diodes U25, U26, U27, U28, U29, U30, U31, U32, U33 and U12, which constitute a one-way charge transmission path to ensure that the charge can only be pumped from low potential to high potential step by step; Each pumping structure is composed of a coupling capacitor, two rectifier diodes and an energy storage and filtering capacitor; The negative +90V voltage doubling chain adopts a five-stage pumping structure, which includes: A plurality of coupling capacitors C22, C20, C18, C16 and C14, wherein one end of the coupling capacitor C22 is connected to the SW excitation source of the high-frequency Boost circuit for transferring energy in the alternating cycle of the square wave; A plurality of energy storage and filtering capacitors C23, C21, C19, C17 and C15 for storing the charge pumped by each pumping structure and gradually increasing the direct current voltage; And a plurality of rectifier diodes U13, U14, U15, U16, U17, U18, U19, U20, U21 and U22, which constitute a one-way charge transmission path to ensure that the charge can only be pumped from low potential to high potential step by step; Each pumping structure is composed of a coupling capacitor, two rectifier diodes and an energy storage and filtering capacitor; The directions of all diodes in the negative -90V voltage doubling chain are completely opposite to those of all diodes in the positive +90V voltage doubling chain.

2. The semiconductor device capacitance voltage test system of claim 1, wherein the signal processing circuit comprises a negative signal generation path and a signal merging path. ​ The negative signal generation path comprises a first operational amplifier U10, an input resistor R1 and a feedback resistor R20; wherein the input resistor R1 and the feedback resistor R20 constitute a reverse amplifier; The second digital-to-analog conversion output node DAC2 of the MCU is connected to one end of the input resistor R1; The second digital-to-analog conversion output node DAC2 outputs a voltage signal of 0 to 3.3V; The other end of the input resistor R1 is connected to the inverting input terminal 1IN- of the first operational amplifier U10; the feedback resistor R20 is connected across the output terminal 1OUT and the inverting input terminal 1IN- of the first operational amplifier U10; The non-inverting input terminal 1IN+ of the first operational amplifier U10 is directly grounded; The output terminal 1OUT of the first operational amplifier U10 outputs a voltage of -3.3V to 0; The signal merging path comprises a second operational amplifier U11, two input resistors R21 and R22, and a non-inverting adder composed of a feedback network; the feedback network is composed of two feedback resistors R23 and R24; The output terminal 1OUT of the first operational amplifier U10 is connected to one end of an input resistor R21; the first digital-to-analog conversion output node DAC1 of the MCU is connected to one end of another input resistor R22; The other ends of the two input resistors R21 and R22 are commonly connected to the non-inverting input terminal 1IN+ of the second operational amplifier U11; the output terminal 1OUT of the second operational amplifier U11 is connected to its inverting input terminal 1IN- through the feedback network; The non-inverting adder superimposes the positive signal from DAC1 of the MCU and the negative signal from U10; Since DAC1 and DAC2 are driven in time-sharing mode, only one of the two input signals is non-zero at any time; therefore, the output terminal of U11 generates a continuous, seamless zero-crossing, low-voltage bipolar reference signal ranging from -3.3V to +3.3V.

3. The semiconductor device capacitance voltage test system according to claim 2, wherein, The high-voltage operational amplifier circuit comprises a high-voltage operational amplifier U9; two power supply pins V+ and V- of the high-voltage operational amplifier U9 are connected to +90V and -90V high-voltage power supply rails of the Boost-voltage boosting circuit, respectively; The non-inverting input terminal +IN of the high-voltage operational amplifier U9 is directly connected to the output terminal of the second operational amplifier U11, for receiving the bipolar low-voltage reference signal synthesized by the signal processing circuit; The high-voltage output OUT of the high-voltage operational amplifier U9 is directly connected to one end of the device under test DUT through the AC-DC isolation circuit, and the high-voltage operational amplifier U9 is used to apply a DC bias voltage to the device under test DUT; The high-voltage operational amplifier circuit further comprises a closed-loop feedback network; wherein the high-voltage output OUT of the high-voltage operational amplifier U9 is fed back to the inverting input terminal -IN of the high-voltage operational amplifier U9 through the closed-loop feedback network.

4. The semiconductor device capacitance voltage test system according to claim 1, wherein, The differential pulse width modulation measurement circuit comprises: The differential pulse width modulation capacitance detection circuit is used for linearly converting the capacitance value of a device under test (DUT) into a differential square wave signal, and the pulse width, i.e. the duty cycle, of the differential square wave signal is proportional to the capacitance value. The analog signal conditioning front-end circuit is used for low-pass filtering the differential square wave signal, demodulating and converting the differential square wave signal into an analog signal with a voltage range matching the voltage range of an ADC of an MCU through subtraction and level lifting operations.

5. The semiconductor device capacitance voltage test system according to claim 4, wherein the differential pulse width modulation capacitance detection circuit is used for converting the capacitance information into a differential square wave signal, and the differential pulse width modulation capacitance detection circuit comprises: The logic and drive unit U3 adopts a D-type flip-flop, and the positive modulation pulse output pin 1Q and the reverse modulation pulse output pin 1Q# of the logic and drive unit U3 complementarily output signals as differential drive sources, which are denoted as u_A and u_B respectively; The two-way comparator U1 is used for sensing an RC charging process and triggering the state inversion of the logic and drive unit U3; The differential RC network comprises an upper arm charging path composed of a charging resistor R3 and a DUT and a lower arm charging path composed of a charging resistor R4 and a reference capacitor C2; and two reset diodes D1 and D2 and two isolation capacitors C48 and C49; The reverse modulation pulse output pin 1Q# of the logic and drive unit U3 is connected to the cathode of the reset diode D1 and one end of the charging resistor R3; the anode of the reset diode D1 and the other end of the charging resistor R3 are connected, and are connected to the DUT through the isolation capacitor C48; The positive modulation pulse output pin 1Q of the logic and drive unit U3 is connected to the cathode of the reset diode D2 and one end of the charging resistor R4; the anode of the reset diode D2 and the other end of the charging resistor R4 are connected, and are connected to the reference capacitor C2, the isolation capacitor C49 and the DUT in sequence.

6. The semiconductor device capacitance voltage test system according to claim 5, wherein the analog signal conditioning front-end circuit comprises a precision reference source U8, an operational amplifier U2 and an output filter; the operational amplifier U2 adopts a two-stage operational amplifier structure and is used for constructing a low-pass filter, a subtraction circuit and a level lifting circuit; The precision reference source U8 is used as a precision reference source and is used for providing a 1.6V reference voltage; The first-stage operational amplifier of the operational amplifier U2, input resistors R7 and R8, a pull-down resistor R9 and a feedback resistor R10 constitute a subtractor circuit, which is used for obtaining a difference signal u_AB by subtracting the divided u_A and u_B signals and outputting the difference signal u_AB, wherein u_AB = u_A - u_B; The positive modulation pulse output pin 1Q of the logic and drive unit U3 is connected to one end of the input resistor R8 through two voltage dividing resistors R6 and R5, and the other end of the input resistor R8 is connected to the reverse input end 1IN- of the first-stage operational amplifier of the operational amplifier U2. ​ ​ One end of the input resistor R7 is connected between the two voltage dividing resistors R6 and R5, and the other end is connected to the positive input terminal 1IN+ of the first operational amplifier of the operational amplifier U2; one end of the pull-down resistor R9 is connected between the positive input terminal 1IN+ of the first operational amplifier and the input resistor R7, and the other end is grounded; the feedback resistor R10 is arranged between the output terminal 1OUT of the first operational amplifier and the first negative input terminal 1IN- of the first operational amplifier; The reverse modulation pulse output pin 1Q# of the logic and driving unit U3 is connected to the reverse input terminal 1IN- of the first operational amplifier of the operational amplifier U2 through the input resistor R8; the output terminal 1OUT of the first operational amplifier outputs a difference signal u_AB and inputs the difference signal u_AB as an output to the adder composed of the second operational amplifier U2, two input resistors R11 and R12, and two feedback resistors R13 and R14; The output terminal 1OUT of the first operational amplifier is connected to the positive input pin 2IN+ of the second operational amplifier through the input resistor R11; the 5V voltage generates a 1.6V reference voltage after passing through the precision reference source U8, and then the 1.6V reference voltage is connected to the positive input pin 2IN+ of the second operational amplifier after passing through the input resistor R12; One feedback resistor R14 is connected between the positive input pin 2IN+ and the output terminal 2OUT of the second operational amplifier, and the other feedback resistor R13 is connected to the positive input pin 2IN+ at one end and grounded at the other end; The output terminal 2OUT of the second operational amplifier outputs a direct current analog voltage signal U_adc; after the peak signal in the output signal is filtered by the output filter, the output signal is finally output through the H1 port, and the H1 port is connected to the ADC of the MCU.

7. A method for testing a voltage of a capacitor of a semiconductor device, based on the system for testing a voltage of a capacitor of a semiconductor device according to any one of claims 1 to 6, characterized by, The method comprises the following steps: Step 1. Bias application and system stabilization A target direct current bias voltage is applied to the capacitor DUT to be measured by the high-voltage bias control circuit, wherein the direct current bias voltage is applied to the DUT only by the AC-DC isolation circuit; after the direct current bias voltage is applied, the MCU waits for a preset time length to enable the slow physical process inside the DUT to fully respond and reach a quasi-static equilibrium; Step 2. Baseline error evaluation and measurement signal acquisition The MCU acquires the direct current analog voltage signal U_adc output by the analog signal conditioning front-end circuit AFE after the waiting is completed; the MCU analyzes the U_adc signal to evaluate the equivalent baseline offset U_offset_measured caused by the slow response; Wherein U_offset_measured represents the direct current offset in the AFE output caused by the slow response non-ideal factor; The MCU further acquires the U_adc signal to obtain the original ADC sampling value ADC_measured_raw; Wherein ADC_measured_raw represents the original ADC sampling value without correction, and the ADC_measured_raw contains the output generated by the capacitance information and the equivalent baseline offset U_offset_measured together; Step 3. Software algorithm compensation; The MCU calculates a correction factor K_adc_compensated, which represents a correction factor for compensating the ADC sampling value; wherein K_adc_compensated is proportional to the equivalent baseline offset U_offset_measured; The MCU corrects ADC_measured_raw by using K_adc_compensated to obtain a true ADC sampling value: ADC_true = ADC_measured_raw - K_adc_compensated; Wherein ADC_true represents the ADC sampling value after correction, reflecting the DUT capacitance information; Step 4. Capacitance calculation: The MCU inverses the transfer function U_adc = M × U0 + N of the AFE according to ADC_true to obtain the theoretical DC voltage U0_compensated output by the DPWM core, which is U0_compensated = (ADC_true - N) / M; Wherein U0_compensated represents the compensated DPWM core output voltage obtained by the AFE inversion; N represents the bias constant of the AFE, and M represents the gain coefficient of the AFE; U0 represents the compensated voltage value; The MCU substitutes U0_compensated into the theoretical model of the DPWM core, and the formula is as follows: U0 = U_high ×( (Cdut - C_ref) / (Cdut + C_ref) ); Wherein U_high represents the charging high level of the DPWM core; Cdut represents the capacitance value of the DUT, and C_ref represents the known calibration value of the fixed reference capacitance C2, and the capacitance value Cdut of the DUT is calculated according to the above formula; The MCU calculates a normalized intermediate variable X: X = U0_compensated / U_high: Wherein X represents the normalized ratio of U0_compensated to U_high; The MCU obtains the capacitance value of the DUT through algebraic operation, and the formula is as follows: Cdut = C_ref× (1 + X) / (1 - X); Step 5. Data storage and iteration; The MCU pairs and stores the value of Cdut with the current target DC bias voltage, and iteratively executes the above steps 1 to 5 to complete the C-V characteristic curve measurement in the preset bias range.

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