Apparatus, method, and medium for establishing a time test

Abstract

The application relates to the technical field of operational amplifier testing, and discloses an apparatus, a method and a medium for establishing time testing, the apparatus comprising: a parameter measurement unit module for sending a first step signal; an inverting module for receiving the first step signal, performing phase inversion on the first step signal based on an inverting operational amplifier, and outputting a first inverted signal; the parameter measurement unit module is further used for sending a second step signal after the first step signal is sent for a preset time length; a superposition module connected with the inverting module and the parameter measurement unit module respectively, the superposition module being used for receiving the first inverted signal and the second step signal, adding the first inverted signal and the second step signal, and outputting a first superposition signal; and the parameter measurement unit module is further used for receiving the first superposition signal and obtaining the setting time of the inverting operational amplifier based on the analysis result of the first superposition signal. In this way, the test result is more accurate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of operational amplifier testing, and particularly relates to a device, a method and a medium for setting time testing. BACKGROUND

[0002] The testing index of an operational amplifier (OPA) chip includes setting time. The setting time is used to represent the time required for the output of the operational amplifier to transit from one stable state to another stable state. The setting time is crucial for ensuring that the signal is accurately transmitted.

[0003] For the testing of the setting time, a step signal is usually applied to the input end of the operational amplifier, and an oscilloscope is used to capture the step signal of the output of the operational amplifier. The jump point of 50% of the value of the step signal applied to the input end of the operational amplifier can be taken as the starting point of the testing of the setting time, and the time from the jump point to the final stable state of the target value error band (for example, the target value ±0.01%) of the measured step signal of the output of the operational amplifier is the setting time.

[0004] However, in the process of the testing of the setting time, the external oscilloscope and signal source are connected to the testing link, which increases the complexity of the testing link and affects the testing result of the setting time to some extent, resulting in inaccurate testing result of the setting time. SUMMARY

[0005] Therefore, the present application provides a device, a method and a medium for setting time testing, so as to solve the problem that the external oscilloscope and signal source are connected to the testing link in the process of the testing of the setting time, which increases the complexity of the testing link and affects the testing result of the setting time to some extent, resulting in inaccurate testing result of the setting time.

[0006] In a first aspect, the present application provides a device for setting time testing, which comprises: a parameter measurement unit module, configured to send a first step signal; an inverting module connected with the parameter measurement unit module, configured to receive the first step signal, perform phase inversion on the first step signal based on an inverting operational amplifier, and output a first inverted signal; the parameter measurement unit module is further configured to send a second step signal after the first step signal is sent for a preset time length; a superposition module connected with the inverting module and the parameter measurement unit module respectively, configured to receive the first inverted signal and the second step signal, add the first inverted signal and the second step signal, and output a first superposition signal; and the parameter measurement unit module is further connected with the superposition module, and the parameter measurement unit module is further configured to receive the first superposition signal, and obtain the setting time of the inverting operational amplifier based on the analysis result of the first superposition signal.

[0007] In an alternative embodiment, the device further comprises a first signal conditioning module and a second signal conditioning module; the first signal conditioning module is connected with the parameter measurement unit module, and is configured to receive the first step signal and reduce the jitter amplitude of the first step signal to output a first test signal; the inverting module is connected with the parameter measurement unit module based on the first signal conditioning module, and is further configured to receive the first test signal, perform phase inversion on the first test signal based on the inverting operational amplifier, and output a second inverted signal; the second signal conditioning module is connected with the parameter measurement unit module, and is configured to receive the second step signal and reduce the jitter amplitude of the second step signal to output a second test signal; the superposition module is connected with the parameter measurement unit module based on the second signal conditioning module, and is further configured to receive the second inverted signal and the second test signal, add the second inverted signal and the second test signal, and output a second superposition signal; the parameter measurement unit module is further configured to receive the second superposition signal, and obtain the setup time of the inverting operational amplifier signal source conditioning based on analysis of the second superposition signal.

[0008] In an alternative embodiment, the device further comprises: the parameter measurement unit module sends the first step signal, the first step signal passes through the first signal conditioning module and the inverting module, and outputs the second inverted signal; the parameter measurement unit module sends a third step signal at the same time in the case of sending the first step signal, and outputs a third test signal after the third step signal passes through the second signal conditioning module to reduce the jitter amplitude; the superposition module adds the second inverted signal and the third test signal to output a third superposition signal; the parameter measurement unit module analyzes the third superposition signal, and if the absolute value of the maximum voltage in the third superposition signal is greater than a preset voltage threshold, the following delay process is performed: the parameter measurement unit module sends the first step signal again, and sends a delay step signal after a preset time step delay after sending the first step signal, and outputs a delay test signal after the delay step signal passes through the second signal conditioning module to reduce the jitter amplitude; the superposition module adds the second inverted signal and the delay test signal to output a delay superposition signal; the parameter measurement unit module analyzes the delay superposition signal, and repeats the delay process until the absolute value of the maximum voltage in the delay superposition signal is less than or equal to the preset voltage threshold; and the preset time length is determined based on the cumulative result of the preset time step in the delay process.

[0009] In an alternative embodiment, the parameter measurement unit module, based on the analysis of the second superimposed signal, obtains the establishment time of the inverting operational amplifier signal source after conditioning, comprising: determining the test start time based on the time corresponding to the first preset voltage value in the second superimposed signal, wherein the first preset voltage value is determined based on the first step signal; dividing the second superimposed signal based on the first division time length to obtain a plurality of first division time length signals, in each of the first division time length signals, if the absolute value of the voltage value is greater than a preset voltage threshold, it is determined that the first division time length signal is a fluctuation segment, and if the absolute value of the voltage value is less than or equal to the preset voltage threshold, it is determined that the first division time length signal is a stable segment; in the previous fluctuation segment of the stable segment, the previous fluctuation segment of the stable segment is divided based on the second division time length to obtain a plurality of second division time length signals, in each of the second division time length signals, if the absolute value of the voltage value is greater than the preset voltage threshold, it is determined that the second division time length signal is the fluctuation segment, and if the absolute value of the voltage value is less than or equal to the preset voltage threshold, it is determined that the second division time length signal is a stable segment; the lengths of each stable segment and the preset length are added to obtain the establishment time of the inverting operational amplifier signal source after conditioning.

[0010] In an alternative embodiment, the inverting module comprises: a third resistor, a fourth resistor, a first inverting operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, a second inverting operational amplifier and an eighth resistor; one end of the third resistor is connected with the first signal conditioning module, the other end of the third resistor is connected with one end of the fourth resistor and the inverting input end of the first inverting operational amplifier respectively, the other end of the fourth resistor and the output end of the first inverting operational amplifier are connected with one end of the seventh resistor, and one end of the seventh resistor is also connected with the superimposed module; one end of the fifth resistor is connected with the second signal conditioning module, the other end of the fifth resistor is connected with one end of the sixth resistor and the inverting input end of the second inverting operational amplifier respectively, the other end of the sixth resistor and the output end of the second inverting operational amplifier are connected with one end of the eighth resistor; the non-inverting input end of the first inverting operational amplifier, the non-inverting input end of the second inverting operational amplifier, the other end of the seventh resistor and the other end of the eighth resistor are grounded.

[0011] In an alternative embodiment, the first signal conditioning module comprises a first Schottky diode, a second Schottky diode, a first resistor and a second resistor; wherein the parameter measurement unit module is connected to the anode of the first Schottky diode and the cathode of the second Schottky diode, respectively; the cathode of the first Schottky diode is connected to one end of the first resistor; the anode of the second Schottky diode is connected to one end of the second resistor; the anode of the second Schottky diode is also connected to one end of the third resistor; the other end of the first resistor and the other end of the second resistor are grounded; the second signal conditioning module comprises a third Schottky diode, a fourth Schottky diode, a ninth resistor and a tenth resistor; wherein the parameter measurement unit module is connected to the anode of the third Schottky diode and the cathode of the fourth Schottky diode, respectively; the cathode of the third Schottky diode is connected to one end of the ninth resistor; the anode of the fourth Schottky diode is connected to one end of the tenth resistor; the anode of the fourth Schottky diode is also connected to one end of the fifth resistor; the other end of the ninth resistor and the other end of the tenth resistor are grounded.

[0012] In an alternative embodiment, the superposition module comprises a sliding resistor, a fifth Schottky diode and a sixth Schottky diode; one end of the sliding resistor is connected to the anode of the fourth Schottky diode; the other end of the sliding resistor is connected to the output end of the first inverting operational amplifier; the middle sliding end of the sliding resistor is connected to the cathode of the fifth Schottky diode and the anode of the sixth Schottky diode, respectively; the anode of the fifth Schottky diode and the cathode of the sixth Schottky diode are grounded.

[0013] In a second aspect, the present application provides a method for establishing a time test, the method comprising: obtaining a first step signal sent by a parameter measurement unit module; inverting the phase of the first step signal based on an inverting operational amplifier to obtain a first inverted signal; obtaining a second step signal sent by the parameter measurement unit module after the first step signal is sent for a preset time length; adding the first inverted signal and the second step signal to obtain a first superposition signal; and obtaining the establishment time of the inverting operational amplifier based on the result of analyzing the first superposition signal by the parameter measurement unit module.

[0014] In an optional implementation, the method further comprises: after the first step signal is acquired, reducing the jitter amplitude of the first step signal to obtain a first test signal; inputting the first test signal into the inverting operational amplifier to perform phase inversion on the first test signal to obtain a second inverted signal; after the second step signal is acquired, reducing the jitter amplitude of the second step signal to obtain a second test signal; adding the second inverted signal and the second test signal to obtain a second superimposed signal; and obtaining the setup time of the inverting operational amplifier source conditioning based on a result of analysis on the second superimposed signal.

[0015] In a third aspect, the present application provides a computer device, comprising: a memory and a processor, which are communicatively connected with each other, and the memory stores computer instructions; the processor executes the computer instructions to perform the method for setup time test according to the first aspect or any one of the corresponding embodiments thereof.

[0016] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions for making a computer execute the method for setup time test according to the first aspect or any one of the corresponding embodiments thereof.

[0017] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions for making a computer execute the method for setup time test according to the first aspect or any one of the corresponding embodiments thereof.

[0018] The device, method and medium for setup time test provided by the present application are based on a parameter measurement unit module, which realizes the functions of signal triggering, delay control and signal analysis, replaces the signal source module and signal analysis module in the related art, can simplify the test link, improve matching, increase efficiency and improve the quality of test signals; compared with the multi-module discrete design, the integrated PMU module reduces the connection lines and interfaces between modules, reduces noise interference in the signal transmission process, and also reduces the test cost; in addition, the preset time delay control realized based on the parameter measurement unit module has higher control precision, so that the test result of the setup time is more accurate. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments or the related art, the drawings needed to be used in the specific embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0020] Figure 1 A structural schematic diagram of the device for establishing time test provided by the present application is shown;

[0021] Figure 2 Another structural schematic diagram of the device for establishing time test provided by the present application is shown;

[0022] Figure 3 A waveform schematic diagram of the third superimposed signal provided by the present application is shown;

[0023] Figure 4 Still another structural schematic diagram of the device for establishing time test provided by the present application is shown;

[0024] Figure 5 Still another structural schematic diagram of the device for establishing time test provided by the present application is shown;

[0025] Figure 6 A schematic diagram of the judgment result of the second superimposed signal in the present application is shown;

[0026] Figure 7 Another schematic diagram of the judgment result of the second superimposed signal in the present application is shown;

[0027] Figure 8 A flow schematic diagram of the method for establishing time test provided by the present application is shown;

[0028] Figure 9 A hardware structural schematic diagram of the computer device of the present application is shown. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0030] According to the embodiments of the present application, a device for establishing time test is provided, Figure 1 A structural schematic diagram of the device for establishing time test provided by the present application is shown, as used below, the term "module" can be a combination of software and / or hardware that realizes predetermined functions, although the device described in the following embodiments is preferably realized in software, the realization of hardware, or the combination of software and hardware is also possible and conceived.

[0031] As Figure 1As shown, the device for establishing time test provided by the application comprises a parameter measurement unit module 101 for sending a first step signal; an inverting module 102 connected with the parameter measurement unit module 101, the inverting module 102 is used for receiving the first step signal, performing phase inversion on the first step signal based on an inverting operational amplifier, and outputting a first inverted signal; the parameter measurement unit module 101 is used for sending a second step signal after the first step signal is sent for a preset time length; a superposition module 104 connected with the inverting module 102 and the parameter measurement unit module 101 respectively, the superposition module 104 is used for receiving the first inverted signal and the second step signal, adding the first inverted signal and the second step signal, and outputting a first superposition signal; the parameter measurement unit module 101 is also connected with the superposition module 104, and the parameter measurement unit module 101 is used for receiving the first superposition signal and obtaining the establishing time of the inverting operational amplifier based on the analysis result of the first superposition signal.

[0032] In the embodiment, the parameter measurement unit (PMU) module can be a semiconductor test instrument module, and the electrical performance of the chip pin is tested based on the PMU module, or PE (Pin Electronics) test is performed.

[0033] The inverting module 102 comprises an inverting operational amplifier, which is a device under test. The superposition module 104 comprises a signal addition circuit, which can perform linear superposition on the received first inverted signal and second step signal, and output a first superposition signal.

[0034] In the process of testing the inverting operational amplifier based on the device for establishing time test provided by the application, the parameter measurement unit module sends a first step signal to the inverting operational amplifier of the inverting module, the operational amplifier starts to respond, enters a dynamic establishing process, and outputs a first inverted signal. The parameter measurement unit module delays for a preset time length after sending the first step signal, sends a second step signal, adds the first inverted signal and the second step signal based on the superposition module, determines the time elapsed when the first superposition signal is stabilized to a target value or within a range allowed by test error based on the waveform of the first superposition signal, and the time is the establishing time of the inverting operational amplifier.

[0035] The device for establishing time test provided in the application is based on a parameter measurement unit module, realizes the functions of signal triggering, delay control and signal analysis, replaces the signal source module and the signal analysis module in the related art, can simplify the test link, improve matching, increase efficiency and improve the quality of test signals; meanwhile, compared with the multi-module discrete design, the integrated PMU module reduces the connection lines and interfaces between modules, reduces noise interference in the signal transmission process, and also reduces the test cost; in addition, the preset time delay control realized based on the parameter measurement unit module has higher control precision, so that the test result of the establishing time is more accurate.

[0036] The step signal sent by the parameter measurement unit module has a large jitter before the step signal tends to be stable. In the embodiment, before the parameter measurement unit module is used to test the measured operational amplifier, the signal source can be conditioned by the signal conditioning circuit, so as to reduce the jitter amplitude of the step signal.

[0037] Figure 2 Another structural schematic diagram of the device for establishing time test provided in the embodiment of the application is shown in FIG. 2. Figure 2 As shown in FIG. 2, in some optional embodiments, the device further includes a first signal conditioning module 201 and a second signal conditioning module 202; the first signal conditioning module 201 is connected with the parameter measurement unit module 101, the first signal conditioning module 201 is used to receive the first step signal, reduce the jitter amplitude of the first step signal, and output the first test signal; the inverting module 102 is connected with the parameter measurement unit module 101 based on the first signal conditioning module 201, the inverting module 102 is also used to receive the first test signal, perform phase inversion on the first test signal based on an inverting operational amplifier, and output the second inverted signal; the second signal conditioning module 202 is connected with the parameter measurement unit module 101, the second signal conditioning module 202 is used to receive the second step signal, reduce the jitter amplitude of the second step signal, and output the second test signal; the superposition module 104 is connected with the parameter measurement unit module 101 based on the second signal conditioning module 202, the superposition module 104 is also used to receive the second inverted signal and the second test signal, add the second inverted signal and the second test signal, and output the second superimposed signal; the parameter measurement unit module 101 is also used to receive the second superimposed signal, and obtain the establishing time of the inverting operational amplifier signal source conditioning based on analysis of the second superimposed signal.

[0038] In the embodiment, before the first step signal is input into the inverting module 102, the first step signal is conditioned by the first signal conditioning module 201, so as to reduce the jitter amplitude of the first step signal and obtain the first test signal with reduced jitter amplitude.

[0039] The first test signal is input into the inverting module 102, and the first test signal is phase-inverted by the inverting operational amplifier under test to obtain a second inverted signal.

[0040] The second step signal is output at intervals of a preset time length, and the second step signal is conditioned by the second signal conditioning module 202 before being input into the superposition module 104, so as to reduce the jitter amplitude of the second step signal and obtain a second test signal with reduced jitter amplitude.

[0041] The second inverted signal and the second test signal are added to output a second superposition signal, and the setup time of the inverting operational amplifier signal source after conditioning is obtained based on analysis of the second superposition signal.

[0042] In this way, the jitter of the step signal is reduced by the signal conditioning module, the input signal of the inverting operational amplifier is closer to the ideal state, and the accuracy of the setup time test result can be further improved. Meanwhile, the jump characteristics of the step signal are stabilized based on the signal conditioning module, the test results under the same conditions are more consistent, and the repeatability and reliability of the test can be improved. In addition, the signal conditioning module can process the step signal with poor quality to meet the test requirements, and the device for setup time test provided in the embodiment does not need to rely on a high-precision signal source, which can reduce the dependence of the device on external equipment and expand the applicability of the device.

[0043] In some optional embodiments, the device for setup time test described above further includes a parameter measurement unit module, which outputs a first step signal, the first step signal passes through a first signal conditioning module and an inverting module to output a second inverted signal; the parameter measurement unit module simultaneously outputs a third step signal when the first step signal is output, and the third step signal passes through a second signal conditioning module to reduce the jitter amplitude and then outputs a third test signal; a superposition module adds the second inverted signal and the third test signal to output a third superposition signal; the parameter measurement unit module analyzes the third superposition signal, and if the absolute value of the maximum voltage in the third superposition signal is greater than a preset voltage threshold, the following delay process is performed: the parameter measurement unit module outputs the first step signal again, and outputs a delay step signal after a delay of a preset time step from the output of the first step signal, the delay step signal passes through the second signal conditioning module to reduce the jitter amplitude and then outputs a delay test signal; the superposition module adds the second inverted signal and the delay test signal to output a delay superposition signal; the parameter measurement unit module analyzes the delay superposition signal and repeats the delay process until the absolute value of the maximum voltage in the delay superposition signal is less than or equal to the preset voltage threshold; and the preset time length is determined based on the cumulative result of the preset time step in the delay process.

[0044] In the first test process, the parameter measurement unit module simultaneously sends out a first step signal and a second step signal, the first step signal is input into the inverting module after the first signal conditioning module reduces the jitter amplitude, the phase is inverted based on the inverting operational amplifier, and the second inverted signal is output. The second step signal is output after the second signal conditioning module reduces the jitter amplitude. The second inverted signal and the third test signal are added, and the third superimposed signal is output. Figure 3 The waveform diagram of the third superimposed signal provided by the embodiment of the application is shown. As shown in Figure 3 The waveform diagram of the third superimposed signal, there is a wave peak 301 that is obviously different from the normal signal jitter. The absolute value of the voltage value of the wave peak 301 is greater than the preset voltage threshold value. The preset voltage threshold value can be determined based on the test requirements. Specifically, if a 2V step signal test is performed, the preset voltage threshold value can be configured as 2V.

[0045] In the second test process, the parameter measurement unit module sends out a delay step signal after a preset time step of the first step signal is sent out. The preset time step can be determined based on specific test requirements, for example, the preset time step can be configured as 0.1ns. The delay test signal is output after the delay step signal passes through the second signal conditioning module to reduce the jitter amplitude; the second inverted signal and the delay test signal are added by the superimposed module to output the delay superimposed signal. The wave peak in the delay superimposed signal waveform has a reduced absolute value of the voltage maximum value compared to Figure 3

[0046] In the subsequent test process, the delay step signal is sent out with a delay of a preset time step based on the last test each time. For example, in the third test process, the delay step signal is sent out with a delay of 0.2ns. Until the absolute value of the voltage maximum value in the delay superimposed signal is less than or equal to the preset voltage threshold value, at this time, the first wave peak in the delay superimposed signal waveform is completely within the setup time test error band. Based on the accumulation result of the preset time step in the delay process, the preset time length e is determined.

[0047] In the specific test process, if the voltage value of the tested step signal is a first voltage value, the voltage value of the step signal sent out by the parameter measurement unit module is a second voltage value, and the absolute value of the second voltage value is greater than the absolute value of the first voltage value. In this way, the problem of the influence of the diode breakdown voltage existing in the circuit on the voltage value of the step signal can be avoided.

[0048] In this way, the preset time length is obtained through dynamic calculation, which can automatically adapt to the response characteristics of different operational amplifiers, and can generate a preset time length matching the current measured operational amplifier without manual intervention, thereby significantly improving the compatibility and universality of the device.

[0049] ​Figure 4 Another structural schematic diagram of the device for establishing time test provided by the embodiment of the application is shown. As shown in the figure, Figure 4 In some optional embodiments, the inverting module comprises a third resistor R3, a fourth resistor R4, a first inverting operational amplifier N1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second inverting operational amplifier N2, and an eighth resistor R8. One end of the third resistor R3 is connected with the first signal conditioning module 201, and the other end of the third resistor R3 is connected with one end of the fourth resistor R4 and the inverting input end of the first inverting operational amplifier N1, respectively. The other end of the fourth resistor R4 and the output end of the first inverting operational amplifier N1 are connected with one end of the seventh resistor R7, and one end of the seventh resistor R7 is also connected with the superposition module. One end of the fifth resistor R5 is connected with the second signal conditioning module 202, and the other end of the fifth resistor R5 is connected with one end of the sixth resistor R6 and the inverting input end of the second inverting operational amplifier N2, respectively. The other end of the sixth resistor R6 and the output end of the second inverting operational amplifier N2 are connected with one end of the eighth resistor R8. The non-inverting input end of the first inverting operational amplifier N1, the non-inverting input end of the second inverting operational amplifier N2, the other end of the seventh resistor R7, and the other end of the eighth resistor R8 are grounded.

[0050] In the embodiment, D1, D2, D3, D4, D5, and D6 are Schottky diodes, which are only turned on when the anode voltage is greater than the cathode voltage; R1, R2, R3, R4, R5, R6, R7, R8, R9, and R10 are constant resistors. The seventh resistor R7 is used as an output load resistor on the one hand, and is grounded on the other hand to form a DC loop, thereby avoiding noise interference caused by the floating output end of the first inverting operational amplifier N1. Similarly, the eighth resistor R8 is used to stabilize the output voltage of the second inverting operational amplifier N2 and provide a grounding loop.

[0051] Specifically, a first test signal of -2V to 0V is input at one end of the third resistor R3, and a second reverse signal of 0V to 2V can be collected at the other end of the fourth resistor R4 after a certain degree of delay.

[0052] In this way, the phase inversion of the input signal is strictly guaranteed by the negative feedback structure of the inverting operational amplifier. Meanwhile, the non-inverting input end is grounded, thereby providing a stable DC bias reference for the operational amplifier, avoiding output errors caused by common-mode voltage drift, and making the circuit stable and highly adaptable.

[0053] Figure 5 Another structural schematic diagram of the device for establishing time test provided by the embodiment of the application is shown. As shown in the figure, Figure 5As shown in some optional embodiments, the first signal conditioning module 201 comprises: a first Schottky diode D1, a second Schottky diode D2, a first resistor R1 and a second resistor R2; wherein the parameter measurement unit module 101 is connected with the anode of the first Schottky diode D1 and the cathode of the second Schottky diode D2 respectively, the cathode of the first Schottky diode D1 is connected with one end of the first resistor R1, the anode of the second Schottky diode D2 is connected with one end of the second resistor R2, the anode of the second Schottky diode D2 is also connected with one end of the third resistor R3, the other end of the first resistor R1 and the other end of the second resistor R2 are grounded.

[0054] The second signal conditioning module 202 comprises: a third Schottky diode D3, a fourth Schottky diode D4, a ninth resistor R9 and a tenth resistor R10; wherein the parameter measurement unit module 101 is connected with the anode of the third Schottky diode D3 and the cathode of the fourth Schottky diode D4 respectively, the cathode of the third Schottky diode D3 is connected with one end of the ninth resistor R9, the anode of the fourth Schottky diode D4 is connected with one end of the tenth resistor R10, the anode of the fourth Schottky diode D4 is also connected with one end of the fifth resistor R5, the other end of the ninth resistor R9 and the other end of the tenth resistor R10 are grounded.

[0055] In the present embodiment, the first signal conditioning module 201 and the second signal conditioning module 202 have the same circuit structure and the same working principle. The working principle of the signal source conditioning circuit is exemplarily described below by taking the first signal conditioning module 201 as an example.

[0056] The parameter measurement unit module 101 generates a first step signal with a voltage value of -2.3V to 1V. In the case that the voltage value of the first step signal is -2.3V, D1 is off and D2 is on. However, since D2 has a small voltage drop, if the voltage drop is 0.3V, the voltage value of B end is -2V.

[0057] In the case that the voltage value of the first step signal jumps to 1V, D1 is on and D2 is off, and the voltage value of B end is 0V. B end can output a first test signal with a voltage value of -2V to 0V after being conditioned and having a small jitter. The step signal emitted by the PMU has a large jitter before the signal tends to be stable. The signal emitted by the PMU can be conditioned by the first and second signal source conditioning modules before being measured by the PMU, so as to reduce the jitter amplitude of the step signal emitted by the PMU.

[0058] For the inverting module 102, as shown in Figure 5 if a step signal with a voltage value of -2V to 0V is input at B end, a step signal with a voltage value of 2V to 0V can be collected at C end after a certain time delay.

[0059] The circuit structure of the second signal conditioning module 202 is the same as that of the first signal conditioning module 201. It performs the same bidirectional amplitude limiting and current limiting processing on the second step signal output by the parameter measurement unit module 101, which can ensure that the conditioning standards of the second test signal and the first test signal are consistent and avoid subsequent superposition errors caused by the difference in preprocessing of the two signals.

[0060] In this way, the low on-voltage and fast response characteristics of the Schottky diode can accurately clamp the positive or negative overshoot or random jitter of the step signal, especially the amplitude fluctuation during high-speed transitions, making the output first and second test signals closer to the ideal step waveform. At the same time, it can provide high-quality input for the accurate inversion processing of the inverting module and the signal cancellation of the superposition module, which can improve the accuracy of the basic signal for settling time testing.

[0061] like Figure 5 As shown, in some optional embodiments, the superposition module 104 includes: a sliding rheostat R11, a fifth Schottky diode D5, and a sixth Schottky diode D6; one end of the sliding rheostat R11 is connected to the anode of the fourth Schottky diode D4; the other end of the sliding rheostat R11 is connected to the output terminal of the first inverting operational amplifier N1; the middle sliding end of the sliding rheostat R11 is connected to the cathode of the fifth Schottky diode D5 and the anode of the sixth Schottky diode D6, respectively, and the anode of the fifth Schottky diode D5 and the cathode of the sixth Schottky diode D6 are grounded.

[0062] In this embodiment, the superposition module 104 has two input signals: one is the second test signal from the second signal conditioning module, which is connected to one end of the sliding rheostat R11; the other is the second inverted signal from the inverting module, which is connected to the other end of the sliding rheostat R11. The sliding rheostat R11 achieves the superposition of the two signals through the middle sliding end.

[0063] The fifth Schottky diode, D5, and the sixth Schottky diode, D6, form a bidirectional limiting circuit, connected to the middle sliding terminal of the variable resistor. When the superimposed signal is a positive voltage and exceeds the turn-on voltage of D5, D5 conducts, clamping the positive voltage near its turn-on voltage to suppress positive overshoot or noise. When the superimposed signal is a negative voltage and its absolute value exceeds the turn-on voltage of D6, D6 conducts, clamping the negative voltage near its turn-on voltage to suppress negative overshoot or noise. This avoids measurement errors in subsequent signal analysis modules caused by excessive signal amplitude or sudden noise.

[0064] The overlay module 104 can shorten the measurement range. If the original range is 2V, after passing through the overlay module 104, the range can be shortened to 0.8V, or from -0.4V to 0.4V, which can meet the test requirements for smaller resolution settling time.

[0065] In this way, the bidirectional limiting action of the fifth and sixth Schottky diodes can effectively filter out positive or negative overshoot, high-frequency noise or burst interference in the superimposed signal; at the same time, the fast response characteristic of the Schottky diode can adapt to high-speed superimposed signals, avoiding the introduction of additional delay or signal distortion in the limiting process.

[0066] In some optional embodiments, the parameter measurement unit module obtains the setup time of the inverting operational amplifier signal source after conditioning based on analysis of the second superimposed signal, including: determining a test start time based on a time corresponding to a voltage value of a first preset voltage value in the second superimposed signal, wherein the first preset voltage value is determined based on the first step signal; dividing the second superimposed signal based on a first division time length to obtain a plurality of signals of the first division time length, in each of the signals of the first division time length, if the absolute value of the voltage value is greater than a preset voltage threshold, determining that the signal of the first division time length is a fluctuation segment, and if the absolute value of the voltage value is less than or equal to the preset voltage threshold, determining that the signal of the first division time length is a stable segment; dividing a preceding fluctuation segment of the stable segment based on a second division time length to obtain a plurality of signals of the second division time length in the preceding fluctuation segment of the stable segment, in each of the signals of the second division time length, if the absolute value of the voltage value is greater than the preset voltage threshold, determining that the signal of the second division time length is a fluctuation segment, and if the absolute value of the voltage value is less than or equal to the preset voltage threshold, determining that the signal of the second division time length is a stable segment; and adding the time length of each stable segment to a preset time length to obtain the setup time of the inverting operational amplifier signal source after conditioning.

[0067] In the present embodiment, the first preset voltage value can be determined as 50% of the input pulse, i.e. -1V, based on the voltage value of the first step signal, -2V to 0V. The time corresponding to the first preset voltage value -1V is determined as the test start time t0.

[0068] The setup time of the inverting operational amplifier signal source after conditioning is more accurate than the setup time of the inverting operational amplifier without conditioning. In the present embodiment, the test process of the setup time is exemplarily described based on the analysis process of the parameter measurement unit module on the second superimposed signal.

[0069] The typical value or standard value of the settling time of the tested operational amplifier can be determined before testing the operational amplifier. In the embodiment, the typical value of the settling time of the tested operational amplifier is 24 ns. The error band can be configured in the PMU, and the upper limit and lower limit of the error band are used as the standard for judging whether the step signal is stable. For example, if the test accuracy requirement is 0.01% of the range, the error band can be configured as -0.2 mV~0.2 mV, and -0.2 mV can be used as the lower limit of the error band and 0.2 mV can be used as the upper limit of the error band. In the waveform of the second superimposed signal, the mark H is used for indicating that the signal exceeds the upper limit of the error band, the mark L is used for indicating that the signal exceeds the lower limit of the error band, and the mark M is used for indicating that the signal is in the middle of the error band. When the signal waveforms in the signal segments are all in the error band, the signal segments are determined as stable segments, and the signal segments can be marked as Pass. Otherwise, the signal segments can be marked as Fail.

[0070] In the process of analyzing the first superimposed signal, there is no source conditioning process, and the principles of other parts are the same as those in the analysis process of the second superimposed signal, which will not be described here.

[0071] The first preset voltage value can be a voltage value corresponding to 50% of the rising edge of the signal collected at the B terminal. Figure 6 A schematic diagram of the judgment result of the second superimposed signal in the embodiment is shown. Figure 6 As shown in the figure, the first division duration can be configured as 10 ns. The signal of the first segment 601 is determined as Fail, indicating that the first segment is a fluctuation segment, and the signal of the first segment 601 does not reach a stable state. Similarly, the signals of the second segment 602 and the third segment 603 also do not reach a stable state. The signal of the fourth segment 604 is determined as Pass, indicating that the signal of the fourth segment 604 has reached a stable state. It can be known that the stable point is in the previous fluctuation segment of the stable segment, that is, the third segment 603.

[0072] Figure 7 Another schematic diagram of the judgment result of the second superimposed signal in the embodiment is shown. Figure 7 As shown in the figure, a judgment band can be configured in the third segment 603 based on the second division duration, for example, 1 ns. The starting point of the judgment band is RN0, and the ending point RN1 is the time point at which the third segment ends. If RN0=1 ns, it is determined whether the result of the judgment band is Pass or Fail. The judgment mechanism is the same as before. If the judgment result is Fail, RN0=2 ns. If the judgment result is Fail, RN0=3 ns. If the judgment result is Fail, RN0=4 ns. If the judgment result is Pass, the stable time can be calculated as 10+10+4=24 ns. If the delay time is 0.3 ns, the settling time is the sum of the stable time and the preset duration (that is, the delay time), that is, 24.3 ns.

[0073] Thus, without manual marking of time points or determining stable moments, random errors caused by subjective experience differences of operators are completely eliminated, the result deviation of multiple tests of the same device is smaller, the repeatability and reliability of the test are significantly improved, and the method is especially suitable for consistency detection in batch production.

[0074] The parameter measurement unit module is adopted to perform the setup time test, the test link is simplified, the matching efficiency and the quality of the test signal can be improved, the PMU is directly integrated in the test link, compared with a scheme requiring an external oscilloscope and a signal source, the link complexity is reduced, and the system development cost is also reduced; in addition, the parameter measurement unit has multiple channels, and the test efficiency can be significantly improved.

[0075] Specifically, the standard PMU usually has at least 32 channels, and some models can support 128, 256 or even 512 channels, and multiple groups of operational amplifier chips can be tested at the same time, so that the test throughput can be greatly improved; the oscilloscope in the related art usually only provides 2 or 4 channels, and there is an obvious limitation in test efficiency.

[0076] According to the embodiment of the application, a method for setup time test is provided, it should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0077] In the embodiment, a method for setup time test is provided, which can be used in the device for setup time test described above, Figure 8 The flowchart of the method for setup time test of the embodiment of the application is shown, as shown in the figure, the flow includes the following steps: Figure 8

[0078] In step S801, a first step signal sent by a parameter measurement unit module is acquired.

[0079] In step S802, the first step signal is phase-inverted based on an inverting operational amplifier to obtain a first inverted signal.

[0080] In step S803, a second step signal sent by the parameter measurement unit module is acquired after the first step signal is sent for a preset time length.

[0081] In step S804, the first inverted signal and the second step signal are added to obtain a first superimposed signal, and the setup time of the inverting operational amplifier is obtained based on the analysis result of the parameter measurement unit module on the first superimposed signal.

[0082] ​The method for establishing time test provided in the embodiment is based on a parameter measurement unit module, realizes the functions of signal triggering, delay control and signal analysis, replaces the signal source module and the signal analysis module in the related art, can simplify a test link, improves matching, improves efficiency and improves the quality of a test signal; meanwhile, compared with a multi-module discrete design, the integrated PMU module reduces the connection lines and interfaces between modules, reduces noise interference in a signal transmission process, and also reduces test cost; in addition, the preset time delay control realized based on the parameter measurement unit module has higher control precision, so that the test result of the establishing time is more accurate.

[0083] In some optional embodiments, the foregoing method for establishing time test further includes: after the first step signal is acquired, reducing the jitter amplitude of the first step signal to obtain a first test signal; inputting the first test signal into an inverting operational amplifier to perform phase inversion on the first test signal to obtain a second inverted signal; after the second step signal is acquired, reducing the jitter amplitude of the second step signal to obtain a second test signal; adding the second inverted signal and the second test signal to obtain a second superimposed signal; and based on the analysis result of the second superimposed signal, obtaining the establishing time after the inverting operational amplifier signal source is conditioned.

[0084] The device for establishing time test in the embodiment is presented in the form of a functional unit, and the unit herein refers to an Application Specific Integrated Circuit (ASIC) circuit, a processor and a memory executing one or more software or fixed programs, and / or other devices that can provide the above functions.

[0085] The embodiment of the application further provides a computer device having the device for establishing time test shown in the foregoing Figure 1 .

[0086] Please refer to Figure 9 , Figure 9 is a structural schematic diagram of a computer device provided in an optional embodiment of the application, as shown in Figure 9As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0087] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0088] The aforementioned memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0089] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0090] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0091] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 can be connected by a bus or other means, Figure 9 The bus connection is taken as an example.

[0092] The input device 30 can receive inputted digital or character information, and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (such as a light-emitting diode), a tactile feedback device (such as a vibration motor), etc. The display device includes but is not limited to a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0093] The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller or the programmable hardware include a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor or the hardware, the method shown in the above embodiments is implemented.

[0094] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, the operation of the computer can invoke or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc. Correspondingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer executes the corresponding compiled program after compiling the instructions, or the computer reads and executes the instructions, or the computer executes the corresponding installed program after reading and installing the instructions. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0095] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the application, and that such modifications and changes fall within the scope of the appended claims.

Claims

1. An apparatus for establishing a time test, characterized by, The device comprises: a parameter measurement unit module for sending a first step signal; an inverting module connected with the parameter measurement unit module, the inverting module being configured to receive the first step signal, perform phase inversion on the first step signal based on an inverting operational amplifier, and output a first inverted signal; the parameter measurement unit module is further configured to send a second step signal after the first step signal is sent for a preset time length; a superposition module connected with the inverting module and the parameter measurement unit module respectively, the superposition module being configured to receive the first inverted signal and the second step signal, add the first inverted signal and the second step signal, and output a first superposition signal; the parameter measurement unit module is further connected with the superposition module, and is further configured to receive the first superposition signal, analyze the waveform of the first superposition signal, determine the time taken for the first superposition signal to stabilize to a target value or the time taken for the first superposition signal to stabilize to a range allowed by a test error, and represent the setup time of the inverting operational amplifier based on the time.

2. The apparatus of claim 1, wherein, The device further comprises a first signal conditioning module and a second signal conditioning module; the first signal conditioning module is connected with the parameter measurement unit module, and is configured to receive the first step signal, reduce the jitter amplitude of the first step signal, and output a first test signal; the inverting module is connected with the first signal conditioning module and the parameter measurement unit module, and is further configured to receive the first test signal, perform phase inversion on the first test signal based on the inverting operational amplifier, and output a second inverted signal; the second signal conditioning module is connected with the parameter measurement unit module, and is configured to receive the second step signal, reduce the jitter amplitude of the second step signal, and output a second test signal; the superposition module is connected with the second signal conditioning module and the parameter measurement unit module, and is further configured to receive the second inverted signal and the second test signal, add the second inverted signal and the second test signal, and output a second superposition signal; the parameter measurement unit module is further configured to receive the second superposition signal, and obtain the setup time of the inverting operational amplifier after source conditioning based on analysis of the second superposition signal.

3. The apparatus of claim 2, wherein, The device further comprises: the parameter measurement unit module sends the first step signal, the first step signal passes through the first signal conditioning module and the inverting module, and outputs the second inverted signal; the parameter measurement unit module sends a third step signal at the same time in the case of sending the first step signal, and outputs a third test signal after the third step signal passes through the second signal conditioning module to reduce the jitter amplitude; the superposition module adds the second inverted signal and the third test signal, and outputs a third superposition signal; The parameter measurement unit module analyzes the third superimposed signal, and if the absolute value of the maximum voltage in the third superimposed signal is greater than a preset voltage threshold, the following delay process is performed: Based on the parameter measurement unit module, the first step signal is sent again, and after the first step signal is sent, a delay step signal is sent after a preset time step, and the delay step signal is output after the jitter amplitude of the delay step signal is reduced by the second signal conditioning module; the superimposed module adds the second inverted signal and the delay test signal to output a delay superimposed signal; the parameter measurement unit module analyzes the delay superimposed signal, and repeats the delay process until the absolute value of the maximum voltage in the delay superimposed signal is less than or equal to the preset voltage threshold; Based on the accumulation result of the preset time step in the delay process, the preset time length is determined.

4. The apparatus of claim 2, wherein, Based on the analysis of the second superimposed signal, the parameter measurement unit module obtains the establishment time of the inverting operational amplifier signal source after conditioning, including: Based on the time corresponding to the voltage value being a first preset voltage value in the second superimposed signal, a test start time is determined, wherein the first preset voltage value is determined based on the first step signal; Based on a first division time length, the second superimposed signal is divided to obtain a plurality of signals of the first division time length, and in each of the signals of the first division time length, if the absolute value of the voltage value is greater than a preset voltage threshold, the signal of the first division time length is determined to be a fluctuation segment, and if the absolute value of the voltage value is less than or equal to the preset voltage threshold, the signal of the first division time length is determined to be a stable segment; In the preceding fluctuation segment of the stable segment, based on a second division time length, the preceding fluctuation segment of the stable segment is divided to obtain a plurality of signals of the second division time length, and in each of the signals of the second division time length, if the absolute value of the voltage value is greater than the preset voltage threshold, the signal of the second division time length is determined to be the fluctuation segment, and if the absolute value of the voltage value is less than or equal to the preset voltage threshold, the signal of the second division time length is determined to be a stable segment; The time lengths of each of the stable segments are accumulated with the preset time length to obtain the establishment time of the inverting operational amplifier signal source after conditioning.

5. The apparatus of claim 2, wherein, The inverting module includes: A third resistor, a fourth resistor, a first inverting operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, a second inverting operational amplifier, and an eighth resistor; One end of the third resistor is connected with the first signal conditioning module, and the other end of the third resistor is connected with one end of the fourth resistor and an inverting input end of the first inverting operational amplifier, respectively; the other end of the fourth resistor and an output end of the first inverting operational amplifier are connected with one end of the seventh resistor, and one end of the seventh resistor is also connected with the superimposed module; One end of the fifth resistor is connected with the second signal conditioning module, and the other end of the fifth resistor is connected with one end of the sixth resistor and the inverting input end of the second inverting operational amplifier respectively, and the other end of the sixth resistor and the output end of the second inverting operational amplifier are connected with one end of the eighth resistor; The non-inverting input end of the first inverting operational amplifier, the non-inverting input end of the second inverting operational amplifier, the other end of the seventh resistor and the other end of the eighth resistor are grounded.

6. The apparatus of claim 5, wherein, The first signal conditioning module comprises a first Schottky diode, a second Schottky diode, a first resistor and a second resistor; The parameter measurement unit module is connected with the anode of the first Schottky diode and the cathode of the second Schottky diode respectively, the cathode of the first Schottky diode is connected with one end of the first resistor, the anode of the second Schottky diode is connected with one end of the second resistor, the anode of the second Schottky diode is also connected with one end of the third resistor, and the other end of the first resistor and the other end of the second resistor are grounded. The second signal conditioning module comprises a third Schottky diode, a fourth Schottky diode, a ninth resistor and a tenth resistor; The parameter measurement unit module is connected with the anode of the third Schottky diode and the cathode of the fourth Schottky diode respectively, the cathode of the third Schottky diode is connected with one end of the ninth resistor, the anode of the fourth Schottky diode is connected with one end of the tenth resistor, the anode of the fourth Schottky diode is also connected with one end of the fifth resistor, and the other end of the ninth resistor and the other end of the tenth resistor are grounded.

7. The apparatus of claim 6, wherein, The superposition module comprises: a sliding resistor, a fifth Schottky diode and a sixth Schottky diode; One end of the sliding resistor is connected with the anode of the fourth Schottky diode; The other end of the sliding resistor is connected with the output end of the first inverting operational amplifier; The middle sliding end of the sliding resistor is connected with the cathode of the fifth Schottky diode and the anode of the sixth Schottky diode respectively, and the anode of the fifth Schottky diode and the cathode of the sixth Schottky diode are grounded.

8. A method for establishing a time test, characterized by, The method comprises: acquiring a first step signal sent by a parameter measurement unit module; phase-inverting the first step signal based on an inverting operational amplifier to obtain a first inverted signal; acquiring a second step signal sent by the parameter measurement unit module after the first step signal is sent for a preset time length; adding the first inverted signal and the second step signal to obtain a first superposition signal, and analyzing a waveform of the first superposition signal based on the parameter measurement unit module to determine a time taken for the first superposition signal to stabilize to a target value or a time taken for the first superposition signal to stabilize to a range allowed by a test error, and the time represents a build-up time of the inverting operational amplifier.

9. The method of claim 8, wherein, The method further comprises: After the first step signal is acquired, a jitter amplitude of the first step signal is reduced to obtain a first test signal; the first test signal is input into the inverting operational amplifier, and the first test signal is phase-inverted to obtain a second inverted signal; After the second step signal is acquired, a jitter amplitude of the second step signal is reduced to obtain a second test signal; the second inverted signal and the second test signal are added to obtain a second superimposed signal; and based on a result of analysis on the second superimposed signal, an establishment time of the inverting operational amplifier source conditioning is obtained.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium has stored thereon computer instructions for causing a computer to execute the method for establishment time testing according to claim 8 or 9. The computer readable storage medium has stored thereon computer instructions for causing a computer to execute the method for establishment time testing according to claim 8 or 9.

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