Photolithography techniques for high-density interconnection of multiple chips

Abstract

This application discloses a photolithography method for achieving high-density interconnection of multiple chips, including: acquiring a substrate map reflecting the positional distribution information of existing patterned units on a substrate to be exposed; generating a sub-map based on the substrate map reflecting the positional distribution information of existing patterned units on the substrate to be exposed by a mask; the mask being provided with layout information for interconnecting at least two chips in a set direction; loading the mask onto a mask stage of a photolithography apparatus and biasing it; loading the substrate onto a stage of the photolithography apparatus and aligning it using a first alignment mark; controlling the stage to move according to a set direction and path based on the sub-map, and aligning and biasing the mask with the existing patterned units to be exposed using a second alignment mark, so as to transfer the mask pattern to the corresponding exposure area, thereby realizing multi-chip interconnection.

Description

Technical Field

[0001] This application relates to the field of lithography machine technology, specifically to a method for implementing lithography technology with high-density interconnection of multiple chips. Background Technology

[0002] In modern semiconductor manufacturing, photolithography is a crucial step in realizing high-density integrated circuits. The photolithography process precisely transfers a pattern from a photomask onto a photoresist surface on a silicon wafer to form the desired circuit structure. With the continuous increase in the integration density of integrated circuits, the requirements for the minimum critical dimension (CD) are becoming increasingly stringent. In the pattern exposure of a photolithography machine, the theoretical limit of the minimum critical dimension can be given by Rayleigh's rule for resolution, as shown in equation (1):

[0003] Formula (1)

[0004] in, It refers to the wavelength of the light source used in the lithography machine. It is the numerical aperture of the projection system in a lithography machine used for exposure. It is an adjustment factor dependent on the photolithography process, also known as the Rayleigh constant. This is the minimum size of the graphic. From formula (1), we can see that there are three main ways to reduce the minimum size of the graphic: shortening the exposure wavelength... Increase numerical aperture or reduce Reducing the minimum pattern size through the three methods mentioned above is too difficult and costly. Furthermore, as device dimensions continue to shrink, leakage current problems caused by quantum tunneling become increasingly severe, limiting the feasibility of further reducing the minimum pattern size. Therefore, simply relying on reducing the critical dimensions of the device to increase the number of transistors is no longer feasible.

[0005] To accommodate more transistors, manufacturing larger chips has become extremely important. However, the maximum exposure field size of traditional lithography machines is limited to approximately 26mm × 33mm, which cannot meet the demand for manufacturing larger chips. While large exposure fields have been achieved in some LCD panel applications, the resulting line sizes are too wide, making it difficult to meet the high-density integration requirements of integrated circuits. Therefore, how to achieve high-density interconnection of multiple chips (such as multiple chips around 26mm × 33mm in size, or 25mm × 32mm) has become a pressing technical problem in lithography. Summary of the Invention

[0006] This application provides a photolithography method for high-density interconnection of multiple chips, a chip-level chip interconnection method, a method for fabricating mask lines, and a photolithography apparatus. This enables high-density interconnection of multiple chips, thereby forming a large-size chip, providing photolithography support for the high-density interconnection and integration of M×N large chips. The specific solution is as follows:

[0007] In a first aspect, embodiments of this application provide a photolithography method for achieving high-density interconnection of multiple chips, including:

[0008] Obtain a substrate map, which reflects the positional distribution information of the original pattern units on the substrate to be exposed;

[0009] For the mask to be loaded, a sub-map is generated based on the substrate map; the sub-map is used to reflect the positional distribution information of the original pattern units that need to be exposed on the substrate; the mask is provided with layout information for interconnecting at least two chips in a set direction;

[0010] The photomask is loaded onto the photomask stage of the photolithography equipment, and the photomask is offset by a preset offset distance;

[0011] The substrate is loaded onto the stage of the photolithography equipment, and a first alignment is performed using a first alignment mark on the substrate;

[0012] Based on the sub-map, the stage is controlled to move according to a set direction and path. The second alignment mark on the substrate aligns the mask with the original graphic unit on the substrate that needs to be exposed. The substrate is offset by a preset offset distance, and exposure is performed to transfer the preset graphic on the mask to the exposure area corresponding to the original graphic unit on the substrate that needs to be exposed.

[0013] Secondly, a chip-level chip interconnection method includes;

[0014] A substrate is provided on which a semiconductor structure comprising at least two semiconductor chips is formed, each semiconductor chip having an in-chip interconnect and no interconnect between the semiconductor chips;

[0015] The interconnection between the at least two semiconductor chips is achieved by means of photolithography technology as described in the first or second aspect.

[0016] Thirdly, embodiments of this application provide a method for creating mask lines, including:

[0017] A first line, a second line, and a third line are created on a photomask; the first line and the third line are connected, and the second line and the third line are connected.

[0018] Wherein, the first line of the mask is used to expose and form a first line as described in the first aspect in the first overlapping area of ​​the substrate; the second line of the mask is used to expose and form a second line as described in the first aspect in the first overlapping area of ​​the substrate; and the third line of the mask is used to expose and form a third line as described in the first aspect in the first overlapping area of ​​the substrate.

[0019] Fourthly, embodiments of this application provide a photolithography apparatus, including two mask stages, three or four stages, two upper and lower silicon wafer systems, and two silicon wafer measurement systems.

[0020] Compared with the prior art, this application has the following advantages:

[0021] This application provides a method for implementing high-density interconnection of multiple chips using photolithography, comprising the following steps: acquiring a substrate map, the substrate map reflecting the positional distribution information of existing pattern units on the substrate to be exposed; generating a sub-map based on the substrate map for a mask to be loaded; the sub-map reflecting the positional distribution information of existing pattern units on the substrate to be exposed by the mask; the mask being provided with layout information for interconnecting at least two chips in a set direction; loading the mask onto the mask stage of the photolithography equipment, offsetting the mask by a preset offset distance; loading the substrate onto the stage of the photolithography equipment, performing a first alignment using a first alignment mark on the substrate; controlling the stage to move according to a set direction and path based on the sub-map, aligning the mask with the existing pattern units on the substrate to be exposed by the mask using a second alignment mark on the substrate, offsetting the substrate by a preset offset distance, and performing exposure to transfer the preset pattern on the mask to the exposure area corresponding to the existing pattern units on the substrate to be exposed. In this way, the movement of the substrate can be controlled based on the sub-map, and the pattern of the mask can be transferred to the substrate so that at least two chips can be interconnected, thereby realizing high-density interconnection of multiple chips and forming a large-size chip. This provides photolithography technology support for the high-density interconnection and integration of M×N large chips (such as multiple chips of about 26mm×33mm size, such as 25mm×32mm chips).

[0022] Furthermore, in existing technologies, chip interconnection is mainly achieved through on-board level interconnection. This method typically involves interconnecting chips via a circuit board after packaging, resulting in a complex structure and large size. During use, signals need to travel along long circuit board paths, leading to significant signal delays. Long traces are also susceptible to electromagnetic interference, causing signal distortion. The longer traces and drive circuits also result in larger capacitive loads, inevitably increasing power consumption. Simultaneously, the larger trace and solder joint sizes limit the interconnection density between chips, and the need for larger communication drive circuits further restricts this density. In contrast, the photolithography method for high-density multi-chip interconnection provided in this application enables chip-level interconnection. This allows multiple chips to be connected simultaneously during chip manufacturing. During use, the shortened interconnection distance significantly reduces signal transmission time, lowers the risk of signal distortion, improves signal integrity, and reduces parasitic loads, thereby reducing power consumption. Furthermore, this invention directly uses existing high-performance lithography machines (such as DUV lithography machines and EUV lithography machines) to perform chip interconnect lithography, with the smallest line size reaching 0.1um or even a few nm, which can greatly improve the density of chip interconnect lines, ultimately forming a large chip with high-density chip interconnects (such as M×N×25mm×32mm) formed by M×N large chips (such as 25mm×32mm). Attached Figure Description

[0023] Figure 1 This is a structural diagram of an example of the photolithography equipment used in the photolithography technology implementation method for multi-chip high-density interconnection provided in the embodiments of this application.

[0024] Figure 2 This is a schematic diagram of an example of a substrate in the photolithography method for implementing high-density interconnection of multiple chips provided in the embodiments of this application.

[0025] Figure 3 This is a structural diagram of the lithography equipment based on the EUV light source provided in the embodiments of this application.

[0026] Figure 4 This is a structural diagram of another example of the photolithography equipment used in the photolithography technology implementation method provided in the embodiments of this application.

[0027] Figure 5 This is a flowchart of a photolithography method for implementing high-density interconnection of multiple chips provided in an embodiment of this application.

[0028] Figure 6 This is a schematic diagram illustrating an example of using a single mask to implement the interconnection of a 2×2 chipset in the photolithography method for high-density multi-chip interconnection provided in this application embodiment.

[0029] Figure 7 This is a schematic diagram illustrating an example of using two photomasks to achieve the interconnection of a 2×2 chipset in the photolithography technology implementation method for multi-chip high-density interconnection provided in the embodiments of this application.

[0030] Figure 8 This is a schematic diagram illustrating an example of using four photomasks to achieve the interconnection of a 2×2 chipset in the photolithography technology implementation method for multi-chip high-density interconnection provided in the embodiments of this application.

[0031] Figure 9 This is a schematic diagram of an example of an M×N chipset in the photolithography implementation method provided in the embodiments of this application.

[0032] Figure 10 This is a schematic diagram illustrating an example of the relative positional relationship between the original mask and the mask selected for exposure in the photolithography method for implementing multi-chip high-density interconnection provided in this application embodiment, as well as the positional relationship between the exposure area to be formed during exposure and the original pattern unit covered by the exposure area to be formed.

[0033] Figure 11 This is a schematic diagram of an example of a non-exposure pattern unit corresponding to a photomask in the photolithography implementation method provided in this application embodiment.

[0034] Figure 12 This is a schematic diagram of the sub-map corresponding to the first mask in the photolithography implementation method provided in the embodiments of this application.

[0035] Figure 13 This is a schematic diagram of an example of the first M×N chipset in the photolithography technology implementation method provided in the embodiments of this application.

[0036] Figure 14 This is a schematic diagram of an example of connecting two original pattern units with other photomasks in the photolithography implementation method provided in the embodiments of this application.

[0037] Figure 15 This is a schematic diagram of an example of the photolithography implementation method provided in this application, in which the exposure area of ​​the first mask is connected to three existing pattern units.

[0038] Figure 16 This is a schematic diagram illustrating an example of connecting the exposure areas of other photomasks to three existing graphic units in the photolithography implementation method provided in this application embodiment.

[0039] Figure 17 This is a schematic diagram illustrating an example of a photolithography implementation method provided in this application, where the exposure area of ​​each mask is connected to three existing pattern units.

[0040] Figure 18This is a schematic diagram illustrating an example of achieving a large exposure field using a photomask in the photolithography method provided in this application embodiment.

[0041] Figure 19 This is a schematic diagram of an example of a photolithography method provided in this application, in which the substrate includes original patterned units of different sizes.

[0042] Figure 20 This is a schematic diagram of an example of an original pattern unit including two sizes in the original pattern unit in the photolithography implementation method provided in the embodiments of this application.

[0043] Figure 21 This is a schematic diagram of an example of the first line, second line, and third line in the photolithography method for implementing high-density interconnection of multiple chips provided in the embodiments of this application.

[0044] Figure 22 This is a schematic diagram of an example of the fourth, fifth, and sixth lines in the photolithography method for implementing high-density interconnection of multiple chips provided in this application embodiment.

[0045] Figure 23 This is a schematic diagram illustrating an example of the overlap between the first and second overlapping regions in the photolithography method for implementing high-density multi-chip interconnection provided in this application.

[0046] Figure 24 This is a schematic diagram illustrating an example of a photolithography technique implementation method for multi-chip high-density interconnection provided in this application, in which the first overlapping region includes multiple sets of lines and the second overlapping region includes multiple sets of lines.

[0047] Figure 25 This is a schematic diagram illustrating an example of a photolithography technique implementation method for multi-chip high-density interconnection provided in this application, where the overlapping area includes multiple sets of lines. Detailed Implementation

[0048] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0049] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0050] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0051] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0052] It should be noted that the colored exposure areas in the accompanying drawings provided in this application are provided for the purpose of making the distinctions clearer and are not intended to limit this application.

[0053] Based on the reasons mentioned in the background art, in order to achieve high-density interconnection of multiple chips and thus form a large-size chip, this application provides a photolithography method for high-density interconnection of multiple chips and a chip-level chip interconnection method.

[0054] First, the application scenarios of the photolithography technology implementation method for multi-chip high-density interconnection and the chip-level chip interconnection method provided in the embodiments of this application are introduced:

[0055] The method provided in this application can be applied to top-layer or second-layer photolithography processes. Top-layer or second-layer photolithography processes are back-end steps in integrated circuit manufacturing, mainly used to form the topmost metal interconnects and contact holes. In the top-layer or second-layer photolithography process, the photolithography technology and chip-level chip interconnection method for multi-chip high-density interconnection provided in this application can be used to achieve multi-chip high-density interconnection, thereby forming a large-size chip.

[0056] For example, two adjacent integrated circuit patterns have already been formed on a substrate, each containing hole patterns formed through photolithography and etching processes. The interconnection between these two adjacent integrated circuit patterns can be achieved through the following steps: First, a metal layer (such as aluminum or copper) is deposited on the substrate surface. This metal layer connects to the existing metal pattern through the formed hole patterns and the connecting metal within the holes, thus achieving electrical connection between the upper and lower metal layers. Next, photolithography is used to expose the required interconnect pattern between the two adjacent integrated circuit patterns, and unwanted metal portions are removed by etching, leaving the interconnect lines. These interconnect lines cover the original hole patterns and vertically connect to the original integrated circuit metal layer through the hole patterns, reaching the lower circuit layer, thereby achieving electrical connection between the two adjacent integrated circuit patterns. Then, bonding pads are added so that the chip can connect to external circuits during subsequent packaging. Finally, the wafer is diced into individual chip units, each containing two adjacent integrated circuit patterns.

[0057] It should be noted that, generally, the top or second-top layer uses a positive photoresist process and an aluminum metal layer. Areas exposed (transmitted light) will be developed and the metal etched away, while unexposed areas retain the metal. Therefore, if the internal connections of each existing pattern unit (including the target pattern unit) use the same material as those used in this application, such as exposing the internal connections on the same photoresist layer or fabricating the lines on the same metal layer, or as... Figure 8When the method of this application is used to create internal connecting lines (including target graphic units), there is no need to consider the problem of metal layer coverage due to unexposed corresponding areas inside the original graphic units. If the internal interconnection patterns of each existing graphic unit (including the target graphic unit) chip have been completed in the previous process, that is, if internal interconnection is not required in the steps of this application and different metal layers (such as aluminum) are used, then the problem of metal layer coverage in the corresponding areas inside the existing graphic unit that are not exposed needs to be considered. The approach is to expose at least one mask used in this application for the area inside the existing graphic unit where no metal layer needs to be retained, and make the corresponding area of ​​the mask transparent (clear). The target graphic unit and each mask mentioned in this application are all non-exposed existing graphic units that do not need to be exposed. A separate mask or a lithography blind is used to form a transparent area in the corresponding area for exposure and development, and the metal layer on it is etched away. Whether the same mask or a lithography blind is used to form a transparent area in the corresponding area for the target graphic unit and each mask mentioned in this application that do not need to be exposed can be selected according to the actual situation. If negative photoresist or damascus steel is used to fabricate inter-chip interconnects, the exposed areas (transparent areas) will retain the lines, while the unexposed areas will not, so this issue does not need to be considered. If this process requires considering the micro-load effect during etching and a dummy block is used, this should be taken into account when fabricating the mask (when considering dummies, a mask needs to be fabricated; a blind (light-blocking sheet) cannot be used to create a transparent area in the corresponding region). In specific operations, handle according to the actual situation; further details are omitted.

[0058] like Figure 1 The diagram shown is a structural diagram of an example of the photolithography equipment used in the photolithography technology implementation method for multi-chip high-density interconnection provided in this application embodiment. The photolithography equipment includes:

[0059] Light source 100 is used to provide the exposure beam required for photolithography. The light source 100 can be, but is not limited to, a light source generated by a mercury lamp, a light source generated by an excimer laser, or an extreme ultraviolet (EUV) light source. Mercury lamps can emit light of multiple discrete wavelengths, including g-lines (436 nm), i-lines (365 nm), etc., wavelengths suitable for photolithography processes with different resolution requirements. Excimer lasers can generate shorter wavelengths of ultraviolet light, such as KrF (248 nm) and ArF (193 nm), short wavelengths which help improve photolithography resolution and are suitable for fine patterning requirements. The wavelength of the EUV light source is 13.5 nm, much shorter than that of traditional DUV light sources. This allows for photolithography at extremely high resolution, suitable for state-of-the-art semiconductor manufacturing processes. Methods for generating EUV light sources include, but are limited to, converting materials into a plasma state having at least one element with one or more emission lines in the EUV range (e.g., xenon, lithium, or tin).

[0060] Mask 200 is used to provide the preset pattern required for exposure.

[0061] The projection system 300 is used to transfer a preset pattern on the mask 200 onto the substrate 500 to be exposed. The projection system 300 can be a conventional projection system with a reduction ratio of 4 to 10 times or other reduction ratios. Specifically, the reduction ratio of the projection system 300 can be any one of 4, 5, 8, or 10 times, or one of 2.5, 2, 1.25, 1, 0.8, 0.5, 0.4, 0.2, 0.125, or 0.1. The required reduction ratio can be selected based on the size of the original pattern unit fabricated in the previous layer, the minimum critical size requirement, and the size requirement of the exposure field to be formed (i.e., the first exposure area and the second exposure area). This application does not impose specific limitations on this.

[0062] The stage 400 is used to mount the substrate 500 to be exposed and to perform stepping on the substrate 500.

[0063] The substrate 500 may be one of a silicon substrate, a germanium substrate, a compound semiconductor substrate, a ceramic substrate, a glass substrate, a quartz substrate, a silicon substrate, or a metal substrate, or the substrate may have one or more of a silicon substrate, a germanium substrate, or a compound semiconductor substrate mounted on it. The substrate may be circular or square.

[0064] like Figure 2The diagram shown is a schematic representation of an example substrate in the photolithography method for implementing high-density interconnection of multiple chips provided in this application. The substrate 500 can be a composite substrate composed of a substrate 503 containing integrated circuits (including silicon substrates, germanium substrates, compound semiconductors, etc.) and a carrier plate 502 (including ceramic carrier plates, glass carrier plates, quartz carrier plates, silicon carrier plates, or metal carrier plates, etc.) supporting the substrate 503. Using the photolithography method provided in this application, KGD (know-good die) chips can be precisely bonded to the carrier plate 502, and the composite substrate can then be further interconnected at high density through this invention. Here, KGD (know-good die) chips refer to independent chips that have been verified to be functionally normal in wafer-level testing, possessing good functionality and reliability before being integrated into more complex systems.

[0065] The substrate 500 can be a substrate with integrated circuit patterns, or a substrate with metal wiring, and / or optical wiring, and / or microfluidic circuitry, and / or MEMS circuitry. That is, the method provided in the embodiments of this application can be used to achieve the desired results when there is a need to connect some small functional structures into a larger functional structure, or when there is a need for high-density interconnection.

[0066] In other words, the photolithography method provided in this application is feasible for patterned silicon wafers, as well as patterned compound semiconductors or substrates. It allows for the interconnection of multiple patterns based on the same exposure field size, achieving high-density interconnection between compound semiconductors or substrates. Compound semiconductors, like traditional silicon wafers, have the capability to fabricate large-size chips. To achieve high-density interconnection between these chips, bonding techniques (such as direct copper bonding) can be used to fix the chips onto the substrate.

[0067] The substrate of the carrier plate can be a high-hardness, low-deformation substrate. Specifically, the carrier plate can be one of a ceramic carrier plate, a glass carrier plate, a quartz carrier plate, a silicon carrier plate, or a metal carrier plate.

[0068] When using a lithography machine with a large exposure field (e.g., 50mm × 50mm), the lithography technology implementation method provided in this application embodiment can achieve high-density interconnection of large carrier boards at the decimeter level. It should be noted that high-density optical interconnection between chips is a key link in solving communication between chips and between cards. Using the lithography technology implementation method provided in this application embodiment, corresponding optical communication lines can be fabricated, and the fabricated optical communication lines have the advantages of narrow linewidth and high precision.

[0069] The substrate 500 may also be loaded with one or more of the following: silicon substrate, germanium substrate, compound semiconductor substrate, and carrier plate.

[0070] In this way, mounting multiple small silicon wafers or small carrier boards on a large carrier board can improve efficiency. Furthermore, mounting small silicon wafers or small carrier boards of different models on a large carrier board can achieve high-density interconnection of different models of small silicon wafers or small carrier boards in the form of large-size chips.

[0071] When multiple silicon substrates, or multiple germanium substrates, or multiple compound semiconductor substrates, or multiple carrier plates are mounted on the substrate 500, the silicon substrates may be the same or different, and / or the germanium substrates may be the same or different, and / or the compound semiconductor substrates may be the same or different, and / or the carrier plates may be the same or different. The silicon substrates, germanium substrates, compound semiconductor substrates, and carrier plates can be placed according to actual needs, and this application does not impose any restrictions on this.

[0072] The size of the carrier plate can be from 40 mm to 4000 mm. For example, the size of the carrier plate can be one of 40 mm, 80 mm, 100 mm, 150 mm, 300 mm, 600 mm, 1200 mm, 2400 mm, 3000 mm, 3600 mm or 4000 mm.

[0073] It should be noted that since the projection lens used in this embodiment is a conventional reduced-magnification projection lens, the lines it produces are finer and the alignment accuracy is higher. In this case, to prevent multiple silicon substrates, germanium substrates, compound semiconductor substrates, and carriers from failing to connect, the silicon substrates, germanium substrates, compound semiconductor substrates, and carriers can be placed with high precision. This effectively avoids the problem of connection failure caused by only aligning a portion of the components while other components cannot be correctly aligned due to changes in their relative positions. Especially when processing silicon substrates, germanium substrates, compound semiconductor substrates, and carriers of different sizes, it is necessary to accurately determine the position of each component and fill the chip-free areas to ensure that the alignment accuracy meets actual requirements and to guarantee the stability of photoresist coating and exposure. If the chip-free areas are not filled, photoresist may seep into them during the photoresist coating process, resulting in uneven surfaces and affecting the quality of subsequent processes.

[0074] exist Figure 1 In the photolithography apparatus shown, the light source 100 forms an exposure beam through an illumination system. The exposure beam passes through the mask 200 and transfers the preset pattern on the mask 200 to the substrate 500 mounted on the stage 400 through a projection system 300. Then, photolithography is performed on the photoresist material to form an exposure field pattern.

[0075] It should be noted that if the light source 100 is an EUV light source, and the projection system 300 is a reflective projection system, such as... Figure 3The diagram shown is a structural diagram of a lithography device based on an EUV light source provided in an embodiment of this application. Figure 3 In the lithography apparatus shown, the light source 100 forms an exposure beam through an illumination system. The exposure beam passes through the mask 200, and the preset pattern on the mask 200 is reflected onto the substrate 500 mounted on the stage 400 by a reflective projection system 300. Then, photolithography is performed on the photoresist material to form the exposure field pattern. This avoids the problem that extreme ultraviolet (EUV) light is easily absorbed by light-transmitting materials, preventing the exposure beam from reaching the substrate.

[0076] If the light source 100 is a mercury lamp or an excimer laser, the space between the projection system 300 and the substrate 500 is filled with an immersion liquid (such as deionized water). Compared to the traditional photolithography method where the exposure beam directly reaches the silicon wafer surface from the projection system, this embodiment increases the refractive index of the medium by filling with an immersion liquid, thereby increasing the numerical aperture NA of the optical system and reducing the minimum critical size.

[0077] The existing patterned unit on the substrate 500 can be one or more of the following: integrated circuit pattern, optical path pattern, microfluidic path, metal wiring, and sensor pattern. The integrated circuit pattern can be a single integrated circuit pattern unit. The size of a single integrated circuit pattern unit is less than 26mm × 33mm (e.g., 25mm × 32mm), and the specific size can be determined according to actual needs; no limitation is imposed here.

[0078] The type of integrated circuit may include, but is not limited to, at least one of integrated circuits integrating electrical functions, integrated circuits integrating optical-optoelectronic functions, and integrated circuits integrating sensor functions. In other words, the photolithography technology provided in this application embodiment can be applied to all of the above-mentioned integrated circuits to achieve large-area, high-density interconnection of the chip. The type of integrated circuit can be selected according to actual needs, and this application does not specifically limit it.

[0079] The integrated circuit can be an integrated circuit with or without completed bonding pad (PAD) fabrication. In other words, the photolithography method provided in this application is applicable to integrated circuits with or without bonding pads. It should be noted that initially, some bonding pads may already exist on the chip. These bonding pads are mainly used for internal interconnection or preliminary external connections. However, as the number of chips increases and the interconnection density improves, the existing bonding pads may be insufficient to meet all external connection requirements. Therefore, after completing the high-density free interconnection of M×N chips, bonding pads can be further fabricated. The photolithography method provided in this application can generate a certain number of bonding pads while completing high-density chip interconnection, which not only simplifies the process flow but also reduces the number of pattern fabrication layers, thereby reducing manufacturing costs and time consumption.

[0080] The integrated circuit pattern can be a single-layer integrated circuit pattern or a multi-layer integrated circuit pattern. As 3D integrated circuit technology matures, the photolithography method provided in this application can also be applied to chips with stacked multi-layer integrated circuits. In other words, the method provided in this application can be effectively implemented even under complex structures formed after multi-layer circuit integration.

[0081] In the multi-layer pattern, the materials of the patterns in different layers can be the same or different. In this way, silicon-based, silicon-compound semiconductor, silicon-carbon semiconductor, or silicon-germanium semiconductor can be integrated together to obtain complex large chips.

[0082] The integrated circuits in the existing patterned units on the substrate to be exposed in the photolithography implementation method provided in this application can be integrated circuits that have completed both the front end of line (FEOL) and back end of line (BEOL) processes, and / or integrated circuits that have partially completed both the front end of line (FEOL) and back end of line (BEOL) processes. The specific process step from which to begin can be selected according to actual needs to achieve the desired effect.

[0083] The substrate 500 also includes a primary alignment device for preliminary alignment of the substrate. It should be noted that when the substrate 500 lacks a primary alignment device, alignment can also be achieved through the shape of the substrate itself.

[0084] like Figure 4The diagram shown is a structural diagram of another example of the photolithography equipment used in the photolithography technology implementation method provided in this application embodiment. The photolithography equipment includes one stage (e.g., stage 410), two stages (e.g., stage 410 and stage 430), three stages (e.g., stage 410, stage 420, and stage 430), or four stages (e.g., stage 410, stage 420, stage 430, and stage 440). When there are two stages (e.g., stage 410 and stage 430), both stages are loaded with the silicon substrate, or the germanium substrate, or the compound semiconductor substrate, or the carrier plate. Figure 4 In the example, substrate 1500 is mounted on stage 410, and substrate 3500 is mounted on stage 430. The two stages are moved alternately under the projection system 310 to complete the exposure.

[0085] Furthermore, such as Figure 4 As shown, the photolithography equipment includes two mask stages, namely the stage corresponding to mask 210 and the stage corresponding to mask 220. Each mask stage is equipped with an independent projection system. Figure 4 In the example, the mask stage corresponding to mask 210 corresponds to projection system 310, and the mask stage corresponding to mask 220 corresponds to projection system 320.

[0086] In the case where the photolithography equipment includes two mask stages and comprises one stage (e.g., stage 410), two stages (e.g., stages 410 and 430), three stages (e.g., stages 410, 420, and 430), or four stages (e.g., stages 410, 420, and 430), each stage corresponds to a projection system for achieving exposure. The one, two, three, or four stages are respectively moved to the projection systems corresponding to the two mask stages (as shown in the attached diagram). Figure 4 Exposure under projection systems 310 and 320.

[0087] Furthermore, such as Figure 4 As shown, when the photolithography equipment includes two mask stages and three stages (such as stage 410, stage 420, and stage 430) or four stages (such as stage 410, stage 420, stage 430, and stage 440), the photolithography equipment further includes two upper and lower silicon wafer systems (respectively attached). Figure 4 The upper and lower silicon wafer systems 1001 and 1002 are included, along with two silicon wafer measurement systems (attached respectively). Figure 4(Silicon wafer measurement system 930 and silicon wafer measurement system 940).

[0088] In contrast, in the case of only one silicon wafer measurement system (such as silicon wafer measurement system 930), assuming there are three stages (such as stage 410, stage 420, and stage 430), with stage 410 and stage 420 having their wiring in front and stage 430 having its wiring in the back, since there is only one silicon wafer measurement system, the wiring system needs to be bypassed. Stage 410 needs to be moved to the left of silicon wafer measurement system 930 so that stage 420 can be moved to the measurement position. If stage 410 is moved below projection system 320, then stage 420 needs to be moved to the right of projection system 320.

[0089] Using two upper and lower silicon wafer systems (e.g., upper and lower silicon wafer systems 1001 and 1002) and two silicon wafer measurement systems (e.g., silicon wafer measurement systems 930 and 940), and taking four stages (e.g., stages 410, 420, 430, and 440) as an example, stages 430 and 410 utilize silicon wafer measurement system 930 and upper and lower silicon wafer systems 1001, with the wiring system positioned one in front (stage 430) and one behind (stage 410); stages 440 and 420 utilize silicon wafer measurement system 940 and upper and lower silicon wafer systems 1002, with the wiring system positioned one in front (stage 420) and one behind (stage 440). Throughout the process, the photomasks (e.g., photomasks 210 and 220) and projection systems (e.g., projection systems 310 and 320) are shared resources. By using reasonable stage rotation and path planning, it can be ensured that each stage can smoothly perform measurement, film loading and unloading preparation, and projection exposure operations without interruption or delay due to path conflicts.

[0090] It is evident that when the lithography equipment includes two mask stages and three or four stages, and when the lithography equipment includes two upper and lower silicon wafer systems and two silicon wafer measurement systems, mutual interference between the wiring systems can be effectively avoided, thereby improving the flexibility and efficiency of the lithography equipment and ensuring that each stage can smoothly perform measurement, preparation, and projection exposure actions.

[0091] It should be understood that the left, right, front, and back mentioned above are all relative, and in actual operation, the platform runs on platform 10.

[0092] The above is an introduction to the photolithography equipment provided in the embodiments of this application.

[0093] It should be noted that the photolithography method provided in this application is mainly used to solve the interconnection between multiple large chips smaller than the exposure field limit of traditional integrated circuits (approximately 26mm*33mm). It can achieve high-density interconnection of multiple chips without changing the exposure field size, thereby efficiently manufacturing chips larger than those manufactured by traditional photolithography methods, or manufacturing substrates with higher density lines while maintaining a large area compared to traditional substrate manufacturing methods. These are the inherent intentions of this application and will not be elaborated further here.

[0094] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0095] like Figure 5 The diagram shown is a flowchart of a photolithography method for implementing high-density interconnection of multiple chips provided in the first embodiment of this application, including the following steps S101 to S105.

[0096] Step S101: Obtain a substrate map, which is used to reflect the positional distribution information of the original pattern units on the substrate to be exposed.

[0097] This step is used to obtain a substrate map (also known as a wafer map) that reflects the location distribution information of the original patterned units on the substrate to be exposed.

[0098] It should be noted that the Wafer Map is a mapping map created based on the actual size of the existing patterned units on the substrate to be exposed. The Wafer Map specifically includes, but is not limited to, at least one of the following: position information (position information is used to indicate the specific position of each existing patterned unit on the substrate), status information (status information is used to indicate the status of each existing patterned unit (such as test successful, test failed, not tested, etc.)), and size information (size information is used to indicate the actual size of each existing patterned unit).

[0099] Users can pre-divide the existing patterned units in the substrate to be exposed into units that need to form a chip group with M×N chip interconnects (i.e., identify which existing patterned units in the substrate can be connected together to form a chip group with M×N chip interconnects) and existing patterned units that do not need to form a chip group with M×N chip interconnects but have complete functionality (referred to as target patterned units in this application). It should be noted that the target patterned units that do not need to form an M×N chip group should retain their functionality or have their pattern circuitry further improved.

[0100] The original pattern unit generally refers to a single integrated circuit (e.g., 25mm × 32mm) slightly smaller than the maximum exposure field size (approximately 26mm × 33mm) of a traditional lithography machine (e.g., a DUV (deep ultraviolet) lithography machine). The original pattern unit can be a single-exposure pattern formed using a projection system with a reduction ratio of 4 to 10 times or other ratios. For example, the original pattern unit is a single-exposure pattern formed using a projection system with a reduction ratio of 4 times; another example is a single-exposure pattern formed using a projection system with a reduction ratio of 5 times; yet another example is a single-exposure pattern formed using a projection system with a reduction ratio of 8 times; and yet another example is a single-exposure pattern formed using a projection system with a reduction ratio of 10 times. Taking a reduction ratio of 5 times for the projection system as an example, after synchronous scanning movement of the lithography machine's workpiece stage and mask stage, the maximum exposure field size formed is generally 26mm × 33mm. In this case, the maximum size of the original pattern unit is generally less than or equal to 26mm × 33mm.

[0101] It should be noted that the 26mm×33mm mentioned above is a special example. In reality, the original graphic unit is generally slightly smaller than 26mm×33mm, such as 25mm×32mm, etc.

[0102] Step S102: For the mask to be loaded, a sub-map is generated based on the substrate map; the sub-map is used to reflect the position distribution information of the original pattern units that need to be exposed on the substrate; the mask is provided with layout information for interconnecting at least two chips in a set direction.

[0103] This step generates a corresponding sub-map for each mask to be loaded, thereby defining the photolithography program for that mask. Here, a sub-map refers to a subroutine or a new program generated based on the wafer map. For example, an exposure program is created for the substrate to be exposed and forty masks to be loaded for exposing the substrate. This program includes forty subroutines corresponding to each of the forty masks. The exposure program includes alignment mark position information, wafer map, mask barcode information, mask or wafer offset information, etc. When a mask is about to be loaded to expose the substrate, the subroutine corresponding to that mask is adjusted, the mask is loaded, and the wafer is loaded for alignment and exposure.

[0104] In a specific implementation, in response to a deletion operation on the position information of the non-exposure original graphic units that do not require exposure in the wafer map, the position information corresponding to the non-exposure original graphic units of the mask that do not require exposure is deleted from the substrate map, generating a sub-map. In this way, the generated sub-map only retains the original graphic units of the mask that need exposure. Based on the sub-map, it is possible to control the stage carrying the substrate to move to the corresponding position of the original graphic unit that needs exposure each time to perform exposure. Alternatively, in response to a marking operation on the position information of the non-exposure original graphic units that do not require exposure in the wafer map, the position information of the non-exposure original graphic units that do not require exposure is marked in the substrate map, generating a sub-map. In this way, the generated sub-map marks the non-exposure original graphic units of the mask that do not require exposure. Based on the sub-map, it is possible to control the stage carrying the substrate to skip the marked non-exposure original graphic units when moving and move to the corresponding position of the original graphic unit that needs exposure to perform exposure.

[0105] In one alternative implementation, a mask can be used to implement the interconnection of the M×N chipset, such as... Figure 6 The diagram shown is a schematic of an example of using a mask to realize the interconnection of a 2×2 chipset in the photolithography technology implementation method for high-density interconnection of multiple chips provided in this application embodiment. It can be seen that an exposure area 700 covering the original pattern unit 610, original pattern unit 620, original pattern unit 630 and original pattern unit 640 can be formed on the substrate through a mask.

[0106] In another alternative implementation, at least two of the aforementioned photomasks can be used to achieve the interconnection of the M×N chipset. For example... Figure 7 The diagram illustrates an example of using two masks to interconnect a 2×2 chipset in the photolithography method for high-density multi-chip interconnection provided in this application. As can be seen, one mask can form an exposure region 800 on the substrate for interconnecting existing patterned units 610 and 620, and an exposure region 801 on the substrate for interconnecting existing patterned units 630 and 640. The other mask can form an exposure region 803 on the substrate for interconnecting existing patterned units 610 and 630, and an exposure region 804 on the substrate for interconnecting existing patterned units 620 and 640. Figure 8The diagram illustrates an example of using four masks to interconnect a 2×2 chipset in the photolithography method for high-density multi-chip interconnection provided in this application. As can be seen, one mask can form an exposure area 900 on the substrate for interconnecting existing patterned units 610 and 620, and for interconnecting existing patterned units 620 and 640. Another mask can form an exposure area 900 on the substrate for interconnecting existing patterned units 610 and 620, and for interconnecting existing patterned units 620 and 640. The exposure area 903, which interconnects the original pattern unit 610 and the original pattern unit 630, can be formed on the substrate using another mask to form an exposure area 901 for interconnecting the original pattern unit 610 and the original pattern unit 630, and for interconnecting the original pattern unit 630 and the original pattern unit 640. The exposure area 902, which interconnects the original pattern unit 630 and the original pattern unit 640, and for interconnecting the original pattern unit 640 and the original pattern unit 620, can also be formed on the substrate using another mask.

[0107] In any M×N chipset, there are no interconnect lines on the outer scribe lines of the connected M×N chips that penetrate into the original graphics unit and connect to the original graphics unit; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2.

[0108] It should be noted that the layout information on the mask used to interconnect at least two chips in a defined direction can be used to directly form the interconnection of at least two chips in the defined direction (as shown in the attached diagram). Figure 6 As shown, the layout information set on the mask of the exposure area 700 obtained by projection is directly used to realize the interconnection of the original graphic unit 610, the original graphic unit 620, the original graphic unit 630 and the original graphic unit 640, or as shown in the attached figure. Figure 7 As shown, the layout information set on the mask of the exposure area 800 obtained by projection is directly used to realize the interconnection of the original graphic unit 610 and the original graphic unit 620. It can also be used together with the layout information set on other masks for interconnecting at least two chips in a set direction to realize the interconnection of at least two chips in a set direction (as shown in the attached figure). Figure 8 As shown, the layout information set on the mask of the exposure area 900 and the layout information set on the mask of the exposure area 903 are projected together to realize the interconnection of the original graphic unit 610 and the original graphic unit 620.

[0109] An M×N chipset refers to a chip region on the substrate that contains M original pattern units (taking non-composite original pattern units as an example) vertically and N original pattern units horizontally. M and N are both integers greater than or equal to 1. M and N can be the same or different, but at least one must be greater than or equal to 2. This application does not impose further restrictions on the specific values ​​of M and N. For example, when interconnecting four chips arranged in a 2×2 matrix (i.e., two chips distributed horizontally and two chips distributed vertically), M can be chosen to be 2 and N to be 2. Similarly, when interconnecting six chips arranged in a 2×3 matrix (i.e., two chips distributed horizontally and three chips distributed vertically), M can be chosen to be 2 and N to be 3. This embodiment uses a 3×3 matrix as an example for illustration.

[0110] Specifically, such as Figure 9The diagram shown is a schematic representation of an example of an M×N chipset in the photolithography implementation method provided in this application embodiment. A wafer is fabricated based on the original pattern unit size (01, 02…ij, etc.). The map clearly defines the production target as a 3×3 chipset. The 3×3 chipset 101 includes existing graphics units 01, 02, 03, 11, 12, 13, 21, 22, and 23. The 3×3 chipset 102 includes existing graphics units 31, 32, 33, 41, 42, 43, 51, 52, and 53. The 3×3 chipset 103 includes existing graphics units 61, 62, 63, 71, 72, 73, 81, and 84. 2. Existing graphics unit 83; The 3×3 chipset 104 includes existing graphics units 04, 05, 06, 14, 15, 16, 24, 25, and 26; The 3×3 chipset 105 includes existing graphics units 34, 35, 36, 44, 45, 46, 54, 55, and 56; The 3×3 chipset 106 includes existing graphics units 64, 65, 66, 74, 75, 76, 84, 85, and 86. Among them, the original graphics units 0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, i1, i2, i3, i4, i5, i6, and ij, which cannot form a 3×3 chipset, are planned as target graphics units.

[0111] This step clarifies the existing patterned units on the substrate that need to be exposed on the mask to be loaded. It should be noted that the existing patterned units on the substrate that need to be exposed on the mask to be loaded include at least the existing patterned units that need to be exposed in the M×N chip group, and may further include target patterned units that do not require the formation of an M×N chip group. It should be observed that in some cases, the target patterned units have already completed the necessary intra-chip metal interconnects and do not require inter-chip interconnects, in which case exposure is not required in this step; in other cases, such as... Figure 8 As shown, the internal metal interconnects of a single original graphic unit can also be achieved through... Figure 8 The use of photomasks allows for more flexible connections between and within chips. In this case, a fifth photomask can be used to expose the target pattern unit separately, or one of the photomasks can be used, such as... Figure 8 When using the mask corresponding to exposure area 901, this mask must not have any interconnect lines extending into the original pattern unit and connecting to it on the dicing path. The chip-to-chip connections are completed by exposure areas 902 and 903 extending into the original pattern unit 630 and connecting with exposure area 901. When using the mask to be loaded to expose the target pattern unit, the layout information on the mask is only used to form the exposure pattern in the corresponding area of ​​the target pattern unit, and is not used to interconnect the target pattern unit with other pattern units. After initial positioning on the substrate, the mask and one of the original pattern units on the substrate that the mask needs to expose are aligned, and the pattern on the mask is precisely transferred to the expected exposure area.

[0112] Step S103: Load the mask onto the mask stage of the photolithography equipment and offset the mask by a preset offset distance.

[0113] After generating a corresponding sub-map for the mask to be loaded, the mask is loaded onto the mask stage of the lithography equipment, and then the mask is offset by a preset offset distance.

[0114] It should be noted that the exposure area to be formed by the mask described in this application is used to connect two or more existing pattern units, which generally presents an alignment misalignment issue. Therefore, the mask can be offset by a preset offset distance when loading it, and / or the substrate can be offset by a preset offset distance after aligning the mask with the substrate. During exposure, alignment and exposure are performed according to the offset position. It should be noted that the preset offset distance of the substrate can be set in the silicon wafer alignment offset, and the preset offset distance of the mask can be set in the mask alignment offset.

[0115] It should be noted that the preset offset distance for the mask in step S103 and the preset offset distance for the substrate in subsequent step S105 do not mean that both the mask and the substrate must be actually offset. The preset offset distance for the substrate can be set to 0 (i.e., the substrate is not actually offset), or the preset offset distance for the mask can be set to 0 and the actual offset distance for the substrate can be set to 0 (i.e., the mask is not actually offset). Alternatively, both the silicon wafer and the mask can be actually offset. Or, after alignment with the second alignment mark and an offset already existing between the mask and the silicon wafer, the preset offset distances for both the mask and the substrate can be set to 0. All of these methods achieve the goal of ensuring a certain offset between the exposure area to be formed by the mask and the aligned original pattern unit.

[0116] By offsetting the substrate or mask by a preset offset distance, the alignment mismatch problem caused by the inconsistency in size between the mask used to connect the M×N chip group and the mask used to expose and form the original pattern unit, as mentioned above, can be overcome. Figure 9 As shown in the diagram, if a preset offset distance is not set for the first mask and / or for the substrate, and exposure is performed after the first mask is aligned with the original pattern unit 01, the center of the resulting exposure area A01 should overlap with the center of the original pattern unit 01, thus failing to form the desired pattern. Figure 9 The exposure area A01 shown connects the original pattern unit 01 and the original pattern unit 11. In this embodiment, the exposure area formed by performing exposure can achieve the desired effect by setting a preset mask alignment offset, a preset substrate alignment offset, or a partial offset of both. Figure 9 The effect shown overcomes the alignment mismatch problem caused by the inconsistency in size between the first mask used to connect the M×N chipset and the mask used to expose and form the original pattern unit.

[0117] In one alternative implementation, when the second alignment mark of the original graphic unit is an alignment mark set for the original graphic unit, the mask lithography program selected for the exposure is preset with a corresponding offset distance.

[0118] In this embodiment, the mask selected for each exposure has a preset offset distance. Different masks may have different offset distances.

[0119] In one implementation, the mask selected for the exposure can be offset by a corresponding offset distance when it is loaded onto the mask stage. Specifically, if the mask selected for the exposure is a first mask, it is offset by a corresponding offset distance when loaded onto the mask stage; if the mask selected for the exposure is a second mask, it is offset by a corresponding offset distance when loaded onto the mask stage; and so on.

[0120] In another implementation, after aligning the mask selected for exposure with the corresponding existing pattern unit using a second alignment mark on the substrate, the substrate can be biased by a preset offset distance. Specifically, if the mask selected for exposure is a first mask, after aligning the first mask with an existing pattern unit of the M×N chipset using the second alignment mark on the substrate, the substrate is biased by a preset offset distance; if the mask selected for exposure is a second mask, after aligning the second mask with another existing pattern unit in the M×N chipset using the second alignment mark on the substrate, the substrate is biased by a preset offset distance; and so on.

[0121] Thus, by biasing the mask selected for exposure or the substrate, a preset offset distance can be achieved between the mask selected for exposure and the substrate, thereby transferring the pattern on the mask selected for exposure to the exposure area to be exposed.

[0122] In another alternative implementation, when the second alignment mark on the substrate is an alignment mark for the exposure setting to be performed, the set offset distance is 0. If the offset distance is set to 0, no offset is required, and in this case, neither the mask nor the substrate needs to be offset.

[0123] In another optional implementation, the set offset distance is 0 when the relative positional relationship between the position of the mask pattern of the selected mask in the mask and the position of the mask pattern of the original mask in the original mask is the same as the positional relationship between the exposure area to be formed and the original pattern unit covered by the exposure area to be formed; wherein, the original mask is the mask used to create the original pattern unit.

[0124] In this embodiment, the mask pattern is offset during mask fabrication. Furthermore, the relative positional relationship between the position of the mask pattern of the selected mask and the position of the original mask (which can be determined based on the center of the selected mask relative to the center of the selected mask, and the center of the original mask relative to the center of the original mask) is the same as the positional relationship between the exposure area to be formed and the original pattern units covered by that exposure area (which can be determined based on the center of the exposure area to be formed relative to the center of the original pattern units covered by that exposure area). In this case, when aligning the mask and substrate subsequently, a certain offset already exists between them; therefore, no further offset is required, i.e., the set offset distance is 0.

[0125] like Figure 10 The diagram illustrates an example of the relative positional relationship between the original mask and the mask selected for exposure in the multi-chip high-density interconnect lithography technology implementation method provided in this application embodiment, as well as the positional relationship between the exposure area to be formed during exposure and the original pattern unit covered by the exposure area. Specifically, the center of the mask pattern 203 on the original mask 201 is aligned with the set center of the original mask 201, while the center of the mask pattern 204 on the mask selected for exposure is slightly lower than the set center of the mask 202 (the set centers of the original mask 201 and the mask selected for exposure follow the same rule according to the lithography machine model). This ensures that, without misalignment, the positional relationship between the exposure area 720 to be formed during exposure and the original pattern unit 620 covered by the exposure area 720 is such that the area 726 of the exposure area 720 corresponding to the original pattern unit 620 overlaps with the original pattern unit 620. That is, the relative positional relationship between the mask pattern 204 and the mask pattern 203 is the same as the positional relationship between the exposure area 720 to be formed during exposure and the original pattern unit 620 covered by the exposure area 720. At this time, the set offset distance is 0.

[0126] Step S104: Load the substrate onto the stage of the photolithography equipment and perform a first alignment using the first alignment mark on the substrate.

[0127] This step is used to initially position the substrate when it is initially loaded onto the stage with the original patterned units.

[0128] Optionally, prior to step S102, the photolithography method for implementing high-density interconnection of multiple chips provided in this application embodiment may further include the following steps: using the inherent features of the substrate or a primary alignment device on the substrate (attached) Figure 7 The primary alignment mark 510 in the middle is used for the initial positioning of the substrate.

[0129] The substrate has a first alignment mark (as shown in the attached image). Figure 7 The first alignment mark 520 shown, taking a NIKON lithography machine as an example, can be a laser step alignment mark (LSA) and / or a field image alignment mark (FIA), or an alignment mark designed for the alignment system of the lithography equipment involved in this application. One or more first alignment marks can be provided on the substrate, and the first alignment marks can be provided in the dicing track to avoid affecting the functional areas of the chip.

[0130] Specifically, before photolithography begins, the substrate to be exposed is transferred from the carrier to the stage of the photolithography equipment by a robotic arm or vacuum adsorption system. At this time, the substrate is roughly placed at a certain position on the stage. Then, the substrate is scanned by a high-resolution camera or other sensors installed on the photolithography equipment, and preliminary alignment is performed by primary alignment mark 510 or the shape characteristics of the substrate itself. After that, the substrate is precisely aligned by one or more first alignment marks to prepare for exposure.

[0131] Step S105: Based on the sub-map, control the stage to move according to the set direction and path, and use the second alignment mark on the substrate to align the mask with the original graphic unit on the substrate that needs to be exposed. Offset the substrate by a preset offset distance and perform exposure to transfer the preset graphic on the mask to the exposure area corresponding to the original graphic unit on the substrate that needs to be exposed.

[0132] This step is used to complete the exposure of the original patterned unit on the substrate by the mask that needs to be exposed. If the target patterned unit needs further exposure, the mask can also be used to form the exposure of the target patterned unit's exposure area (in this embodiment, the target patterned unit does not need to be exposed).

[0133] The substrate has a second alignment mark (as shown in the attached image). Figure 8 The second alignment mark (530) shown is similar to the first alignment mark. The second alignment mark can be a laser step alignment mark (LSA) and / or a field image alignment mark (FIA), or an alignment mark designed for the alignment system of the lithography equipment involved in this application. One or more second alignment marks can be provided on the substrate. The second alignment marks can be located in the dicing path to avoid affecting the functional areas of the chip.

[0134] Specifically, based on the sub-map corresponding to the mask, the stage on which the substrate is loaded can be controlled to move the substrate, sending the area to be exposed on the substrate to the projection system, and the mask can be precisely aligned with the original graphic unit on the substrate that needs to be exposed through one or more second alignment marks on the substrate.

[0135] The following is a detailed description of using two photomasks to complete the interconnection between the original patterned units in the M×N chipset on the substrate:

[0136] Taking the first non-exposure area unit corresponding to the first mask, which does not require exposure, as an example, it includes some graphic units in the original graphic units that can form an M×N chip group, and target graphic units that do not require forming an M×N chip group. Figure 9 As shown, assuming the existing patterned units have already completed the hole fabrication required for connection (the existing patterned units are fabricated using conventional photolithography or the technology of this invention), the target patterned unit and the existing patterned units without connection requirements do not require this photolithography step. Taking the vertical connection of the existing patterned units completed by the first mask as an example (such as the exposure area A01 between the existing patterned units 01 and 11), the vertical connection formed by the first mask in the 3×3 chipset 101 includes exposure areas A01, A02, A03, A11, A12, and A13; the vertical connection formed by the first mask in the 3×3 chipset 102 includes exposure areas A31, A32, A33, A41, A42, and A43; and the vertical connection formed by the first mask in the 3×3 chipset 103 includes exposure areas A61, A62, and A63. Exposure areas A71, A72, and A73; the vertical connections formed by the first mask in the 3×3 chipset 104 include exposure areas A04, A05, A06, A14, A15, and A16; the vertical connections formed by the first mask in the 3×3 chipset 105 include exposure areas A34, A35, A36, A44, A45, and A46; the vertical connections formed by the first mask in the 3×3 chipset 106 include exposure areas A64, A65, A66, A74, A75, and A76. Therefore, Figure 9Original graphic unit 01, Original graphic unit 02, Original graphic unit 03, Original graphic unit 11, Original graphic unit 12, Original graphic unit 13, Original graphic unit 04, Original graphic unit 05, Original graphic unit 06, Original graphic unit 14, Original graphic unit 15, Original graphic unit 16, Original graphic unit 31, Original graphic unit 32, Original graphic unit 33, Original graphic unit 41, Original graphic unit 42, Original graphic unit 43, Original graphic unit 34, Original graphic unit Original graphic unit 35, original graphic unit 36, original graphic unit 44, original graphic unit 45, original graphic unit 46, original graphic unit 61, original graphic unit 62, original graphic unit 63, original graphic unit 71, original graphic unit 72, original graphic unit 73, original graphic unit 64, original graphic unit 65, original graphic unit 66, original graphic unit 74, original graphic unit 75, and original graphic unit 76 are the graphic units that need to be exposed and are retained or marked in the sub-map of the first mask.

[0137] like Figure 11The diagram shown is an example of a non-exposure area unit corresponding to a photomask in the photolithography implementation method provided in this application embodiment. If the first photomask forms an exposure area A21 between the original graphic unit 21 and the original graphic unit 31, an exposure area A22 between the original graphic unit 22 and the original graphic unit 32, and an exposure area A23 between the original graphic unit 23 and the original graphic unit 33, it will cause the 3×3 chip group 101 and the 3×3 chip group 102 to form a vertical connection. Therefore, the first non-exposure area that does not require exposure and is deleted or marked in the sub-map of the first photomask includes the original graphic unit 21, the original graphic unit 22, and the original graphic unit 23. Similarly, forming exposure areas A51 between existing graphics units 51 and 61, A52 between existing graphics units 52 and 62, and A53 between existing graphics units 53 and 63 will result in a vertical connection between the 3×3 chipset 102 and 3×3 chipset 103; forming exposure areas A24 between existing graphics units 24 and 34, A25 between existing graphics units 25 and 35, and A26 between existing graphics units 26 and 36 will result in a vertical connection between the 3×3 chipset 104 and 3×3 chipset 105. Next, an exposure area A54 is formed between the original graphic unit 54 and the original graphic unit 64, an exposure area A55 is formed between the original graphic unit 55 and the original graphic unit 65, and an exposure area A56 is formed between the original graphic unit 56 and the original graphic unit 66. This will result in a vertical connection between the 3×3 chipset 105 and the 3×3 chipset 106. Therefore, the first non-exposure area that does not require exposure and is deleted or marked in the sub-map of the first mask also includes the original graphic unit 51, the original graphic unit 52, the original graphic unit 53, the original graphic unit 24, the original graphic unit 25, the original graphic unit 26, the original graphic unit 54, the original graphic unit 55, and the original graphic unit 56.If the first mask forms an exposure area A81 at the position corresponding to the original graphic unit 81, an exposure area A82 at the position corresponding to the original graphic unit 82, and an exposure area A83 at the position corresponding to the original graphic unit 83, it will result in patterns on the dicing track outside the 3×3 chipset 103. If the first mask forms an exposure area A84 at the position corresponding to the original graphic unit 84, an exposure area A85 at the position corresponding to the original graphic unit 85, and an exposure area A86 at the position corresponding to the original graphic unit 86, it will result in patterns on the dicing track outside the 3×3 chipset 106, thereby causing a connection leakage failure during dicing. Therefore, the first non-exposure area that does not need to be exposed and is deleted or marked in the sub-map of the first mask also includes the original graphic unit 81, the original graphic unit 82, the original graphic unit 83, the original graphic unit 84, the original graphic unit 85, and the original graphic unit 86. In addition, the original graphic units 0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, i1, i2, i3, i4, i5, i6, and ij, etc., cannot form a 3×3 chip group and therefore do not need to be connected in this embodiment. They also belong to the first non-exposure area corresponding to the first mask that does not need to be exposed.

[0138] Thus, as Figure 9As shown, the exposure patterns retained or marked in the sub-map of the first mask include original graphic units 01, 02, 03, 04, 05, 06, 11, 12, 13, 14, 15, 16, 31, 32, 33, and 34. Original graphic unit 35, original graphic unit 36, original graphic unit 41, original graphic unit 42, original graphic unit 43, original graphic unit 44, original graphic unit 45, original graphic unit 46, original graphic unit 61, original graphic unit 62, original graphic unit 63, original graphic unit 64, original graphic unit 65, original graphic unit 66, original graphic unit 71, original graphic unit 72, original graphic unit 73, original graphic unit 74, original graphic unit 75, original There is graphic unit 76, that is, retaining the original graphic units 01, 02, 03, 04, 05, 06, 11, 12, 13, 14, 15, 16, 31, 32, 33, 34, 35, and so on. The exposure positions of the original pattern units 41, 42, 43, 44, 45, and 46; the original pattern units 61, 62, 63, 64, 65, and 66; and the original pattern units 71, 72, 73, 74, 75, and 76 are corresponding to the wafer map exposure positions. In this way, by generating a corresponding sub-map for the first mask, the preset pattern on the first mask can be transferred to the substrate, forming the vertical connection pattern of the corresponding original pattern units. The specific pattern positions are as follows... Figure 9As shown, the first mask will form the following exposure areas on the substrate: exposure area A01, exposure area A02, exposure area A03, exposure area A04, exposure area A05, exposure area A06, exposure area A11, exposure area A12, exposure area A13, exposure area A14, exposure area A15, exposure area A16, exposure area A31, exposure area A32, exposure area A33, exposure area A34, exposure area A35, exposure area A36, exposure area A41, exposure area A42, exposure area A43, exposure area A44, exposure area A45, exposure area A46, exposure area A61, exposure area A62, exposure area A63, exposure area A64, exposure area A65, exposure area A66, exposure area A71, exposure area A72, exposure area A73, exposure area A74, exposure area A75, exposure area A76. As mentioned earlier, exposure area A01 is used to connect the original graphic unit 01 and the original graphic unit 11, and exposure area A75 is used to connect the original graphic unit 75 and the original graphic unit 85, etc. For details, please refer to [reference needed]. Figure 9 Examples are not detailed here. For the first mask, firstly, a sub-map corresponding to the first mask is generated based on the substrate map. This sub-map reflects the positional distribution information of the original pattern units that need to be exposed on the substrate. After the first mask is configured with layout information for interconnecting M chips vertically, and after deleting or marking the first non-exposure area units corresponding to the first mask that do not require exposure in the sub-map, an original pattern unit that needs to be exposed on the first mask can be aligned with it in the substrate map, and the substrate or the first mask can be offset by a preset offset distance.

[0139] like Figure 12The diagram shown is a schematic representation of the sub-map corresponding to the first photomask in the photolithography implementation method provided in this application embodiment. It can be seen that the sub-map corresponding to the first photomask retains the original graphic units 01, 02, 03, 04, 05, 06, 11, 12, 13, 14, 15, 16, 31, 32, 33, 34, and 35 that need to be exposed on the first photomask. 35. Wafers corresponding to existing graphic units 36, 41, 42, 43, 44, 45, 46, 61, 62, 63, 64, 65, 66, 71, 72, 73, 74, 75, and 76. The MAP exposure positions are used to reflect the original graphic units 01, 02, 03, 04, 05, 06, 11, 12, 13, 14, 15, 16, 31, 32, 33, 34, 35, and 6 that need to be exposed on the first mask. The positional distribution information of unit 36, original graphic unit 41, original graphic unit 42, original graphic unit 43, original graphic unit 44, original graphic unit 45, original graphic unit 46, original graphic unit 61, original graphic unit 62, original graphic unit 63, original graphic unit 64, original graphic unit 65, original graphic unit 66, original graphic unit 71, original graphic unit 72, original graphic unit 73, original graphic unit 74, original graphic unit 75, and original graphic unit 76 on the substrate.

[0140] A first mask is used to form vertical connections between the existing patterned units in the M×N chipset on the substrate. Thus, using the methods described above, fabricated through conventional mask fabrication methods or improved mask fabrication methods (mask pattern placement offset), before exposure, the first mask can be aligned with the first exposure area where the pattern on the first mask is to be transferred by alignment and offsetting by a preset distance. After exposure, the pattern on the first mask can be transferred to the first exposure area. The first exposure area covers the scribe lines between two or more existing patterned units in the first M×N chipset and at least a portion of the patterned area of ​​each of the two or more existing patterned units. Figure 9 , Figure 11 (There are two examples each).

[0141] It should be noted that the substrate may include multiple M×N chip groups, and the multiple M×N chip groups include a first M×N chip group. In a specific embodiment, the first M×N chip group can be any one of the multiple M×N chip groups included on the substrate. Figure 13 The diagram shown is a schematic diagram of an example of the first M×N chipset in the photolithography technology implementation method provided in this application embodiment. The first M×N chipset may include an original graphic unit 610, an original graphic unit 620, an original graphic unit 630, and an original graphic unit 640. The first original graphic unit may be an original graphic unit 610, an original graphic unit 620, an original graphic unit 630, or an original graphic unit 640.

[0142] by Figure 13 For example, let's assume we choose... Figure 9 The 101 is used as the first M×N chipset, and the original graphics unit 620 (as per the corresponding...) Figure 9 When the original graphic unit 01 is the first original graphic unit, the graphic of the first mask is transferred to cover the original graphic unit 620 and the original graphic unit 640 (as corresponding to the original graphic unit 620 and the original graphic unit 640). Figure 9 The grating between the original graphic unit 11), and the first exposure area 700 of the original graphic unit 620 and the portion of the original graphic unit 640 (as corresponding to the original graphic unit 640). Figure 9 The exposure area A01). The original graphic unit 620 and the original graphic unit 640 are vertically connected through the first exposure area 700.

[0143] by Figure 9For example, M×N is 3×3. As mentioned earlier, after aligning with the original graphic unit 01, the exposure area A01 is completed, forming a connection between the original graphic unit 01 and the original graphic unit 11. Assume that this exposure is first vertical and then horizontal. For ease of description, assume that after the previous column of vertical exposure is completed, the exposure returns to the top to start the current column (it should be noted that the actual setting is usually S-shaped, such as exposing from top to bottom and then from bottom to top. The example of returning to the top to start the current column of exposure after the previous column of vertical exposure is completed is only for ease of description and is not intended to limit this application). Thus, as described above, after aligning the first mask with the second alignment mark of the original graphic unit 01 and exposing the substrate or the first mask at a preset offset distance to complete the exposure of the first mask exposure area A01, the substrate is moved longitudinally by the longitudinal dimension of the original graphic unit to the corresponding position of the original graphic unit 11. After aligning the first mask with the second alignment mark of the original graphic unit 11 and exposing the substrate or the first mask at a preset offset distance, the first mask pattern is transferred to the exposure area A11 covering the scribe line between the original graphic unit 11 and the original graphic unit 21. Since the first non-exposure graphic unit that does not need to be exposed and is deleted or marked in the sub-map of the first mask includes the original graphic unit 21, when the substrate is moved longitudinally by the longitudinal dimension of the original graphic unit to the corresponding position of the original graphic unit 21, the original graphic unit 21 is skipped to reach the corresponding position of the original graphic unit 31, and the exposure of the exposure area A31 is completed. This process is repeated, proceeding sequentially from original graphic unit 41 to complete the exposure of exposure area A41, skipping original graphic unit 51 to complete the exposure of exposure area A61 in original graphic unit 61, completing the exposure of exposure area A71 in original graphic unit 71, skipping original graphic unit 81, and so on, until all the original graphic units corresponding to the required exposure positions of the first mask in the vertical column are exposed. When reaching the target graphic unit i1, since the first non-exposure graphic unit that does not need exposure is deleted or marked in the sub-map of the first mask, the target graphic unit i1 is skipped and no exposure is required. Then, it returns to the starting position of the vertical column (the position corresponding to the original graphic unit 01) and steps horizontally by the horizontal dimension of the original graphic unit to reach the position corresponding to the original graphic unit 02, completing the exposure of exposure area A02. This process is repeated until the exposure of exposure areas A01 to A76 is completed. If there are still graphics to be exposed to the right of the original graphic unit 06, repeat the above action... When the target graphic unit 0j is reached, since the first non-exposed graphic unit that does not need to be exposed in the sub-map of the first mask includes the original graphic unit 0j-original graphic unit ij, the original graphic unit 0j-original graphic unit ij is skipped and no exposure is required.It should be noted that... Figure 9 The description uses the example of a target graphic unit that does not require exposure and is not intended to limit this application.

[0144] Through the above actions, the exposure area of ​​the first mask corresponding to the graphic unit of the M×N chip group on the substrate is completed, or the exposure area of ​​the first mask on the target graphic unit can be further completed. That is, in this embodiment, the first mask completes the vertical connection between the original graphic units in the M×N chip group on the substrate (the target graphic unit does not need to be exposed in this embodiment).

[0145] Subsequently, for the second mask to be loaded, a sub-map corresponding to the second mask is generated based on the substrate map, and the exposure of the original pattern unit of the second mask on the substrate is completed, thereby forming a complete M×N chipset connection.

[0146] by Figure 9 For example, M×N is 3×3. As mentioned earlier, the vertical connection of each 3×3 chipset is completed through the first mask. The target graphic unit does not need exposure and does not require processing. Further, the mask needs to be replaced to complete the horizontal connection.

[0147] First, a sub-map corresponding to the second mask is generated based on the substrate map. This sub-map reflects the positional distribution of the original pattern units on the substrate that need to be exposed by the second mask. The second mask has layout information for interconnecting N chips horizontally. Specifically, the non-exposure pattern units corresponding to the second mask that do not require exposure can be deleted from the substrate map, retaining only the original pattern units that need exposure. Alternatively, the non-exposure pattern units corresponding to the second mask that do not require exposure can be marked in the substrate map to generate the sub-map. This allows the stage loaded with the substrate to move according to a set direction and path based on the sub-map during exposure, exposing the positions corresponding to the original pattern units that need exposure on the second mask.

[0148] exist Figure 9In the second mask, the horizontally connected exposure areas formed in the 3×3 chipset 101 are exposure areas B01, B02, B11, B12, B21, and B22; the horizontally connected exposure areas formed in the 3×3 chipset 102 are exposure areas B31, B32, B41, B42, B51, and B52; and the horizontally connected exposure areas formed in the 3×3 chipset 103 are exposure areas B61, B62, and B52. 71. Exposure area B72, Exposure area B81, Exposure area B82; The horizontally connected exposure areas formed in the 3×3 chipset 104 are exposure area B04, Exposure area B05, Exposure area B14, Exposure area B15, Exposure area B24, Exposure area B25; The horizontally connected exposure areas formed in the 3×3 chipset 105 are exposure area B34, Exposure area B35, Exposure area B44, Exposure area B45, Exposure area B54, Exposure area B55; The horizontally connected exposure areas formed in the 3×3 chipset 106 are exposure area B72, Exposure area B81, Exposure area B82; The horizontally connected exposure areas formed in the 3×3 chipset 106 are exposure area B72, Exposure area B81, Exposure area B82, Exposure area B82, Exposure area B04, Exposure area B05, Exposure area B14, Exposure area B15, Exposure area B24, Exposure area B25; The horizontally connected exposure areas formed in the 3×3 chipset 105 are exposure area B34, Exposure area B35, Exposure area B44, Exposure area B45, Exposure area B54, Exposure area B55; The horizontally connected exposure areas formed in the 3×3 chipset 106 are exposure area B72, Exposure area B72, Exposure area B81, Exposure area B82 ... Area B64, Exposure Area B65, Exposure Area B74, Exposure Area B75, Exposure Area B84, Exposure Area B85; Therefore, the original graphic unit 01, original graphic unit 02, original graphic unit 11, original graphic unit 12, original graphic unit 21, original graphic unit 22, original graphic unit 31, original graphic unit 32, original graphic unit 41, original graphic unit 42, original graphic unit 51, original graphic unit 52, original graphic unit 61, original graphic unit 62, original graphic unit 71, original graphic unit 72, original graphic unit 72, original graphic unit 01, original graphic unit 02, original graphic unit 03, original graphic unit 04, original graphic unit 05, original graphic unit 06, original graphic unit 07, original graphic unit 08, original graphic unit 09 ... Original graphic unit 81, original graphic unit 82, original graphic unit 04, original graphic unit 05, original graphic unit 14, original graphic unit 15, original graphic unit 24, original graphic unit 25, original graphic unit 34, original graphic unit 35, original graphic unit 44, original graphic unit 45, original graphic unit 54, original graphic unit 55, original graphic unit 64, original graphic unit 65, original graphic unit 74, original graphic unit 75, original graphic unit 84, and original graphic unit 85 are the graphic units that need to be exposed corresponding to the second mask.

[0149] And in Figure 9If the exposure area formed by the second mask on the substrate includes the exposure area B03 corresponding to the original pattern unit 03, the exposure area B13 corresponding to the original pattern unit 13, and the exposure area B23 corresponding to the original pattern unit 23, it will result in a lateral connection between the 3×3 chip group 101 and the 3×3 chip group 104. Therefore, the second non-exposure pattern unit corresponding to the second mask that does not require exposure includes the original pattern unit 03, the original pattern unit 13, and the original pattern unit 23. Similarly, if the exposure area formed by the second mask on the substrate includes the exposure area B33 corresponding to the original pattern unit 33, the exposure area B43 corresponding to the original pattern unit 43, and the exposure area B53 corresponding to the original pattern unit 53, it will result in a lateral connection between the 3×3 chipset 102 and the 3×3 chipset 105; if the exposure area formed by the second mask on the substrate includes the exposure area B63 corresponding to the original pattern unit 63, the exposure area B73 corresponding to the original pattern unit 73, and the exposure area B83 corresponding to the original pattern unit 83, it will result in a lateral connection between the 3×3 chipset 103 and the 3×3 chipset 106; therefore, the second non-exposure pattern unit corresponding to the second mask that does not require exposure also includes the original pattern unit 33, the original pattern unit 43, the original pattern unit 53, the original pattern unit 63, the original pattern unit 73, and the original pattern unit 83. If the second mask forms exposure area B06 at the position corresponding to the original pattern unit 06, exposure area B16 at the position corresponding to the original pattern unit 16, and exposure area B26 at the position corresponding to the original pattern unit 26, it will result in patterns on the scribe lines outside the 3×3 chipset 104. If the second mask forms exposure area B36 at the position corresponding to the original pattern unit 36, exposure area B46 at the position corresponding to the original pattern unit 46, and exposure area B56 at the position corresponding to the original pattern unit 56, it will result in patterns on the scribe lines outside the 3×3 chipset 105. The formation of exposure area B66 at position 66, exposure area B76 at position 76, and exposure area B86 at position 86 will result in patterns on the dicing track outside the 3×3 chipset 106, which will cause leakage and failure during dicing. Therefore, the second non-exposure pattern unit corresponding to the second mask also includes the original pattern unit 06, original pattern unit 16, original pattern unit 26, original pattern unit 36, original pattern unit 46, original pattern unit 56, original pattern unit 66, original pattern unit 76, and original pattern unit 86.In addition, the original graphic units i1, i2, i3, i4, i5, i6, 0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, and 8j, as well as the original graphic units i1, i2, i3, i4, i5, i6, 0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, and 8j, are also considered as second non-exposure area units corresponding to the second mask because the target graphic units i1, i2, i3, i4, i5, i6, 0j, i7j, and 8j cannot form a 3×3 chip group and therefore do not need to be connected in this embodiment.

[0150] Thus, as Figure 9As shown, the original graphic units that need to be exposed and are retained or marked in the sub-map of the second mask include original graphic units 01, 02, 04, 05, 11, 12, 14, 15, 21, 22, 24, 25, 31, 32, 34, and so on. Shape unit 35, original shape unit 41, original shape unit 42, original shape unit 44, original shape unit 45, original shape unit 51, original shape unit 52, original shape unit 54, original shape unit 55, original shape unit 61, original shape unit 62, original shape unit 64, original shape unit 65, original shape unit 71, original shape unit 72, original shape unit 74, original shape unit 75, original shape unit 81, original shape unit 82, original shape unit 84. Existing graphic unit 85, that is, retaining existing graphic units 01, 02, 04, 05, 11, 12, 14, 15, 21, 22, 24, 25, 31, 32, 34, 35, and 41. The exposure positions of units 42, 44, 45, 51, 52, 54, 55, 61, 62, 64, 65, 71, 72, 74, 75, and 81, 82, 84, and 85 correspond to the wafer map exposure positions. Thus, based on the sub-map of the second mask, the preset pattern on the selected second mask can be transferred to the substrate, forming the lateral connection pattern of the corresponding original pattern units. Specific pattern positions are as follows... Figure 9As shown, the second mask will form the following exposure regions on the substrate: exposure region B01, exposure region B02, exposure region B04, exposure region B05, exposure region B11, exposure region B12, exposure region B14, exposure region B15, exposure region B21, exposure region B22, exposure region B24, exposure region B25, exposure region B31, exposure region B32, exposure region B34, exposure region B35, exposure region B41, exposure region B42, exposure region B44, exposure region B45, exposure region B51, exposure region B52, exposure region B54, exposure region B55, exposure region B61, exposure region B62, exposure region B64, exposure region B65, exposure region B71, exposure region B72, exposure region B74, exposure region B75, exposure region B81, exposure region B82, exposure region B84, exposure region B85. As mentioned earlier, exposure area B01 is used to connect the original graphic unit 01 and the original graphic unit 02, and exposure area B75 is used to connect the original graphic unit 75 and the original graphic unit 76, etc. For details, please refer to [reference needed]. Figure 9 Examples are not listed here.

[0151] After generating the sub-map of the second mask, the second mask can be loaded onto the mask stage and offset by a preset offset distance, or the substrate can be offset by a preset offset distance after the substrate is aligned with the second mask. The second mask is then used to align the corresponding graphic units in the first M×N chip group in the substrate map, excluding the first original graphic unit, and the exposure step is performed.

[0152] After mounting the substrate and aligning, as follows Figure 14 The diagram shown is a schematic representation of an example of a photolithography method provided in this application where a second mask connects two existing pattern units. Assuming a selection is made... Figure 9 The 3×3 chipset 101 is the first M×N chipset, with the original graphics unit 620 (as per the corresponding...). Figure 9 If the original graphic unit 01 is the original graphic unit corresponding to the second mask selected for this exposure, the graphic of the selected second mask is transferred to cover the original graphic unit 620 and the original graphic unit 610 (as shown in the original graphic unit 620). Figure 9 The gradation path between the original graphic unit 02), and the exposure area 800 of the original graphic unit 620 and the original graphic unit 610 (as corresponding to the original graphic unit 02). Figure 9The exposure area B01). The original graphic unit 620 and the original graphic unit 610 are horizontally connected through the exposure area 800. As can be seen from the figure, although the original graphic unit 01 is always selected as the first original graphic unit, different exposure areas A01 and B01 can be obtained at the corresponding positions of the original graphic unit 01 by using different masks and preset offset distances.

[0153] like Figure 9As shown above, by aligning with the original graphic unit 01 and offsetting by a preset distance, the exposure area B01 is exposed, forming a horizontal connection between the original graphic unit 01 and the original graphic unit 02. Assuming this exposure proceeds horizontally first and then vertically, for ease of description, it is assumed that after each horizontal exposure of the previous row is completed, the system returns to the left to begin the current row's exposure (in reality, this is set according to requirements, usually in an S-shape, such as exposing from left to right, then from right to left; the example of returning to the left to begin the current row's exposure after each horizontal exposure is completed is merely for ease of description and is not intended to limit this application). Thus, as described above, after aligning the second mask with the second alignment mark of the original pattern unit 01, and offsetting the substrate or the second mask by a preset offset distance (the mask offset is performed when the mask is loaded onto the mask stage), exposure is performed. After the selected exposure area B01 of the second mask is exposed, the substrate is moved laterally by the lateral dimension of the original pattern unit to the corresponding position of the original pattern unit 02. Then, the second mask is aligned with the second alignment mark of the original pattern unit 02, and the substrate or the second mask is offset by a preset offset distance for repeated exposure. After aligning the second alignment mark on the substrate, offsetting it by a preset distance, and performing the exposure steps, the selected second mask pattern is transferred to the exposure area B02 covering the scribe line between the original pattern unit 02 and the original pattern unit 03. Since the deleted or marked second non-exposure pattern unit that does not require exposure in the submap of the second mask includes the original pattern unit 03, when the substrate is moved longitudinally by the longitudinal dimension of the original pattern unit to the position corresponding to the original pattern unit 03, the original pattern unit 03 is skipped to the position corresponding to the original pattern unit 04, completing the exposure of the exposure area B04. This process is repeated, reaching the original pattern unit 05 to complete the exposure of the exposure area B05, skipping the original pattern unit 06, and so on, until all the positions corresponding to the original pattern units that need exposure in the horizontal direction of the second mask are exposed. When reaching the target pattern unit 0j, since the deleted or marked second non-exposure pattern unit that does not require exposure in the submap of the second mask includes the target pattern unit 0j, the target pattern unit 0j is skipped, and no exposure is required. Then return to the horizontal starting position of the current row (the position corresponding to the original graphic unit 01) and step vertically by the vertical dimension of the original graphic unit to reach the position corresponding to the original graphic unit 11, completing the exposure of exposure area B11. Repeat this process to finally complete the exposure of exposure areas B01 to B85. If there are still graphics below the original graphic unit 81 to be exposed, repeat the above actions... When reaching the target graphic unit i1, since the first non-exposure graphic units that do not need to be exposed in the sub-map of the second mask include the original graphic units i1 to ij, the original graphic units i1 to ij are skipped.

[0154] Through the above actions, the exposure areas of the selected second mask corresponding to the graphic units and / or target graphic units of the M×N chip group on the substrate are completed. That is, in this embodiment, the second mask completes the formation of lateral connections between the original graphic units in the M×N chip group on the substrate (in this embodiment, the target graphic unit does not need to be exposed).

[0155] It should be noted that, Figure 9 The interconnection between chips in an M×N (3×3) chipset is formed by selecting two photomasks. One photomask is used to form the vertical connection between the original graphic units in the M×N (3×3) chipset, and the other photomask is used to form the horizontal connection between the original graphic units in the M×N (3×3) chipset. This ultimately forms a complete interconnection of all the original graphic units in the M×N (3×3) chipset, achieving the effect of high-density interconnection of M×N multi-chips.

[0156] It should be noted that, Figure 9 The example shown uses a single exposure area on a photomask that can connect to two existing pattern units. In reality, using a conventional lithography machine, when the existing pattern size is small (e.g., 25mm*32mm), a single exposure area may cover three existing pattern units. The following will combine... Figure 15 , Figure 16 , Figure 17 and Figure 18 A detailed introduction will be provided.

[0157] like Figure 15 The diagram shown is a schematic representation of an example of the photolithography implementation method provided in this application, where the exposure area of ​​the first mask connects to three existing pattern units. Figure 15 This example also uses a 3x3 chipset and target graphics units that do not require exposure. For example... Figure 17 The diagram shown is an example of a photolithography method provided in this application where the exposure area of ​​each mask is connected to three existing pattern units. Assuming that a selection is made... Figure 17 The 3×3 chipset 101 serves as the first M×N chipset. Figure 15 Existing graphic unit 620 (as corresponding) Figure 17 When the original graphic unit 11 is the first original graphic unit, the graphic of the first mask is transferred to cover the original graphic unit 620 and the original graphic unit 640 (as corresponding to the original graphic unit 620 and the original graphic unit 640). Figure 17 The slicing paths between the original graphic unit 21), the original graphic unit 620 and the original graphic unit 660 (as corresponding to) Figure 17The grating between the original graphic unit 01 and the portion of the original graphic unit 620 (although the illustration covers the entire area, in actual use, the portion closer to the original graphic unit 640 and the original graphic unit 660 is usually selected), the portion of the original graphic unit 640 and the portion of the original graphic unit 660, and the first exposure area 700 (as corresponding to the original graphic unit 660). Figure 17 The exposure area A11). The original graphic unit 620, the original graphic unit 640, and the original graphic unit 660 are vertically connected through the exposure area 700.

[0158] Thus, as Figure 17 As shown, when the first mask completes the vertical connection of each original pattern unit of the 3×3 chipset, the original pattern units that need to be exposed corresponding to the first mask include original pattern unit 11, original pattern unit 12, original pattern unit 13, original pattern unit 14, original pattern unit 15, original pattern unit 16, original pattern unit 41, original pattern unit 42, original pattern unit 43, original pattern unit 44, original pattern unit 45, original pattern unit 46, and original pattern unit 71, original pattern unit 72, original pattern unit 73, original pattern unit 74, original pattern unit 75, and original pattern unit 76.

[0159] Similarly, as Figure 16 The diagram shown is a schematic representation of an example of connecting the exposure areas of other photomasks to three existing pattern units in the photolithography implementation method provided in this application embodiment. In the existing pattern unit 620 (as corresponding to...) Figure 17 When the original graphic unit 02 is the first original graphic unit, the graphics of other masks are transferred to cover the original graphic units 620 and 610 (as shown in the corresponding...). Figure 17 The slicing path between the original graphic unit 03), the original graphic unit 620 and the original graphic unit 670 (as corresponding to) Figure 17 The grating between the original graphic unit 01) and a portion of the original graphic unit 620 (although the illustration covers the entire area, in actual use, the portion closer to the original graphic unit 610 and the original graphic unit 670 is usually selected), the exposure area 800 of the portion of the original graphic unit 610 and the portion of the original graphic unit 670 (as shown in the corresponding diagram). Figure 17 The exposure area B02). The original graphic unit 620, the original graphic unit 610, and the original graphic unit 670 are horizontally connected through the exposure area 800.

[0160] Thus, as Figure 17As shown, when other masks complete the horizontal connection of the original graphic units of the 3×3 chipset, the original graphic units that need to be exposed for the other masks include original graphic units 02, 05, 12, 15, 22, 25, 32, 35, 42, 45, 52, 55, 62, 65, 72, 75, 82, and 85.

[0161] It should be noted that covering two or three existing pattern units is mainly limited by the exposure size of traditional lithography machines. Because the minimum line width required for top-layer interconnects is wider than that of bottom-layer lines, lithography machines with smaller scaling ratios (such as 2.5, 2, 1.25, 1, 0.8, 0.5, 0.4, 0.2, 0.125, or 0.1) can also be used. In this way, a single exposure area can cover more existing pattern units. For example, if the exposure area of ​​the first mask directly covers all pattern units of a 3×3 chipset, then chipsets 101, 102, 103, 104, 105, and 106 can be exposed sequentially using only the first mask. Figure 18 The diagram illustrates an example of achieving a large exposure field using a single photomask in the photolithography method provided in this application. The original graphic units to be exposed in the sub-map corresponding to the photomask include original graphic units 12, 15, 42, 45, 72, and 75. After aligning and offsetting the photomask with the original graphic units 12 and performing exposure, an exposure area A12 covering original graphic units 01, 02, 03, 11, 12, 13, 21, 22, and 23 is formed. In this case, no additional second photomask is needed to complete the overall connection of the M×N original graphic units, achieving the effect of high-density M×N multi-chip connections.

[0162] It should be noted that the foregoing description primarily uses the example of existing graphics units with the same size. With the development of integrated circuit technology, 3D chip integration technology has become increasingly important, and high-density planar interconnects between different chips (such as GPUs and DRAM) have become the mainstream technology. To further improve interconnect density, employing this invention for high-density interconnects between different chips is also crucial; that is, the existing graphics units on the substrate described in the embodiments of this application have one or more sizes.

[0163] like Figure 19 The diagram shown is a schematic representation of an example of a photolithography method provided in this application, where a substrate includes original patterned units of different sizes. Original patterned units 02, 12, 22, 32, 42, 52, 62, 72, and 82, and original patterned units 05, 15, 25, 35, 45, 55, 65, 75, and 85 are computing chips, each with the same size. Original patterned units 01, 11, 21, 31, 41, 51, and 62 are also included. Graphics unit 61, original graphics unit 71, original graphics unit 81, original graphics unit 03, original graphics unit 13, original graphics unit 23, original graphics unit 33, original graphics unit 43, original graphics unit 53, original graphics unit 63, original graphics unit 73, original graphics unit 83, original graphics unit 04, original graphics unit 14, original graphics unit 24, original graphics unit 34, original graphics unit 44, original graphics unit 54, original graphics unit 64, original graphics unit 74, original graphics unit 84, original graphics unit 06, original graphics unit 16, original graphics unit 26, original graphics unit 36, original graphics unit 46, original graphics unit 56, original graphics unit 66, original graphics unit 76, and original graphics unit 86 are memory chips, and all memory chips are the same size. However, the horizontal dimension of the memory chip is different from the horizontal dimension of the main processing chip (the vertical dimensions of the two are the same or precisely set to be the same step size). Each chip is precisely placed on the carrier board, and after gap filling, photolithographic interconnection is performed. For carrier boards that have already completed preliminary precise wiring, this solution can be further used to achieve high-density interconnection between chips, thereby improving the overall circuit performance and integration. The following combines... Figure 19 The specific steps of the photolithography implementation method provided in the embodiments of this application will be described in detail:

[0164] First, the step distance is set for different types of existing graphics units (such as computing chips and memory chips), and the existing M×N chipset of graphics units is planned and a wafer map is fabricated. Specifically, this can be achieved using the sub-die method. The sub-die method involves dividing a single wafer into multiple main dies during semiconductor manufacturing or packaging, and each main die contains multiple smaller sub-dies. These sub-dies can be further cut from the same main die. Figure 19 In the substrate map, chipsets 101, 102, 103, 104, 105, and 106 can be designated as Main dies. Each Main die contains two types of Sub-dies: a computing chip (referred to as Die1 in this embodiment) and a memory chip (referred to as Die2 in this embodiment). Taking chipset 101 as an example, original pattern units 02, 12, and 22 are designated as Die1, while original pattern units 01, 11, 21, 03, 13, and 23 are designated as Die2. It should be noted that when processing original pattern units of different sizes, a method is typically used where known, well-preserved chips (KGD) are first attached to the target substrate, and then uniform exposure is performed. This method effectively avoids the problem of being unable to form the predetermined M×N chipset due to differences in pattern unit size. This allows the lithography machine to obtain... Figure 19 The substrate map shown corresponds to the substrate shown.

[0165] Next, the first mask is selected, and a sub-map corresponding to the first mask is generated based on the aforementioned substrate map. This sub-map reflects the positional distribution information of the original pattern units that need to be exposed on the substrate. Then, the offset distance corresponding to the substrate or the first mask is preset. Figure 19 In the example of the 3×3 chipset 101 being the first M×N chipset, and using the mask corresponding to the original graphics unit 01 and the original graphics unit 11 as the first mask, refer to... Figure 13 Example of vertical connection of two existing graphic units, original graphic unit 620 (as corresponding to...) Figure 19 When the original graphic unit 01 is the first original graphic unit, the graphic of the first mask is transferred to cover the original graphic unit 620 and the original graphic unit 640 (as corresponding to the original graphic unit 620 and the original graphic unit 640). Figure 19 The grating between the original graphic unit 11), and the first exposure area 700 of the original graphic unit 620 and the portion of the original graphic unit 640 (as corresponding to the original graphic unit 640). Figure 19The exposure area A01). The original pattern units 620 and 640 are vertically connected through the exposure area 700 to achieve vertical interconnection between the two memory chips. Thus, the original pattern units to be exposed corresponding to the first mask include original pattern units 01, 11, 31, 41, 61, 71, 03, 13, 33, 43, 63, 73, 04, 14, 34, 44, 64, 74, 06, 16, 36, 46, 66, and 76.

[0166] Taking vertical exposure followed by horizontal exposure as an example, after the first mask exposure area A01 is completed as described above, the substrate is moved vertically by the vertical dimension of the original pattern unit 01 (Die2 type) to the corresponding position of the original pattern unit 11. The steps of aligning with the second alignment mark on the substrate (original pattern unit 11), offsetting by a preset offset distance, and exposure are repeated, thereby transferring the preset pattern on the first mask to the exposure area A11 covering the scribe line between the original pattern unit 11 and the original pattern unit 21. Then, the vertical dimension of the original pattern unit 11 (Die2 type) is moved vertically to the original pattern unit 21, and the... Since the original pattern unit 21 is the first non-exposed pattern unit corresponding to the first mask that does not require exposure, the original pattern unit 21 is skipped (that is, the longitudinal dimension of the original pattern unit 21 is moved vertically to the original pattern unit 31). The steps of aligning with the second alignment mark on the substrate (original pattern unit 31), offsetting by a preset offset distance, and exposure are repeated to complete the exposure of the exposure area A31. In this way, the exposure area A41 is completed by reaching the original pattern unit 41, the exposure area A61 is completed by skipping the original pattern unit 51 and reaching the original pattern unit 61, and the exposure area A71 is completed by reaching the original pattern unit 71. Then return to the starting position of the column (the position corresponding to the original graphic unit 01) and step horizontally to the original graphic unit 02. Since the first non-exposed graphic unit corresponding to the first mask includes the original graphic unit 02, further step horizontally to the original graphic unit 02 (Die1 type) (that is, skip the original graphic unit 02) to the position corresponding to the original graphic unit 03 (Die2 type), and complete the exposure of the exposure area A03. The original pattern unit 03 (Die2 type) is further stepped to the original pattern unit 13 in the vertical dimension, and the exposure area A13 is completed. Then, the original pattern unit 13 (Die2 type) is moved vertically to the original pattern unit 23. Since the original pattern unit 23 is the first non-exposed pattern unit corresponding to the first mask that does not need to be exposed, the original pattern unit 23 is skipped (that is, the original pattern unit 23 is moved vertically to the original pattern unit 33 in the vertical dimension). The steps of aligning with the second alignment mark on the substrate (original pattern unit 33), offsetting by a preset offset distance, and exposure are repeated to complete the exposure area A33. In this way, the exposure area A43 is completed by reaching the original pattern unit 43. The exposure area A63 is completed by skipping the original pattern unit 53 and reaching the original pattern unit 63. Finally, the exposure area A73 is completed by reaching the original pattern unit 73. Then return to the starting position of the column and step horizontally to the horizontal dimension of the original graphic unit 03 (Die2 type) to reach the corresponding position of the original graphic unit 04 (Die2 type), thus completing the exposure of the exposure area A04.This process is repeated until exposure of areas A01 to A76 is completed. This completes the vertical interconnection between memory chips in the M×N (3×3) chipset.

[0167] Next, using the first other mask from the other masks, the position information of the first other non-exposure area cells corresponding to the first other mask that do not need exposure is deleted or marked in the substrate map, and the offset distance corresponding to the substrate or the first other mask is preset. Figure 19 The 3×3 chipset 101 is the first M×N chipset. The mask corresponding to the original graphics unit 02 and the original graphics unit 12 is the first mask. For other masks, refer to... Figure 13 Example of vertical connection of two existing graphic units, original graphic unit 620 (as corresponding to...) Figure 19 When the original graphic unit 02 is the first original graphic unit, the graphic of the first other mask is transferred to cover the original graphic unit 620 and the original graphic unit 640 (as corresponding to the original graphic unit 620 and the original graphic unit 640). Figure 19 The grating between the original graphic unit 12), and the first exposure area 700 of the original graphic unit 620 and the portion of the original graphic unit 640 (as corresponding to the original graphic unit 640). Figure 19 The exposure area C02). The original graphic units 620 and 640 are vertically connected through the exposure area 700 to achieve vertical interconnection between the two computing chips (Die1). Thus, the original graphic units that need to be exposed for the other masks include original graphic units 02, 12, 32, 42, 62, 72, 05, 15, 35, 45, 65, and 75.

[0168] Taking vertical exposure followed by horizontal exposure as an example, after exposing the corresponding exposure area C02 of the first other mask as described above, the substrate is moved vertically by the vertical dimension of the original pattern unit 02 (Die1 type) to the corresponding position of the original pattern unit 12. The steps of aligning with the second alignment mark on the substrate (original pattern unit 12), offsetting by a preset offset distance, and exposure are repeated, thereby transferring the preset pattern on the first other mask to the exposure area C12 covering the scribe line between the original pattern unit 12 and the original pattern unit 22; then, the vertical dimension of the original pattern unit 12 (Die1 type) is moved vertically to the original pattern unit 22. Since the original pattern unit 22 is the first other non-exposure pattern unit corresponding to the first other mask that does not require exposure, the original pattern unit 22 is skipped (that is, the longitudinal dimension of the original pattern unit 22 is moved vertically to the original pattern unit 32), and the steps of aligning with the second alignment mark on the substrate (original pattern unit 32), offsetting by a preset offset distance, and exposure are repeated to complete the exposure of the exposure area C32. In this way, the exposure area C42 is completed by reaching the original pattern unit 42, the exposure area C62 is completed by skipping the original pattern unit 52 and reaching the original pattern unit 62, and the exposure area C72 is completed by reaching the original pattern unit 72.Then, return to the starting position in the vertical direction of this column (the position corresponding to the original graphic unit 02) and step horizontally by the horizontal dimension of the original graphic unit 02 (Die1 type) to reach the original graphic unit 03. Since the original graphic unit 03 is included in the first other non-exposure graphic unit corresponding to the first other mask, step horizontally by the horizontal dimension of the original graphic unit 03 (Die2 type) to reach the original graphic unit 04. Since the original graphic unit 04 is also included in the first other non-exposure graphic unit corresponding to the first other mask, continue to step horizontally by the horizontal dimension of the original graphic unit 04 (Die2 type) to reach the position corresponding to the original graphic unit 05 (Die1 type), completing the exposure of the exposure area C05; move the substrate vertically by the vertical dimension of the original graphic unit 05 (Die1 type) to reach the position corresponding to the original graphic unit 15, and repeat the alignment through the second alignment mark on the substrate (original graphic unit 15) and offset by a preset offset distance. The process involves separating and exposing the original pattern on the first other mask to the exposure area C15 covering the scribe line between the original pattern unit 15 and the original pattern unit 25. Then, the original pattern unit 15 (Die 1 type) is moved vertically to the original pattern unit 25. Since the original pattern unit 25 is the first non-exposed pattern unit corresponding to the first other mask, it is skipped (i.e., the original pattern unit 25 is moved vertically to the original pattern unit 35). The process of aligning with the second alignment mark on the substrate (original pattern unit 35), offsetting by a preset distance, and exposing is repeated to complete the exposure of the exposure area C35. This process continues until the original pattern unit 45 is reached to complete the exposure of the exposure area C45. The process then skips the original pattern unit 55 to reach the original pattern unit 65 to complete the exposure of C65, and finally reaches the original pattern unit 75 to complete the exposure of the exposure area C75. Finally, the exposure of the exposure areas C02 to C75 is completed. Complete the vertical interconnection between computing chips in an M×N (3×3) chipset.

[0169] Next, using a second mask from among other masks, the position information of the second non-exposed pattern units corresponding to the second mask that do not require exposure is deleted or marked in the substrate map, and the offset distance corresponding to the substrate or the second mask is preset. It should be noted that, with Figure 19Taking the 3×3 chipset 101 as an example, when the original graphic unit 01 and original graphic unit 03 are memory chips and the original graphic unit 02 is a computing chip, the connection between the original graphic units 01 and 02, and the connection between the original graphic units 02 and 03, although both are computing chip-memory chip connection structures, are symmetrical structures during photolithography. Unless the two exposure areas of the original graphic unit 01-original graphic unit 02 and the original graphic unit 02-original graphic unit 03 are completely symmetrical, the photomask cannot be shared. Therefore, for this embodiment, exposure is usually performed using a photomask that completely covers the exposure area of ​​the original graphic unit 02 and partially covers the exposure areas of the original graphic units 01 and 03 respectively. For specific methods, refer to [reference needed]. Figure 16 .

[0170] by Figure 19 The 3×3 chipset 101 is the first M×N chipset, and the mask corresponding to the original graphic unit 01, original graphic unit 02, and original graphic unit 03 is the second. For other mask examples, refer to... Figure 16 Example of horizontal connection of three existing graphic units, original graphic unit 620 (as corresponding to...) Figure 19 When the original graphic unit 02 is the first original graphic unit, the preset graphics of the second other mask are transferred to cover the original graphic unit 620 and the original graphic unit 670 (as shown in the corresponding...). Figure 19 The slicing path between the original graphic unit 01), the original graphic unit 620 and the original graphic unit 610 (as corresponding to) Figure 19 The first exposure area 800 (as corresponding to the original graphic unit 03) between the grating paths and all of the original graphic unit 620, part of the original graphic unit 670 and part of the original graphic unit 610. Figure 19 The exposure area B02). The original pattern units 670, 620, and 610 are laterally connected through the exposure area 800 to achieve lateral interconnection between the three chips. Thus, the original pattern units that need to be exposed for the other masks in the second mask include original pattern units 02, 12, 22, 32, 42, 52, 62, 72, 82, 05, 15, 25, 35, 45, 55, 65, 75, and 85.

[0171] Taking vertical exposure followed by horizontal exposure as an example, after exposing the corresponding exposure area B02 of the second other mask as described above, the substrate is moved vertically by the vertical dimension of the original pattern unit 02 (Die1 type) to the corresponding position of the original pattern unit 12. The steps of aligning with the second alignment mark on the substrate (original pattern unit 12), offsetting by a preset offset distance, and exposure are repeated, thereby transferring the preset pattern on the second other mask to the exposure area B12 covering the original pattern unit 12, the original pattern unit 11, and the original pattern unit 13. Then, the vertical dimension of the original pattern unit 12 (Die1 type) is moved vertically. The process continues until the original pattern unit 22 is reached. The steps of alignment with the second alignment mark on the substrate (original pattern unit 22), offset by a preset offset distance, and exposure are repeated to complete the exposure of the exposure area B22. This process is repeated until the original pattern unit 32 is reached to complete the exposure of the exposure area B32, the original pattern unit 42 is reached to complete the exposure of the exposure area B42, the original pattern unit 52 is reached to complete the exposure of the exposure area B52, the original pattern unit 62 is reached to complete the exposure of the exposure area B62, the original pattern unit 72 is reached to complete the exposure of the exposure area B72, and the original pattern unit 82 is reached to complete the exposure of the exposure area B82. Then, return to the starting position in the vertical direction of this column (the position corresponding to the original pattern unit 02) and step horizontally by the horizontal dimension of the original pattern unit 02 (Die1 type) to reach the original pattern unit 03. The second other non-exposed pattern unit corresponding to the second other mask includes the original pattern unit 03. Therefore, step horizontally by the horizontal dimension of the original pattern unit 03 (Die2 type) to reach the original pattern unit 04. Since the second other non-exposed pattern unit corresponding to the second other mask also includes the original pattern unit 04, continue to step horizontally by the horizontal dimension of the original pattern unit 04 (Die2 type) to reach the position corresponding to the original pattern unit 05 (Die1 type). Repeat the second alignment mark on the substrate (original pattern unit 05). The process involves alignment, offset by a preset distance, and exposure steps to complete the exposure of area B05. Then, the original graphic unit 05 (Die1 type) is vertically moved to the original graphic unit 15 to complete the exposure of area B15. This process is repeated until the original graphic unit 25 is reached to complete the exposure of area B25, then to the original graphic unit 35 to complete the exposure of area B35, then to the original graphic unit 45 to complete the exposure of area B45, then to the original graphic unit 55 to complete the exposure of area B55, then to the original graphic unit 65 to complete the exposure of area B65, then to the original graphic unit 75 to complete the exposure of area B75, and finally to the original graphic unit 85 to complete the exposure of area B85. This completes the lateral interconnection between the computing chip and the memory chip in the M×N (3×3) chipset.

[0172] It can be seen that, in Figure 19 In the example, three masks are selected. Two masks (the first mask and the first other mask) are used to form the vertical connections of the original M×N (3×3) pattern units, and the third mask (the second other mask) is used to form the horizontal connections of the original M×N (3×3) pattern units, ultimately forming a complete M×N (3×3) overall connection of the original pattern units. This achieves the effect of high-density interconnection of M×N multi-chips.

[0173] Figure 19 The example demonstrates the implementation of high-density planar interconnects between multiple chips (such as GPU and DRAM). Furthermore, since chip yield typically decreases with increasing area (i.e., the larger the chip area, the higher the defect probability), to improve overall yield, small chips are often combined to form a large chip, resulting in a composite chip. Specifically, two smaller chips can be fabricated in one exposure field instead of one larger chip. These two smaller chips are then tested, and the known good chip (KGD) is selected. These are then recombined into a fully functional large chip. This method avoids the problem of the entire large chip being scrapped due to a defect in one chip, thus effectively improving the yield of the final product. In other words, in the embodiments of this application, an existing pattern unit on the substrate can be a composite pattern unit composed of at least two sizes of existing pattern units. It should be noted that the size is slightly smaller than the limit size of the exposure field of a traditional lithography machine (e.g., 26mm × 33mm) (e.g., 25mm × 32mm) (i.e., the aforementioned composite chip). For example, taking the GPU-DRAM system as an example, the above... Figure 19 The GPU in the system can be composed of two GPU chips.

[0174] like Figure 20 The diagram illustrates an example of two sizes of original patterning units in the photolithography implementation method provided in this application. Original patterning unit 620 is composed of two computational chips, computational chip 6201 and computational chip 6202, while original patterning unit 640 is composed of two chips, chip 6401 and chip 6402. Computational chips 6201 and 6202 are not interconnected, nor are chips 6401 and 6402 interconnected. As can be seen from the diagram, if computational chips 6201 and 6202 can be connected to form an integral chip of original patterning unit 620, and chips 6401 and 6402 can be connected to form an integral chip of original patterning unit 640, then by attaching... Figure 19 The interconnection is achieved in the manner shown. In this case, it is only necessary to place the connection pattern between the operational chips 6201 and 6202 in the exposure area 800, that is... Figure 19In the exposure area B02, a connecting pattern is placed inside the original graphic unit 02 to form a horizontal connection between the two computational chips. That is, the second mask used adds a horizontal connecting pattern inside the mask to form a horizontal connection between the two computational chips, thus allowing for complete utilization. Figure 19 The exposure scheme is used for photolithography; please refer to [reference needed]. Figure 19 The relevant descriptions will not be repeated here.

[0175] It should be noted that in the process of using KGD Die for die bonding followed by photolithography, in addition to requirements for chip thickness, gap filling, and high-precision die bonding, the setting of alignment marks is also very important. In order to ensure the accurate overlay and interconnection between the patterns of each layer in the subsequent photolithography process, appropriate and complete alignment marks need to be retained on the relevant chips to ensure the alignment accuracy and reliability of the overall process.

[0176] The aforementioned implementation method primarily involves connecting the M×N chips to existing patterned units via vias, thereby forming chip-to-chip interconnects. Alternatively, the chip-to-chip interconnects in an M×N chipset can also be connected using the same material. For example, if the existing patterned unit is a photolithographically etched pattern, the existing patterned unit and the exposed area are connected on the same layer of photoresist; or if the top layer of the existing patterned unit is a metal layer, the exposed area, after photolithography, is connected to the existing patterned unit on the same metal layer, thus connecting the M×N chipset.

[0177] It should be noted that when using vias to achieve chip interconnection in an M×N chipset, only the alignment accuracy between the exposed area and the via needs to be considered during implementation. However, when using the same layer material to achieve chip interconnection in an M×N chipset, it is necessary to consider the damage to the original pattern caused by placing the exposed area, and to perform pattern protection processing in the overlapping areas.

[0178] In this embodiment, the exposed area and the top layer of the original patterned unit can be on the same material layer, which is photoresist. This saves one metal layer and corresponding process steps, and the connections between the original patterned units can be made directly with metal lines without the need for vias. Furthermore, in this case, there is an overlapping area between the exposed area and the covered original patterned unit. The exposed area and the covered original patterned unit are connected through this overlapping area.

[0179] The following section provides a detailed explanation of how to handle lines in overlapping areas:

[0180] The overlapping area includes at least a first overlapping area in the exposure area and a second overlapping area of ​​the top layer of the original graphic unit. The first overlapping area may include a first line, a second line, and a third line, and the second overlapping area may include a fourth line, a fifth line, and a sixth line; the first line and the third line are connected, and the second line is connected to the third line; the fourth line and the sixth line are connected, and the sixth line and the fifth line are connected.

[0181] Wherein, the first line is a line in the first overlapping area used to connect the first overlapping area and the second overlapping area; the fourth line is a line in the second overlapping area used to connect the first overlapping area and the second overlapping area; the second line is a line formed in the first overlapping area after expanding or contracting the fourth line; the third line is a line in the first overlapping area that strengthens the connection between the first overlapping area and the second overlapping area; the fifth line is a line in the second overlapping area after expanding or contracting the first line; and the sixth line is a line in the second overlapping area that strengthens the connection between the first overlapping area and the second overlapping area.

[0182] It should be noted that the first, second, third, fourth, fifth, and sixth lines here refer to a patterned structure formed on the substrate surface through photolithography. Taking positive photoresist and aluminum metal wires as examples, the first, second, third, fourth, fifth, and sixth lines refer to the portions not dissolved by the developer. That is, the first, second, third, fourth, fifth, and sixth lines are the portions where photoresist remains, representing a part of the future circuit layout, and do not actually form conductive paths. The actual conductive lines used to transmit current (such as copper wires) are formed through subsequent processes.

[0183] When a positive photoresist is used, the parts exposed to light during exposure undergo chemical changes, making them easier to dissolve in the developer. In other words, the photoresist in the exposed areas is removed, while the unexposed areas remain. When a negative photoresist is used, the parts exposed to light during exposure cross-link and solidify, becoming more difficult to dissolve in the developer. In other words, the unexposed photoresist is removed by the developer, while the exposed photoresist remains on the wafer.

[0184] In this embodiment, when a positive photoresist is used, the mask lines of the first, second, third, fourth, fifth, and sixth lines on their respective photomasks are all dark; when a negative photoresist is used, the mask lines of the first, second, third, fourth, fifth, and sixth lines on their respective photomasks are all clear. The actual application depends not only on whether the photoresist is positive or negative, but also on the specific use. This embodiment primarily uses aluminum metal wires and the positive photoresist scenario as examples; other scenarios will not be elaborated upon.

[0185] The following is through the appendix Figure 21 and attached Figure 22 Introducing lines one through six above:

[0186] like Figure 21 The diagram shown is a schematic representation of an example of the first line, second line, and third line in the photolithography implementation method provided in this application. The first overlapping area is the region enclosed by the boundary (physical boundary or defined boundary) 2036 of the exposure area to which the first overlapping area belongs and the line 20351 corresponding to the boundary 2035 of the top-level graphic of the original graphic unit to which the second overlapping area belongs. The first overlapping area includes the first line 2021, the second line 2022, and the third line 2034. The second line 2022 is formed by expanding and contracting the fourth line 2011 included in the second overlapping area. The physical boundary is the actual exposure field boundary. The defined boundary, such as... Figure 16 In the case where the entire area of ​​the original graphic unit 620 is covered, in order to connect the original graphic unit 620 with the original graphic unit 610 and with the original graphic unit 670, the exposure area 800 needs to set overlapping area boundaries on the side of the area covering the original graphic unit 620 closest to the original graphic unit 610 and on the side of the original graphic unit 670. These overlapping area boundaries are called defined boundaries. By setting these boundaries, the original graphic unit 610, the original graphic unit 620, and the exposure area 800 achieve a similar... Figure 14 The diagram shows the overlapping effect of the original graphic unit 610, the original graphic unit 620, and the exposure area 800. In this embodiment, the exposure area 800 typically does not contain any graphic in the area between the two defined boundaries, meaning it is opaque. The boundaries mentioned below are similar and will not be described in detail hereafter.

[0187] like Figure 22The diagram shown is a schematic representation of an example of the fourth, fifth, and sixth lines in the photolithography implementation method provided in this application. The second overlapping region is the area formed by the boundary 2035 of the second overlapping region and the line 20361 in the second overlapping region corresponding to the boundary 2036 of the first overlapping region. The second overlapping region includes the fourth line 2011, the fifth line 2012, and the sixth line 2033. The fifth line 2012 is a line formed by expanding and contracting the first line 2021 included in the first overlapping region.

[0188] As can be seen, the second line has an expansion / contraction amount relative to the fourth line, and the fifth line has an expansion / contraction amount relative to the first line. That is to say, the width of the second line is greater than the width of the fourth line, and the width of the fifth line is greater than the width of the first line. In this way, when the first overlapping area and the second overlapping area are misaligned, the second line will not destroy the fourth line, and the fifth line will not destroy the first line. This avoids the problem that the first overlapping area and the second overlapping area cannot be interconnected when they are misaligned.

[0189] It should be noted that the expansion or contraction of the second line relative to the fourth line is greater than or equal to a preset alignment deviation limit between the first overlapping area and the second overlapping area; and the expansion or contraction of the fifth line relative to the first line is greater than or equal to the alignment deviation limit.

[0190] For example, the expansion or contraction of the second line relative to the fourth line and the expansion or contraction of the fifth line relative to the first line can be 1.1 times, 1.2 times, or 1.5 times the preset alignment deviation limit between the first overlapping area and the second overlapping area.

[0191] like Figure 23 The diagram shown is a schematic representation of an example of the overlap between the first and second overlapping regions in the photolithography method for implementing high-density multi-chip interconnection provided in this application. Figure 23This includes 18-a and 18-b. 18-a is a schematic diagram when the first and second overlapping areas are perfectly aligned; 18-b is a schematic diagram when the first and second overlapping areas are misaligned. Figure 203334-1 shows the overlapping portion of the third and sixth lines when the first and second overlapping areas are aligned; Figure 203334-2 shows the overlapping portion of the third and sixth lines when the first and second overlapping areas are misaligned. It can be seen that the size (width) of Figure 203334-2 is smaller than that of Figure 203334-1. If the fifth line 2012 is not expanded or contracted, and only the original width of the first line 2021 is maintained, then when the first and second overlapping areas are misaligned, the first line 2021 will appear outside the area of ​​the fifth line 2012, causing the first line 2021 in the first overlapping area to be destroyed. Correspondingly, if the second line 2022 is not expanded or contracted, and only the original width of the fourth line 2011 is maintained, then when the first and second overlapping areas are misaligned, the fourth line 2011 will appear outside the area of ​​the second line 2022, causing the fourth line 2011 in the second overlapping area to be damaged. By expanding or contracting the second line 2022 and the fifth line 2012, even under misalignment, the fifth line 2012 still has a sufficiently wide unexposed photoresist, thus ensuring that the first line 2021 is within the coverage area of ​​the fifth line 2012. Correspondingly, the second line 2022 also has a sufficiently wide unexposed photoresist, thus ensuring that the fourth line 2011 is also within the coverage area of ​​the second line 2022, avoiding the risk of damaging the exposed lines of the other side.

[0192] In this embodiment, the second line is set to have expansion and contraction relative to the fourth line, and the fifth line is set to have expansion and contraction relative to the first line. This can prevent the line connecting the first and second overlapping areas from being destroyed when the first overlapping area and the second overlapping area are misaligned.

[0193] It should be noted that the second line is located within the overlapping region and does not exceed the boundary of the first overlapping region within the overlapping region, and the fifth line is located within the overlapping region and does not exceed the boundary of the second overlapping region within the overlapping region. (See attached...) Figure 21 and attached Figure 22For example, the second line 2022 does not exceed the boundary 2036 of the first overlapping area within the overlapping area, and the fifth line 2012 does not exceed the boundary 2035 of the second overlapping area within the overlapping area. That is, the area 20101 outside the boundary 2036 of the first overlapping area does not contain any line patterns from the first overlapping area, and area 20101 is opaque; the area 20201 outside the boundary 2035 of the second overlapping area does not contain any line patterns from the second overlapping area, and area 20201 is opaque.

[0194] In this way, the patterns produced by the exposure of the first overlapping area and the second overlapping area are both within their respective boundaries, and the area outside the boundaries is an opaque area, which will not damage the patterns produced by the exposure.

[0195] In one optional implementation, the first overlapping area includes a plurality of first lines, a plurality of second lines, and a plurality of third lines; there is a first interval between each pair of adjacent first lines, a second interval between each pair of adjacent second lines, and a third interval between each pair of adjacent third lines.

[0196] The second overlapping area includes a plurality of fourth lines, a plurality of fifth lines, and a plurality of sixth lines; there is a fourth interval between each pair of adjacent fourth lines, a fifth interval between each pair of adjacent fifth lines, and a sixth interval between each pair of adjacent sixth lines.

[0197] like Figure 24 The diagram illustrates an example of a first overlapping region comprising multiple sets of lines and a second overlapping region comprising multiple sets of lines in an implementation of the multi-chip high-density interconnect lithography technology provided in this application. The first overlapping region includes multiple first lines 2021, namely a first first line 20211, a second first line 20212, and a third first line 20213; multiple second lines 2022, namely a first second line 20221, a second second line 20222, and a third second line 20223; and multiple third lines 2034, namely a first third line 20341, a second third line 20342, and a third third line 20343. The second overlapping area includes multiple fourth lines 2011, namely the first fourth line 20111, the second fourth line 20112, and the third fourth line 20113, as well as multiple fifth lines, namely the first fifth line 20121, the second fifth line 20122, and the third fifth line 20123, and multiple sixth lines 2033, namely the first sixth line 20331, the second sixth line 20332, and the third sixth line 20333.

[0198] There is a first interval between every two adjacent ones of the first lines, a second interval between every two adjacent ones of the second lines, and a third interval between every two adjacent ones of the third lines. Taking the appendix Figure 24 as an example, the first intervals are respectively the first interval 20161 and the first interval 20162, the second intervals are respectively the second interval 20181 and the second interval 20182. Since the Figure 24 second lines and the third lines in the appendix have the same dimensions, the third intervals are also respectively the third interval 20181 and the third interval 20182.

[0199] There is a fourth interval between every two adjacent ones of the fourth lines, a fifth interval between every two adjacent ones of the fifth lines, and a sixth interval between every two adjacent ones of the sixth lines. Taking the appendix Figure 24 as an example, the fourth intervals are respectively the fourth interval 20151 and the fourth interval 20152, the fifth intervals are respectively the fifth interval 20171 and the fifth interval 20172. Since the Figure 24 fifth lines and the sixth lines in the appendix have the same dimensions, the sixth intervals are also respectively the sixth interval 20171 and the sixth interval 20172.

[0200] The interval region 2018 and the interval region 2017 are light-transmitting regions. That is to say, on the manufactured mask plate, the mask plate regions corresponding to the interval region 2018 and the interval region 2017 are designed as light-transmitting regions so that the light source can pass through this region. However, during the dry etching process, due to the etching rate difference phenomenon caused by the different pattern densities of the etched structures, that is, in the high-density pattern region (such as dense lines or through holes), the gas reactants are easily "consumed", resulting in a decrease in the local reaction rate, while in the low-density region (such as isolated features), the reactants are more likely to reach the surface and the etching rate is faster instead. This will make the etching in the high-density region slow and the etching in the low-density region fast, resulting in inconsistent minimum critical dimensions and affecting the device performance and consistency. To avoid the above phenomenon, the interval region 2018 and the interval region 2017 can also be subjected to pattern filling treatment, that is, adding virtual patterns that do not affect the function in the interval region 2018 and the interval region 2017, so as to increase the overall pattern density of the interval region 2018 and the interval region 2017 and slow down the influence of the microloading effect. It should be noted that due to the problem of double exposure, attention should also be paid to preventing adverse effects (such as the problem of thin lines (such as lines smaller than the minimum lithography resolution) falling off after development) in the pattern filling of the overlapping region (especially the overlapping exposure with reasonable misalignment).

[0201] When the first overlapping area and the second overlapping area overlap vertically, the first interval is a horizontal interval, and the second interval and the third interval are vertical intervals. When the first overlapping area and the second overlapping area overlap horizontally, the first interval is a vertical interval, and the second interval and the third interval are horizontal intervals.

[0202] When the first overlapping area and the second overlapping area overlap vertically, the fourth interval is a horizontal interval, and the fifth and sixth intervals are vertical intervals. When the first overlapping area and the second overlapping area overlap horizontally, the fourth interval is a vertical interval, and the fifth and sixth intervals are horizontal intervals.

[0203] Furthermore, the first interval is greater than or equal to the minimum critical dimension of the lithography equipment. The fourth interval is greater than or equal to the minimum critical dimension of the lithography equipment.

[0204] When the size of the second line is greater than or equal to the size of the third line, the second interval is greater than or equal to a target value, where the target value is the maximum value among the minimum critical size of the lithography apparatus and the alignment deviation limit between the first overlapping area and the second overlapping area. When the size of the second line is less than the size of the third line, the third interval is greater than or equal to the target value.

[0205] When the size of the fifth line is greater than or equal to the size of the sixth line, the fifth interval is greater than or equal to the target value. When the size of the fifth line is less than the size of the sixth line, the sixth interval is greater than or equal to the target value.

[0206] This can prevent the influence of the offset. On the one hand, the third line 2034 of the first overlapping area and the sixth line 2033 of the second overlapping area may be made thicker and / or longer. When they are made thicker, if the spacing between the second lines is still greater than the target value and the spacing between the fifth lines is greater than the target value, the spacing between the third lines will become smaller. When the offset between the first overlapping area and the second overlapping area is close to the alignment deviation limit, the third line 2034 of the first overlapping area and the sixth line 2033 of the second overlapping area may overlap in a non-preset way, resulting in additional overlapping graphics.

[0207] To fully utilize the overlapping area, the overlapping area can include a large number of lines. Specifically, the first overlapping area includes multiple first line sets, and the second overlapping area includes multiple second line sets; each first line set includes multiple first lines, multiple second lines, and multiple third lines; each second line set includes multiple fourth lines, multiple fifth lines, and multiple sixth lines; there is a first set interval between each pair of adjacent first line sets; and there is a second set interval between each pair of adjacent second line sets.

[0208] like Figure 25 The diagram shown illustrates an example of an implementation of the multi-chip high-density interconnect lithography technology provided in this application, where the overlapping region includes multiple sets of lines. It can be seen that the first overlapping region includes multiple sets of first lines, with a first set interval between each pair of adjacent sets of first lines, namely first set interval 20141 and first set interval 20142; the second overlapping region includes multiple sets of second lines, with a second set interval between each pair of adjacent sets of second lines, namely second set interval 20241 and second set interval 20242.

[0209] When the first overlapping area and the second overlapping area overlap vertically, both the first set interval and the second set interval are horizontal intervals. When the first overlapping area and the second overlapping area overlap horizontally, both the first set interval and the second set interval are vertical intervals.

[0210] Both the first set interval and the second set interval are greater than or equal to the target value. That is, both the first set interval and the second set interval are greater than or equal to the maximum value among the minimum critical size of the lithography equipment and the alignment deviation limit between the first overlapping area and the second overlapping area.

[0211] It should be noted that there is a difference in the lithography scale between the mask pattern and its actual exposure area on the substrate. Each line, spacing, etc., needs to be described in terms of both the mask and the actual exposure area on the substrate. Considering the difference in the scale between the two based on the content of this invention is the proper approach and does not need to be elaborated.

[0212] It should be noted that the above overlapping area is only an example of solving the connection between an exposure area and an original graphic unit. In reality, it is usually necessary to solve the connection between an exposure area and two original graphic units, or the connection between multiple exposure areas and multiple original graphic units. In fact, each connection has an overlapping area, and each overlapping area has a corresponding first overlapping area of ​​the exposure area and a second overlapping area of ​​the top layer graphic of the original graphic unit. The first overlapping area overlaps with the second overlapping area, and the above method can be used to process the corresponding overlapping areas.

[0213] In one optional implementation, the first exposure area and the exposure areas formed by other photomasks are on the same material layer or on different material layers. The same material layer is a photoresist layer, an insulating layer (such as dielectric materials such as oxides and nitrides), or a metal layer (such as conductive materials such as aluminum and copper).

[0214] In one specific implementation, when the first exposure area and the exposure areas formed by other masks are on the same layer of material, the first exposure area and the exposure areas formed by other masks are on the same layer of photoresist; that is, the first exposure area and the exposure areas formed by other masks are exposure areas formed on the same layer of photoresist. When the first exposure area and the exposure areas formed by other masks are on the same material layer but not on a different material layer from the top layer of the original pattern unit, the connection is generally formed by connecting the lines after development and etching with the holes of the original pattern unit. Only the alignment deviation between layers needs to be considered. However, when the first exposure area and the exposure areas formed by other masks are on the same material layer as the original pattern unit, especially when they are on the same photoresist layer, overlapping area processing is required as described above. In addition, when the first exposure area and the exposure areas formed by other masks are on the same material layer as the original pattern unit, even if the same material layer is not photoresist, if the first exposure area and the exposure areas formed by other masks are on the same metal layer as the top layer of the original pattern unit, overlapping area processing is still required. The method for processing the overlapping area lines is similar to that when they are all on photoresist.

[0215] When the exposure areas formed by the first exposure area and other masks are on the same layer of photoresist, the photolithography equipment includes two mask stages, each of which loads either the first mask or any of the other masks.

[0216] The first exposure area and the exposure areas formed by other masks are usually on the same layer of material, but there are also cases where they are on different layers of material. For example, when different functional modules are installed on a carrier board for connection, some need to form an electrical connection between two functional patterns through the first exposure area, while others need to form an optical connection through the exposure areas formed by other masks. In such cases, different materials may be used for processing.

[0217] In one optional embodiment, there are one or two stages. When there are two stages, each stage is loaded with a substrate to be exposed.

[0218] When there are two stages, multiple stages can be controlled to move in turn under the projection system to complete the exposure. During the alignment and exposure process performed by the first stage, the second stage is controlled to perform silicon wafer loading / unloading and pre-alignment steps.

[0219] By using a method of alternating movement of the stage to the projection system to complete the exposure, one stage can perform other preparatory work while the other stage is performing exposure, such as loading the substrate or performing preliminary substrate alignment. In one example, multiple stages include a first stage and a second stage. During the exposure performed by the first stage, the second stage can be controlled to perform silicon wafer loading and unloading and pre-alignment steps. Here, pre-alignment refers to preliminary alignment using alignment marks on the substrate to be exposed loaded on the second stage.

[0220] For example, a lithography machine includes stage a and stage b. During alignment and exposure on stage a, stage b is controlled to perform wafer loading / unloading and pre-alignment. Correspondingly, during alignment and exposure on stage b, stage a is controlled to perform wafer loading / unloading and pre-alignment. In this way, after the first stage completes exposure, the exposure of the second stage can be started immediately, effectively reducing the time the lithography machine is idle. On the other hand, the time consumed by switching between stages is shorter than the time consumed by substrate replacement and preliminary alignment on a single stage, achieving a near-seamless workflow and thus improving lithography efficiency.

[0221] The above is a description of the photolithography method for implementing high-density interconnection of multiple chips provided in the embodiments of this application.

[0222] As can be seen, the photolithography method for high-density interconnection of multiple chips provided in this application includes the following steps: obtaining a substrate map, which reflects the positional distribution information of the original pattern units on the substrate to be exposed; generating a sub-map based on the substrate map for a mask to be loaded; the sub-map reflects the positional distribution information of the original pattern units to be exposed on the substrate; the mask is provided with layout information for interconnecting at least two chips in a set direction; loading the mask onto the mask stage of the photolithography equipment and offsetting the mask by a preset offset distance; loading the substrate onto the stage of the photolithography equipment and performing a first alignment using a first alignment mark on the substrate; controlling the stage to move according to a set direction and path based on the sub-map, aligning the mask with the original pattern units to be exposed on the substrate using a second alignment mark on the substrate, offsetting the substrate by a preset offset distance, and performing exposure to transfer the preset pattern on the mask to the exposure area corresponding to the original pattern units to be exposed on the substrate. In this way, the movement of the substrate can be controlled based on the sub-map, and the pattern of the mask can be transferred to the substrate so that at least two chips can be interconnected, thereby realizing high-density interconnection of multiple chips and forming a large-size chip. This provides photolithography technology support for the high-density interconnection and integration of M×N large chips (such as multiple chips of about 26mm×33mm size, such as 25mm×32mm chips).

[0223] Furthermore, in existing technologies, chip interconnection is mainly achieved through on-board level interconnection. This method typically involves interconnecting chips via a circuit board after packaging, resulting in a complex structure and large size. During use, signals need to travel along long circuit board paths, leading to significant signal delays. Long traces are also susceptible to electromagnetic interference, causing signal distortion. The longer traces and drive circuits also result in larger capacitive loads, inevitably increasing power consumption. Simultaneously, the larger trace and solder joint sizes limit the interconnection density between chips, and the need for larger communication drive circuits further restricts this density. In contrast, the photolithography method for high-density multi-chip interconnection provided in this application enables chip-level interconnection. This allows multiple chips to be connected simultaneously during chip manufacturing. During use, the shortened interconnection distance significantly reduces signal transmission time, lowers the risk of signal distortion, improves signal integrity, and reduces parasitic loads, thereby reducing power consumption. Furthermore, this invention directly uses existing high-performance lithography machines (such as DUV lithography machines and EUV lithography machines) to perform chip interconnect lithography, with the smallest line size reaching 0.1um or even a few nm, which can greatly improve the density of chip interconnect lines, ultimately forming a large chip with high-density chip interconnects (such as M×N×25mm×32mm) formed by M×N large chips (such as 25mm×32mm).

[0224] A second embodiment of this application provides a chip-level interconnection method, comprising the following steps: providing a substrate, forming a semiconductor structure including at least two semiconductor chips on the substrate, each semiconductor chip having an intra-chip interconnect, and no inter-chip interconnect; and realizing the interconnection between the at least two semiconductor chips using the photolithography technology implementation method for high-density multi-chip interconnection provided in the first embodiment of this application. In this embodiment, two, three, four, six, eight, or nine semiconductor chips have been fabricated on the substrate using processes such as photolithography, etching, and deposition. Furthermore, the internal metal layers (such as copper interconnects) within each semiconductor chip have formed intra-chip interconnects, but there are no inter-chip interconnects.

[0225] The at least two semiconductor chips can be arranged horizontally, vertically, or in a matrix. For example, a semiconductor structure comprising 1×2 semiconductor chips can be formed on the substrate; another example is a semiconductor structure comprising 2×1 semiconductor chips; yet another example is a semiconductor structure comprising 2×3 semiconductor chips. Each semiconductor chip can be a single-exposure patterned area formed using a projection system with a reduction ratio of 4 to 10 times or other reduction ratios. For example, each semiconductor chip can be a single-exposure patterned area formed using a projection system with a reduction ratio of 4 times; another example is a single-exposure patterned area formed using a projection system with a reduction ratio of 5 times; another example is a single-exposure patterned area formed using a projection system with a reduction ratio of 8 times; yet another example is a single-exposure patterned area formed using a projection system with a reduction ratio of 10 times. Taking a reduction ratio of 5 times for the projection system as an example, the maximum size of each semiconductor chip formed is generally 26mm × 33mm. It should be understood that the size of each semiconductor chip formed can also be smaller than 26mm × 33mm, such as 25mm × 32mm, etc., as long as it is smaller than the maximum size. This application does not further limit the specific size of the semiconductor chip. A single semiconductor chip can be understood as the original patterned unit in the photolithography technology implementation method for high-density interconnection of multiple chips provided in the first embodiment of this application. With the substrate as described above provided, the interconnection between at least two semiconductor chips can be realized through the photolithography technology implementation method for high-density interconnection of multiple chips provided in the first embodiment of this application. It should be noted that the interconnection between at least two semiconductor chips can be realized through the photolithography technology implementation method for high-density interconnection of multiple chips provided in the first embodiment of this application, and will not be repeated here. It can be seen that the chip-level chip interconnection method provided in this application embodiment can realize high-density interconnection of integrated circuits, providing photolithography technology support for high-density interconnection integration of multiple large chips.

[0226] A third embodiment of this application also provides a method for fabricating mask lines, comprising the following steps: fabricating a first mask line, a second mask line, and a third mask line on a mask; the first mask line and the third mask line are connected, and the second mask line is connected to the third mask line; wherein, the first mask line is used to expose and form a first line as described in the first embodiment of this application in a first exposure area of ​​a substrate; the second mask line is used to expose and form a second line as described in the first embodiment of this application in the first exposure area of ​​the substrate; and the third mask line is used to expose and form a third line as described in the first embodiment of this application in the first exposure area of ​​the substrate.

[0227] The fourth embodiment of this application also provides a photolithography apparatus, including two mask stages, three or four stages, two upper and lower silicon wafer systems, and two silicon wafer measurement systems. The photolithography apparatus has been described in detail above and will not be repeated here.

[0228] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for implementing a lithographic technique for multi-chip high-density connection, characterized in that, The method comprises the following steps: acquiring a substrate map, which reflects the position distribution information of the original pattern units present on a substrate to be exposed; the substrate map comprises at least one of the position information, state information and size information of each original pattern unit on the substrate; generating a sub-map for a mask to be loaded according to the substrate map; the sub-map reflects the position distribution information of the original pattern units on the substrate that need to be exposed by the mask; the mask is provided with layout information for interconnecting at least two chips in a set direction; loading the mask to a mask stage of a photolithography device and biasing the mask by a preset offset distance; loading the substrate to a stage of the photolithography device and performing first alignment by a first alignment mark on the substrate; controlling the stage to move in a set direction and path based on the sub-map, aligning the mask with the original pattern units on the substrate that need to be exposed by the mask through a second alignment mark on the substrate, biasing the substrate by a preset offset distance, performing exposure to transfer a preset pattern on the mask to an exposure region on the substrate corresponding to the original pattern units that need to be exposed by the mask.

2. The method of claim 1, wherein, The step of generating a sub-map according to the substrate map comprises: deleting the position information of non-exposure original pattern units that do not need to be exposed by the mask from the substrate map to generate a sub-map; or marking the position information of non-exposure original pattern units that do not need to be exposed in the substrate map to generate a sub-map.

3. The method of claim 1, wherein, At least two masks are used to realize the interconnection of an M×N chip group; for any M×N chip group, the interconnection line pattern on the peripheral scribe lane of the M×N chips connected together does not penetrate into the interior of the original pattern units and connects the original pattern units; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2.

4. The method of claim 1, wherein, The size of the original pattern unit is one or more.

5. The method according to any one of claims 1-3, wherein the original pattern units comprise composite pattern units composed of original pattern units of at least two sizes.

6. The method according to claim 1, wherein the substrate is one of a silicon substrate, a germanium substrate, a compound semiconductor substrate, a ceramic carrier plate, a glass carrier plate, a quartz carrier plate, a silicon carrier plate and a metal carrier plate, or the substrate is loaded with one or more of a silicon substrate, a germanium substrate and a compound semiconductor substrate.

7. The method of claim 1, wherein, In the case where the exposure region and the top layer pattern material of the original pattern unit are in the same layer of photoresist, the exposure region and the covered original pattern unit have an overlapping region, and the exposure region and the covered original pattern unit are connected through the overlapping region.

8. The method according to claim 7, wherein the overlapping region comprises at least a first overlapping region in the exposure region and a second overlapping region in the top layer pattern of the original pattern unit.

9. The method of claim 8, wherein, The first overlapping area includes a first line, a second line and a third line; the second overlapping area includes a fourth line, a fifth line and a sixth line; the first line and the third line are connected and the second line and the third line are connected; the fourth line and the sixth line are connected and the sixth line and the fifth line are connected; The first line is a line in the first overlapping area for connecting the first overlapping area and the second overlapping area; the fourth line is a line in the second overlapping area for connecting the first overlapping area and the second overlapping area; the second line is a line formed in the first overlapping area after the fourth line is expanded or contracted; the third line is a line for strengthening the connection between the first overlapping area and the second overlapping area in the first overlapping area; the fifth line is a line formed in the second overlapping area after the first line is expanded or contracted; and the sixth line is a line for strengthening the connection between the first overlapping area and the second overlapping area in the second overlapping area.

10. A chip-to-chip interconnection method, characterized by, The method comprises: providing a substrate, forming a semiconductor structure including at least two semiconductor chips on the substrate, each semiconductor chip having at least formed an intra-chip partial interconnection, and no inter-chip interconnection; realizing the interconnection between the at least two semiconductor chips by the photolithography technology realization method according to any one of claims 1-9.

11. A lithographic apparatus, characterized in that, The photolithography equipment comprises two mask tables, three or four object tables, two upper and lower silicon wafer systems and two silicon wafer measurement systems; the photolithography equipment is used to realize the interconnection between the at least two semiconductor chips by the photolithography technology realization method according to any one of claims 1-9.

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