A bias adaptive device and method against semiconductor threshold voltage dispersion

Abstract

The application discloses a kind of bias adaptive devices and methods of semiconductor threshold voltage dispersion, bias adaptive devices and single piece homogeneous integration with multifunction chip, the same state is experienced in multifunction chip and bias adaptive device, when the threshold voltage of bias adaptive device and multifunction chip is generated consistent dispersion, the link resistance of bias adaptive device changes, output multiple follow threshold voltage dispersion changes bias voltage, to provide different threshold voltage dispersion sensitivity under the gate dynamic reference voltage curve of any type of combination of multifunction chip, ensure that the static working state of multifunction chip die does not change.The device of the application is suitable for wafer production, chip assembly, reliability test and environmental test and other processes caused by threshold voltage shift of multifunction chip.Can significantly expand the design window of multifunction chip that needs to accurately control the precision of gate bias voltage, while significantly improving the yield of chip.

Description

Technical Field

[0001] This invention relates to a bias adaptive device and method for resisting semiconductor threshold voltage discrepancies, belonging to the field of integrated circuit technology. Background Technology

[0002] With the rapid development of the scale and integration of monolithic integrated circuits, the requirements for static bias voltage of the multifunctional circuit units within current monolithic multifunctional integrated circuits are becoming more diversified, and their sensitivity to the static operating point is also increasing. This is especially true for multifunctional chips combining one or more functions such as RF / microwave / terahertz power amplifiers (PAs), variable gain amplifiers (VGAs), analog predistorters (APDs), phase shifters, and attenuators, where the static bias voltage accuracy needs to be precisely controlled within ≤10~20 mV. However, compound semiconductor devices are affected by stress and defects during the manufacturing process, resulting in threshold voltage dispersion between batches, different locations on the chip, and different die sizes. The maximum value of this threshold voltage dispersion is typically ±200 mV, making it impossible to control the static current fluctuation of multifunctional circuits to ≤±5% through static bias voltage, severely limiting chip performance. Furthermore, threshold voltage deviations caused by chip assembly, reliability testing, or environmental testing also significantly affect chip performance. Specifically, the aforementioned discrete phenomena will greatly affect various performance indicators of the circuit, including but not limited to the gain flatness, efficiency, and linearity at rated power of the PA; the gain linearity, noise, and input sensitivity of the VGA; and the gain and phase nonlinearity compensation range of the APD.

[0003] On the other hand, the dispersion of threshold voltages of devices at different locations within a wafer can significantly reduce the yield of multifunctional monolithic integrated circuits produced using compound semiconductor processes.

[0004] Currently, commonly used bias adaptive circuit designs typically address only input signal power fluctuations, external voltage variations, and temperature changes. Research on bias adaptive circuit designs for chip threshold voltage discrepancies is limited. Existing research only performs envelope tracking on the RF input signal to achieve bias voltage adaptation under large dynamic excitation.

[0005] In addition, the commonly used bias adaptive circuit structure is the LDO (Low Dropout Regulator) structure. Its basic structure includes a reference voltage source (providing a stable reference voltage), an error amplifier (comparing the feedback voltage with the reference voltage and amplifying the error signal), a power transistor (adjusting the output voltage), a feedback network (sampling the output voltage and feeding it back to the error amplifier), and a load capacitor (stabilizing the output voltage and reducing noise and transient response). It can be seen that the LDO structure has the following obvious drawbacks: ① This structure, based on a feedback loop for adaptive adjustment of the output voltage, is complex, occupies a large amount of chip area, and has a certain delay; ② This structure contains an amplifier, consuming a large amount of power and chip area; ③ During the manufacturing process, the discreteness of the device threshold voltage in the circuit units can cause a shift in the reference voltage, making it impossible to achieve high-precision output voltage adaptation; ④ This structure is a general-purpose circuit unit manufactured using Si technology, which inherently limits its monolithic integration with multi-functional circuit units to heterogeneous integration, increasing the difficulty and cost of use.

[0006] Therefore, for multifunctional circuits that require precise control of static bias voltage accuracy, there is an urgent need for a low-cost, easy-to-implement method to combat semiconductor threshold voltage discrepancies and improve their performance and yield. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a bias adaptive device and method for resisting semiconductor threshold voltage dispersion. The bias adaptive device is monolithically integrated with a multifunctional circuit. The voltage output by the device follows the threshold voltage dispersion of the multifunctional chip as the gate bias voltage of the multifunctional chip. This ensures that the gate bias voltage of the multifunctional chip at any position on the wafer changes synchronously with the threshold voltage, thus ensuring the performance stability of the multifunctional chips within the same wafer.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] A bias adaptive device for resisting semiconductor threshold voltage discrepancies is provided. The bias adaptive device is monolithically homogeneously integrated with each multifunctional chip on a wafer. For each multifunctional chip and the corresponding bias adaptive device on the wafer, when the multifunctional chip and the bias adaptive device are in the same state and the threshold voltage of the bias adaptive device and the multifunctional chip both produce consistent discrepancies, the output voltage of the bias adaptive device is used as the gate bias voltage required by the multifunctional chip. Moreover, the voltage output by the bias adaptive device at different positions on the wafer changes with the threshold voltage discrepancy of the corresponding multifunctional chip, thereby keeping the gate bias voltage and threshold voltage of each multifunctional chip on the wafer changing synchronously.

[0010] The bias adaptive device includes a threshold discrete sampling adaptive network and a multi-sensitivity bias reconstruction network. The threshold discrete sampling adaptive network includes cascaded threshold discrete sampling resistors and 1 to k levels of threshold adaptive units, where k ≥ 1. The connection between the threshold discrete sampling resistor and the first-level threshold adaptive unit serves as the output terminal of the threshold discrete sampling adaptive network. The threshold discrete sampling resistor is used to obtain the maximum absolute value of the threshold voltage discreteness of each multi-functional chip on the wafer, i.e. This determines the operating range of the bias adaptive device; the 1 to k level threshold adaptive units are used to provide the maximum absolute value of all gate bias voltages required by the multi-functional chip, i.e. The bias voltage VG1 output by the threshold discrete sampling adaptive network satisfies: , This represents the x-th gate bias voltage required by the multi-functional chip, where x = 1, ..., i, and i is the number of gate bias voltages required by the multi-functional chip.

[0011] The multi-sensitivity bias reconfiguration network includes parallel dynamic bias modules of dimensions 1 to j, where 1 ≤ j ≤ i. Each dynamic bias module is used to adjust VG1 in stages, thereby outputting all the gate bias voltages required by the multi-functional chip, or outputting all the gate bias voltages except for i. The remaining gate bias voltage besides the corresponding gate bias voltage. Provided by VG1.

[0012] As a preferred embodiment of the device, in the threshold discrete sampling adaptive network, threshold adaptive units of level 1 to k are connected in series. One end of the threshold discrete sampling resistor is connected to one end of the level 1 threshold adaptive unit as the output terminal of the threshold discrete sampling adaptive network. The other end of the threshold discrete sampling resistor is grounded. One end of the k-level threshold adaptive unit is connected to the k-1 level threshold adaptive unit. The other end of the k-level threshold adaptive unit is connected to the power supply voltage.

[0013] Alternatively, in the threshold discrete sampling adaptive network, threshold adaptive units of levels 1 to k are connected in series. One end of the threshold discrete sampling resistor is connected to one end of the level 1 threshold adaptive unit as the output of the threshold discrete sampling adaptive network. The other end of the threshold discrete sampling resistor is connected to the power supply voltage. One end of the level k threshold adaptive unit is connected to the (k-1) level threshold adaptive unit, and the other end of the level k threshold adaptive unit is grounded.

[0014] In a preferred embodiment of the device, the input terminals of the first to j-th dimension dynamic bias modules are all connected to the output terminals of the threshold discrete sampling adaptive network, the first output terminals of the first to j-th dimension dynamic bias modules are connected to the gate bias voltage input terminals of the multi-functional chip, and the first output terminals of the first to j-th dimension dynamic bias modules output all or all of the gate bias voltages required by the multi-functional chip. The remaining gate bias voltages, excluding the corresponding gate bias voltages, are all grounded at the second output terminals of the first to j-th dimension dynamic bias modules.

[0015] As a preferred embodiment of the device, the first to j-th dimension dynamic bias modules are each composed of at least two levels of bias adjustment units connected in series.

[0016] As a preferred embodiment of the device, the threshold voltage discrete value is 0, i.e. At that time, the output voltage VG1 of the threshold discrete sampling adaptive network is the same as that required by the multi-functional chip. The corresponding gate bias voltages are equal.

[0017] As a preferred embodiment of the device, the multifunctional chip includes one or any combination of at least two of the following: a radio frequency power amplifier, a microwave power amplifier, a terahertz power amplifier, a variable gain amplifier, an analog predistorter, a phase shifter, and an attenuator.

[0018] As a preferred embodiment of the device, the bias adaptive device is applicable to the process in which the threshold voltage of a multifunctional chip deviates from the reference threshold voltage, including wafer manufacturing process, chip assembly process, reliability testing process, and environmental testing process.

[0019] A bias adaptive method based on the aforementioned bias adaptive device that resists semiconductor threshold voltage discrepancies is provided, the specific bias adaptive method being as follows:

[0020] When the threshold voltage of the multi-functional chip at different locations within the wafer... Compared to the reference threshold voltage When a deviation occurs, for each multi-functional chip's corresponding bias adaptive device, the threshold voltage of the threshold adaptive unit contained within the threshold discrete sampling adaptive network of the device generates a value corresponding to the multi-functional chip. When synchronization deviates, the resistance of the threshold adaptive unit within the threshold discrete sampling adaptive network changes accordingly. The network generates a bias voltage VG1 that changes synchronously with the threshold voltage discreteness of the multi-functional chip. VG1 changes synchronously with the maximum discrete range of the threshold voltage of the multi-functional chip at different locations within the wafer, resulting in overdrive voltages corresponding to the multi-functional chips at different locations within the wafer. The value remains stable;

[0021] The multi-sensitivity bias reconfiguration network generates multiple voltage divider networks between VG1 and ground through various dynamic bias modules. The threshold voltage of the bias adjustment unit contained within each dynamic bias module corresponds to the multi-functional chip of the device. The synchronous discreteness causes the resistance values ​​of the bias adjustment units within each dynamic bias module to change accordingly during operation. The overall resistance of the dynamic bias module link changes differently as the threshold voltage discreteness occurs. This allows for graded adjustment of VG1 to achieve the functionality required by the multi-functional chip. The output of the gate bias voltage remaining after the corresponding gate bias voltage. The corresponding gate bias voltage is provided by VG1, x=1,…,i, where i is the number of gate bias voltages required by the multi-function chip, or the output of all gate bias voltages required to realize the multi-function chip.

[0022] As a preferred embodiment of the method, the bias adaptive device is applicable to the process in which the threshold voltage of a multifunctional chip deviates from a reference threshold voltage, including wafer fabrication, chip assembly, reliability testing, and environmental testing.

[0023] A design method for a bias adaptive device based on the aforementioned anti-semiconductor threshold voltage discrepancy, the design method being as follows:

[0024] Based on all the gate bias voltages required by the multi-functional chip, determine the maximum absolute value of all gate bias voltages, i.e. , x=1,…,i, where i is the number of gate bias voltages required by the multi-functional chip;

[0025] Based on the power consumption of the bias adaptive device and Together, they determine the resistance range of the threshold discrete sampling resistor and the resistance range of the threshold discrete sampling adaptive network;

[0026] Discretize the maximum absolute value based on the threshold voltage The resistance range of the threshold discrete sampling resistor and the resistance range of the threshold discrete sampling adaptive network jointly determine the number of stages of the threshold adaptive unit;

[0027] The dimension of the dynamic bias module is determined based on the required number of all gate bias voltages for the multi-functional chip, and the number of bias adjustment units is determined by the required number of devices with different gate index quantities and different sizes within the multi-functional chip.

[0028] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0029] 1. This invention uses a bias adaptive device to automatically compensate for the dispersion of the die threshold voltage. After introducing the bias adaptive device, the fluctuation range of the static current of the multi-functional chip with the dispersion of the threshold voltage is significantly compressed, thus expanding the design window of the multi-functional circuit that is sensitive to the static operating point.

[0030] 2. This invention provides gate bias voltage curves under different threshold voltage discrete sensitivities through a bias adaptive device. By adjusting the dimension of the dynamic bias module and the number of stages of the bias adjustment unit, it can be made equal to or close to the threshold voltage discrete curves of each multifunctional chip die. It can be applied to one or more combined multifunctional chips such as RF / microwave / terahertz power amplifiers (PA), variable gain amplifiers (VGA), analog predistorters (APD), phase shifters, and attenuators.

[0031] 3. This invention achieves high-precision adaptive compensation of the gate bias voltage of a multi-functional chip through a bias adaptive device. The bias voltage accuracy can be precisely controlled within ≤10~20 mV, filling the gap in existing bias adaptive circuits (such as LDOs) that cannot achieve high-precision compensation.

[0032] 4. The bias adaptive device of the present invention is applicable to integrated circuits and systems using general semiconductor processes, including but not limited to GaAs pHEMT / HEMT, GaN pHEMT / HEMT, InP pHEMT / HEMT, silicon-based, etc., and can be homogeneously integrated with multifunctional circuit units, thus possessing universality of application.

[0033] 5. This invention effectively improves the chip's resistance to threshold dispersion through a bias adaptive device, which can significantly improve the yield of multifunctional circuits that are sensitive to the static operating point, and greatly increase the number of chips with qualified performance indicators in the final batch test on a single wafer.

[0034] 6. The bias adaptive device of the present invention is applicable to scenarios in which the actual threshold voltage of a multifunctional chip deviates from the reference threshold voltage due to heat, stress, etc. during wafer manufacturing, chip assembly, reliability testing, environmental testing, etc., effectively improving the reliability of chip products. Attached Figure Description

[0035] Figure 1 This is a schematic diagram illustrating the discrete distribution of threshold voltage within a wafer;

[0036] Figure 2 This is a network architecture diagram of a bias adaptive device;

[0037] Figure 3 This describes the characteristic of the output voltage of the threshold discrete sampling adaptive network to vary discretely with the threshold.

[0038] Figure 4It is the characteristic of the output voltage of the multi-sensitivity bias reconstruction network varying discretely with the threshold.

[0039] Figure 5 This refers to the characteristic of the gate bias voltage of a multi-functional chip varying discretely with a threshold voltage.

[0040] Figure 6 It describes the current variation characteristics of the multi-functional chip before and after the introduction of the bias adaptive device;

[0041] Figure 7 This is a flowchart illustrating the application of a bias adaptive method to resist semiconductor threshold voltage discrepancies.

[0042] Figure 8 This is a comparison of the number of qualified chips per wafer before and after the introduction of the bias adaptive device;

[0043] Figure 9 This is a schematic diagram of a multi-stage bias adaptive power amplifier formed by a multi-functional chip and a bias adaptive device when the chip is used as a power amplifier chip.

[0044] Figure 10 It corresponds Figure 9 Schematic diagram of an embodiment of the mid-bias adaptive device;

[0045] Figure 11 This is a schematic diagram of a multi-stage bias adaptive linear power enhancement transmitter device formed by the chip and the bias adaptive device when the multi-functional chip is used as a linear power enhancement transmitter module.

[0046] Figure 12 It corresponds Figure 11 A schematic diagram of an embodiment of the mid-bias adaptive device. Detailed Implementation

[0047] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0048] Figure 1 Demonstrates wafer-level threshold voltage ( As shown in the diagram of contour lines, the closer a chip is to the edge of the wafer, the more pronounced the device threshold voltage dispersion becomes. This phenomenon severely impacts chip performance and yield. Therefore, this invention provides a bias adaptive device and method to combat semiconductor threshold voltage dispersion. The bias adaptive device is monolithically integrated with a multi-functional circuit 100. The voltage output from the bias adaptive device, which varies in response to the threshold voltage dispersion of the multi-functional chip, serves as the gate bias voltage of the multi-functional chip. This ensures that the gate bias voltage of the multi-functional chip at any location on the wafer changes synchronously with the threshold voltage, guaranteeing stable performance of the multi-functional chip within the same wafer. This significantly expands the design window for multi-functional chips requiring precise gate bias voltage control and simultaneously improves chip yield.

[0049] like Figure 2 As shown, a bias adaptive device 200 for resisting semiconductor threshold voltage discrepancies includes a threshold discrete sampling adaptive network 210 and a multi-sensitivity bias reconstruction network 220.

[0050] The threshold discrete sampling adaptive network 210 includes a threshold discrete sampling resistor and threshold adaptive units of levels 1 to k. The threshold discrete sampling resistor is connected to the level 1 threshold adaptive unit, and this connection point is the output terminal of the threshold discrete sampling adaptive network 210. The remaining level threshold adaptive units are connected in sequence.

[0051] The threshold discrete sampling resistor samples the maximum value of the device threshold voltage discreteness of the multi-functional chip at different locations within the wafer, and is used to adapt the output bias voltage to the maximum threshold voltage discrete range of the multi-functional chip at different locations within the wafer; the gate bias voltage with the largest absolute value among all the gate bias voltages required by each multi-functional chip is defined as the gate bias voltage extreme value, and the threshold adaptive unit of level 1 to k is used to provide the gate bias voltage extreme value required by the multi-functional chip.

[0052] The multi-sensitivity bias reconstruction network 220 includes dynamic bias modules 221 to 22j from the first to the jth dimension. Each dynamic bias module is formed by at least two levels of bias adjustment units cascaded together. The number of bias adjustment units in each dynamic bias module can be the same or different. The connection points of each level of bias adjustment units can all serve as the output terminals of the multi-sensitivity bias reconstruction network 220.

[0053] The input terminals VG11, VG21, ..., VGj1 of each dynamic bias module are connected to the output terminal VG1 of the threshold discrete sampling adaptive network. The bias reference and the sensitivity of VG1 to discrete changes with the threshold voltage are adjusted in stages to meet the different requirements of the multi-functional chip for the bias reference and the different requirements for the sensitivity of the gate bias voltage to discrete changes with the threshold voltage.

[0054] The gate bias voltage input terminals VG_mf1, VG_mf2, ..., VG_mfi of the multi-functional chip can be arbitrarily connected and combined with the output terminal VG1 of the threshold discrete sampling adaptive network 210 and the output terminals VG12, VG13, ..., VG1n, VG22, VG23, ..., VG2n, VGj2, VGj3, ..., VGjn of the multi-sensitivity bias reconstruction network 220.

[0055] A bias adaptive method to resist semiconductor threshold voltage discrepancies is as follows:

[0056] The threshold discrete sampling adaptive network forms a voltage divider network between the power supply voltage and ground through a cascade of threshold discrete sampling resistors and 1 to k levels of threshold adaptive units. This provides an output voltage that varies synchronously with the discrete threshold voltage. This output voltage varies synchronously with the maximum discrete range of the device threshold voltage of the multi-functional chip at different locations within the wafer, and, in the case where the threshold voltage is not discrete, it is the maximum absolute value of the gate bias voltage of the multi-functional chip. To maintain consistency, the multi-sensitivity bias reconstruction network further adjusts the voltage in stages, providing bias voltage outputs with different threshold voltage discrete sensitivities and different reference values.

[0057] The output voltage VG1 of the threshold discrete sampling adaptive network satisfies The maximum range of threshold voltage discreteness It can be obtained by superimposing the deviation margin (e.g., 20%) of the discrete values ​​of the threshold voltage of multiple batches of wafers in various processes; the multi-sensitivity bias reconstruction network realizes the voltage output of different bias references by changing the dimension of the dynamic bias module, and realizes the adaptive output voltage for different exponents and different size die threshold voltage discreteness by changing the number of stages of the adjustment unit.

[0058] The specific working process of the threshold discrete sampling adaptive network is as follows: This network is homogeneously integrated with the multi-functional chip. When the device threshold voltage of the multi-functional chip at different locations within the wafer exhibits discreteness, the device threshold voltage contained within the threshold discrete sampling adaptive network becomes discrete synchronously with the device threshold voltage of the multi-functional chip at that location. The resistance value of the device changes accordingly during operation, and the overall resistance value of the link in the threshold discrete sampling adaptive network changes along with the discrete threshold voltage, ultimately generating a bias voltage VG1 that changes synchronously with the discrete threshold voltage of the multi-functional chip. Figure 3 As shown, within the maximum range of device threshold voltage dispersion of the multifunctional chip in the wafer, VG1 changes synchronously with the threshold voltage dispersion value. The slope of this curve is defined as the sensitivity of the bias voltage to the change of threshold voltage dispersion.

[0059] The specific working process of the multi-sensitivity bias reconfiguration network is as follows: The network includes 1 to m-dimensional dynamic bias modules. Each dynamic bias module is cascaded between VG1 and ground through a bias adjustment unit to form a voltage divider network. This network inherits the maximum adaptive range of the bias extrema and threshold discreteness of VG1. When the device threshold voltage of the multi-functional chip at different locations within the same wafer exhibits discreteness, the device threshold voltage contained within the multi-sensitivity bias reconfiguration network at each location generates a discreteness synchronized with the device threshold voltage of the multi-functional chip at that location. The link resistance of the dynamic bias module changes with the discreteness of the threshold voltage. Ultimately, each module generates a bias voltage output with different threshold voltage discrete sensitivities and different reference values, such as... Figure 4 As shown, VG12, VG22, ..., VGj2, VG1n, VG2n, ..., VGjn are the bias voltage outputs with different threshold voltage discrete sensitivities and different bias reference values ​​generated based on VG1.

[0060] The gate bias voltage input terminals VG_mf1, VG_mf2, ..., VG_mfi of the multi-functional chip are arbitrarily connected and combined with the output terminals VG12, VG13, ..., VG1n, VG22, VG23, ..., VG2n, VGj2, VGj3, ..., VGjn of the bias adaptive device. When the device threshold voltage of the multi-functional chip at different locations within the wafer exhibits discreteness, such as... Figure 5 As shown, VG is the fixed gate bias voltage, and VG1 is the output voltage of the bias adaptive device. Given the threshold voltage of the device, it can be seen that... The value of varies with the threshold voltage discretely, while The value of remains essentially constant as the threshold voltage discrepancies, thus ultimately resulting in a quiescent current that does not change with the threshold voltage discrepancies, such as... Figure 6 As shown, this ensures the stable performance of multifunctional chips at different locations within the wafer.

[0061] The bias adaptive device 200 is applicable to integrated circuits and systems using general semiconductor processes, including but not limited to GaAs pHEMT / HEMT, GaN pHEMT / HEMT, InP pHEMT / HEMT, and silicon-based systems. The process selection can be tailored to the needs of multifunctional circuits, and this invention does not impose any limitations on this. For integrated circuits and systems using general semiconductor processes, the application flowchart of the bias adaptive method against semiconductor threshold voltage dispersion is as follows: Figure 7 As shown, firstly, through power consumption and The resistance range of the threshold discrete sampling resistor and the resistance range of the threshold discrete sampling adaptive network are jointly determined. The next step is to... The resistance range of the threshold discrete sampling resistor and the resistance range of the threshold discrete sampling adaptive network jointly determine the number of stages of the threshold adaptive unit. Then, through... The required quantity determines the dimension of the dynamic bias module, and finally, the required quantity of devices with different indices and sizes within the multi-functional chip determines the number of bias adjustment units. It should be noted that, under specific process conditions, A clear correspondence can be established between the required quantity and the dimension of the dynamic bias module. Similarly, a clear correspondence can be established between the required quantity of devices with different indices and sizes within a multi-functional chip and the number of stages of the bias adjustment unit. This correspondence changes with the process.

[0062] It should be noted that the bias adaptive device and method proposed in this invention directly and homogeneously sample the threshold offset of transistors in multifunctional circuits manufactured using the same batch of semiconductor processes and the same shot. Therefore, it has universal applicability.

[0063] The threshold discrete sampling adaptive network in the bias adaptive device has no restrictions on the positive and negative discreteness of the threshold voltage. By adjusting the resistance value of the threshold discrete sampling resistor and the number of threshold adaptive unit stages, the gate bias voltage can be adapted to the bidirectional discrete state of the device threshold voltage of the multifunctional chip. Under the bidirectional discrete state of the threshold voltage, the static current change trend of the multifunctional chip can be suppressed, ensuring its working state.

[0064] Figure 8 The figure compares the number of qualified chips per wafer before and after the introduction of the bias adaptive device. As can be seen from the figure, after the introduction of the bias adaptive device, the yield of multi-functional chips increased by an average of 15%-32%, and the number of chips with qualified performance indicators in the final batch test on a single wafer increased significantly.

[0065] Example 1: Multi-stage bias adaptive power amplifier

[0066] When the multi-functional chip is a power amplifier chip, the power amplifier chip and the bias adaptive device form a multi-stage bias adaptive power amplifier, such as... Figure 9 As shown, it includes a power amplifier chip 900 and a bias adaptive device 200. The power amplifier chip 900 is formed by cascading a first-stage PA unit 910, a second-stage PA unit 920, and a third-stage PA unit 930, and receives the radio frequency signal input. Connected to the input of the first-stage PA unit 910, the signal is gradually amplified by the three-stage PA unit to finally generate the radio frequency output signal. , It is connected to the output of the third-stage PA unit. It should be noted that VG_mf1, VG_mf2, and VG_mf3 are all connected to the gate of each PA unit to provide the gate bias voltage for each PA unit.

[0067] The bias adaptive device 200 includes a threshold discrete sampling adaptive network 210 and a multi-sensitivity bias reconstruction network 220.

[0068] The threshold discrete sampling adaptive network 210 is formed by cascading a threshold discrete sampling resistor, a first-stage threshold adaptive unit, a second-stage threshold adaptive unit, and a third-stage threshold adaptive unit. The link resistance of this network changes synchronously with the threshold voltage discreteness, and finally generates an output voltage VG1 that changes synchronously with the threshold voltage discreteness through voltage division. VG1 is connected to the gate bias voltage input terminal of the first-stage PA unit 910 to provide the first-stage PA unit 910 with a gate adaptive bias voltage that is resistant to threshold voltage discreteness.

[0069] The multi-sensitivity bias reconfiguration network 220 includes a first-dimensional dynamic bias module 221, which is formed by cascading a first-stage bias adjustment unit, a second-stage bias adjustment unit, and a third-stage bias adjustment unit. The input terminal VG11 of this module is connected to the output terminal VG1 of the threshold discrete sampling adaptive network 210. At the same time, the resistance values ​​of each bias adjustment unit change synchronously with the threshold voltage discreteness, and finally, output voltages VG12 and VG13 with different bias references and different sensitivities are generated through voltage division. VG12 is connected to the gate bias voltage input terminal VG_mf2 of the second-stage PA unit 920 to provide the second-stage PA unit 920 with an adaptive gate bias voltage that is resistant to threshold voltage discreteness. VG13 is connected to the gate bias voltage input terminal VG_mf3 of the third-stage PA unit 930 to provide the third-stage PA unit 930 with an adaptive gate bias voltage that is resistant to threshold voltage discreteness.

[0070] It should be noted that this embodiment can be implemented using various semiconductor processes such as GaAs pHEMT / HEMT, GaN pHEMT / HEMT, InPpHEMT / HEMT, and silicon-based processes, all of which fall within the protection scope of this invention.

[0071] Furthermore, the three-stage PA unit is merely a schematic illustration of one specific implementation of the power amplifier chip used in this invention. This invention does not limit the number of stages in the PA unit, and all such stages fall within the protection scope of this invention.

[0072] Furthermore, the gate bias voltages VG_mf1, VG_mf2, and VG_mf3 of each PA unit can be arbitrarily combined and connected with the output voltages VG1, VG12, and VG13 of the bias adaptive device 200, and the specific connection method is determined by the gate bias voltage requirements of each PA unit. Among the output voltages VG1, VG12, and VG13 of the bias adaptive device 200, the absolute value of the output voltage VG1 of the threshold discrete sampling adaptive network 210 is the largest.

[0073] like Figure 10As shown, a specific embodiment of the bias adaptive device 200 is provided, wherein the threshold discrete sampling adaptive network 210 includes a threshold discrete sampling resistor, a first-level threshold adaptive unit, a second-level threshold adaptive unit, and a third-level threshold adaptive unit; the first-dimensional dynamic bias module 221 includes a first-level bias adjustment unit, a second-level bias adjustment unit, and a third-level bias adjustment unit.

[0074] The threshold discrete sampling resistor includes a sampling resistor; the first-stage threshold adaptive unit includes a first bias resistor R1, a first adjustment resistor RS1, and a first adjustment device HEMT1; the second-stage threshold adaptive unit includes a second bias resistor R2, a second adjustment resistor RS2, and a second adjustment device HEMT2; the third-stage threshold adaptive unit includes a third bias resistor R3, a third adjustment resistor RS3, and a third adjustment device HEMT3. A voltage divider network is formed by cascading the sampling resistor, HEMT1, RS1, HEMT2, RS2, HEMT3, and RS3. The resistance values ​​of HEMT1, HEMT2, and HEMT3 connected in series in this voltage divider network change synchronously with the discrete threshold voltage of the device. Therefore, the overall resistance value of the voltage divider network changes synchronously with the discrete threshold voltage, ultimately generating an output voltage VG1 that changes synchronously with the discrete threshold voltage.

[0075] Furthermore, in this embodiment, the 3-level threshold adaptive unit is only one specific implementation of the threshold discrete sampling adaptive network, and the specific number of levels required is determined according to the specific requirements of the gate bias voltage of the power amplifier chip.

[0076] Furthermore, the first regulating resistor RS1, the second regulating resistor RS2, and the third regulating resistor RS3 are used to fine-tune the output voltage VG1, and the specific number required is determined according to the specific requirements of the gate bias voltage of the power amplifier chip.

[0077] Each bias adjustment unit includes a source-drain shorting device. All devices are cascaded to form a voltage divider network. The resistance of the devices connected in series into the voltage divider network changes synchronously with the discrete threshold voltage of the devices. Thus, the overall resistance of the voltage divider network changes synchronously with the discrete threshold voltage, ultimately generating output voltages VG12 and VG13 that change synchronously with the discrete threshold voltage.

[0078] Furthermore, in this embodiment, the dimension of the dynamic bias module is only one specific implementation of the multi-sensitivity bias reconstruction network, and the specific order required is determined according to the specific requirements of the gate bias voltage of the power amplifier chip.

[0079] Furthermore, in this embodiment, the 3-stage bias adjustment unit is only one specific implementation of the first-dimensional dynamic bias module, and the specific number of stages required is determined according to the specific requirements of the gate bias voltage of the power amplifier chip.

[0080] It should be noted that Embodiment 1 is only one implementation of the bias adaptive device of the present invention applied to a hybrid multifunctional chip, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention to any connection method between any output position in the bias adaptive device and any gate of the power amplifier chip should be included within the protection scope of the present invention.

[0081] Example 2: Multi-order bias adaptive linear power enhancement transmitter

[0082] When the multi-functional chip is a linear boost power transmitter module, the linear boost power transmitter module and the bias adaptive device form a multi-order bias adaptive linear boost power transmitter device, such as... Figure 11 As shown, it includes a linear power enhancement transmission module 1100 and a bias adaptive device 200.

[0083] The linear power enhancement transmitter module 1100 is formed by cascading a first VGA unit 1110, an APD unit 1120, a second VGA unit 1130, and a PA unit 1140, with radio frequency signal input. Connected to the input terminal of the first VGA unit 1110, the signal undergoes phase and amplitude adjustment and gradual amplification through the VGA unit, APD unit, and PA unit, ultimately generating a radio frequency output signal. , It is connected to the output of PA unit 1140. It should be noted that VG_mf1, VG_mf2, VG_mf3, VG_mf4 and VG_mf5 are all connected to the gate of each functional circuit unit to provide the gate bias voltage of each functional circuit unit.

[0084] The bias adaptive device 200 includes a threshold discrete sampling adaptive network 210 and a multi-sensitivity bias reconstruction network 220.

[0085] The threshold discrete sampling adaptive network 210 is formed by cascading threshold discrete sampling resistors, a first-stage threshold adaptive unit, a second-stage threshold adaptive unit, a third-stage threshold adaptive unit, and a fourth-stage threshold adaptive unit. The link resistance of this network changes synchronously with the threshold voltage discreteness, and finally generates an output voltage VG1 that changes synchronously with the threshold voltage discreteness through voltage division. VG1 is connected to the gate bias voltage input terminal of the amplitude-independently adjustable nonlinear circuit in the APD unit 1120 to provide the gate bias adaptive voltage of the amplitude-independently adjustable nonlinear circuit to resist threshold voltage discreteness.

[0086] The multi-sensitivity bias reconstruction network 220 includes a first-dimensional dynamic bias module 221, a second-dimensional dynamic bias module 222, and a third-dimensional dynamic bias module 223. 221 is formed by cascading a first-level bias adjustment unit, a second-level bias adjustment unit, and a third-level bias adjustment unit; 222 is formed by cascading a first-level bias adjustment unit, a second-level bias adjustment unit, a third-level bias adjustment unit, and a fourth-level bias adjustment unit; and 223 is formed by cascading a first-level bias adjustment unit and a second-level bias adjustment unit.

[0087] Furthermore, the input terminal VG11 of the first-dimensional dynamic bias module 221 is connected to the output terminal VG1 of the threshold discrete sampling adaptive network 210. At the same time, the resistance values ​​of each bias adjustment unit inside 221 change synchronously with the threshold voltage discreteness. Finally, output voltages VG12 and VG13 with different bias references and different sensitivities are generated through voltage division. VG12 is connected to the gate bias voltage input terminal of the phase-independent adjustable nonlinear circuit in the APD unit 1120 to provide the gate bias adaptive voltage of the phase-independent adjustable nonlinear circuit to resist threshold voltage discreteness. VG13 is connected to the gate bias voltage input terminal of the first VGA unit 1110 to provide the gate bias adaptive voltage of the first VGA unit 1110 to resist threshold voltage discreteness.

[0088] Furthermore, the input terminal VG21 of the second-dimensional dynamic bias module 222 is connected to the output terminal VG1 of the threshold discrete sampling adaptive network 210. At the same time, the resistance values ​​of each bias adjustment unit inside 222 change synchronously with the threshold voltage discreteness, and finally generate the output voltage VG23 through voltage division. VG23 is connected to the gate bias voltage input terminal of PA unit 1140 to provide PA unit 1140 with gate bias adaptive voltage that resists threshold voltage discreteness.

[0089] Furthermore, the input terminal VG31 of the third-dimensional dynamic bias module 223 is connected to the output terminal VG1 of the threshold discrete sampling adaptive network 210. At the same time, the resistance values ​​of each bias adjustment unit inside 223 change synchronously with the threshold voltage discreteness, and finally generate the output voltage VG32 through voltage division. VG32 is connected to the gate bias voltage input terminal of the second VGA unit 1130 to provide the second VGA unit 1130 with an adaptive gate bias voltage that resists threshold voltage discreteness.

[0090] It should be noted that this embodiment can be implemented using various semiconductor processes such as GaAs pHEMT / HEMT, GaN pHEMT / HEMT, InPpHEMT / HEMT, and silicon-based processes, all of which fall within the protection scope of this invention.

[0091] Furthermore, the connection order and number of stages of the VGA unit, APD unit, and PA unit can be adjusted as needed. At the same time, the connection order of the phase-independent adjustable nonlinear circuit and the amplitude-independent adjustable nonlinear circuit in the APD unit can also be adjusted as needed. This invention does not limit this. Any cascaded form of hybrid multifunctional circuit units and multi-order bias adaptive networks falls within the protection scope of this invention.

[0092] Furthermore, the gate bias voltages VG_mf1, VG_mf2, VG_mf3, VG_mf4, and VG_mf5 of each multi-functional circuit unit can be arbitrarily combined and connected with the output voltages VG1, VG12, VG13, VG23, and VG32 of the bias adaptive device 200. The specific connection method is determined by the gate bias voltage requirements of each multi-functional circuit unit.

[0093] Furthermore, among the output voltages VG1, VG12, VG13, VG23, and VG32 of the bias adaptive device 200, the absolute value of the output voltage VG1 of the threshold discrete sampling adaptive network is the largest.

[0094] like Figure 12 As shown, a specific embodiment of the bias adaptive device 200 is provided, wherein the threshold discrete sampling adaptive network 210 includes a threshold discrete sampling resistor, a first-level threshold adaptive unit, a second-level threshold adaptive unit, a third-level threshold adaptive unit, and a fourth-level threshold adaptive unit; the first-dimensional dynamic bias module 221 includes a first-level bias adjustment unit, a second-level bias adjustment unit, and a third-level bias adjustment unit; the second-dimensional dynamic bias module 222 includes a first-level bias adjustment unit, a second-level bias adjustment unit, a third-level bias adjustment unit, and a fourth-level bias adjustment unit; and the third-dimensional dynamic bias module 223 includes a first-level bias adjustment unit and a second-level bias adjustment unit.

[0095] Further, the threshold discrete sampling resistor includes a sampling resistor; the first-stage threshold adaptive unit includes a first bias resistor R11, a first adjustment resistor RS11, and a first adjustment device HEMT11; the second-stage threshold adaptive unit includes a second bias resistor R12, a second adjustment resistor RS12, and a second adjustment device HEMT12; the third-stage threshold adaptive unit includes a third bias resistor R13, a third adjustment resistor RS13, and a third adjustment device HEMT13; and the fourth-stage threshold adaptive unit includes a fourth bias resistor R14, a fourth adjustment resistor RS14, and a fourth adjustment device HEMT14. A voltage divider network is formed by cascading the sampling resistor, HEMT11, RS11, HEMT12, RS12, HEMT13, RS13, HEMT14, and RS14. The resistance values ​​of HEMT11, HEMT12, HEMT13, and HEMT14 connected in series in this voltage divider network change synchronously with the discrete threshold voltage of the device. Therefore, the overall resistance value of the voltage divider network changes synchronously with the discrete threshold voltage, ultimately generating an output voltage VG1 that changes synchronously with the discrete threshold voltage.

[0096] Furthermore, in this embodiment, the 4-level threshold adaptive unit is only one specific implementation of the threshold discrete sampling adaptive network, and the specific number of levels required is determined according to the specific requirements of the gate bias voltage of each multifunctional circuit unit.

[0097] Furthermore, the first regulating resistor RS11, the second regulating resistor RS12, the third regulating resistor RS13, and the fourth regulating resistor RS14 are used for fine-tuning the output voltage VG1. The specific number required is determined according to the specific requirements of the gate bias voltage of each multi-functional circuit unit.

[0098] Each bias adjustment unit includes a source-drain shorting device. All devices are cascaded to form a voltage divider network. The resistance of the devices connected in series into the voltage divider network changes synchronously with the discrete threshold voltage of the devices. Thus, the overall resistance of the voltage divider network changes synchronously with the discrete threshold voltage, ultimately generating output voltages VG12, VG13, VG23, and VG32 that change synchronously with the discrete threshold voltage.

[0099] Furthermore, in this embodiment, the dimension of the dynamic bias module is only one specific implementation of the multi-sensitivity bias reconstruction network, and the specific order required is determined according to the specific requirements of the gate bias voltage of each multifunctional circuit unit.

[0100] Furthermore, in this embodiment, the specific number of bias adjustment unit stages required for each dimension of the dynamic bias module is determined according to the specific requirements of the gate bias voltage of each multifunctional circuit unit.

[0101] It should be noted that Embodiment 2 is only one implementation of the bias adaptive device of the present invention applied to a hybrid multifunctional chip, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to any cascading order and form of the hybrid multifunctional chip and the bias adaptive device within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0102] This invention takes into account operating frequency band, power, efficiency, consistency, yield, and cost, and manufactures the wafer using appropriate semiconductor technology. The wafer can use GaN, GaAs, or InP materials as substrates, but is not limited to these.

[0103] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention, particularly regarding the connection combination of the gate and multi-level bias adaptive network of any hybrid multifunctional circuit chip, should be included within the scope of protection of the present invention.

Claims

1. A bias adaptive device for resisting semiconductor threshold voltage discrepancies, characterized in that, The bias adaptive device is monolithically integrated with each multifunctional chip on the wafer. For each multifunctional chip and the corresponding bias adaptive device on the wafer, when the multifunctional chip and the bias adaptive device are in the same state and the threshold voltages of the bias adaptive device and the multifunctional chip are both discrete, the output voltage of the bias adaptive device is used as the gate bias voltage required by the multifunctional chip. Moreover, the voltage output by the bias adaptive device at different positions on the wafer changes with the discrete threshold voltage of the corresponding multifunctional chip, so that the gate bias voltage and threshold voltage of each multifunctional chip on the wafer change synchronously. The bias adaptive device includes a threshold discrete sampling adaptive network and a multi-sensitivity bias reconstruction network. The threshold discrete sampling adaptive network includes cascaded threshold discrete sampling resistors and 1 to k levels of threshold adaptive units, where k ≥ 1. The connection between the threshold discrete sampling resistor and the first-level threshold adaptive unit serves as the output terminal of the threshold discrete sampling adaptive network. The threshold discrete sampling resistor is used to obtain the maximum absolute value of the threshold voltage discreteness of each multi-functional chip on the wafer, i.e. This determines the operating range of the bias adaptive device; the 1 to k level threshold adaptive units are used to provide the maximum absolute value of all gate bias voltages required by the multi-functional chip, i.e. The bias voltage VG1 output by the threshold discrete sampling adaptive network satisfies: , This represents the x-th gate bias voltage required by the multi-functional chip, where x = 1, ..., i, and i is the number of gate bias voltages required by the multi-functional chip. The multi-sensitivity bias reconfiguration network includes parallel dynamic bias modules of dimensions 1 to j, where 1 ≤ j ≤ i. Each dynamic bias module is used to adjust VG1 in stages, thereby outputting all the gate bias voltages required by the multi-functional chip, or outputting all the gate bias voltages except for i. The remaining gate bias voltage besides the corresponding gate bias voltage. Provided by VG1.

2. The bias adaptive device for resisting semiconductor threshold voltage discrepancies according to claim 1, characterized in that, In the threshold discrete sampling adaptive network, threshold adaptive units of levels 1 to k are connected in series. One end of the threshold discrete sampling resistor is connected to one end of the level 1 threshold adaptive unit as the output of the threshold discrete sampling adaptive network. The other end of the threshold discrete sampling resistor is grounded. One end of the level k threshold adaptive unit is connected to the (k-1) level threshold adaptive unit. The other end of the level k threshold adaptive unit is connected to the power supply voltage. Alternatively, in the threshold discrete sampling adaptive network, threshold adaptive units of levels 1 to k are connected in series. One end of the threshold discrete sampling resistor is connected to one end of the level 1 threshold adaptive unit as the output of the threshold discrete sampling adaptive network. The other end of the threshold discrete sampling resistor is connected to the power supply voltage. One end of the level k threshold adaptive unit is connected to the (k-1) level threshold adaptive unit, and the other end of the level k threshold adaptive unit is grounded.

3. The bias adaptive device for resisting semiconductor threshold voltage discrepancies according to claim 1, characterized in that, The input terminals of the first to j-th dimension dynamic bias modules are all connected to the output terminal of the threshold discrete sampling adaptive network. The first output terminal of the first to j-th dimension dynamic bias modules is connected to the gate bias voltage input terminal of the multi-functional chip. The first output terminal of the first to j-th dimension dynamic bias modules outputs all gate bias voltages required by the multi-functional chip, or excluding the gate bias voltages required by the multi-functional chip. The remaining gate bias voltages, excluding the corresponding gate bias voltages, are all grounded at the second output terminals of the first to j-th dimension dynamic bias modules.

4. The bias adaptive device for resisting semiconductor threshold voltage discrepancies according to claim 1, characterized in that, The first to j-th dimension dynamic bias modules are each composed of at least two levels of bias adjustment units connected in series.

5. The bias adaptive device for resisting semiconductor threshold voltage discrepancies according to claim 1, characterized in that, When the threshold voltage discrete value is 0, that is At that time, the output voltage VG1 of the threshold discrete sampling adaptive network is the same as that required by the multi-functional chip. The corresponding gate bias voltages are equal.

6. The bias adaptive device for resisting semiconductor threshold voltage discrepancies according to claim 1, characterized in that, The multifunctional chip includes one or any combination of at least two of the following: radio frequency power amplifier, microwave power amplifier, terahertz power amplifier, variable gain amplifier, analog predistorter, phase shifter, and attenuator.

7. The bias adaptive device for resisting semiconductor threshold voltage discrepancies according to claim 1, characterized in that, The bias adaptive device is applicable to the process in which the threshold voltage of a multifunctional chip deviates from the reference threshold voltage, including wafer manufacturing process, chip assembly process, reliability testing process, and environmental testing process.

8. A bias adaptive method based on the bias adaptive device for resisting semiconductor threshold voltage discrepancies according to any one of claims 1-7, characterized in that, The specific bias adaptive method is as follows: When the threshold voltage of the multi-functional chip at different locations within the wafer... Compared to the reference threshold voltage When a deviation occurs, for each multi-functional chip's corresponding bias adaptive device, the threshold voltage of the threshold adaptive unit contained within the threshold discrete sampling adaptive network of the device generates a value corresponding to the multi-functional chip. When synchronization deviates, the resistance of the threshold adaptive unit within the threshold discrete sampling adaptive network changes accordingly. The network generates a bias voltage VG1 that changes synchronously with the threshold voltage discreteness of the multi-functional chip. VG1 changes synchronously with the maximum discrete range of the threshold voltage of the multi-functional chip at different locations within the wafer, resulting in overdrive voltages corresponding to the multi-functional chips at different locations within the wafer. The value remains stable; The multi-sensitivity bias reconfiguration network generates multiple voltage divider networks between VG1 and ground through various dynamic bias modules. The threshold voltage of the bias adjustment unit contained within each dynamic bias module corresponds to the multi-functional chip of the device. The synchronous discreteness causes the resistance values ​​of the bias adjustment units within each dynamic bias module to change accordingly during operation. The overall resistance of the dynamic bias module link changes differently as the threshold voltage discreteness occurs. This allows for graded adjustment of VG1 to achieve the functionality required by the multi-functional chip. The output of the gate bias voltage remaining after the corresponding gate bias voltage. The corresponding gate bias voltage is provided by VG1, x=1,…,i, where i is the number of gate bias voltages required by the multi-function chip, or the output of all gate bias voltages required to realize the multi-function chip.

9. The bias adaptive method according to claim 8, characterized in that, The bias adaptive device is applicable to the process in which the threshold voltage of a multifunctional chip deviates from the reference threshold voltage, including wafer manufacturing process, chip assembly process, reliability testing process, and environmental testing process.

10. A design method for a bias adaptive device based on any one of claims 1-7 that resists semiconductor threshold voltage discrepancies, characterized in that, The design method is as follows: Based on all the gate bias voltages required by the multi-functional chip, determine the maximum absolute value of all gate bias voltages, i.e. , x=1,…,i, where i is the number of gate bias voltages required by the multi-functional chip; Based on the power consumption of the bias adaptive device and Together, they determine the resistance range of the threshold discrete sampling resistor and the resistance range of the threshold discrete sampling adaptive network; Discretize the maximum absolute value based on the threshold voltage The resistance range of the threshold discrete sampling resistor and the resistance range of the threshold discrete sampling adaptive network jointly determine the number of stages of the threshold adaptive unit; The dimension of the dynamic bias module is determined based on the required number of all gate bias voltages for the multi-functional chip, and the number of bias adjustment units is determined by the required number of devices with different gate index quantities and different sizes within the multi-functional chip.

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