FPGA-based electronic control system and method for phased array radar beam control

Abstract

The invention relates to an FPGA (Field Programmable Gate Array)-based electronic control system and method for phased array radar beam control. The electronic control system comprises a shell, and a beam control unit, a voltage conversion unit and an input voltage preprocessing unit which are mounted in the shell, the wave beam control unit adopts a wave beam control printed board, and the voltage conversion unit and the input voltage preprocessing unit adopt power supply module printed boards; the shell is of a double-cavity electromagnetic shielding structure, and a wave beam control printed board and a power module printed board are placed in two cavities respectively. The wave beam control printed board distributes power supply signals input by the power supply module printed board through three-dimensional wiring and then distributes the power supply signals to the radar radio frequency assembly and other assemblies. According to the electric control system, the FPGA, the voltage conversion unit and the communication interface serve as main hardware, system integration of high-power signals and high-density signals is achieved, combined output of various control interfaces and power sources is supported, and good electromagnetic compatibility is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of phased array radar beam control technology, in particular to a FPGA-based electric control system and method for phased array radar beam control. BACKGROUND

[0002] The beam control unit and the power supply are the control center and the power supply system of the front end of the phased array radar antenna, and are important components for realizing the electric scanning function of the phased array radar, and bear the control, power supply and monitoring tasks of each antenna unit and numerous T / R components of the array. The main functions of the beam control unit are: receiving the beam pointing instruction, calculating and distributing the amplitude and phase control signals of the antenna unit, realizing the spatial synthesis of the antenna beam, converting the antenna calibration mode and the working mode, controlling the power supply, collecting the temperature and returning the state of the antenna single module, and additionally completing the functions of the wave control system timing generation, the wave control internal self-checking, the antenna channel phase monitoring and the like. The power supply is responsible for supplying power to the antenna subsystem.

[0003] FPGA (Field Programmable Gate Array) has the advantages of parallel computing capability, high real-time performance, reconfigurability, flexible interface and the like. The FPGA-based beam control unit has better real-time performance than the traditional DSP / CPU scheme, has the parallel processing large-scale array element phase calculation capability, and has strong flexibility compared with the traditional ASIC scheme. The development of the FPGA-based beam control unit is a key link for the evolution of the phased array radar to digitalization, software, and intelligence. Through the parallelism, reconfigurability and low delay characteristics of the FPGA, not only the bottlenecks of the traditional scheme in real-time performance, flexibility and computing power can be solved, but also the urgent needs of high-performance radar systems in the military and civilian fields can be met.

[0004] The existing radar has the problems of difficult combination design of the FPGA-based beam control and the high-power power supply component, the superposition of electromagnetic interference of the FPGA high-speed signal and the switching power supply due to electromagnetic compatibility (EMC) coupling, the deterioration of the beam sidelobe level by 3-5dB, the conduction of the power supply module temperature rise to the FPGA through the PCB, the aggravation of the clock jitter to >1ps RMS, and the influence on the beam pointing accuracy. SUMMARY

[0005] In order to solve the problems in the prior art, the purpose of the present application is to provide a FPGA-based electric control system and method for phased array radar beam control, which realizes the integrated design of the FPGA-based beam control and the power supply component in the radar, improves the anti-electromagnetic interference characteristics of the power supply and the wave control system, and realizes the health management of the electric control system electric-thermal-magnetic through the optimization of the system functions, the increase of the voltage monitoring, the current monitoring, the temperature monitoring closed-loop thermal management and the like.

[0006] To achieve the above object, the application adopts the following technical solutions: In the first aspect of the application, an FPGA-based electric control system for phased array radar beam control is disclosed, which comprises a shell and a beam control unit, a voltage conversion unit and an input voltage preprocessing unit installed in the shell.

[0007] The beam control unit adopts a beam control printed board, and the voltage conversion unit and the input voltage preprocessing unit adopt a power module printed board.

[0008] The shell is a double-cavity electromagnetic shielding cavity with two cavities, and a separation layer composed of conductive rubber and ferrite is arranged between the two cavities; the two cavities are used to place the beam control printed board and the power module printed board respectively; single-point interconnection is realized between the beam control printed board and the power module printed board through point-to-point interconnection lines; the beam control printed board adopts a three-dimensional wiring anti-interference design, and after distributing and processing the power supply signals, the signals are distributed to radar radio frequency components and other components. The thickness of the separation layer is 1.0±0.05 mm, and the separation layer is used to realize cross-band isolation of the power supply system and the beam control. The two cavities of the double-cavity electromagnetic shielding cavity are independent and isolated from each other, and a lead-through hole is opened on the separation layer between the two cavities. Single-point interconnection is adopted between the beam control printed board and the power module printed board. The interconnection line passes through the lead-through hole and inputs the power supply signals on the power module printed board to the beam control printed board.

[0009] The beam control printed board distributes and processes the power supply signals through a three-dimensional wiring anti-interference design, and then distributes the signals to radar radio frequency components and other components. The three-dimensional wiring anti-interference design adopts an interlayer vertical wiring process, and the power supply signals input by the power module printed board and the signals on the beam control board are orthogonally distributed on different layers of the PCB, cooperating with a densely distributed ground via array (hole spacing is one tenth of the highest working frequency wavelength), to realize high-frequency isolation performance, and the crosstalk strength is effectively suppressed to a very low level that can be detected by the instrument.

[0010] Each external interface of the electric control system is uniformly output by the beam control printed board, and each output port contains multiple power supply signals and control signals. The electric control system has multiple output ports connected to radar backend components, meeting the input requirements of radar radio frequency components and other components for power supply and control signals.

[0011] The beam control unit is used for communication interface control and data signal processing, while performing power management, program and data storage, implementing voltage, current and temperature detection and controlling phased array antenna subsystem components through various communication interfaces. The voltage conversion unit is used for providing required voltage outputs for the phased array radar, and can convert the input power into 6 or more different voltage levels, and each current output is designed according to the required power of the back end. The input voltage preprocessing unit P30 includes a short circuit protection circuit, a spike protection circuit and an EMI filter circuit. The input voltage preprocessing unit P30 reduces the noise interference of the front end by short circuit protection, spike protection and filter circuit.

[0012] As a further improvement of the above technical solution, the beam control unit includes an FPGA module, a power management module, a storage module, a voltage detection module, a current detection module, a temperature detection module and various communication interfaces.

[0013] Specifically, the FPGA module serves as a core control unit, and forms a bidirectional control and data interaction link with each functional module through power supply lines, data buses (I2C, single bus), IO ports and level conversion chips, so as to realize centralized management of the entire electric control system and control of the phased array radar components.

[0014] Further, the power management module provides a working voltage for the FPGA module, converts the input voltage into the voltage required by the FPGA module, and powers on in a time sequence; the two are connected through power supply lines, and the output voltage of the power management module is directly supplied to the FPGA chip to ensure stable startup.

[0015] Further, the FPGA module serially inputs instructions, addresses and data to the storage module through a clock signal to realize program loading and data read / write; the storage module includes two 256M Flash chips for program storage and data storage, and is connected with the FPGA module through clock lines, instruction lines, address lines and data lines. The FPGA chip serially inputs instructions, addresses and data to the Flash chip through a clock signal to realize program loading and data read / write.

[0016] Further, the output end of the voltage detection module is connected with the IO port of the FPGA module; the 4-way output end (OUT1-OUT4) of the voltage detection module is connected with the IO port of the FPGA module. The voltage detection module outputs high and low levels through a comparator (high level indicates normal voltage and low level indicates abnormality), and the FPGA module realizes state monitoring of multiple voltages (such as +5V, -5V, +12V and self-defined voltage) by reading the level state of the IO port.

[0017] Further, the current detection module communicates with the FPGA module bidirectionally through an I2C bus; the control logic unit of the current detection module transmits the processed voltage data (V1-V4) to the FPGA module through the I2C bus (SCL clock line, SDA data line), and the FPGA module sends control instructions (such as configuration register and selection of detection channel) to the current detection module through the I2C bus, so as to control the current detection process.

[0018] Further, the temperature detection module is connected with the FPGA module through a single bus and communicates by using a single bus protocol; the temperature sensor in the temperature detection module transmits the collected temperature data (stored in the form of 2 bytes) to the FPGA module, the FPGA module sends a control command (such as [44h] measurement command) to the temperature sensor, the system maps the real-time temperature value into a PWM duty cycle parameter according to a preset temperature control algorithm, and drives a cooling fan through a GPIO output adjustable pulse width signal to construct a closed-loop thermal management system.

[0019] Further, the IO port of the FPGA module is directly connected to each communication interface, and outputs and receives various signals through level conversion. After the IO port output signal of the FPGA module is converted through a level conversion chip, it is output through an LVTTL 3.3V / 5.0V interface with a 50Ω isolation resistor, so as to control the phase shift and attenuation of a radio frequency component; the FPGA module communicates with an external digital control board through an RS422 signal transceiver, receives a control instruction (such as frequency word and beam pointing) and reports the system state; the IO port output single-ended signal of the FPGA module is converted into a differential signal through an LVDS chip, and communicates with an external switch component through a J30J interface to realize switch control.

[0020] As a further improvement of the above technical solution, the FPGA module comprises an FPGA chip, which is used for controlling various communication interfaces and processing data signals; the FPGA chip adopts an XC7K325T chip; the power management module is used for converting an input voltage into different voltages required by a beam control unit and managing the power-on sequence of different voltages; the storage module is used for storing programs and data of the FPGA module; the storage module comprises two pieces of 256M Flash, namely a first Flash and a second Flash, the first Flash is used for FPGA program storage and configuration, and the second Flash is used for data storage.

[0021] As a further improvement of the above technical solution, the voltage detection module is used for detecting the multi-output voltage of the power supply. The voltage detection module includes a first voltage comparator, a second voltage comparator, a third voltage comparator, a fourth voltage comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube; the non-inverting input terminal of the first voltage comparator is connected to a first voltage dividing circuit, the first voltage dividing circuit includes two first voltage dividing resistors connected in series, the non-inverting input terminal of the first voltage comparator is connected to a node between the two first voltage dividing resistors, one end of the two first voltage dividing resistors is connected to +5V, and the other end is connected to ground; the inverting input terminal of the first voltage comparator is connected to the inverting input terminal of the second voltage comparator, the inverting input terminal of the third voltage comparator, the inverting input terminal of the fourth voltage comparator, and a 1.24V reference voltage; the output terminal of the first voltage comparator is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the gate of the first MOS tube, the source of the first MOS tube is connected to ground, and the drain of the first MOS tube serves as an output terminal OUT1; the non-inverting input terminal of the second voltage comparator is connected to a second voltage dividing circuit, the second voltage dividing circuit includes two second voltage dividing resistors connected in series, the non-inverting input terminal of the second voltage comparator is connected to a node between the two second voltage dividing resistors, one end of the two second voltage dividing resistors is connected to +5V, and the other end is connected to ground; the output terminal of the second voltage comparator is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the gate of the second MOS tube, the source of the second MOS tube is connected to ground, and the drain of the second MOS tube serves as an output terminal OUT2; the non-inverting input terminal of the third voltage comparator is connected to a third voltage dividing circuit, the third voltage dividing circuit includes two third voltage dividing resistors connected in series, the non-inverting input terminal of the third voltage comparator is connected to a node between the two third voltage dividing resistors, one end of the two third voltage dividing resistors is connected to +12V, and the other end is connected to ground; the output terminal of the third voltage comparator is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the gate of the third MOS tube, the source of the third MOS tube is connected to ground, and the drain of the third MOS tube serves as an output terminal OUT3; the non-inverting input terminal of the fourth voltage comparator is connected to a fourth voltage dividing circuit, the fourth voltage dividing circuit includes two fourth voltage dividing resistors connected in series, the non-inverting input terminal of the fourth voltage comparator is connected to a node between the two fourth voltage dividing resistors, one end of the two fourth voltage dividing resistors is connected to DIN, and the other end is connected to ground; the output terminal of the fourth voltage comparator is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is connected to the gate of the fourth MOS tube, the source of the fourth MOS tube is connected to ground, and the drain of the fourth MOS tube serves as an output terminal OUT4.

[0022] As a further improvement of the above technical solution, the current detection module is used for monitoring the current of the radio frequency component in real time to determine whether the radio frequency component is working normally; the current detection module comprises a first current sensing resistor, a second current sensing resistor, a multiplexing unit, an analog-to-digital converter (ADC), a control logic unit, an oscillator (OSC) and an I2C bus; the input end of the first current sensing resistor is connected to a first radio frequency component, and the input end of the second current sensing resistor is connected to a second radio frequency component; the two ends of the first current sensing resistor are respectively connected to the first data input end and the second data input end of the multiplexing unit, one end of the first current sensing resistor is connected to a power supply, and the other end is connected to the first radio frequency component; the two ends of the second current sensing resistor are respectively connected to the third data input end and the fourth data input end of the multiplexing unit; one end of the second current sensing resistor is connected to the power supply, and the other end is connected to the second radio frequency component; the output end of the multiplexing unit is connected to the input end of the analog-to-digital converter; the multiplexing unit selects a signal from the two current sensing resistors according to the instruction of the control logic unit and transmits the signal to the analog-to-digital converter for analog-to-digital conversion; the output end of the analog-to-digital converter is connected to the input end of the control logic unit, and the analog-to-digital converter transmits the converted digital signal to the control logic unit for data processing, analysis or storage; the output end of the oscillator is connected to the clock signal input end of the control logic unit; the control signal output end of the control logic unit is connected to the selection control end of the multiplexing unit. The control logic unit sends a control signal to the multiplexing unit according to a preset rule or an external instruction to determine whether to select the signal of the first current sensing resistor or the signal of the second current sensing resistor; the digital signal processed by the control logic unit is transmitted to the FPGA module through the I2C bus, and the control instruction of the FPGA module is received through the I2C bus.

[0023] As a further improvement of the above technical solution, the temperature detection module comprises a temperature sensor; the temperature sensor is connected to the FPGA module through a single bus.

[0024] As a further improvement of the above technical solution, the plurality of communication interfaces comprise an LVTTL 3.3V interface, an LVTTL 5.0V interface, an RS422 interface and an LVDS interface.

[0025] As a further improvement of the above technical solution, the voltage conversion unit comprises an input filter circuit, a DC / DC converter, an output filter circuit and a protection circuit, and the input filter circuit and the output filter circuit are used for filtering common mode interference and differential mode interference in the power supply system.

[0026] The input filter circuit and the output filter circuit adopt a filter network circuit, the filter network circuit adopts a multi-stage filtering technology, and common mode filtering and differential mode filtering are combined in multiple stages;The filter network circuit comprises capacitors C1, C2, C3, C4 and C5;The first end of the capacitor C1 is connected to the power supply VI+, and the second end of the capacitor C1 is connected to the power supply VI-;The first end of the capacitor C1 is connected to the first end of the capacitor C2, the first end of the capacitor C3 and the first end of the capacitor C4 through the inductor L1;The second end of the capacitor C1 is connected to the second end of the capacitor C2, the second end of the capacitor C3 and the second end of the capacitor C5 respectively;The second end of the capacitor C4 is connected to the first end of the capacitor C5 and grounded;The first end of the capacitor C4 is the output voltage VO+, and the second end of the capacitor C5 is the output voltage VO-.

[0027] As a further improvement of the above technical solution, the input voltage preprocessing unit adopts a two-stage EMI filter design;The input voltage preprocessing unit comprises a short circuit protection circuit, a spike protection circuit and an EMI filter circuit;The spike protection circuit and the EMI filter circuit both adopt LC filter circuit to realize.

[0028] The spike protection circuit and the EMI filter circuit comprise capacitors C6, common mode inductor L2, capacitors C7, C8, C9, C10, common mode inductor L3, capacitors C4, C5, C11 and C12;The first end of the capacitor C6 is connected to the power supply VI+, and the second end of the capacitor C6 is connected to the power supply VI-;The two ends of the winding one of the common mode inductor L2 are connected to the first end of the capacitor C6 and the first end of the capacitor C7 respectively, and the two ends of the winding two of the common mode inductor L2 are connected to the second end of the capacitor C6 and the second end of the capacitor C8 respectively;The second end of the capacitor C6 is connected to the first end of the capacitor C8 and grounded;The first end of the capacitor C9 is connected to the first end of the capacitor C7 and the first end of the capacitor C10 respectively;The second end of the capacitor C8 is connected to the second end of the capacitor C9 and the second end of the capacitor C10 respectively;The two ends of the winding one of the common mode inductor L3 are connected to the first end of the capacitor C10 and the first end of the capacitor C4 respectively;The two ends of the winding two of the common mode inductor L3 are connected to the second end of the capacitor C10 and the second end of the capacitor C5 respectively;The second end of the capacitor C4 is connected to the first end of the capacitor C5 and grounded;The first end of the capacitor C4 is connected to the first end of the capacitor C11 and the first end of the capacitor C12 respectively;The second end of the capacitor C11 is connected to the second end of the capacitor C12;The first end of the capacitor C12 is the output VO+, and the second end of the capacitor C12 is the output VO-.

[0029] In the second aspect of the present application, a control method of the FPGA-based electric control system for phased array radar beam control is also disclosed, which comprises the following steps: S1, the FPGA module performs system initialization, and synchronously detects the system state, and reports the detection result to the digital control board; S2, the FPGA module receives the control information transmitted by the digital control board, and checks the received control information, judges whether the received control information meets the requirements, if not, retransmits, if meets the requirements, executes step S3; S3, the FPGA module transmits the code value in the system call in the control information, finds and selects the corresponding time sequence mode in the preset time sequence mode library, and determines the working mode; S4, the FPGA module calculates the code value of the selected mode, and outputs the IO port to the level conversion chip, and outputs to the corresponding communication interface after level conversion, controls the phased array radar component.

[0030] Compared with the prior art, the advantages of the present application are: (1) The power supply and the FPGA module process various communication and electrical signals on the wave control board, and transmit them to the phased array antenna array, which can not only realize the working mode, frequency point phase control and state feedback of the phased array antenna array, but also realize power supply and power supply state monitoring of various modules of the phased array antenna array. The electric control system adopts an integrated shell design to realize the cooperative work of high-density signal system (single board integrated 500+IO) and high-power signal (300W power output), has excellent anti-interference performance, and meets the control and power supply requirements of the phased array radar antenna front end.

[0031] (2) The power supply system and the wave control system are integrated and designed, and a double-cavity electromagnetic shielding structure is adopted, and a conductive rubber+ferriet composite isolation layer (thickness 1.0±0.05mm) is arranged between the cavities, which realizes the cross-band isolation of the power supply system (EMI noise>60dB) and the control system (signal sensitivity<1uV), and can reduce the crosstalk by 42% compared with the traditional metal partition scheme. The electric control system adopts two-stage EMI filtering design, common mode inductance and common mode capacitance filter out common mode interference current, effectively suppresses the conducted interference of the power bus, effectively solves the electromagnetic compatibility problem of coexistence of high-density digital system and strong analog power supply, and provides a stable and efficient electric control solution for phased array radar.

[0032] (3) The electric control system comprehensively designs voltage detection, current detection and temperature detection functions, and dynamically adjusts the speed curve of the cooling fan according to the temperature control, realizes the optimal thermal balance management of energy efficiency.

[0033] (4) The electronic control system described in this invention employs a three-dimensional wiring anti-interference design on its beam control printed circuit board. Utilizing interlayer vertical wiring technology, power lines and control signal lines are orthogonally distributed across different layers of the PCB. Simultaneously, a densely distributed array of grounding vias (with a via spacing of one-tenth of the wavelength of the highest operating frequency) achieves high-frequency isolation performance, effectively suppressing crosstalk intensity to an extremely low level detectable by the instrument. Through its three-dimensional wiring anti-interference design, the beam control printed circuit board distributes and processes power signals to the radar RF components and other components, providing multiple power outputs to meet the overall radar power requirements. Power and control signals are output to the RF components via a single connector. Compared to traditional radar systems where power and control signals are output from two separate units (power supply and beam control), this electronic control system reduces connector usage by 50%, lowers overall structural complexity, saves hardware costs, and effectively improves system reliability. This invention has passed the GJB150A-2009 military electronic equipment environmental test verification and is applicable to phased array radar, electronic countermeasures, and other system application scenarios. Attached Figure Description

[0034] Figure 1 This is a schematic block diagram of the FPGA-based electronic control system in this invention. Figure 2 This is a schematic block diagram illustrating the control principle of the FPGA module; Figure 3 This is the schematic diagram of the power management module; Figure 4 This is a schematic block diagram of the storage module. Figure 5 This is a schematic block diagram of the voltage detection module. Figure 6 This is a schematic block diagram of the current detection module. Figure 7 This is the control timing diagram for the current detection module; Figure 8 This is a schematic block diagram illustrating the principle of the temperature detection module; Figure 9 This is a schematic block diagram illustrating the principle of LVTTL 3.3V level conversion in various communication interfaces; Figure 10 This is a schematic block diagram illustrating the principle of the LVDS interface among various communication interfaces; Figure 11 This is a schematic block diagram illustrating the input and output filtering principle in a voltage conversion unit. Figure 12 This is a schematic block diagram of the spike protection circuit and EMI filter circuit in the input voltage preprocessing unit; Figure 13 This is a flowchart of the control method for the FPGA-based electronic control system in this invention. DETAILED DESCRIPTION

[0035] The application is further described below in conjunction with the accompanying drawings: As Figure 1 The FPGA-based electric control system for phased array radar beam control shown in the figure comprises a shell and a beam control unit, a voltage conversion unit and an input voltage preprocessing unit installed in the shell. The electric control system is developed based on phased array radar, and the beam control unit, the voltage conversion unit and the input voltage preprocessing unit are integrated in one shell. The beam control unit is a high-density signal system (single-board integration 500+IO), the beam control unit, the high-power voltage conversion unit (300W power output) and the input voltage preprocessing unit adopt a double-cavity electromagnetic shielding structure and a point-to-point interconnection line single-point connection to avoid ground electromagnetic interference. The beam control unit adopts a beam control printed board design, and the voltage conversion unit and the input voltage preprocessing unit adopt a power module printed board design. The double-cavity electromagnetic shielding structure is two independent cavities isolated from each other, and a lead-through hole is opened in the middle of the shielding structure, and the two cavities are respectively used to place the beam control printed board and the power module printed board. The beam control printed board and the power module printed board adopt a point-to-point interconnection line interconnection, and the interconnection line passes through the lead-through hole in the middle of the shielding structure. By setting two independent cavities to place the two printed boards, the power supply and the beam control unit electromagnetic interference can be prevented.

[0036] The electric control system described in the application takes FPGA module, power module and communication interface as main hardware, realizes system combination of high power and high density signal according to phased array radar power and control demand, completes multiple control interfaces and voltage combination output, and has good electromagnetic compatibility. The beam control unit is a high density signal system (single board integration 500+IO), the beam control unit, the high power voltage conversion unit (300W power output) and the input voltage preprocessing unit adopt double cavity electromagnetic shielding structure isolation, adopt point-to-point interconnection line single point connection, and avoid ground plane electromagnetic interference. The double cavity electromagnetic shielding structure refers to that, inside the shell of the electric control system, by setting physical separation structure, the high density signal system (beam control unit) and the high power signal system (voltage conversion unit and input voltage preprocessing unit) are separated in two independent cavities through the arrangement of conductive rubber+ferroelectric composite isolation layer (thickness 1.0±0.05mm). The FPGA module in the beam control unit will generate high-speed digital signals, which belong to high density signal sources; the power modules such as the voltage conversion unit and the input voltage preprocessing unit belong to high power signal sources, which are easy to produce electromagnetic radiation and conduction interference. By blocking the electromagnetic coupling path between the two systems through the metal+conductive rubber+ferroelectric composite isolation layer, the electromagnetic interference of the two types of signal systems can be avoided by the double cavity electromagnetic shielding structure isolation, the electromagnetic noise of the power module is prevented from affecting the clock signal of the FPGA module through the ground plane or space radiation, which leads to the decrease of the beam pointing accuracy, and the point-to-point interconnection line single point connection mode is further adopted to reduce the ground plane interference, thereby improving the electromagnetic compatibility of the whole electric control system.

[0037] The beam control printed board distributes and processes the power supply signals and then distributes them to the radio frequency components through the three-dimensional wiring anti-interference design; the three-dimensional wiring anti-interference design adopts an interlayer vertical wiring process to make the power supply signals input by the power module printed board and the signals on the beam control board orthogonally distributed on different layers of the PCB, realizes high-frequency isolation performance through the use of a dense distribution of ground via arrays (hole spacing is one tenth of the highest working frequency wavelength), and effectively suppresses the crosstalk strength to a very low level that can be detected by the instrument. All external interfaces of the electric control system are uniformly output by the beam control printed board, each output port contains multiple power supply signals and control signals, can meet the power supply and control signal input requirements of radar radio frequency components and other components, and only needs a single connector to connect a single connector. Compared with the traditional radar power and control signals output from the power component and the beam control component, the use amount of connectors is reduced by 50%, the structure complexity of the whole machine is reduced, the hardware cost is saved, and the system reliability is improved.

[0038] In some embodiments, as Figure 1As shown, the beam control unit P10 includes: an FPGA module P101, a power management module P102, a storage module P103, a voltage detection module P104, a current detection module P105, a temperature detection module P106, and multiple communication interfaces P107. The beam control unit P10 is used for communication interface control and data signal processing, as well as power management, program and data storage, voltage, current, and temperature detection, and control of the phased array antenna subsystem components through multiple communication interfaces. The voltage conversion unit P20 is used to provide the phased array radar with multiple voltage outputs required, converting the input power supply into six or more different voltage levels, with each current output designed according to the power requirements of the downstream device. The input voltage preprocessing unit P30 includes: a short-circuit protection circuit, a spike protection circuit, and an EMI filter circuit. The input voltage preprocessing unit P30 reduces input front-end noise interference through short-circuit protection, spike protection, and filtering circuits.

[0039] In some implementations, such as Figure 2 As shown, the FPGA module P101 includes an FPGA chip. This module is used to control various communication interfaces and process data signals. Based on control commands such as frequency words, beam pointing, and switch states sent from the digital control board's serial port, the FPGA module selects the corresponding timing mode, decodes the code values ​​into serial codes such as data, clock, and latch, and outputs them to the level conversion chip through the FPGA chip's I / O port, and then to the corresponding communication interface to control the phased array radar components.

[0040] Specifically, the peripheral and power management module P102, the storage module P103, the voltage detection module P104, the current detection module P105, the temperature detection module P106 and other functional units of the FPGA chip are connected, so as to realize the detection and reporting of voltage, current and temperature. In the embodiment, the FPGA chip adopts an XC7K325T chip. The FPGA chip converts the 3.3V TTL or 1.8V TTL level output by the IO port of the FPGA chip into 3.3V TTL and 5V TTL signals through a level conversion chip, which is used to control the phase shift, attenuation, transceiver state and power consumption switching of the radio frequency assembly. The FPGA chip converts the output of the IO port of the FPGA chip into an LVDS signal through an LVDS chip, communicates with the switch assembly, and thus controls the switch assembly to switch the gating assembly. The LVDS chip is a device used to realize low-voltage differential signal (LVDS) conversion and transmission. The FPGA chip communicates with an external digital control board through an RS422 signal transceiver. According to the frequency word, beam pointing, switch state and other control commands sent by the digital control board through the RS422 serial port, a corresponding timing mode is selected, the code value is calculated into data, clock, latch and other serial codes, and the output is output to the corresponding interface through the IO port of the FPGA chip and the level conversion chip, so as to control the phased array radar assembly.

[0041] Further, a matching resistor R2, R2=100Ω, is connected to the differential input of the RS422 signal transceiver, which does not support suspension. Pull-up and pull-down resistors are connected to the RX+ and RX- ends of the RS422 signal transceiver, so as to ensure that the voltage difference between the two ends of the resistor R2 is VID>200mV. The resistors R1 and R3 are selected as 600Ω, and VID=3.3*R2 / (R2+R1+R3)=254mV, so that the design can ensure that the output high level is output after suspension. In order to improve the external ESD level, a TVS is connected to the differential end RX+ and RX- for device protection, and the TVS is selected to meet the absolute maximum voltage requirement of the port (-7.5~12.5V). A matching resistor R4, R4=100Ω, is connected to the RS422 differential output end, which does not support suspension. Pull-up and pull-down resistors are connected to the TX+ and TX- ends, so as to ensure that the voltage difference between the two ends of the resistor R4 is VID>200mV. The resistors R5 and R6 are selected as 600Ω, and VID=3.3*R2 / (R2+R1+R3)=254mV, so that the design can ensure that the output high level is output after suspension. In order to improve the external ESD level, a TVS is connected to the differential end TX+ and TX- for device protection, and the TVS is selected to meet the absolute maximum voltage requirement of the port (-7.5~12.5V).

[0042] In some embodiments, as Figure 3As shown, the power management module P102 is used to convert the input voltage into different voltages required by the beam control unit, while managing the power-on sequence of different voltages. In this embodiment, the power management module P102 is used to convert the input voltage 5V into different voltages required by the FPGA. In this embodiment, the core function of the power management module P102 is to convert the input 5V voltage into three voltages 1.0V, 1.8V and 3.3V required by the FPGA module, and strictly manage the power-on sequence of the three voltages. First, enable output 1 by inputting 5V to ensure that 1.0V is powered on first; after 1.0V is powered on, the power-on indication signal PGOOD1 is pulled high, which is connected to the enable end of output 2 to trigger 1.8V power-on; after 1.8V is powered on, the power-on indication signal PGOOD2 is pulled high, which is connected to the enable end of output 3 to trigger 3.3V power-on; when 3.3V is powered on, it meets the full power-on requirements of the FPGA module. This design realizes voltage conversion through feedback setting resistance, and relies on the chain triggering mechanism of the power-on indication signal to ensure that different voltages are powered on in sequence, providing reliable power support for the stable start of the FPGA module.

[0043] Further, the power management module is used to convert the input voltage 5V into 1.0V, 1.8V and 3.3V through feedback setting resistance, enable 1.0V to power on first, and then disable 1.8V power-on through 1.0V power-on indication, and then disable 3.3V power-on through 1.8V power-on indication. Calculate the feedback setting resistance according to the power output value, and the power input requirements are 1.0V for output 1, 1.8V for output 2, and 3.3V for output 3. Enable output 1 by inputting 5V to make 1.0V power on first, and after 1.0V is powered on, the output 1 power-on indication PGOOD1 is pulled high, PGOOD1 is pulled high and connected to the enable end of output 2 to enable 1.8V power-on. After 1.8V is powered on, the output 2 power-on indication PGOOD2 is pulled high, and PGOOD2 is pulled high and connected to the enable end of output 3 to enable 3.3V power-on. After 3.3V is powered on, the power-on requirements of the FPGA module are met.

[0044] In some embodiments, as Figure 4 As shown, the storage module P103 is used for FPGA program and data storage. The storage module P103 includes two 256M Flash, namely a first Flash and a second Flash, the first Flash (Flash 1 in the figure) is used for FPGA program storage and configuration, and the second Flash (Flash 2 in the figure) is used for data storage, which is used to store detection data and beam control code value information. The working voltage of the two Flash is 3.3V, and the FPGA chip inputs instructions, addresses and data to the internal Flash chip in series through a clock.

[0045] In some implementations, such as Figure 5 As shown, the voltage detection module P104 is used to detect the multiple output voltages of the power supply. The voltage detection module has a 4-channel voltage monitoring function, which can monitor whether the output voltages of 4 different types are normal. Voltage detection is mainly implemented through a microprocessor monitoring chip, which contains a bandgap reference, three dedicated voltage comparators, and one auxiliary voltage comparator. The three dedicated comparators monitor +5V, -5V, and +12V respectively, and the auxiliary comparator's monitoring voltage can be customized as needed. All comparators are open-drain outputs with hysteresis characteristics, which can be used for overvoltage / undervoltage monitoring. Each input voltage is internally divided and compared with the reference voltage. If it is higher than the reference voltage, a high level is output; if it is lower than the reference voltage, a low level is output. The output port is connected to the I / O port of the FPGA module. The FPGA module detects the high and low levels to determine whether the voltage is normal. A high level indicates normal voltage, and a low level indicates abnormal voltage.

[0046] In some implementations, such as Figure 5As shown, the voltage detection module P104 includes a first voltage comparator, a second voltage comparator, a third voltage comparator, a fourth voltage comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube. The non-inverting input terminal of the first voltage comparator is connected to a first voltage dividing circuit including two first voltage dividing resistors connected in series, and the non-inverting input terminal of the first voltage comparator is connected to a node between the two first voltage dividing resistors. One end of the two first voltage dividing resistors is connected to +5V, and the other end is connected to ground. The inverting input terminal of the first voltage comparator is connected to the inverting input terminal of the second voltage comparator, the inverting input terminal of the third voltage comparator, the inverting input terminal of the fourth voltage comparator, and a 1.24V reference voltage. The output terminal of the first voltage comparator is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the gate of the first MOS tube. The source of the first MOS tube is connected to ground, and the drain of the first MOS tube serves as an output terminal OUT1. The non-inverting input terminal of the second voltage comparator is connected to a second voltage dividing circuit including two second voltage dividing resistors connected in series, and the non-inverting input terminal of the second voltage comparator is connected to a node between the two second voltage dividing resistors. One end of the two second voltage dividing resistors is connected to +5V, and the other end is connected to ground. The output terminal of the second voltage comparator is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the gate of the second MOS tube. The source of the second MOS tube is connected to ground, and the drain of the second MOS tube serves as an output terminal OUT2. The non-inverting input terminal of the third voltage comparator is connected to a third voltage dividing circuit including two third voltage dividing resistors connected in series, and the non-inverting input terminal of the third voltage comparator is connected to a node between the two third voltage dividing resistors. One end of the two third voltage dividing resistors is connected to +12V, and the other end is connected to ground. The output terminal of the third voltage comparator is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the gate of the third MOS tube. The source of the third MOS tube is connected to ground, and the drain of the third MOS tube serves as an output terminal OUT3. The non-inverting input terminal of the fourth voltage comparator is connected to a fourth voltage dividing circuit including two fourth voltage dividing resistors connected in series, and the non-inverting input terminal of the fourth voltage comparator is connected to a node between the two fourth voltage dividing resistors. One end of the two fourth voltage dividing resistors is connected to DIN (the voltage of DIN is set as required), and the other end is connected to ground. The output terminal of the fourth voltage comparator is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the gate of the fourth MOS tube. The source of the fourth MOS tube is connected to ground, and the drain of the fourth MOS tube serves as an output terminal OUT4.

[0047] In some embodiments, as Figure 6As shown, the current detection module P105 is used to monitor the magnitude of a certain current in the RF component in real time, thereby determining whether the component is working properly. The current detection module P105 includes four voltage measurement channels. In this embodiment, the measurement is performed by connecting a current sensing resistor in series between the power output and the RF component. The selection of the current sensing resistor is determined by the full-swing differential input voltage (0.3V) of the current detection module. The current sensing resistor can be expressed as a function of the maximum measurable current, R = 0.3 / IMAX, where IMAX is the maximum measurable current. In this embodiment, the maximum measurable current IMAX is 6A, and the current sensing resistor R is 50mΩ. The current detection module uses I... 2 The C-bus communicates with the FPGA module. The FPGA module reads and writes byte data through the bus to obtain the measured voltage values ​​of V1, V2, V3, and V4. The current value for each channel can be obtained by dividing the current by (V2-V1) / R. By detecting the current value, the normal operating status of the RF components can be quickly determined. See the timing diagram for current reading. Figure 7 The I²C bus signals include the clock line SCL and the data line SDA. The high / low level changes and timing relationship of these two lines are crucial for reading current data. When SCL is high, the state of SDA indicates the data bit; when SCL is low, it indicates that SDA switching is enabled. The control register is configured according to its definition. The data register consists of 8 high and low bytes, with a voltage conversion accuracy of 14 bits. After configuration, the value in the register is read to obtain the measured voltage.

[0048] In some implementations, such as Figure 6As shown, the current detection module P105 includes a first current sensing resistor, a second current sensing resistor, a multiplexing unit, an analog-to-digital converter ADC, a control logic unit, an oscillator OSC, and an I2C bus. The input end of the first current sensing resistor is connected to a first radio frequency component, and the input end of the second current sensing resistor is connected to a second radio frequency component. The two ends of the first current sensing resistor are respectively connected to the first data input end and the second data input end of the multiplexing unit, and one end of the first current sensing resistor is connected to a power supply and the other end is connected to the first radio frequency component. The two ends of the second current sensing resistor are respectively connected to the third data input end and the fourth data input end of the multiplexing unit, and one end of the second current sensing resistor is connected to the power supply and the other end is connected to the second radio frequency component. The current signals detected by the two sensing resistors are in the form of voltage and are input as raw signals to the multiplexing unit, waiting for subsequent gating processing. The output end of the multiplexing unit is connected to the input end of the analog-to-digital converter ADC. The multiplexing unit selects one of the signals from the two current sensing resistors according to the instructions of the control logic unit and transmits it to the analog-to-digital converter ADC for analog-to-digital conversion. The output end of the analog-to-digital converter ADC is connected to the input end of the control logic unit, and the analog-to-digital converter ADC transmits the converted digital signal to the control logic unit for data processing, analysis, or storage. The output end of the oscillator is connected to the clock signal input end of the control logic unit. The oscillator OSC provides a stable clock signal for the control logic unit as the time reference of the entire module, ensuring that the timing control of the control logic unit is accurate and orderly. The control signal output end of the control logic unit is connected to the selection control end of the multiplexing unit. The control logic unit sends control signals to the multiplexing unit according to pre-set rules or external instructions to determine whether to gate the signals of the first current sensing resistor or the second current sensing resistor. The data interface of the control logic unit is connected to the I2C bus. The digital signal processed by the control logic unit is transmitted to the FPGA module through the I2C bus, and the control instructions of the FPGA module can also be received through the I2C bus.

[0049] In some embodiments, the temperature detection module P106 is composed of a temperature monitoring device, and the temperature is read back through the FPGA module to control the fan speed according to the temperature. Figure 8 As shown, the temperature detection module P106 includes a temperature sensor, and the temperature sensor is connected to the FPGA module through a single bus. The temperature sensor is installed on the power module printed board. In this embodiment, two DC / DC converters are included, which are a first DC / DC converter (DC / DC 5) and a second DC / DC converter (DC / DC 6). Figure 8 Figure 8 ​The output of the FPGA module is connected to a fan, and the fan speed is controlled by a PWM wave. The temperature detection module P106 places the temperature sensor on the power module printed circuit board, which needs to be close to the DC / DC 5 with the highest power to accurately measure the maximum heat generation of the entire electronic control system. The temperature sensor communicates with the FPGA module through a single-bus protocol, including a "read / write timing". When performing temperature measurement, the FPGA module issues a [44h] command, and the temperature data is stored in the temperature register of the FPGA module in the form of 2 bytes. The FPGA module issues a read initiation timing. When the temperature sensor returns 1, it indicates that the temperature conversion is complete, and the temperature is obtained by reading the temperature register value. The system maps the real-time temperature value to a PWM duty cycle parameter according to a preset temperature control algorithm, and drives the cooling fan through the GPIO output of an adjustable pulse width signal, thus constructing a closed-loop thermal management system.

[0050] In some implementations, such as Figure 9 As shown, the various communication interfaces P107 include an LVTTL 3.3V interface, an LVTTL 5.0V interface, an RS422 interface, and an LVDS interface; these are derived from various I / O outputs of the FPGA and are responsible for controlling various component units in the phased array antenna subsystem. The LVTTL 3.3V interface is output through nine 16-channel level conversion chips, with each output port having a 50-ohm resistor added to isolate external signal backflow, increasing interface security. The LVTTL 5.0V interface is output through three 16-channel level conversion chips, with each output port having a 50-ohm resistor added to isolate external signal backflow, also increasing interface security. The RS422 interface is... Figure 2 The RS422 signal transceiver in the example. Figure 10 As shown, the LVDS interface consists of four pairs of LVDS transceiver chips, and the FPGA module controls the transmission and reception. The single-ended signal output from the FPGA module's I / O port is converted into an LVDS signal and connected to the corresponding J30J interface to communicate with the external switch module, thereby enabling the FPGA to control the external switch.

[0051] In some implementations, such as Figure 1 As shown, the voltage conversion unit P20 consists of multiple DC / DC converters and processing circuits, outputting different voltages required by the phased array radar. The voltage conversion unit P20 includes: an input filter circuit, a DC / DC converter, an output filter circuit, and a protection circuit. Both the input and output filter circuits filter out common-mode and differential-mode interference within the power supply system. The input and output filter circuits employ... Figure 11The filter network circuit shown adopts multi-stage filtering technology, a common mode filtering and a differential mode filtering multi-stage combined mode, and can eliminate electromagnetic interference and reduce power output ripple. Figure 11 As shown, the filter network circuit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, and a capacitor C5; a first end of the capacitor C1 is connected to a power supply VI+, and a second end of the capacitor C1 is connected to a power supply VI-; the first end of the capacitor C1 is connected to the first end of the capacitor C2, the first end of the capacitor C3, and the first end of the capacitor C4 through an inductor L1; the second end of the capacitor C1 is connected to the second end of the capacitor C2, the second end of the capacitor C3, and the second end of the capacitor C5 respectively; the second end of the capacitor C4 is connected to the first end of the capacitor C5 and grounded; the first end of the capacitor C4 is an output voltage VO+, and the second end of the capacitor C5 is an output voltage VO-. The protection circuit is an overcurrent protection circuit, which adopts a self-resetting fuse design. When overcurrent occurs, the resistance increases sharply, and the system automatically recovers after the fault is removed.

[0052] In some embodiments, the input voltage preprocessing unit adopts EMI filtering to filter out common mode interference and differential mode interference of the power supply system, adopts a two-stage EMI filtering design, and filters out common mode interference current through a common mode inductor and a common mode capacitor to effectively suppress power bus conducted interference and achieve better anti-electromagnetic interference capability of the electric control system. As shown in Figure 1 The input voltage preprocessing unit P30 includes a short circuit protection circuit, a spike protection circuit, and an EMI filter circuit. The short circuit protection circuit is realized by connecting a fuse in series at the input end. The spike protection circuit and the EMI filter circuit are realized by LC filter circuits as shown in Figure 12 The LC filter circuit can effectively suppress high-frequency spike voltage and attenuate spikes through the combination of capacitors and inductors. The power module generates radiation and conducted electromagnetic interference noise during operation. Radiation noise is mainly caused by rapid changes in voltage and current, which are caused by the opening and closing of power switching devices. The combination of capacitors and inductors can filter out high-frequency oscillations caused by rapid switching. Conducted noise is divided into common mode noise and differential mode noise. In order to reduce noise interference, differential mode and common mode filters are added to the circuit. The two-stage EMI filtering design in the present application can effectively filter out electromagnetic interference at the power supply end and reduce noise for the system.

[0053] As shown in Figure 12As shown, the spike protection circuit and the EMI filter circuit include a capacitor C6, a common mode inductor L2, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a common mode inductor L3, a capacitor C4, a capacitor C5, a capacitor C11, and a capacitor C12. A first end of the capacitor C6 is connected to the power supply VI+, and a second end of the capacitor C6 is connected to the power supply VI-. Two ends of a winding one of the common mode inductor L2 are respectively connected to the first end of the capacitor C6 and the first end of the capacitor C7, and two ends of a winding two of the common mode inductor L2 are respectively connected to the second end of the capacitor C6 and the second end of the capacitor C8. The second end of the capacitor C6 is connected to the first end of the capacitor C8 and grounded. The first end of the capacitor C9 is respectively connected to the first end of the capacitor C7 and the first end of the capacitor C10. The second end of the capacitor C8 is respectively connected to the second end of the capacitor C9 and the second end of the capacitor C10. Two ends of the winding one of the common mode inductor L3 are respectively connected to the first end of the capacitor C10 and the first end of the capacitor C4. Two ends of the winding two of the common mode inductor L3 are respectively connected to the second end of the capacitor C10 and the second end of the capacitor C5. The second end of the capacitor C4 is connected to the first end of the capacitor C5 and grounded. The first end of the capacitor C4 is respectively connected to the first end of the capacitor C11 and the first end of the capacitor C12, and the second end of the capacitor C11 is connected to the second end of the capacitor C12. The first end of the capacitor C12 is an output VO+, and the second end of the capacitor C12 is an output VO-. Through the combination of the common mode inductors L2 and L3 and the capacitors C6, C7, C8, C9, C10, C4, C5, C11, and C12, common mode and differential mode noise on the input side of the power supply is filtered out, while noise generated by the circuit itself is prevented from back-polluting the power supply, so that the input / output power supply signal is more pure.

[0054] The application also includes a control method for the above-mentioned FPGA-based electric control system for phased array radar beam control, which comprises the following steps: S1, the FPGA module performs system initialization and synchronously detects the system state, and reports the detection result to the digital control board.

[0055] The FPGA module performs system initialization, and after system initialization, synchronously detects the system state, detects whether the voltage, current, temperature, and other modules are normal, and reports to the digital control board.

[0056] S2, the FPGA module receives the control information transmitted by the digital control board, and checks the received control information to determine whether the received control information meets the requirements; if not, retransmit; if yes, perform step S3. The FPGA module receives the control information transmitted by the upper digital control board through the RS422 interface, and the control information is written according to the communication protocol agreed by both parties, including the word head, data bits, control bits, check bits, system call transmission code value, and other information.

[0057] S3, the FPGA module looks up and selects the corresponding timing mode in the preset timing mode library according to the system call transmission code value in the control information, and determines the working mode. After the control information verification passes, the FPGA module looks up the matching item in the preset timing mode library according to the system call transmission code value in the information, automatically selects the corresponding working mode (such as mode 1, mode 2… mode n), and prepares for subsequent control of the phased array radar component.

[0058] S4, the FPGA module calculates the code value of the selected mode and outputs it to the level conversion chip through the IO port, and outputs it to the corresponding communication interface after level conversion, and controls the phased array radar component.

[0059] The FPGA module calculates the code value of the selected mode into data, clock, latch and other serial code formats, outputs it to the level conversion chip through the IO port, and then sends it to the phased array radar component through the corresponding communication interface after level conversion, and finally realizes the accurate control of the radar component.

[0060] The control method of the FPGA-based electric control system for phased array radar beam control provided by the application completes the control of the phased array radar component by initializing detection→information interaction verification→mode matching→code value calculation and output, so that the FPGA module cooperates with the digital control board efficiently, and guarantees the stable and accurate operation of the system.

[0061] In summary, the power supply system and the wave control system are integrated and designed in the application, the double-cavity electromagnetic shielding structure is adopted for isolation, the point-to-point interconnection line is adopted for single-point connection, the ground electromagnetic interference can be avoided, the two-stage EMI filtering design is adopted, the common-mode inductance and common-mode capacitance are used to filter the common-mode interference current, the power bus conduction interference can be effectively suppressed, and the traditional high-density signal and high-power signal electromagnetic interference problems are solved. Compared with the conventional radar beam control, the phased array antenna front-end power supply design is added in the application, the multi-path power supply output is provided, the whole radar power supply use requirement is met, the double-board cooperative design of the beam control printed board and the power module printed board is adopted, the high-density signal integration (single-board integration 500+IO) and high-power signal (supporting 300W power output) distribution are realized through three-dimensional wiring, all external interfaces are uniformly output by the beam control printed board, each output port contains multiple power signals and control signals, the power signals and the control signals are output to the radio frequency assembly through a single connector, compared with the traditional radar power supply and control signal output from the power assembly and the wave control assembly, the connector usage amount is reduced by 50%, the whole machine structure complexity is reduced, the radar phased array front-end integration is improved, the hardware cost is saved, the system reliability is improved, the universal platform design is beneficial, in addition, the voltage detection, the current detection and the temperature detection functions are comprehensively designed, the fan speed is controlled according to the temperature, and the closed-loop thermal management system is realized. The design has passed the GJB150A-2009 military electronic equipment environment test verification, and is suitable for phased array radar, electronic countermeasure and other system application scenarios.

[0062] The above-described embodiments are only used to describe the preferred embodiments of the present application, and do not limit the scope of the present application, and various modifications and improvements to the technical solutions of the present application made by those skilled in the art without departing from the design spirit of the present application shall fall within the protection scope of the present application.

Claims

1. An FPGA-based electronic control system for beam control of phased array radar, characterized in that, The electronic control system includes a housing and a beam control unit (P10), a voltage conversion unit (P20), and an input voltage preprocessing unit (P30) installed in the housing. The beam control unit (P10) uses a beam control printed circuit board, and the voltage conversion unit (P20) and the input voltage preprocessing unit (P30) use a power module printed circuit board. The housing is a dual-cavity electromagnetic shielding cavity with two chambers, and an isolation layer composed of conductive rubber and ferrite is arranged between the two chambers. The two chambers are used to house the beam control printed circuit board and the power module printed circuit board, respectively. The beam control printed circuit board and the power module printed circuit board are interconnected at a single point through point-to-point interconnection lines. The beam control printed circuit board adopts three-dimensional wiring to distribute and process the power signal and then distribute it to the radar radio frequency components and other components.

2. The FPGA-based electronic control system for phased array radar beam control according to claim 1, characterized in that, The beam control unit (P10) includes: an FPGA module (P101), a power management module (P102), a storage module (P103), a voltage detection module (P104), a current detection module (P105), a temperature detection module (P106), and multiple communication interfaces (P107). The power management module (P102) provides operating voltage to the FPGA module (P101), converts the input voltage into the voltage required by the FPGA module (P101), and powers it on according to the timing sequence. The FPGA module (P101) serially inputs instructions, addresses, and data to the storage module (P103) via a clock signal to realize program loading and data reading and writing. The output terminal of the voltage detection module (P104) is connected to the I / O port of the FPGA module (P101). The current detection module (P105) communicates bidirectionally with the FPGA module (P101) via an I²C bus. The temperature detection module (P106) is connected to the FPGA module (P101) via a single bus and communicates using a single bus protocol. The I / O ports of the FPGA module (P101) are directly connected to various communication interfaces, and various signals are output and received through level conversion.

3. The FPGA-based electronic control system for phased array radar beam control according to claim 2, characterized in that, The FPGA module (P101) includes an FPGA chip, which is used to control various communication interfaces and process data signals; the FPGA chip is an XC7K325T chip. The power management module (P102) is used to convert the input voltage into different voltages required by the beam control unit, and to manage the power-on sequence of different voltages. The storage module (P103) is used for the program and data storage of the FPGA module. The storage module (P103) includes two 256M Flash chips, namely the first Flash and the second Flash. The first Flash is used for FPGA program storage and configuration, and the second Flash is used for data storage.

4. The FPGA-based electronic control system for phased array radar beam control according to claim 2, characterized in that, The voltage detection module (P104) is used to detect the multiple output voltages of the power supply; The voltage detection module (P104) includes a first voltage comparator, a second voltage comparator, a third voltage comparator, a fourth voltage comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET. The non-inverting input of the first voltage comparator is connected to a first voltage divider circuit, which includes two series-connected first voltage divider resistors. The non-inverting input of the first voltage comparator is connected to the node between the two series-connected first voltage divider resistors. One end of the two series-connected first voltage divider resistors is connected to +5V, and the other end is grounded. The inverting input of the first voltage comparator is connected to the second voltage comparator. The inverting inputs of the first voltage comparator, the third voltage comparator, the fourth voltage comparator, and a 1.24V reference voltage are connected. The output of the first voltage comparator is connected to the input of the first inverter, and the output of the first inverter is connected to the gate of the first MOSFET. The source of the first MOSFET is grounded, and the drain of the first MOSFET serves as the output terminal OUT1. The non-inverting input of the second voltage comparator is connected to a second voltage divider circuit, which includes two series-connected second voltage divider resistors. The non-inverting input of the second voltage comparator is connected to the node between the two series-connected second voltage divider resistors, and one end of the two series-connected second voltage divider resistors is connected to +5V. V, the other end is grounded; the output terminal of the second voltage comparator is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the gate of the second MOSFET, the source of the second MOSFET is grounded, and the drain of the second MOSFET serves as the output terminal OUT2; the non-inverting input terminal of the third voltage comparator is connected to the third voltage divider circuit, which includes two series-connected third voltage divider resistors, the non-inverting input terminal of the third voltage comparator is connected to the node between the two series-connected third voltage divider resistors, one end of the two series-connected third voltage divider resistors is connected to +12V, and the other end is grounded; the output terminal of the third voltage comparator is connected to the input terminal of the third inverter, and the output terminal of the third ... The gate of the third MOSFET is connected to the ground, the source of the third MOSFET is grounded, and the drain of the third MOSFET serves as the output terminal OUT3. The non-inverting input of the fourth voltage comparator is connected to the fourth voltage divider circuit, which includes two series-connected fourth voltage divider resistors. The non-inverting input of the fourth voltage comparator is connected to the node between the two series-connected fourth voltage divider resistors. One end of the two series-connected fourth voltage divider resistors is connected to DIN, and the other end is grounded. The output of the fourth voltage comparator is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the gate of the fourth MOSFET, the source of the fourth MOSFET is grounded, and the drain of the fourth MOSFET serves as the output terminal OUT4.

5. The FPGA-based electronic control system for phased array radar beam control according to claim 2, characterized in that, The current detection module (P105) is used to monitor the magnitude of a certain current in the radio frequency component in real time in order to determine whether the radio frequency component is working properly. The current detection module (P105) includes a first current sensing resistor, a second current sensing resistor, a multiplexer unit, an analog-to-digital converter (ADC), a control logic unit, an oscillator (OSC), and an I²C bus. The input terminal of the first current sensing resistor is connected to a first radio frequency (RF) component, and the input terminal of the second current sensing resistor is connected to a second RF component. The two ends of the first current sensing resistor are respectively connected to the first and second data input terminals of the multiplexer unit, and one end of the first current sensing resistor is connected to a power supply, while the other end is connected to the first RF component. The two ends of the second current sensing resistor are respectively connected to the third and fourth data input terminals of the multiplexer unit. One end of the sensing resistor is connected to the power supply, and the other end is connected to the second RF component. The output of the multiplexing unit is connected to the input of the analog-to-digital converter (ADC). According to the instructions of the control logic unit, the multiplexing unit selects one signal from the two current sensing resistors and outputs it to the ADC for analog-to-digital conversion. The output of the ADC is connected to the input of the control logic unit, which transmits the converted digital signal to the control logic unit for data processing, analysis, or storage. The output of the oscillator is connected to the clock signal input of the control logic unit. The control signal output of the control logic unit is connected to the selection control terminal of the multiplexing unit. The control logic unit sends a control signal to the multiplexing unit according to preset rules or external instructions, determining whether to select the first or second current sensing resistor. The processed digital signal is transmitted to the FPGA module (P101) via the I²C bus, and the control instructions from the FPGA module (P101) are received via the I²C bus.

6. The FPGA-based electronic control system for phased array radar beam control according to claim 2, characterized in that, The temperature detection module (P106) includes a temperature sensor; the temperature sensor is connected to the FPGA module (P101) via a single bus.

7. The FPGA-based electronic control system for phased array radar beam control according to claim 2, characterized in that, The various communication interfaces (P107) include an LVTTL 3.3V interface, an LVTTL 5.0V interface, an RS422 interface, and an LVDS interface.

8. The FPGA-based electronic control system for phased array radar beam control according to claim 1, characterized in that, The voltage conversion unit (P20) includes: an input filter circuit, a DC / DC converter, an output filter circuit, and a protection circuit. The input filter circuit and the output filter circuit are used to filter out common-mode interference and differential-mode interference in the power supply system. The input filtering circuit and the output filtering circuit adopt a filtering network circuit, which employs multi-stage filtering technology, combining common-mode filtering and differential-mode filtering in multiple stages. The filtering network circuit includes capacitors C1, C2, C3, C4, and C5. The first terminal of capacitor C1 is connected to power supply VI+, and the second terminal of capacitor C1 is connected to power supply VI-. The first terminal of capacitor C1 is connected to the first terminals of capacitors C2, C3, and C4 via inductor L1. The second terminal of capacitor C1 is connected to the second terminals of capacitors C2, C3, and C5, respectively. The second terminal of capacitor C4 is connected to the first terminal of capacitor C5 and grounded. The first terminal of capacitor C4 is the output voltage VO+, and the second terminal of capacitor C5 is the output voltage VO-.

9. The FPGA-based electronic control system for phased array radar beam control according to claim 1, characterized in that, The input voltage preprocessing unit (P30) adopts a two-stage EMI filter design; the input voltage preprocessing unit (P30) includes: a short-circuit protection circuit, a spike protection circuit, and an EMI filter circuit; both the spike protection circuit and the EMI filter circuit are implemented using LC filter circuits; The spike protection circuit and the EMI filter circuit include capacitor C6, common-mode inductor L2, capacitor C7, capacitor C8, capacitor C9, capacitor C10, common-mode inductor L3, capacitor C4, capacitor C5, capacitor C11, and capacitor C12; the first terminal of capacitor C6 is connected to power supply VI+, and the second terminal of capacitor C6 is connected to power supply VI-; the two ends of the first winding of common-mode inductor L2 are respectively connected to the first terminals of capacitor C6 and capacitor C7, and the two ends of the second winding of common-mode inductor L2 are respectively connected to the second terminals of capacitor C6 and capacitor C8; the second terminal of capacitor C6 is connected to the first terminal of capacitor C8 and grounded; the first terminal of capacitor C9 is respectively connected to the first terminal of capacitor C7, The first terminal of capacitor C10 is connected to the ground; the second terminal of capacitor C8 is connected to the second terminal of capacitor C9 and the second terminal of capacitor C10 respectively; the two ends of the first winding of common mode inductor L3 are connected to the first terminal of capacitor C10 and the first terminal of capacitor C4 respectively; the two ends of the second winding of common mode inductor L3 are connected to the second terminal of capacitor C10 and the second terminal of capacitor C5 respectively; the second terminal of capacitor C4 is connected to the first terminal of capacitor C5 and grounded; the first terminal of capacitor C4 is connected to the first terminal of capacitor C11 and the first terminal of capacitor C12 respectively; the second terminal of capacitor C11 is connected to the second terminal of capacitor C12; the first terminal of capacitor C12 is the output VO+, and the second terminal of capacitor C12 is the output VO-.

10. The control method for an FPGA-based electronic control system for phased array radar beam control according to any one of claims 1 to 9, characterized in that, The method includes the following steps: S1, the FPGA module (P101) performs system initialization and synchronously performs system status detection, and reports the detection results to the digital control board; S2. The FPGA module (P101) receives the control information transmitted by the digital control board and verifies the received control information to determine whether the received control information meets the requirements. If it does not meet the requirements, it retransmits the information. If it meets the requirements, it executes step S3. S3, FPGA module (P101) searches for and selects the corresponding timing mode in the preset timing mode library according to the system call transmission code value in the control information to determine the working mode; S4, the FPGA module (P101) calculates the code value of the selected mode and outputs it to the level conversion chip via its IO port. After level conversion, it is output to the corresponding communication interface to control the phased array radar components.

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