Band-gap reference voltage source with low power consumption and low temperature drift

Abstract

The invention discloses a low-power-consumption low-temperature-drift band-gap reference voltage source which comprises a VBE nonlinear term compensation circuit and an output voltage generation circuit, the VBE nonlinear term compensation circuit is matched with a bipolar transistor through an MOS tube current mirror image, the nonlinear temperature drift of output voltage is compensated, linearized VBE voltage is generated, and the output voltage generation circuit is connected with the VBE nonlinear term compensation circuit. And the output voltage generation circuit generates a voltage in direct proportion to absolute temperature through a differential pair structure, superposes the voltage with the linearized VBE voltage, and outputs a reference voltage. According to the low-power-consumption low-temperature-drift band-gap reference voltage source, temperature drift is compensated through the VBE nonlinear term compensation circuit, the output voltage generation circuit integrates signals to generate initial stable reference voltage, the temperature drift coefficient trimming circuit finely adjusts the temperature drift coefficient, and finally the reference voltage which is high in precision, low in temperature drift and good in consistency is output.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a low-power low-temperature drift bandgap reference voltage source. BACKGROUND

[0002] In integrated circuit design, a reference voltage source is a core component of many electronic systems, and is widely used in medical devices, automotive electronics, communication systems and other fields. These application scenarios have very high requirements for the accuracy and stability of the reference voltage, especially in environments with large temperature changes, the temperature drift of the reference voltage will seriously affect the performance of the entire system.

[0003] Traditional reference voltage generation circuits often have problems such as large temperature drift and insufficient accuracy. On the one hand, the base-emitter voltage V BE has a nonlinear temperature characteristic, which will cause the reference voltage to produce nonlinear temperature drift; on the other hand, the process deviation in the integrated circuit manufacturing process will cause large differences in the reference voltage characteristics between different chips, making it difficult to meet the requirements of chip consistency in high-precision application scenarios. SUMMARY

[0004] The purpose of the present application is to provide a low-power low-temperature drift bandgap reference voltage source to solve the above problems.

[0005] To achieve the above purpose, the present application adopts the following technical solutions:

[0006] A low-power low-temperature drift bandgap reference voltage source, comprising V BE a nonlinear term compensation circuit and an output voltage generation circuit, the V BE The nonlinear term compensation circuit compensates for the nonlinear temperature drift of the output voltage by cooperating with the bipolar transistor through the MOS tube current mirror, generates a linearized V BE voltage, and the output voltage generation circuit generates a voltage proportional to the absolute temperature and superimposes it with the linearized V BE voltage to output the reference voltage.

[0007] Preferably, the V BE nonlinear term compensation circuit comprises PMOS tube M P5 , PMOS tube M P6 , PMOS tube M P8 , NMOS tube M N9 , NMOS tube M N10 , NMOS tube M N11 and bipolar transistor Q1; the source of the PMOS tube M P5 , PMOS tube M P6 is connected to the power supply, and the PMOS tube M P5 and PMOS tube MP6 the drain of NMOS transistor M N9 and the drain of NMOS transistor M N11 form a current mirror, the source of NMOS transistor M N9 is grounded, the drain of NMOS transistor M N9 is connected to the drain of PMOS transistor M P5 , the gate of NMOS transistor M N9 is connected to an internal node of the compensation circuit, the source of NMOS transistor M N10 is grounded, the drain of NMOS transistor M N10 is connected to the emitter of bipolar transistor Ql, the gate of NMOS transistor M N10 is connected to the drain of NMOS transistor M N11 , the source of NMOS transistor M N11 is grounded, the drain of NMOS transistor M N11 is connected to the drain of PMOS transistor M P6 , the collector of bipolar transistor Ql is grounded, and the base of bipolar transistor Ql is connected to V N node.

[0008] Preferably, the V BE nonlinear term compensation circuit is based on the V BE temperature characteristic of bipolar transistor Ql, in combination with the current mirror, when the temperature changes, the change of V BE of bipolar transistor Ql causes the gate voltage of NMOS transistor M N10 to change, and the current of the related NMOS transistors M N9 , NMOS transistor M N10 and NMOS transistor M N11 is adjusted through the current mirror, wherein the NMOS transistors M N10 and NMOS transistor M N11 working in the sub-threshold region are stacked and output a compensation current exponentially related to temperature to the bipolar transistor Ql to compensate for the temperature drift caused by the V BE nonlinear term.

[0009] Preferably, the output voltage generation circuit includes PMOS transistor M P9 , PMOS transistor M P10 , PMOS transistor M P11 , PMOS transistor M P12 , PMOS transistor M P13 , NMOS transistor M N12 , NMOS transistor M N13 , NMOS transistor M N14 , NMOS transistor M N15 , NMOS transistor M N16 , NMOS transistor MN17 , resistance R TRIM , resistance R2 and resistance R3;

[0010] The source of the PMOS tube M P9 is connected to the power supply, and the drain of the PMOS tube M P9 is connected in series with resistance R TRIM , resistance R2 and resistance R3 in turn and then connected to the ground, forming V X node and V P node;

[0011] The source of the PMOS tube M P10 is connected to the power supply, and the drain of the PMOS tube M P10 is connected to the drain of the NMOS tube M N16 , and the gate of the PMOS tube M P10 is connected to the bias voltage V b ;

[0012] The source of the PMOS tube M P11 is connected to the power supply, and the drain of the PMOS tube M P11 is connected to the drain of the NMOS tube M N17 , and the gate of the PMOS tube M P11 is short-circuited between the drain and the gate;

[0013] The source of the PMOS tube M P12 is connected to V P node, and the drain of the PMOS tube M P12 is connected to the drain of the NMOS tube M N12 ;

[0014] The source of the PMOS tube M P13 is connected to V P node, and the drain of the PMOS tube M P13 is connected to the drain of the NMOS tube M N13 , and the gate of the PMOS tube M P13 is connected to V P node;

[0015] The sources of the NMOS tube M N12 and the NMOS tube M N13 are connected to the ground, and the drains of the NMOS tube M N12 and the NMOS tube M N13 are respectively connected to the drains of the PMOS tube M P12 and the PMOS tube M P13 ;

[0016] The NMOS tube M N14 and the NMOS tube M N15 constitute a current mirror, and the NMOS tube M N14and the source of the NMOS transistor M N15 is grounded, the drain of the NMOS transistor M N14 is connected to the drain of the PMOS transistor M N15 , the gate of the NMOS transistor M N12 is connected to the gate of the PMOS transistor M N13 ;

[0017] the source of the NMOS transistor M N16 is connected to the drain of the PMOS transistor M P10 , the drain of the NMOS transistor M N16 is connected to a reference voltage V out ;

[0018] the source of the NMOS transistor M N17 is connected to the drain of the PMOS transistor M P11 , the drain of the NMOS transistor M N17 is connected to the drain of the PMOS transistor M P13 .

[0019] Preferably, the power supply in the output voltage generating circuit is connected to the drain of the PMOS transistor M P9 and the series resistance R TRIM , the resistance R2 and the resistance R3 are divided, the bias voltage V b controls the current of the PMOS transistor M P10 , the compensation current V BE is combined, the currents and voltages of the nodes are adjusted under the action of multiple feedback loops, the stable output reference voltage V N16 is generated at the drain of the NMOS transistor M out , and the output reference voltage V TRIM is preliminarily and coarsely adjusted by the R out .

[0020] Preferably, a temperature drift coefficient adjustment circuit is further included for adjusting the resistance division ratio inside the circuit to finely adjust the temperature drift coefficient of the output voltage; the temperature drift coefficient adjustment circuit includes switches S0, S1, S2, R TRIM1 , R TRIM2 and R TRIM3 ; the R TRIM1 , R TRIM2 and R TRIM3 are connected in series, the lower end of the R TRIM1 is connected to the node V X , the upper end of the R TRIM1 is connected to the R TRIM2 , R TRIM3 in turn, and then connected to the reference voltage V out , the S0 is connected in parallel to the R TRIM1 , the S1 is connected in parallel to the R TRIM2 , and the S2 is connected in parallel to the R TRIM3 .

[0021] Preferably, the temperature drift coefficient adjustment circuit controls the on or off of S0, S1 and S2 through a digital control signal, changes V X The node is connected with a reference voltage V out The total resistance value and the voltage division ratio, and adjusts the output voltage temperature drift coefficient.

[0022] Preferably, the V BE The front end of the non-linear term compensation circuit is sequentially provided with a left starting circuit, a bias circuit and a right starting circuit from front to back, the left starting circuit is used for providing an initial signal for the bias circuit and subsequent circuits when the circuit is connected with a power supply, the bias circuit is used for providing a stable DC bias voltage and current for other active devices in the circuit, and the right starting circuit is used for providing a starting signal for the V BE The non-linear term compensation circuit and subsequent circuits.

[0023] Preferably, the left starting circuit comprises an NMOS tube M N1 , an NMOS tube M N2 and a capacitor C0; the bias circuit comprises an NMOS tube M N3 , an NMOS tube M N4 , an NMOS tube M N5 , an NMOS tube M N6 , a PMOS tube M P1 , a PMOS tube M P2 , a PMOS tube M P3 , a PMOS tube M P4 and a resistor R1; and the right starting circuit comprises an NMOS tube M N7 , an NMOS tube M N2 and a capacitor C1.

[0024] One end of the capacitor C0 is connected with a power supply, the other end of the capacitor C0 is connected with a gate of the NMOS tube M N2 , a source of the NMOS tube M N1 is grounded, a drain of the NMOS tube M N1 is connected with a source of the NMOS tube M N2 , and a drain of the NMOS tube M N2 is connected with a gate of the PMOS tube M P1 .

[0025] One end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is connected with a drain of the PMOS tube M P1 and a drain of the PMOS tube M P3 , a source of the PMOS tube M P1 is connected with the power supply, and a drain of the PMOS tube M P1 is connected with the resistor R1 and the PMOS tube MP3 the drain of the PMOS transistor M P1 the source of the PMOS transistor M P1 the drain of the NMOS transistor M N6 the drain of the PMOS transistor M P1 the gate of the PMOS transistor M P3 the source of the PMOS transistor M N3 the drain of the PMOS transistor M P3 the gate of the PMOS transistor M b the source of the PMOS transistor M P4 the drain of the NMOS transistor M P4 the drain of the PMOS transistor M N5 the gate of the PMOS transistor M P4 the gate of the PMOS transistor M b the source of the NMOS transistor M N3 the drain of the NMOS transistor M N3 the source of the NMOS transistor M P3 the drain of the NMOS transistor M N4 the source of the NMOS transistor M N5 the drain of the NMOS transistor M N4 the gate of the NMOS transistor M N3 the drain of the NMOS transistor M N5 the source of the NMOS transistor M P4 the drain of the NMOS transistor M N6 the source of the NMOS transistor M N6 the drain of the PMOS transistor M P2 the drain of the PMOS transistor M

[0026] one end of the capacitor C1 is connected to the power supply, and the other end of the capacitor C1 is connected to the gate of the NMOS transistor M N8 the source of the NMOS transistor M N7 the drain of the NMOS transistor M N7 the source of the NMOS transistor M N8 the drain of the NMOS transistor M N8 the V BE nonlinear term compensation circuit I CP node.

[0027] Compared with the background art, the present application has the following advantages:

[0028] 1. The present application provides a low-power low-temperature drift bandgap reference voltage source, which comprises a V BEThe nonlinear term compensation circuit compensates for temperature drift, the output voltage generation circuit integrates the signal to generate a preliminary stable reference voltage, and the temperature drift coefficient adjustment circuit finely adjusts the temperature drift coefficient, ultimately outputting a high-precision reference voltage with low temperature drift and good consistency.

[0029] 2. This invention provides a low-power, low-temperature-drift bandgap reference voltage source, V BE The nonlinear term compensation circuit generates a voltage proportional to absolute temperature through a differential pair structure and compares it with the linearized V. BE The voltages are superimposed to effectively cancel out the transistor base-emitter voltage V. BE The nonlinear temperature drift of the reference voltage caused by the nonlinear temperature characteristics significantly improves the temperature stability of the reference voltage, enabling it to remain stable over a wider temperature range.

[0030] 3. This invention provides a low-power, low-temperature-drift bandgap reference voltage source. The temperature drift coefficient adjustment circuit can adjust the internal resistor voltage division ratio by controlling the control signal to finely adjust the temperature drift coefficient of the output voltage in response to process deviations in integrated circuit manufacturing. This makes the temperature drift characteristics of the reference voltage as consistent as possible between different chips, thereby improving the mass production quality and application reliability of the chips. Attached Figure Description

[0031] Fig. 1 This is a circuit structure diagram of the present invention;

[0032] Fig. 2 V of the present invention BE Schematic diagram of the nonlinear term compensation circuit;

[0033] Fig. 3 V of the present invention BE Circuit diagram of nonlinear term compensation circuit. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0035] Example

[0036] Please refer to Figs. 1 to 3 As shown, this invention discloses a low-power, low-temperature-drift bandgap reference voltage source, including V BE Nonlinear term compensation circuit and output voltage generation circuit, V BE The nonlinearity compensation circuit, through the cooperation of a MOSFET current mirror and a bipolar transistor, compensates for the nonlinear temperature drift of the output voltage, generating a linearized Vo. BEVoltage, the output voltage generation circuit generates a voltage proportional to absolute temperature through a differential pair structure and superimposes it with a linearized V BE Voltage to output a reference voltage.

[0037] V BE The non-linear term compensation circuit includes PMOS M P5 , PMOS M P6 , PMOS M P8 , NMOS M N9 , NMOS M N10 , NMOS M N11 and bipolar transistor Q1; the source of PMOS M P5 , PMOS M P6 is connected to the power supply, the drain of PMOS M P5 and PMOS M P6 is connected to the drain of NMOS M N9 and NMOS M N11 , respectively, to form a current mirror, the source of NMOS M N9 is connected to the ground, the drain of NMOS M N9 is connected to the drain of PMOS M P5 , the gate of NMOS M N9 is connected to an internal node of the compensation circuit, the source of NMOS M N10 is connected to the ground, the drain of NMOS M N10 is connected to the emitter of bipolar transistor Q1, the gate of NMOS M N10 is connected to the drain of NMOS M N11 , the source of NMOS M N11 is connected to the ground, the drain of NMOS M N11 is connected to the drain of PMOS M P6 , and the collector of bipolar transistor Q1 is connected to the ground, and the base of bipolar transistor Q1 is connected to V N node.

[0038] V BE The non-linear term compensation circuit is based on the V BE temperature characteristic of bipolar transistor Q1, which is not purely linear (V BE ≈V T lnI S / I C , containing a non-linear term), and the change at different temperatures will cause the reference voltage to have a non-linear temperature drift. Through a specific circuit structure and component combination, the circuit offsets this non-linear temperature drift and improves the temperature stability of the reference voltage. In this embodiment, V BE The non-linear term compensation circuit is based on the V BEThe temperature characteristic is combined with the current mirror. When the temperature changes, the V BE of the bipolar transistor Q1 changes, which causes the gate voltage of the NMOS transistor M N10 to change. The related NMOS transistors M N9 , M N10 and M N11 are adjusted by the current mirror, and the NMOS transistors M N10 and M N11 working in the sub-threshold region are stacked and output a compensation current exponentially related to the temperature to the bipolar transistor Q1 to compensate the temperature drift caused by the non-linear term of V BE .

[0039] The working process of the non-linear term compensation circuit is as follows: when the temperature rises, the V BE of the bipolar transistor Q1 (assuming PNP type, which can be adjusted to NPN type according to the design) decreases, which causes the gate voltage of the NMOS transistor M BE to decrease, and the NMOS transistors M N10 and M N10 work in the sub-threshold region to generate a compensation current exponentially changing to be injected into the bipolar transistor Q1 to offset the high-order non-linear term of V N11 . The current of the PMOS transistor M BE -PMOS transistor M P5 / NMOS transistor M P6 -NMOS transistor M N9 is adjusted by the current mirror, and a linearized V N11 voltage is output to the V BE node.

[0040] The output voltage generation circuit includes PMOS transistors M N , M P9 , M P10 , M P11 , M P12 , M P13 , NMOS transistors M N12 , M N13 , M N14 , M N15 , M N16 , M N17 , resistors R TRIM , R2 and R3.

[0041] The source of the PMOS transistor M P9 is connected to the power supply, and the drain of the PMOS transistor M P9 is connected to the ground in sequence through resistors R TRIM , R2 and R3 to form VX node and V P node;

[0042] PMOS transistor M P10 source connected to a power supply, PMOS transistor M P10 drain connected to NMOS transistor M N16 drain, PMOS transistor M P10 gate connected to a bias voltage V b ;

[0043] PMOS transistor M P11 source connected to a power supply, PMOS transistor M P11 drain connected to NMOS transistor M N17 drain, PMOS transistor M P11 gate connected to the drain;

[0044] PMOS transistor M P12 source connected to V P node, PMOS transistor M P12 drain connected to NMOS transistor M N12 drain;

[0045] PMOS transistor M P13 source connected to V P node, PMOS transistor M P13 drain connected to NMOS transistor M N13 drain, PMOS transistor M P13 gate connected to V P node;

[0046] NMOS transistor M N12 and NMOS transistor M N13 source connected to ground, NMOS transistor M N12 and NMOS transistor M N13 drain connected to the drain of PMOS transistor M P12 and PMOS transistor M P13 respectively;

[0047] NMOS transistor M N14 and NMOS transistor M N15 constitute a current mirror, NMOS transistor M N14 and NMOS transistor M N15 source connected to ground, NMOS transistor M N14 and NMOS transistor M N15 drain connected to the drain of NMOS transistor M N12 and NMOS transistor M N13 respectively;

[0048] NMOS transistor M N16 source connected to PMOS transistor M P10the drain of the NMOS transistor M N16 the drain of the NMOS transistor M out ;

[0049] the source of the NMOS transistor M N17 the drain of the PMOS transistor M P11 the drain of the NMOS transistor M N17 the drain of the PMOS transistor M P13 the drain of the PMOS transistor M

[0050] the power supply in the output voltage generation circuit passes through the PMOS transistor M P9 and a series resistor R TRIM , the resistor R2 and the resistor R3 divide a bias voltage V b to control the PMOS transistor M P10 current, in combination with V BE compensation current, under the action of multiple feedback loops, adjust the current and voltage of each node, generate a stable output reference voltage V N16 at the drain of the NMOS transistor M out , and pass through R TRIM to preliminarily coarsely adjust the output reference voltage V out .

[0051] The working process of the output voltage generation circuit is as follows: the resistor R TRIM , the resistor R2 and the resistor R3 constitute a resistor voltage dividing network to generate a temperature-dependent voltage, the PMOS transistor M P10 -PMOS transistor M P11 and the NMOS transistor M N16 -NMOS transistor M N17 constitute a differential pair, superimpose the PTAT (proportional to absolute temperature) voltage and the linearized V N node voltage V BE , pass through the NMOS transistor M N14 -NMOS transistor M N15 current mirror feedback adjustment, output a stable V N16 at the drain of the NMOS transistor M out , and R TRIM is used to coarsely adjust the value of V out .

[0052] Due to process deviation and other factors in the integrated circuit manufacturing process, even after the previous compensation and adjustment, the temperature drift coefficients of the reference voltages of different chips may still differ. The temperature drift coefficient trimming circuit adjusts the resistance voltage dividing ratio inside the circuit through an external control signal, finely adjusts the temperature drift coefficient of the output voltage, makes the reference voltage temperature drift characteristics of different chips as consistent as possible, and meets the requirements of chip consistency in high-precision application scenarios.

[0053] Therefore, the embodiment also includes a temperature drift coefficient trimming circuit for adjusting the internal resistance voltage division ratio of the circuit to finely adjust the temperature drift coefficient of the output voltage; the temperature drift coefficient trimming circuit includes switches S0, S1, S2, R TRIM1 , R TRIM2 , and R TRIM3 ; R TRIM1 , R TRIM2 , and R TRIM3 are connected in series, the lower end of R TRIM1 is connected to a V X node, and the upper end of R TRIM1 is connected to R TRIM2 , R TRIM3 in turn and then connected to a reference voltage V out , S0 is connected in parallel to R TRIM1 , S1 is connected in parallel to R TRIM2 , and S2 is connected in parallel to R TRIM3 .

[0054] The temperature drift coefficient trimming circuit controls the conduction or turn-off of S0, S1, and S2 through a digital control signal, changes the total resistance value and voltage division ratio between the V X node and the reference voltage V out , and adjusts the temperature drift coefficient of the output voltage. For example, when S0 is turned on, R TRIM1 is short-circuited, the total resistance value is reduced, and the voltage division ratio is changed, thereby adjusting the rate of change of the output voltage with temperature, i.e., the temperature drift coefficient. By reasonably setting the switch combination, the temperature drift coefficient can be accurately trimmed for different process deviations of chips, and the consistency and stability of the output reference voltage of the chip in the full temperature range can be improved.

[0055] The front end of the V BE nonlinear term compensation circuit is sequentially provided from front to back with a left start-up circuit, a bias circuit, and a right start-up circuit, the left start-up circuit is used to provide an initial signal for the bias circuit and subsequent circuits when the circuit is powered on, the bias circuit is used to provide a stable direct current bias voltage and current, such as a bias voltage V b , for other active devices in the circuit, and the right start-up circuit is used to provide a start-up signal for the V BE nonlinear term compensation circuit and subsequent circuits in the initial stage of circuit start-up.

[0056] The left start-up circuit includes NMOS tubes M N1 , M N2 , and a capacitor C0; the bias circuit includes NMOS tubes M N3 , M N4 , M N5 , M N6 , PMOS tubes M P1 , M P2 , M P3 , and MP4 and resistor R1; the right start-up circuit comprises NMOS transistor M N7 , NMOS transistor M N2 and capacitor C1;

[0057] One end of capacitor CO is connected to the power supply, and the other end of capacitor CO is connected to the gate of NMOS transistor M N2 The source of NMOS transistor M N1 is connected to the ground, and the drain of NMOS transistor M N1 is connected to the source of NMOS transistor M N2 The drain of NMOS transistor M N2 is connected to the gate of PMOS transistor M P1 When the power supply is powered on, capacitor CO couples a high level to the gate of NMOS transistor M N2 to activate the bias circuit.

[0058] One end of resistor R1 is connected to the power supply, and the other end of resistor R1 is connected to the drain of PMOS transistor M P1 The drain of PMOS transistor M P3 is connected to the drain of PMOS transistor M P1 The source of PMOS transistor M P1 is connected to the power supply, and the drain of PMOS transistor M P3 is connected to resistor R1 and PMOS transistor M P1 The source of PMOS transistor M P1 is connected to the drain of NMOS transistor M N6 The drain of PMOS transistor M P1 is short-circuited between the gate and the drain of PMOS transistor M P3 The source of PMOS transistor M N3 is connected to the drain of NMOS transistor M P3 The gate of PMOS transistor M b is connected to bias voltage V P4 , and the source of PMOS transistor M P4 is connected to the drain of NMOS transistor M N5 The drain of PMOS transistor M P4 is connected to bias voltage V b , and the source of NMOS transistor M N3 is connected to the ground, and the drain of NMOS transistor M N3 is connected to the source of PMOS transistor M P3 The source of NMOS transistor M N4 and the source of NMOS transistor M N5 are connected to the ground, and the drain of NMOS transistor M N4 is connected to the source of PMOS transistor M N3 The gate of NMOS transistor M N5 is connected to the drain of PMOS transistor M P4 The drain of NMOS transistor M N6source of NMOS M N6 drain of PMOS M P2 drain of NMOS M

[0059] one end of capacitor C1 is connected to power supply, the other end of capacitor C1 is connected to gate of NMOS M N8 gate of NMOS M N7 source of NMOS M N7 drain of NMOS M N8 source of NMOS M N8 drain of NMOS M BE I CP node of non-linear compensation circuit. The signal is coupled to I CP node through capacitor C1, which ensures the compensation circuit to be out of zero current state. At the moment of power-up, the power supply charges the gate of NMOS M N8 through capacitor C1, which makes NMOS M N8 conduct, and then NMOS M N7 conducts as well, forming an initial current path, which can trigger the follow-up circuit to start working. As the circuit works normally, capacitor C1 is gradually charged to a stable voltage, which makes NMOS M N8 tend to be cut off, and the right start-up circuit exits work, avoiding continuous power consumption or interfering with the normal working current path.

[0060] The above merely describes the preferred embodiments of the present application, but the protection scope of the present application is not limited to this. Any changes or replacements within the technical scope disclosed by the present application can be easily thought by those skilled in the art, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A low-power, low-temperature-drift bandgap reference voltage source, characterized in that: Including V BE The nonlinear term compensation circuit and the output voltage generation circuit, wherein V BE The nonlinearity compensation circuit, through the cooperation of a MOSFET current mirror and a bipolar transistor, compensates for the nonlinear temperature drift of the output voltage, generating a linearized Vo. BE The output voltage generation circuit generates a voltage proportional to absolute temperature via a differential pair structure and then compares it with a linearized V. BE The voltages are superimposed to output a reference voltage.

2. The low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: The V BE The nonlinear term compensation circuit includes a PMOS transistor M P5 PMOS transistor M P6 PMOS transistor M P8 NMOS transistor M N9 NMOS transistor M N10 NMOS transistor M N11 and bipolar transistor Q1; the PMOS transistor M P5 PMOS transistor M P6 The source of the PMOS transistor is connected to the power supply. P5 and PMOS transistor M P6 The drains of the two transistors are connected to the NMOS transistor M. N9 and NMOS transistor M N11 The drain of the NMOS transistor forms a current mirror, and the drain of the NMOS transistor M... N9 The source of the NMOS transistor is grounded. N9 The drain of the PMOS transistor M P5 The drain of the NMOS transistor M N9 The gate is connected to the internal node of the compensation circuit, and the NMOS transistor M N10 The source is grounded, and the NMOS transistor M N10 The drain of the NMOS transistor is connected to the emitter of the bipolar transistor Q1. N10 Gate connection of NMOS transistor M N11 The drain of the NMOS transistor M N11 The source of the NMOS transistor is grounded. N11 The drain of the PMOS transistor M P6 The drain of the bipolar transistor Q1 is connected to ground, the collector of the bipolar transistor Q1 is grounded, and the base of the bipolar transistor Q1 is connected to V. N node.

3. The low-power, low-temperature drift bandgap reference voltage source as described in claim 2, characterized in that: The V BE The nonlinear term compensation circuit is based on the V of the bipolar transistor Q1. BE Temperature characteristics, combined with current mirroring, indicate that when the temperature changes, the V of the bipolar transistor Q1... BE Changes cause NMOS transistor M N10 The gate voltage changes, and the relevant NMOS transistor M is adjusted via current mirroring. N9 NMOS transistor M N10 and NMOS transistor M N11 The current, wherein the NMOS transistor M operates in the subthreshold region N10 and NMOS transistor M N11 The transistors are stacked and output a compensation current that is exponentially related to temperature to compensate V of the bipolar transistor Q1. BE Temperature drift caused by nonlinear terms.

4. The low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: The output voltage generation circuit includes a PMOS transistor M P9 PMOS transistor M P10 PMOS transistor M P11 PMOS transistor M P12 PMOS transistor M P13 NMOS transistor M N12 NMOS transistor M N13 NMOS transistor M N14 NMOS transistor M N15 NMOS transistor M N16 NMOS transistor M N17 Resistance R TRIM Resistors R2 and R3; The PMOS transistor M P9 The source of the PMOS transistor is connected to the power supply. P9 The drain is connected in series with resistor R. TRIM Resistors R2 and R3 are grounded to form V X Nodes and V P node; The PMOS transistor M P10 The source of the PMOS transistor is connected to the power supply. P10 The drain of the NMOS transistor M N16 The drain of the PMOS transistor M P10 Gate bias voltage V b ; The PMOS transistor M P11 The source of the PMOS transistor is connected to the power supply. P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P11 The gate and drain are shorted together; The PMOS transistor M P12 The source terminal V P Node, the PMOS transistor M P12 The drain of the NMOS transistor M N12 The drain electrode; The PMOS transistor M P13 The source terminal V P Node, the PMOS transistor M P13 The drain of the NMOS transistor M N13 The drain of the PMOS transistor M P13 gate connected to V P node; The NMOS transistor M N12 and NMOS transistor M N13 The source of the NMOS transistor is grounded. N12 and NMOS transistor M N13 The drains of the PMOS transistors M and M are connected respectively. P12 and PMOS transistor M P13 The drain electrode; The NMOS transistor M N14 and NMOS transistor M N15 Forming a current mirror, the NMOS transistor M N14 and NMOS transistor M N15 The source of the NMOS transistor is grounded. N14 and NMOS transistor M N15 The drains of the two transistors are connected to the NMOS transistor M. N12 and NMOS transistor M N13 The gate; The NMOS transistor M N16 The source of the PMOS transistor M P10 The drain of the NMOS transistor M N16 The drain is connected to the reference voltage V. out ; The NMOS transistor M N17 The source of the PMOS transistor M P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P13 The drain electrode.

5. A low-power, low-temperature drift bandgap reference voltage source as described in claim 4, characterized in that: In the output voltage generation circuit, the power supply is transmitted through the PMOS transistor M. P9 and series resistor R TRIM The bias voltage V is a voltage divider formed by resistors R2 and R3. b Control the PMOS transistor M P10 Current, combined with V BE Compensation current, adjusting the current and voltage of each node under the action of multiple feedback loops, in NMOS transistor M N16 The drain generates a stable output reference voltage V. out and through the R TRIM For the output reference voltage V out Preliminary rough adjustment.

6. A low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: It also includes a temperature drift coefficient adjustment circuit for adjusting the internal resistor voltage division ratio and finely adjusting the output voltage temperature drift coefficient; the temperature drift coefficient adjustment circuit includes switches S0, S1, S2, and R. TRIM1 R TRIM2 and R TRIM3 The R TRIM1 R TRIM2 and R TRIM3 In series, the R TRIM1 The lower end is connected to V X Node, the R TRIM1 R is connected in series at the top end. TRIM2 R TRIM3 Followed by reference voltage V out The S0 parallel R TRIM1 The S1 parallel R TRIM2 The S2 parallel R TRIM3 .

7. A low-power, low-temperature drift bandgap reference voltage source as described in claim 6, characterized in that: The temperature drift coefficient adjustment circuit controls the conduction or cutoff of S0, S1, and S2 via digital control signals, thereby changing V. X Node and reference voltage V out Adjust the total resistance and voltage division ratio to control the output voltage temperature drift coefficient.

8. A low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: The V BE The nonlinear term compensation circuit has a left start-up circuit, a bias circuit, and a right start-up circuit arranged sequentially from front to back at its front end. The left start-up circuit provides an initial signal to the bias circuit and subsequent circuits when the circuit is powered on. The bias circuit provides a stable DC bias voltage and current to other active devices in the circuit. The right start-up circuit provides the V signal to the bias circuit and subsequent circuits during the initial startup of the circuit. BE The nonlinear term compensation circuit and subsequent circuits provide the start signal.

9. A low-power, low-temperature drift bandgap reference voltage source as described in claim 8, characterized in that: The left start-up circuit includes an NMOS transistor M. N1 NMOS transistor M N2 and capacitor C0; the bias circuit includes NMOS transistor M N3 NMOS transistor M N4 NMOS transistor M N5 NMOS transistor M N6 PMOS transistor M P1 PMOS transistor M P2 PMOS transistor M P3 PMOS transistor M P4 and resistor R1; the right startup circuit includes NMOS transistor M N7 NMOS transistor M N2 and capacitor C1; One end of capacitor C0 is connected to the power supply, and the other end of capacitor C0 is connected to NMOS transistor M. N2 The gate of the NMOS transistor M N1 The source of the NMOS transistor is grounded. N1 The drain of the NMOS transistor M N2 The source of the NMOS transistor M N2 The drain of the PMOS transistor M P1 The gate; One end of resistor R1 is connected to the power supply, and the other end of resistor R1 is connected to PMOS transistor M. P1 The drain of the PMOS transistor M P3 The drain of the PMOS transistor M P1 The source of the PMOS transistor is connected to the power supply. P1 The drain resistor R1 and the PMOS transistor M P3 Drain; the PMOS transistor M P1 The source of the PMOS transistor is connected to the power supply. P1 The drain of the NMOS transistor M N6 The drain of the PMOS transistor M P1 The gate and drain of the PMOS transistor M are shorted together. P3 The source of the NMOS transistor M N3 The drain of the PMOS transistor M P3 Gate bias voltage V b The PMOS transistor M P4 The source of the PMOS transistor is connected to the power supply. P4 The drain of the NMOS transistor M N5 The drain of the PMOS transistor M P4 Gate bias voltage V b The NMOS transistor M N3 The source of the NMOS transistor is grounded. N3 The drain of the PMOS transistor M P3 The source of the NMOS transistor M N4 and NMOS transistor M N5 The source of the NMOS transistor is grounded. N4 The drain of the NMOS transistor M N3 The gate of the NMOS transistor M N5 The drain of the PMOS transistor M P4 The drain of the NMOS transistor M N6 The source of the NMOS transistor is grounded. N6 The drain of the PMOS transistor M P2 The drain electrode; One end of capacitor C1 is connected to the power supply, and the other end of capacitor C1 is connected to NMOS transistor M. N8 The gate of the NMOS transistor M N7 The source of the NMOS transistor is grounded. N7 The drain of the NMOS transistor M N8 The source of the NMOS transistor M N8 The drain is connected to the V BE I of the nonlinear term compensation circuit CP node.

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