A low-power low-temperature-drift bandgap reference voltage source

Abstract

The application discloses a low-power-consumption low-temperature-drift band gap reference voltage source BE , comprising V BE , a nonlinear term compensation circuit and an output voltage generation circuit BE . The nonlinear term compensation circuit is matched with a bipolar transistor through a MOS tube current mirror to compensate for the nonlinear temperature drift of an output voltage and generate a linearized V BE . The output voltage generation circuit generates a voltage proportional to absolute temperature through a differential pair structure and superimposes the voltage with the linearized V BE . The application provides a low-power-consumption low-temperature-drift band gap reference voltage source, which compensates for temperature drift through the nonlinear term compensation circuit, generates a preliminary stable reference voltage through the output voltage generation circuit, finely adjusts the temperature drift coefficient through the temperature drift coefficient trimming circuit and finally outputs a reference voltage with high precision, low temperature drift and good consistency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a low-power, low-temperature drift bandgap reference voltage source. Background Technology

[0002] In integrated circuit design, reference voltage sources are a core component of many electronic systems, widely used in medical devices, automotive electronics, and communication systems. These applications have extremely high requirements for the accuracy and stability of the reference voltage, especially in environments with large temperature variations, where temperature drift of the reference voltage can severely affect the performance of the entire system.

[0003] Traditional reference voltage generation circuits often suffer from problems such as large temperature drift and insufficient accuracy. On one hand, the base-emitter voltage V of the transistor... BE The non-linear temperature characteristics can cause non-linear temperature drift in the reference voltage; on the other hand, process deviations in the integrated circuit manufacturing process can cause significant differences in the reference voltage characteristics between different chips, making it difficult to meet the chip consistency requirements of high-precision application scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a low-power, low-temperature drift bandgap reference voltage source to solve the above-mentioned problems.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A low-power, low-temperature-drift bandgap reference voltage source, including V BE The nonlinear term compensation circuit and the output voltage generation circuit, wherein V BE The nonlinearity compensation circuit, through the cooperation of a MOSFET current mirror and a bipolar transistor, compensates for the nonlinear temperature drift of the output voltage, generating a linearized Vo. BE The output voltage generation circuit generates a voltage proportional to absolute temperature via a differential pair structure and then compares it with a linearized V. BE The voltages are superimposed to output a reference voltage.

[0007] Preferably, the V BE The nonlinear term compensation circuit includes a PMOS transistor M P5 PMOS transistor M P6 PMOS transistor M P8 NMOS transistor M N9 NMOS transistor M N10 NMOS transistor M N11 and bipolar transistor Q1; the PMOS transistor M P5 PMOS transistor M P6 The source of the PMOS transistor is connected to the power supply. P5 and PMOS transistor MP6 The drains of the two transistors are connected to the NMOS transistor M. N9 and NMOS transistor M N11 The drain of the NMOS transistor forms a current mirror, and the drain of the NMOS transistor M... N9 The source of the NMOS transistor is grounded. N9 The drain of the PMOS transistor M P5 The drain of the NMOS transistor M N9 The gate is connected to the internal node of the compensation circuit, and the NMOS transistor M N10 The source is grounded, and the NMOS transistor M N10 The drain of the NMOS transistor is connected to the emitter of the bipolar transistor Q1. N10 Gate connection of NMOS transistor M N11 The drain of the NMOS transistor M N11 The source of the NMOS transistor is grounded. N11 The drain of the PMOS transistor M P6 The drain of the bipolar transistor Q1 is connected to ground, the collector of the bipolar transistor Q1 is grounded, and the base of the bipolar transistor Q1 is connected to V. N node.

[0008] Preferably, the V BE The nonlinear term compensation circuit is based on the V of the bipolar transistor Q1. BE Temperature characteristics, combined with current mirroring, indicate that the V of the bipolar transistor Q1 changes with temperature. BE Changes cause NMOS transistor M N10 The gate voltage changes, and the relevant NMOS transistor M is adjusted via current mirroring. N9 NMOS transistor M N10 and NMOS transistor M N11 The current, wherein the NMOS transistor M operates in the subthreshold region N10 and NMOS transistor M N11 The transistors are stacked and a compensation current that is exponentially related to temperature is output to the bipolar transistor Q1 to compensate for V. BE Temperature drift caused by nonlinear terms.

[0009] Preferably, the output voltage generation circuit includes a PMOS transistor M P9 PMOS transistor M P10 PMOS transistor M P11 PMOS transistor M P12 PMOS transistor M P13 NMOS transistor M N12 NMOS transistor M N13 NMOS transistor M N14 NMOS transistor M N15 NMOS transistor M N16 NMOS transistor MN17 Resistance R TRIM Resistors R2 and R3;

[0010] The PMOS transistor M P9 The source of the PMOS transistor is connected to the power supply. P9 The drain is connected in series with resistor R. TRIM Resistors R2 and R3 are grounded to form V X Nodes and V P node;

[0011] The PMOS transistor M P10 The source of the PMOS transistor is connected to the power supply. P10 The drain of the NMOS transistor M N16 The drain of the PMOS transistor M P10 Gate bias voltage V b ;

[0012] The PMOS transistor M P11 The source of the PMOS transistor is connected to the power supply. P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P11 The gate and drain are shorted together;

[0013] The PMOS transistor M P12 The source terminal V P Node, the PMOS transistor M P12 The drain of the NMOS transistor M N12 The drain electrode;

[0014] The PMOS transistor M P13 The source terminal V P Node, the PMOS transistor M P13 The drain of the NMOS transistor M N13 The drain of the PMOS transistor M P13 gate connected to V P node;

[0015] The NMOS transistor M N12 and NMOS transistor M N13 The source of the NMOS transistor is grounded. N12 and NMOS transistor M N13 The drains of the PMOS transistors M and M are connected respectively. P12 and PMOS transistor M P13 The drain electrode;

[0016] The NMOS transistor M N14 and NMOS transistor M N15 Forming a current mirror, the NMOS transistor M N14and NMOS transistor M N15 The source of the NMOS transistor is grounded. N14 and NMOS transistor M N15 The drains of the two transistors are connected to the NMOS transistor M. N12 and NMOS transistor M N13 The gate;

[0017] The NMOS transistor M N16 The source of the PMOS transistor M P10 The drain of the NMOS transistor M N16 The drain is connected to the reference voltage V. out ;

[0018] The NMOS transistor M N17 The source of the PMOS transistor M P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P13 The drain electrode.

[0019] Preferably, in the output voltage generation circuit, the power supply passes through the PMOS transistor M. P9 and series resistor R TRIM The bias voltage V is a voltage divider formed by resistors R2 and R3. b Control the PMOS transistor M P10 Current, combined with V BE Compensation current, adjusting the current and voltage of each node under the action of multiple feedback loops, in NMOS transistor M N16 The drain generates a stable output reference voltage V. out and through the R TRIM For the output reference voltage V out Preliminary rough adjustment.

[0020] Preferably, it also includes a temperature drift coefficient adjustment circuit for adjusting the internal resistor voltage division ratio and finely adjusting the output voltage temperature drift coefficient; the temperature drift coefficient adjustment circuit includes switches S0, S1, S2, and R. TRIM1 R TRIM2 and R TRIM3 The R TRIM1 R TRIM2 and R TRIM3 In series, the R TRIM1 The lower end is connected to V X Node, the R TRIM1 R is connected in series at the top end. TRIM2 R TRIM3 Followed by reference voltage V out The S0 parallel R TRIM1 The S1 parallel R TRIM2 The S2 parallel R TRIM3 .

[0021] Preferably, the temperature drift coefficient adjustment circuit controls the conduction or cutoff of S0, S1, and S2 via digital control signals to change V. X Node and reference voltage V out Adjust the total resistance and voltage division ratio to control the output voltage temperature drift coefficient.

[0022] Preferably, the V BE The nonlinear term compensation circuit has a left start-up circuit, a bias circuit, and a right start-up circuit arranged sequentially from front to back at its front end. The left start-up circuit provides an initial signal to the bias circuit and subsequent circuits when the circuit is powered on. The bias circuit provides a stable DC bias voltage and current to other active devices in the circuit. The right start-up circuit provides the V signal to the bias circuit and subsequent circuits during the initial startup of the circuit. BE The nonlinear term compensation circuit and subsequent circuits provide the start signal.

[0023] Preferably, the left start-up circuit includes an NMOS transistor M. N1 NMOS transistor M N2 and capacitor C0; the bias circuit includes NMOS transistor M N3 NMOS transistor M N4 NMOS transistor M N5 NMOS transistor M N6 PMOS transistor M P1 PMOS transistor M P2 PMOS transistor M P3 PMOS transistor M P4 and resistor R1; the right startup circuit includes NMOS transistor M N7 NMOS transistor M N2 and capacitor C1;

[0024] One end of capacitor C0 is connected to the power supply, and the other end of capacitor C0 is connected to NMOS transistor M. N2 The gate of the NMOS transistor M N1 The source of the NMOS transistor is grounded. N1 The drain of the NMOS transistor M N2 The source of the NMOS transistor M N2 The drain of the PMOS transistor M P1 The gate;

[0025] One end of resistor R1 is connected to the power supply, and the other end of resistor R1 is connected to PMOS transistor M. P1 The drain of the PMOS transistor M P3 The drain of the PMOS transistor M P1 The source of the PMOS transistor is connected to the power supply. P1 The drain resistor R1 and the PMOS transistor MP3 Drain; the PMOS transistor M P1 The source of the PMOS transistor is connected to the power supply. P1 The drain of the NMOS transistor M N6 The drain of the PMOS transistor M P1 The gate and drain of the PMOS transistor M are shorted together. P3 The source of the NMOS transistor M N3 The drain of the PMOS transistor M P3 Gate bias voltage V b The PMOS transistor M P4 The source of the PMOS transistor is connected to the power supply. P4 The drain of the NMOS transistor M N5 The drain of the PMOS transistor M P4 Gate bias voltage V b The NMOS transistor M N3 The source of the NMOS transistor is grounded. N3 The drain of the PMOS transistor M P3 The source of the NMOS transistor M N4 and NMOS transistor M N5 The source of the NMOS transistor is grounded. N4 The drain of the NMOS transistor M N3 The gate of the NMOS transistor M N5 The drain of the PMOS transistor M P4 The drain of the NMOS transistor M N6 The source of the NMOS transistor is grounded. N6 The drain of the PMOS transistor M P2 The drain electrode;

[0026] One end of capacitor C1 is connected to the power supply, and the other end of capacitor C1 is connected to NMOS transistor M. N8 The gate of the NMOS transistor M N7 The source of the NMOS transistor is grounded. N7 The drain of the NMOS transistor M N8 The source of the NMOS transistor M N8 The drain is connected to the V BE I of the nonlinear term compensation circuit CP node.

[0027] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0028] 1. This invention provides a low-power, low-temperature drift bandgap reference voltage source, which, through V BEThe nonlinear term compensation circuit compensates for temperature drift, the output voltage generation circuit integrates the signal to generate a preliminary stable reference voltage, and the temperature drift coefficient adjustment circuit finely adjusts the temperature drift coefficient, ultimately outputting a high-precision reference voltage with low temperature drift and good consistency.

[0029] 2. This invention provides a low-power, low-temperature-drift bandgap reference voltage source, V BE The nonlinear term compensation circuit generates a voltage proportional to absolute temperature through a differential pair structure and compares it with the linearized V. BE The voltages are superimposed to effectively cancel out the transistor base-emitter voltage V. BE The nonlinear temperature drift of the reference voltage caused by the nonlinear temperature characteristics significantly improves the temperature stability of the reference voltage, enabling it to remain stable over a wider temperature range.

[0030] 3. This invention provides a low-power, low-temperature-drift bandgap reference voltage source. The temperature drift coefficient adjustment circuit can adjust the internal resistor voltage division ratio by controlling the control signal to finely adjust the temperature drift coefficient of the output voltage in response to process deviations in integrated circuit manufacturing. This makes the temperature drift characteristics of the reference voltage as consistent as possible between different chips, thereby improving the mass production quality and application reliability of the chips. Attached Figure Description

[0031] Figure 1 This is a circuit structure diagram of the present invention;

[0032] Figure 2 V of the present invention BE Schematic diagram of the nonlinear term compensation circuit;

[0033] Figure 3 V of the present invention BE Circuit diagram of nonlinear term compensation circuit. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0035] Example

[0036] Please refer to Figures 1 to 3 As shown, this invention discloses a low-power, low-temperature-drift bandgap reference voltage source, including V BE Nonlinear term compensation circuit and output voltage generation circuit, V BE The nonlinearity compensation circuit, through the cooperation of a MOSFET current mirror and a bipolar transistor, compensates for the nonlinear temperature drift of the output voltage, generating a linearized Vo. BEThe output voltage generation circuit generates a voltage proportional to absolute temperature using a differential pair structure and then modulates it with a linearized V. BE The voltages are superimposed to output a reference voltage.

[0037] V BE The nonlinear term compensation circuit includes a PMOS transistor M P5 PMOS transistor M P6 PMOS transistor M P8 NMOS transistor M N9 NMOS transistor M N10 NMOS transistor M N11 and bipolar transistor Q1; PMOS transistor M P5 PMOS transistor M P6 The source is connected to the power supply, and the PMOS transistor M P5 and PMOS transistor M P6 The drains of the two transistors are connected to the NMOS transistor M. N9 and NMOS transistor M N11 The drain of the NMOS transistor forms a current mirror, and the drain of the NMOS transistor M... N9 The source is grounded, and the NMOS transistor M N9 The drain of the PMOS transistor M P5 The drain of the NMOS transistor M N9 The gate is connected to the internal node of the compensation circuit, and the NMOS transistor M N10 The source is grounded, and the NMOS transistor M N10 The drain of the transistor is connected to the emitter of the bipolar transistor Q1, and the NMOS transistor M... N10 Gate connection of NMOS transistor M N11 The drain of the NMOS transistor M N11 The source is grounded, and the NMOS transistor M N11 The drain of the PMOS transistor M P6 The drain of the bipolar transistor Q1 is connected to ground, the collector of the bipolar transistor Q1 is connected to ground, and the base of the bipolar transistor Q1 is connected to V. N node.

[0038] V BE The nonlinear term compensation circuit is based on the V of the bipolar transistor Q1. BE The temperature characteristics are not purely linear (V BE ≈V T lnI S / I C (Including nonlinear terms), its variation at different temperatures can cause nonlinear temperature drift in the reference voltage. This circuit, through a specific circuit structure and component combination, counteracts this nonlinear temperature drift, improving the temperature stability of the reference voltage. In this embodiment, V BE The nonlinear term compensation circuit is based on the V of the bipolar transistor Q1. BETemperature characteristics combined with current mirroring mean that when the temperature changes, the V0 of the bipolar transistor Q1... BE Changes cause NMOS transistor M N10 The gate voltage changes, and the relevant NMOS transistor M is adjusted via current mirroring. N9 NMOS transistor M N10 and NMOS transistor M N11 The current, of which the NMOS transistor M operates in the subthreshold region N10 and NMOS transistor M N11 The stacking process outputs a compensation current that is exponentially related to temperature to the bipolar transistor Q1 to compensate for V. BE Temperature drift caused by nonlinear terms.

[0039] V BE The working process of the nonlinear term compensation circuit is as follows: When the temperature rises, the V0 of the bipolar transistor Q1 (assuming it is PNP type, but it can be adjusted to NPN type according to the design) BE The drop causes the NMOS transistor M N10 Gate voltage reduction NMOS transistor M N10 and NMOS transistor M N11 Operating in the subthreshold region, an exponentially varying compensation current is injected into the bipolar transistor Q1 to offset V. BE Higher-order nonlinear terms, via PMOS transistor M P5 -PMOS transistor M P6 / NMOS transistor M N9 -NMOS transistor M N11 Current mirror adjustment, output linearization V BE Voltage to V N node.

[0040] The output voltage generation circuit includes a PMOS transistor M P9 PMOS transistor M P10 PMOS transistor M P11 PMOS transistor M P12 PMOS transistor M P13 NMOS transistor M N12 NMOS transistor M N13 NMOS transistor M N14 NMOS transistor M N15 NMOS transistor M N16 NMOS transistor M N17 Resistance R TRIM Resistors R2 and R3;

[0041] PMOS transistor M P9 The source is connected to the power supply, and the PMOS transistor M P9 The drain is connected in series with resistor R. TRIM Resistors R2 and R3 are grounded to form VX Nodes and V P node;

[0042] PMOS transistor M P10 The source is connected to the power supply, and the PMOS transistor M P10 The drain of the NMOS transistor M N16 The drain of the PMOS transistor M P10 Gate bias voltage V b ;

[0043] PMOS transistor M P11 The source is connected to the power supply, and the PMOS transistor M P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P11 The gate and drain are shorted together;

[0044] PMOS transistor M P12 The source terminal V P Node, PMOS transistor M P12 The drain of the NMOS transistor M N12 The drain electrode;

[0045] PMOS transistor M P13 The source terminal V P Node, PMOS transistor M P13 The drain of the NMOS transistor M N13 The drain of the PMOS transistor M P13 gate connected to V P node;

[0046] NMOS transistor M N12 and NMOS transistor M N13 The source is grounded, and the NMOS transistor M N12 and NMOS transistor M N13 The drains of the PMOS transistors M and M are connected respectively. P12 and PMOS transistor M P13 The drain electrode;

[0047] NMOS transistor M N14 and NMOS transistor M N15 Forming a current mirror, NMOS transistor M N14 and NMOS transistor M N15 The source is grounded, and the NMOS transistor M N14 and NMOS transistor M N15 The drains of the two transistors are connected to the NMOS transistor M. N12 and NMOS transistor M N13 The gate;

[0048] NMOS transistor M N16 The source of the PMOS transistor M P10The drain of the NMOS transistor M N16 The drain is connected to the reference voltage V. out ;

[0049] NMOS transistor M N17 The source of the PMOS transistor M P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P13 The drain electrode.

[0050] In the output voltage generation circuit, the power supply passes through the PMOS transistor M P9 and series resistor R TRIM Voltage divider formed by resistors R2 and R3, bias voltage V b Control PMOS transistor M P10 Current, combined with V BE Compensation current, adjusting the current and voltage of each node under the action of multiple feedback loops, in NMOS transistor M N16 The drain generates a stable output reference voltage V. out And through R TRIM For the output reference voltage V out Preliminary rough adjustment.

[0051] The output voltage generation circuit works as follows: resistor R TRIM Resistors R2 and R3 form a resistor voltage divider network to generate a temperature-dependent voltage. The PMOS transistor M... P10 -PMOS transistor M P11 With NMOS transistor M N16 -NMOS transistor M N17 To form a differential pair, the PTAT (Temporally Proportional to Absolute Temperature) voltage is compared with V. N Linearization of nodes V BE Superimposed, through NMOS transistor M N14 -NMOS transistor M N15 Current mirror feedback regulation, in NMOS transistor M N16 Stable drain output V out R TRIM Used for coarse adjustment of V out value.

[0052] Due to factors such as process deviations during integrated circuit manufacturing, even after the preceding compensation and adjustments, the temperature drift coefficient of the reference voltage may still differ between different chips. The temperature drift coefficient adjustment circuit uses an external control signal to adjust the voltage division ratio of the internal resistors, thereby finely adjusting the temperature drift coefficient of the output voltage to make the temperature drift characteristics of the reference voltage of different chips as consistent as possible, meeting the chip consistency requirements of high-precision applications.

[0053] Therefore, this embodiment also includes a temperature drift coefficient adjustment circuit for adjusting the internal resistor voltage division ratio and finely adjusting the output voltage temperature drift coefficient; the temperature drift coefficient adjustment circuit includes switches S0, S1, S2, and R. TRIM1 R TRIM2 and R TRIM3 ;R TRIM1 R TRIM2 and R TRIM3 Series, R TRIM1 The lower end is connected to V X Node, R TRIM1 R is connected in series at the top end. TRIM2 R TRIM3 Followed by reference voltage V out S0 parallel R TRIM1 S1 parallel R TRIM2 S2 parallel R TRIM3 .

[0054] The temperature drift coefficient adjustment circuit controls the conduction or cutoff of S0, S1, and S2 via digital control signals, thereby changing V. X Node and reference voltage V out Adjust the total resistance and voltage division ratio to control the output voltage temperature drift coefficient. For example, when S0 is on, R... TRIM1 When a circuit is short-circuited, the total resistance decreases, the voltage division ratio changes, and thus the rate of change of the output voltage with temperature is adjusted, i.e., the temperature drift coefficient. By properly setting the switch combination, the temperature drift coefficient can be precisely adjusted to address the process deviations of different chips, thereby improving the consistency and stability of the chip's output reference voltage across the entire temperature range.

[0055] V BE The nonlinear compensation circuit has a left start-up circuit, a bias circuit, and a right start-up circuit arranged sequentially from front to back. The left start-up circuit provides an initial signal to the bias circuit and subsequent circuits when the circuit is powered on. The bias circuit provides a stable DC bias voltage and current to other active devices in the circuit, such as a bias voltage V. b The right-hand start-up circuit is used for the initial stage of circuit startup at V. BE The nonlinear term compensation circuit and subsequent circuits provide the start signal.

[0056] The left startup circuit includes NMOS transistor M N1 NMOS transistor M N2 and capacitor C0; the bias circuit includes NMOS transistor M N3 NMOS transistor M N4 NMOS transistor M N5 NMOS transistor M N6 PMOS transistor M P1 PMOS transistor M P2 PMOS transistor M P3 PMOS transistor MP4 and resistor R1; the right startup circuit includes NMOS transistor M N7 NMOS transistor M N2 and capacitor C1;

[0057] One end of capacitor C0 is connected to the power supply, and the other end of capacitor C0 is connected to NMOS transistor M. N2 The gate of the NMOS transistor M N1 The source is grounded, and the NMOS transistor M N1 The drain of the NMOS transistor M N2 The source of the NMOS transistor M N2 The drain of the PMOS transistor M P1 The gate of the NMOS transistor; when the power supply is on, capacitor C0 couples a high level to the NMOS transistor M. N2 The gate activates the bias circuit.

[0058] One end of resistor R1 is connected to the power supply, and the other end of resistor R1 is connected to PMOS transistor M. P1 The drain of the PMOS transistor M P3 The drain of the PMOS transistor M P1 The source is connected to the power supply, and the PMOS transistor M P1 The drain resistor R1 and the PMOS transistor M P3 Drain; PMOS transistor M P1 The source is connected to the power supply, and the PMOS transistor M P1 The drain of the NMOS transistor M N6 The drain of the PMOS transistor M P1 The gate and drain of the PMOS transistor are shorted together. P3 The source of the NMOS transistor M N3 The drain of the PMOS transistor M P3 Gate bias voltage V b PMOS transistor M P4 The source is connected to the power supply, and the PMOS transistor M P4 The drain of the NMOS transistor M N5 The drain of the PMOS transistor M P4 Gate bias voltage V b NMOS transistor M N3 The source is grounded, and the NMOS transistor M N3 The drain of the PMOS transistor M P3 The source of the NMOS transistor M N4 and NMOS transistor M N5 The source is grounded, and the NMOS transistor M N4 The drain of the NMOS transistor M N3 The gate of the NMOS transistor M N5 The drain of the PMOS transistor M P4 The drain of the NMOS transistor M N6The source is grounded, and the NMOS transistor M N6 The drain of the PMOS transistor M P2 The drain electrode;

[0059] One end of capacitor C1 is connected to the power supply, and the other end of capacitor C1 is connected to NMOS transistor M. N8 The gate of the NMOS transistor M N7 The source is grounded, and the NMOS transistor M N7 The drain of the NMOS transistor M N8 The source of the NMOS transistor M N8 The drain is connected to V BE I of the nonlinear term compensation circuit CP Node. The signal is coupled to I through capacitor C1. CP The node ensures the compensation circuit is out of the zero-current state. At power-on, the power supply flows through capacitor C1 to the NMOS transistor M. N8 The gate of the NMOS transistor M is charged, causing the gate of the NMOS transistor M to be charged. N8 Turn on, and thus the NMOS transistor M N7 It also conducts, forming an initial current path, which can trigger subsequent circuits to start working. As the circuit operates normally, capacitor C1 gradually charges to a stable voltage, causing NMOS transistor M to conduct. N8 As the circuit approaches cutoff, the right-hand start-up circuit ceases operation to avoid continuous power consumption or interference with the normal operating current path.

[0060] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-power, low-temperature-drift bandgap reference voltage source, characterized in that: Including V BE The nonlinear term compensation circuit and the output voltage generation circuit, wherein V BE The nonlinearity compensation circuit, through the cooperation of a MOSFET current mirror and a bipolar transistor, compensates for the nonlinear temperature drift of the output voltage, generating a linearized Vo. BE The output voltage generation circuit generates a voltage proportional to absolute temperature via a differential pair structure and then compares it with a linearized V. BE The voltages are superimposed to output a reference voltage; it also includes a temperature drift coefficient adjustment circuit to adjust the internal resistor voltage division ratio and finely adjust the output voltage temperature drift coefficient; the temperature drift coefficient adjustment circuit includes switches S0, S1, S2, and R. TRIM1 R TRIM2 and R TRIM3 The R TRIM1 R TRIM2 and R TRIM3 In series, the R TRIM1 The lower end is connected to V X Node, the R TRIM1 R is connected in series at the top end. TRIM2 R TRIM3 Followed by reference voltage V out The S0 parallel R TRIM1 The S1 parallel R TRIM2 The S2 parallel R TRIM3 .

2. The low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: The V BE The nonlinear term compensation circuit includes a PMOS transistor M P5 PMOS transistor M P6 PMOS transistor M P8 NMOS transistor M N9 NMOS transistor M N10 NMOS transistor M N11 and bipolar transistor Q1; the PMOS transistor M P5 PMOS transistor M P6 The source of the PMOS transistor is connected to the power supply. P5 and PMOS transistor M P6 The drains of the two transistors are connected to the NMOS transistor M. N9 and NMOS transistor M N11 The drain of the NMOS transistor forms a current mirror, and the drain of the NMOS transistor M... N9 The source of the NMOS transistor is grounded. N9 The drain of the PMOS transistor M P5 The drain of the NMOS transistor M N9 The gate is connected to the internal node of the compensation circuit, and the NMOS transistor M N10 The source is grounded, and the NMOS transistor M N10 The drain of the NMOS transistor is connected to the emitter of the bipolar transistor Q1. N10 Gate connection of NMOS transistor M N11 The drain of the NMOS transistor M N11 The source of the NMOS transistor is grounded. N11 The drain of the PMOS transistor M P6 The drain of the bipolar transistor Q1 is connected to ground, the collector of the bipolar transistor Q1 is grounded, and the base of the bipolar transistor Q1 is connected to V. N node.

3. The low-power, low-temperature drift bandgap reference voltage source as described in claim 2, characterized in that: The V BE The nonlinear term compensation circuit is based on the V of the bipolar transistor Q1. BE Temperature characteristics, combined with current mirroring, indicate that the V of the bipolar transistor Q1 changes with temperature. BE Changes cause NMOS transistor M N10 The gate voltage changes, and the relevant NMOS transistor M is adjusted via current mirroring. N9 NMOS transistor M N10 and NMOS transistor M N11 The current, wherein the NMOS transistor M operates in the subthreshold region N10 and NMOS transistor M N11 The transistors are stacked and a compensation current that is exponentially related to temperature is output to the bipolar transistor Q1 to compensate for V. BE Temperature drift caused by nonlinear terms.

4. The low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: The output voltage generation circuit includes a PMOS transistor M P9 PMOS transistor M P10 PMOS transistor M P11 PMOS transistor M P12 PMOS transistor M P13 NMOS transistor M N12 NMOS transistor M N13 NMOS transistor M N14 NMOS transistor M N15 NMOS transistor M N16 NMOS transistor M N17 Resistance R TRIM Resistors R2 and R3; The PMOS transistor M P9 The source of the PMOS transistor is connected to the power supply. P9 The drain is connected in series with resistor R. TRIM Resistors R2 and R3 are grounded to form V X Nodes and V P node; The PMOS transistor M P10 The source of the PMOS transistor is connected to the power supply. P10 The drain of the NMOS transistor M N16 The drain of the PMOS transistor M P10 Gate bias voltage V b ; The PMOS transistor M P11 The source of the PMOS transistor is connected to the power supply. P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P11 The gate and drain are shorted together; The PMOS transistor M P12 The source terminal V P Node, the PMOS transistor M P12 The drain of the NMOS transistor M N12 The drain electrode; The PMOS transistor M P13 The source terminal V P Node, the PMOS transistor M P13 The drain of the NMOS transistor M N13 The drain of the PMOS transistor M P13 gate connected to V P node; The NMOS transistor M N12 and NMOS transistor M N13 The source of the NMOS transistor is grounded. N12 and NMOS transistor M N13 The drains of the PMOS transistors M and M are connected respectively. P12 and PMOS transistor M P13 The drain electrode; The NMOS transistor M N14 and NMOS transistor M N15 Forming a current mirror, the NMOS transistor M N14 and NMOS transistor M N15 The source of the NMOS transistor is grounded. N14 and NMOS transistor M N15 The drains of the two transistors are connected to the NMOS transistor M. N12 and NMOS transistor M N13 The gate; The NMOS transistor M N16 The source of the PMOS transistor M P10 The drain of the NMOS transistor M N16 The drain is connected to the reference voltage V. out ; The NMOS transistor M N17 The source of the PMOS transistor M P11 The drain of the NMOS transistor M N17 The drain of the PMOS transistor M P13 The drain electrode.

5. A low-power, low-temperature drift bandgap reference voltage source as described in claim 4, characterized in that: In the output voltage generation circuit, the power supply is transmitted through the PMOS transistor M. P9 and series resistor R TRIM The bias voltage V is a voltage divider formed by resistors R2 and R3. b Control the PMOS transistor M P10 Current, combined with V BE Compensation current, adjusting the current and voltage of each node under the action of multiple feedback loops, in NMOS transistor M N16 The drain generates a stable output reference voltage V. out and through the R TRIM For the output reference voltage V out Preliminary rough adjustment.

6. The low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: The temperature drift coefficient adjustment circuit controls the conduction or cutoff of S0, S1, and S2 via digital control signals, thereby changing V. X Node and reference voltage V out Adjust the total resistance and voltage division ratio to control the output voltage temperature drift coefficient.

7. A low-power, low-temperature drift bandgap reference voltage source as described in claim 1, characterized in that: The V BE The nonlinear term compensation circuit has a left start-up circuit, a bias circuit, and a right start-up circuit arranged sequentially from front to back at its front end. The left start-up circuit provides an initial signal to the bias circuit and subsequent circuits when the circuit is powered on. The bias circuit provides a stable DC bias voltage and current to other active devices in the circuit. The right start-up circuit provides the V signal to the bias circuit and subsequent circuits during the initial startup of the circuit. BE The nonlinear term compensation circuit and subsequent circuits provide the start signal.

8. A low-power, low-temperature drift bandgap reference voltage source as described in claim 7, characterized in that: The left start-up circuit includes an NMOS transistor M. N1 NMOS transistor M N2 and capacitor C0; the bias circuit includes NMOS transistor M N3 NMOS transistor M N4 NMOS transistor M N5 NMOS transistor M N6 PMOS transistor M P1 PMOS transistor M P2 PMOS transistor M P3 PMOS transistor M P4 and resistor R1; the right startup circuit includes NMOS transistor M N7 NMOS transistor M N2 and capacitor C1; One end of capacitor C0 is connected to the power supply, and the other end of capacitor C0 is connected to NMOS transistor M. N2 The gate of the NMOS transistor M N1 The source of the NMOS transistor is grounded. N1 The drain of the NMOS transistor M N2 The source of the NMOS transistor M N2 The drain of the PMOS transistor M P1 The gate; One end of resistor R1 is connected to the power supply, and the other end of resistor R1 is connected to PMOS transistor M. P1 The drain of the PMOS transistor M P3 The drain of the PMOS transistor M P1 The source of the PMOS transistor is connected to the power supply. P1 The drain resistor R1 and the PMOS transistor M P3 Drain; the PMOS transistor M P1 The source of the PMOS transistor is connected to the power supply. P1 The drain of the NMOS transistor M N6 The drain of the PMOS transistor M P1 The gate and drain of the PMOS transistor M are shorted together. P3 The source of the NMOS transistor M N3 The drain of the PMOS transistor M P3 Gate bias voltage V b The PMOS transistor M P4 The source of the PMOS transistor is connected to the power supply. P4 The drain of the NMOS transistor M N5 The drain of the PMOS transistor M P4 Gate bias voltage V b The NMOS transistor M N3 The source of the NMOS transistor is grounded. N3 The drain of the PMOS transistor M P3 The source of the NMOS transistor M N4 and NMOS transistor M N5 The source of the NMOS transistor is grounded. N4 The drain of the NMOS transistor M N3 The gate of the NMOS transistor M N5 The drain of the PMOS transistor M P4 The drain of the NMOS transistor M N6 The source of the NMOS transistor is grounded. N6 The drain of the PMOS transistor M P2 The drain electrode; One end of capacitor C1 is connected to the power supply, and the other end of capacitor C1 is connected to NMOS transistor M. N8 The gate of the NMOS transistor M N7 The source of the NMOS transistor is grounded. N7 The drain of the NMOS transistor M N8 The source of the NMOS transistor M N8 The drain is connected to the V BE I of the nonlinear term compensation circuit CP node.

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