Low-temperature-drift low-power-consumption band-gap reference circuit

Abstract

The invention discloses a low-temperature-drift low-power-consumption band-gap reference circuit which comprises a band-gap core circuit, a current summing circuit, an output circuit and a starting circuit. The band gap core circuit is used for generating positive temperature coefficient current and negative temperature coefficient current; the current summation circuit and the output circuit are used for adding the positive temperature coefficient current and the negative temperature coefficient current and generating a reference voltage; the starting circuit is used for driving a post-stage circuit to get rid of a degeneracy point to work in the power-on process of a power source of the band-gap reference circuit and is turned off after the band-gap reference circuit works normally. According to the invention, the temperature drift is less than or equal to 15 ppm / DEG C and the quiescent current is less than or equal to 5 [mu] A in the range of-55 DEG C to 125 DEG C, and the method is suitable for a low-power-consumption Internet of Things chip and a high-precision sensor.

Description

Technical Field

[0001] This invention belongs to the field of bandgap reference circuits, and in particular relates to a low-temperature drift and low-power bandgap reference circuit. Background Technology

[0002] As a core module of analog integrated circuits, the temperature stability of bandgap reference circuits directly determines the accuracy limits of systems such as power management, data converters, and sensors. The classic bandgap architecture based on BJTs (Bipolar Junction Transistors) has long been considered the standard for high-precision reference design due to its advantageous physical characteristics. However, with the evolution of CMOS processes towards deep submicron nodes, the limitations of traditional BJT solutions have become increasingly apparent. Therefore, how to overcome the process integration defects of BJTs while retaining their temperature characteristic advantages, and to achieve low-power, high-reliability bandgap reference circuits, has become a pressing technical challenge in this field. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a low-temperature drift, low-power bandgap reference circuit.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0005] A low-temperature drift, low-power bandgap reference circuit, comprising:

[0006] The bandgap core circuit is used to generate a positive temperature coefficient current I. PTAT and negative temperature coefficient current I CTAT ;

[0007] A current summing circuit is used to sum the positive temperature coefficient current I. PTAT and negative temperature coefficient current I CTAT The summation generates a combined voltage V' with zero temperature coefficient characteristics. REF ;

[0008] Output circuit, used to output the synthesized voltage V' REF Generate reference voltage V REF ;as well as

[0009] The startup circuit is used to drive the subsequent circuits to operate out of the degeneracy point during the power-on process of the bandgap reference circuit, and to turn off after the bandgap reference circuit is operating normally.

[0010] Furthermore, the bandgap core circuit includes

[0011] PTAT circuit, used to generate positive temperature coefficient current I PTAT ;as well as

[0012] CTAT circuit, used to generate negative temperature coefficient current I CTAT .

[0013] Furthermore, the CTAT circuit includes an operational amplifier Amp1, a PMOS transistor M1, and a resistor R4. The source of the PMOS transistor M1 is connected to an external power supply voltage VDD, the drain is grounded through the resistor R4, and the gate is connected to the output terminal of the operational amplifier Amp1. The gate of the PMOS transistor M1 is also electrically connected to its drain through a first phase margin compensation circuit.

[0014] The positive input terminal of the operational amplifier Amp1 is electrically connected to the drain of the PMOS transistor M1; the negative input terminal of the operational amplifier Amp1 is electrically connected to the PTAT circuit; and the output terminal of the operational amplifier Amp1 serves as the output terminal of the CTAT circuit for outputting the negative temperature coefficient current I. CTAT .

[0015] Furthermore, the first phase margin compensation circuit includes a resistor R1 and a capacitor C1 connected in series.

[0016] Furthermore, the PTAT circuit includes an operational amplifier Amp2, a PMOS transistor M2, a PMOS transistor M3, a transistor Q1, a transistor Q2, and a resistor R5; both transistor Q1 and transistor Q2 are bipolar transistors.

[0017] The source of the PMOS transistor M2 is connected to an external power supply voltage VDD, the drain is electrically connected to the negative input terminal of the operational amplifier Amp2, and the gate is connected to the output terminal of the operational amplifier Amp2; the gate of the PMOS transistor M2 is also electrically connected to its drain through a second phase margin compensation circuit.

[0018] The source of the PMOS transistor M3 is connected to an external power supply voltage VDD, the drain is electrically connected to the positive input terminal of the operational amplifier Amp2, and the gate is connected to the output terminal of the operational amplifier Amp2; the gate of the PMOS transistor M3 is also electrically connected to its drain through a third phase margin compensation circuit.

[0019] The output terminal of the operational amplifier Amp2 is used as the output terminal of the PTAT circuit to output the positive temperature coefficient current I. PTAT The negative input terminal of operational amplifier Amp2 is electrically connected to the negative input terminal of operational amplifier Amp1; the negative input terminal of operational amplifier Amp2 is also electrically connected to the emitter of transistor Q1; the positive input terminal of operational amplifier Amp1 is electrically connected to the emitter of transistor Q2 through resistor R5.

[0020] The base and collector of transistor Q1 and the base and collector of transistor Q2 are both grounded.

[0021] Furthermore, the second phase margin compensation circuit includes a resistor R2 and a capacitor C2 connected in series; the third phase margin compensation circuit includes a resistor R3 and a capacitor C3 connected in series.

[0022] Furthermore, the startup circuit includes a PMOS transistor M6, the gate of which is electrically connected to the startup terminal of operational amplifier Amp2, the drain of which is electrically connected to the gate of PMOS transistor M2, and the source of which is electrically connected to the negative input terminals of operational amplifiers Amp1 and Amp2.

[0023] Furthermore, the current summing circuit includes PMOS transistors M4 and M5 and resistor R6. The source of PMOS transistor M4 is externally connected to the power supply voltage VDD, and its gate is electrically connected to the bandgap core circuit for inputting the positive temperature coefficient current I. PTAT The source of the PMOS transistor M5 is externally connected to a power supply voltage VDD, and its gate is electrically connected to the bandgap core circuit for inputting a negative temperature coefficient current I. CTAT The drains of PMOS transistors M4 and M5 are both electrically connected to the first terminal of resistor R6. The first terminal of resistor R6 also serves as the output terminal of the current summing circuit for outputting the synthesized current. The second terminal of resistor R6 is grounded.

[0024] Furthermore, the resistor R6 is a polycrystalline silicon resistor with zero temperature coefficient.

[0025] Furthermore, the output circuit includes an operational amplifier Amp3, a resistor R7, and a resistor R8. The positive input terminal of the operational amplifier Amp3 is electrically connected to the first terminal of the resistor R6, the output terminal is connected to the first terminal of the resistor R8, and the negative input terminal is connected to the second terminal of the resistor R8. The second terminal of the resistor R8 is grounded through the resistor R7.

[0026] The present invention has the following beneficial effects:

[0027] 1. Innovative BJT and MOS co-designed temperature compensation architecture: While retaining the accurate temperature characteristics of BJT devices, the co-design of the current-mode structure and the MOS resistor network significantly reduces the process compatibility issues caused by the dependence on traditional BJT devices.

[0028] 2. Dynamic offset suppression technology: The current-mode feedback mechanism is adopted to convert the process deviation of BJT devices into adjustable current parameters, reducing the dependence on resistor matching accuracy.

[0029] 3. Low-power self-starting hybrid structure: The charging and discharging nodes are controlled by PMOS transistor M6, and the circuit automatically shuts off after startup, with the static current approaching zero. Attached Figure Description

[0030] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0031] Figure 1 This is a schematic diagram for generating a reference voltage.

[0032] Figure 2 This is a structural block diagram of an embodiment of the low-temperature drift, low-power bandgap reference circuit of the present invention.

[0033] Figure 3 This is a circuit diagram of an embodiment of the low-temperature drift, low-power bandgap reference circuit of the present invention.

[0034] Figure 4 This is a curve showing the output voltage of the reference circuit as a function of temperature. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0036] Please see Figure 1 The forward voltage drop V of the BJT BE The voltage decreases approximately linearly with increasing temperature (CTAT characteristic, approximately -2mV / ℃), while the base-emitter voltage difference ΔV... BE This is achieved by varying the emitter areas of the BJT pair, exhibiting a positive temperature coefficient (PTAT characteristic, approximately +0.087 mV / ℃). The PTAT voltage K1·ΔV is then transmitted through a resistor network. BE With CTAT voltage V BE Weighted superposition, with K1 as the weighting coefficient. Theoretically, a zero-temperature coefficient output voltage V can be achieved. REF =V BE +K1·ΔV BE This BJT-based temperature compensation mechanism has advantages such as a clear physical model and strong predictability of temperature coefficients, making it the preferred solution for high-precision design in industry.

[0037] Standard CMOS processes typically do not natively integrate high-performance vertical BJT devices; instead, they must be achieved through parasitic structures (such as deep N-well lateral PNP transistors). This results in significant process fluctuations in device parameters (such as saturation current IS and current gain β). For example, in a 28nm CMOS process, the β value deviation of a lateral PNP transistor can reach ±40%, directly causing PTAT current mismatch and deteriorating the measured temperature drift coefficient to over 50ppm / ℃. Furthermore, the base-emitter voltage VBJT... BEThe nonlinear temperature characteristics (higher-order terms uncompensated) introduce curvature errors in a wide temperature range (-55℃ to 125℃). Traditional first-order compensation schemes can only offset the linear terms, and the residual temperature drift is still as high as 20 to 30 ppm / ℃.

[0038] To improve compensation accuracy, advanced temperature compensation techniques have been widely explored. For example, publication JP2022101234A proposes embedding a nonlinear resistor network in the BJT branch to offset VBE curvature using the second temperature coefficient (TCR) of the polysilicon resistor. However, such solutions require precise matching of the resistor TCR with the BJT temperature characteristics. The nonlinearity of the polysilicon resistor's TCR (±200ppm / ℃) and process fluctuations (±15%) lead to poor mass production consistency, with measured temperature drift standard deviation reaching ±10ppm / ℃. Furthermore, advanced compensation circuits require additional operational amplifiers and feedback loops, increasing the quiescent current to over 150μA, severely limiting their application in low-power scenarios.

[0039] In terms of circuit reliability, BJT-based bandgap references face significant challenges. Because the core current mirror is prone to entering a degenerate state (zero-current lockout) at the initial bias point, traditional startup circuits require complex timing control logic, resulting in a startup failure rate exceeding 25% at low supply voltages (<1.5V). Furthermore, the temperature dependence of the BJT base current (IB∝T3) causes op-amp input offset voltage drift, leading to reference voltage jumps at extreme temperatures (>125℃).

[0040] While all-MOS architectures (such as subthreshold CTAT and gate bootstrap PTAT) can circumvent the process limitations of BJTs, their weak temperature coefficient dependence and nonlinear characteristics lead to insufficient compensation accuracy. For example, the Vt of a subthreshold NMOS transistor... GS The temperature coefficient (approximately -0.6 mV / ℃) is only that of a transistor. BE The process angle fluctuates by ±20%, which is 30% higher than the process angle, forcing designers to adopt multi-level amplification and dynamic adjustment, significantly increasing the design complexity.

[0041] Please see Figure 2 , Figure 2 This is a structural block diagram of an embodiment of the low-temperature drift, low-power bandgap reference circuit of the present invention. The low-temperature drift, low-power bandgap reference circuit of this embodiment includes a bandgap core circuit, a current summing circuit, an output circuit, and a startup circuit.

[0042] The bandgap core circuit is used to generate a positive temperature coefficient current I. PTAT and negative temperature coefficient current I CTAT The bandgap core circuit includes a PTAT circuit and a CTAT circuit.

[0043] Please see Figure 3 The CTAT circuit is used to generate a negative temperature coefficient current I.CTAT The CTAT circuit may include an operational amplifier Amp1, a PMOS transistor M1, and a resistor R4. The source of the PMOS transistor M1 is connected to an external power supply voltage VDD, the drain is grounded through the resistor R4, and the gate is connected to the output of the operational amplifier Amp1. The gate of the PMOS transistor M1 is also electrically connected to its drain through a first phase margin compensation circuit. The first phase margin compensation circuit includes a resistor R1 and a capacitor C1 connected in series. Specifically, the first end of the resistor R1 is electrically connected to the gate of the PMOS transistor M1, and the second end is electrically connected to the drain of the PMOS transistor M1 through the capacitor C1. The positive input terminal of the operational amplifier Amp1 is electrically connected to the drain of the PMOS transistor M1, thereby forming node A. The negative input terminal of the operational amplifier Amp1 is electrically connected to the CTAT circuit, and the output terminal of the operational amplifier Amp1 serves as the output terminal of the CTAT circuit for outputting the negative temperature coefficient current I. CTAT .

[0044] The PTAT circuit is used to generate a positive temperature coefficient current I. PTAT The PTAT circuit may include an operational amplifier Amp2, PMOS transistors M2 and M3, transistors Q1 and Q2, and a resistor R5. PMOS transistors M2 and M3 have the same width-to-length ratio, and transistors Q1 and Q2 are both bipolar junction transistors.

[0045] The source of the PMOS transistor M2 is connected to an external power supply voltage VDD, its drain is electrically connected to the negative input terminal of operational amplifier Amp2, and its gate is connected to the output terminal of operational amplifier Amp2. The gate of the PMOS transistor M2 is also electrically connected to its drain through a second phase margin compensation circuit. This second phase margin compensation circuit includes a resistor R2 and a capacitor C2 connected in series. Specifically, the first end of the resistor R2 is electrically connected to the gate of the PMOS transistor M2, and the second end is electrically connected to the drain of the PMOS transistor M2 through the capacitor C2.

[0046] The source of the PMOS transistor M3 is connected to an external power supply voltage VDD, and the drain of the PMOS transistor M3 is electrically connected to the positive input terminal of the operational amplifier Amp2, thus forming node C. The gate of the PMOS transistor M3 is connected to the output terminal of the operational amplifier Amp2; the gate of the PMOS transistor M3 is also electrically connected to its drain through a third phase margin compensation circuit. The third phase margin compensation circuit includes a resistor R3 and a capacitor C3 connected in series. Specifically, the first end of the resistor R3 is electrically connected to the gate of the PMOS transistor M3, and the second end is electrically connected to the drain of the PMOS transistor M3 through the capacitor C3.

[0047] The output terminal of the operational amplifier Amp2 is used as the output terminal of the PTAT circuit to output the positive temperature coefficient current I.PTAT The negative input terminal of operational amplifier Amp2 is electrically connected to the negative input terminal of operational amplifier Amp1, thus forming node B. The negative input terminal of operational amplifier Amp2 is also electrically connected to the emitter of transistor Q1. The positive input terminal of operational amplifier Amp1 is electrically connected to the emitter of transistor Q2 through resistor R5. The base and collector of transistor Q1 and the base and collector of transistor Q2 are all grounded.

[0048] In a PTAT circuit, the core mechanism is based on the base-emitter voltage difference ΔV between two bipolar transistors (i.e., transistor Q1 and transistor Q2). BE The temperature characteristics are described. Specifically, operational amplifier Amp2 and PMOS transistor M3 form a closed-loop negative feedback network: the non-inverting input of operational amplifier Amp2 is connected to node C, and the inverting input is connected to node B. Its output drives the gate of PMOS transistor M3, dynamically clamping the potential of node C by adjusting the on-resistance of PMOS transistor M3. Simultaneously, the output signal of Amp2 also constructs a local positive feedback loop through PMOS transistor M2, utilizing the source-following characteristic of PMOS transistor M2 to force the potential of node B to track the potential of node C, thereby achieving V... B =V C =V BE1 The stable state. Where V B V is the voltage at node B. C V is the voltage at node C. BE1 This is the base-emitter voltage of transistor Q1.

[0049] By employing the above structure, the emitter area ratio of the bipolar transistor pair (i.e., transistor Q1 and transistor Q2) (in this embodiment, the emitter junction area ratio of transistor Q2 and transistor Q1 is 8:1) and the resistance ratio of resistors R4 and R5 (R4 / R5) can be precisely controlled to make the current flowing through resistor R5 exhibit a characteristic proportional to absolute temperature. C1 I C2 These are the collector currents of transistors Q1 and Q2, respectively. Since PMOS transistors M2 and M3 form a current mirror structure with the same width-to-length ratio, therefore I... C1 I C2 Equal to each other, for a bipolar transistor, its collector current I... C for:

[0050]

[0051] In the formula, V BE I is the base-emitter voltage of a bipolar transistor. S V is the saturation current of the bipolar transistor. TThis is the thermal voltage of the bipolar transistor. Based on the above formula, the base-emitter voltage V of transistor Q1 can be calculated. BE1 and the base-emitter voltage V of transistor Q2 BE2 Therefore, we can obtain:

[0052] ΔV BE =V BE1 -V BE2 =V T ln(n)

[0053]

[0054] In the formula, n is the ratio of the emitter junction area of ​​transistor Q2 to that of transistor Q1.

[0055] In the CTAT circuit, its core relies on the base-emitter voltage V of the bipolar transistor. BE The negative temperature coefficient characteristic. Operational amplifier Amp1 and PMOS transistor M1 form a main negative feedback loop: the non-inverting input of operational amplifier Amp1 is connected to the potential of node A, and the inverting input is connected to the potential of node B. Its output drives the gate of PMOS transistor M1 to form a voltage-to-current conversion link. By adjusting the channel current of PMOS transistor M1, the potential of node A can be precisely stabilized. The generated negative temperature coefficient current I CTAT for:

[0056]

[0057] Furthermore, operational amplifiers Amp1 and Amp2 form a cascaded cooperative control system through a shared bias network (not shown in the figure): since the common-mode level setting of operational amplifier Amp1 is matched with the input stage of operational amplifier Amp2, it can be ensured that the potentials of the three nodes A, B, and C are strictly equal under the joint regulation of the two operational amplifiers (i.e., operational amplifiers Amp1 and Amp2), that is: V A =V B =V C This forced equipotential mechanism effectively eliminates static errors caused by process mismatch in traditional architectures, while simultaneously achieving weighted superposition of PTAT circuit current and CTAT circuit current through the current mirror structure M1-M2-M3.

[0058] The current summing circuit is used to sum the positive temperature coefficient current I PTAT and negative temperature coefficient current I CTAT The summation generates a resultant current with zero temperature coefficient characteristics and outputs a resultant voltage V' with zero temperature coefficient characteristics. REF Please continue reading. Figure 3The current summing circuit includes PMOS transistors M4 and M5 and resistor R6, wherein resistor R6 is a polysilicon resistor with zero temperature coefficient. The source of PMOS transistor M4 is externally connected to a power supply voltage VDD, and its gate is electrically connected to the bandgap core circuit for inputting a positive temperature coefficient current I. PTAT The source of the PMOS transistor M5 is externally connected to a power supply voltage VDD, and its gate is electrically connected to the bandgap core circuit for inputting a negative temperature coefficient current I. CTAT The drains of PMOS transistors M4 and M5 are both electrically connected to the first terminal of resistor R6, which also serves as the output terminal of a current summing circuit for outputting the synthesized current; the second terminal of resistor R6 is grounded.

[0059] From a circuit dynamics perspective, the interaction between the PTAT and CTAT circuit paths manifests as follows: the positive feedback network of operational amplifier Amp2 provides the loop gain required for initial startup, while the global negative feedback of operational amplifier Amp1 dominates the convergence process at the steady-state operating point. By rationally designing the gain-bandwidth product and phase margin of the operational amplifiers, it can be ensured that the core node voltage deviation is less than 1mV within the range of process angle (FF / SS / TT) and temperature (-40℃~125℃) variations. Finally, the positive temperature coefficient current I is applied across resistor R6. PTAT With negative temperature coefficient current I CTAT A first-order temperature-compensated output voltage with high linearity is achieved by superimposing complementary temperature coefficients.

[0060] V REF =V G0 +(k / q)γT

[0061] In the formula, V G0 γ is the bandgap voltage of silicon; k is the Boltzmann constant; q is the charge of electrons; γ is the process-related correction factor (specifically, the nonlinearity factor of resistors R4 and R5, which have the same process); T is the ambient temperature.

[0062] The current summing circuit, as the core output stage of the bandgap reference voltage source, functions primarily to perform temperature coefficient complementary synthesis of the PTAT and CTAT currents. Specifically, the output current of the PTAT circuit (I... PTAT =αT) and the output current (I) of the CTAT circuit CTAT =β-γT) is linearly superimposed using a high-precision current mirror array to generate a composite current I with zero temperature coefficient characteristics. SUM :

[0063] I SUM =I PTAT +I CTAT =β+(α-γ)T

[0064] Where α represents the process parameters of transistors Q1 and Q2 that are related to the negative temperature coefficient, and β represents the process parameters of transistors Q1 and Q2 that are related to the positive temperature coefficient. (Transistors Q1 and Q2 have the same process; for example, transistor Q2 can be obtained by connecting n transistors Q1 in parallel.) By matching the parameters to make α = γ, the temperature dependence can be eliminated. The current flows through a zero-temperature-coefficient polycrystalline silicon resistor R6 (TCR < 10ppm / ℃) designed with temperature characteristic compensation, utilizing Ohm's law V' REF =I SUM R6 generates a reference voltage that is independent of process, power supply, and temperature.

[0065] The output circuit is used to transmit the synthesized voltage V' REF Generate reference voltage V REF Please continue reading. Figure 3 The output circuit may include an operational amplifier Amp3, a resistor R7, and a resistor R8. The positive input terminal of the operational amplifier Amp3 is electrically connected to the first terminal of the resistor R6, the output terminal is connected to the first terminal of the resistor R8, and the negative input terminal is connected to the second terminal of the resistor R8. The second terminal of the resistor R8 is grounded through the resistor R7.

[0066] In the output circuit, operational amplifier Amp3, along with resistors R7 and R8, forms a closed-loop voltage buffer. Its topology is a non-inverting amplifier with a gain of (1 + R8 / R7), which can be set to approximately unity gain (R8 << R7). This design has a dual function:

[0067] (1) High Output Impedance and Load Isolation: The operational amplifier Amp3 uses a negative feedback loop to convert the high-impedance node of the bandgap core into a low-impedance output node, significantly improving the circuit's load regulation. The feedback network is equivalent to introducing a series voltage source at the output, reducing the output impedance to a certain level.

[0068] Zout≈Z OL / (1+A OL β1)

[0069] In the formula, Z OL For open-loop output resistance; A OL β1 is the open-loop gain; β2 is the feedback coefficient, which can suppress the influence of external load fluctuations on the reference accuracy.

[0070] (2) Loop stability optimization: The ratio of resistors R7 and R8, combined with the phase compensation network of operational amplifier Amp3, can adjust the loop gain-bandwidth product and phase margin (PM>60°), avoiding the risk of oscillation caused by capacitive load. In addition, resistor R8, as a series damping resistor, can limit the transient current of the output stage and improve the robustness to ESD events.

[0071] Ultimately, this architecture achieves a reference voltage V across the entire temperature range through two-stage temperature compensation in the current and voltage domains, combined with the impedance transformation characteristics of the output buffer. REF The deviation is less than ±0.1% (-55℃~125℃). Meanwhile, the common-mode input range (CMRR>80dB) and power supply rejection ratio (PSRR>70dB@1kHz) of the operational amplifier Amp3 further reduce the coupling effect of power supply noise and common-mode interference on the reference output. Please refer to... Figure 4 After adopting the structure of this embodiment, the actual curve V of the output voltage changing with temperature is shown. REF (real) is very close to the ideal curve V. REF (ideal).

[0072] The startup circuit is used to drive the subsequent circuits to operate away from the degeneracy point during the power-on process of the bandgap reference circuit, and to shut down after the bandgap reference circuit is operating normally. The degeneracy point refers to one or more undesirable stable operating points in addition to the normal operating point. For bandgap reference circuits, the most common degeneracy point is the state where all currents are zero.

[0073] The startup circuit is a key functional module in the bandgap reference circuit for achieving reliable self-excited startup. Its core function is to eliminate the degenerate bias state that the circuit may fall into during the initial power-up phase. During the establishment of the power supply voltage VDD, due to the multistable solution of the transconductance ratio between the bipolar transistors and MOS devices in the core bandgap circuit, the circuit may lock into a metastable operating point with zero current / zero voltage. At this time, the startup circuit breaks the loop balance condition by injecting a transient excitation signal or applying forced bias, guiding the main circuit out of the degenerate region and into the preset operating range.

[0074] Establish a stable output voltage V based on the bandgap reference REF Subsequently, the startup circuit needs to achieve autonomous shutdown through a feedback control mechanism. A typical solution includes using a voltage monitoring module to detect V. REF The turn-off signal is triggered by a threshold or by utilizing the current mirror ratio. This turn-off process must ensure that the startup branch exhibits high impedance characteristics to avoid introducing additional offset current or noise coupling, thereby guaranteeing key performance indicators such as the power supply rejection ratio and temperature stability of the bandgap reference. The design should focus on optimizing the matching between the startup timing and the main circuit setup time, balancing low quiescent power consumption with high robustness requirements, especially maintaining reliable triggering and complete turn-off characteristics under process corner and temperature variations.

[0075] Please continue reading. Figure 3The startup circuit may include a PMOS transistor M6, the gate of which is electrically connected to the start-up terminal of operational amplifier Amp2, the drain of which is electrically connected to the gate of PMOS transistor M2, and the source of which is electrically connected to the negative input terminals of operational amplifiers Amp1 and Amp2.

[0076] In this embodiment, the PTAT circuit uses a self-biased current mirror structure to generate a positive temperature coefficient current I. PTAT Combined with a subthreshold MOSFET, a negative temperature coefficient current I is generated. CTAT A high-precision reference voltage V is output after weighted superposition through a resistor network (i.e., resistor R6). REF This circuit, by optimizing the resistor ratio and MOSFET size ratio, can achieve a temperature drift of ≤15ppm / ℃ and a quiescent current of ≤5μA within a temperature range of -55℃ to 125℃, making it suitable for low-power IoT chips and high-precision sensors.

[0077] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A low-temperature drift, low-power bandgap reference circuit, characterized in that: include Bandgap core circuit for generating a positive temperature coefficient current I PTAT and a negative temperature coefficient current I CTAT ; a current summation circuit for adding a positive temperature coefficient current I PTAT and a negative temperature coefficient current I CTAT to generate a resultant voltage V' having zero temperature coefficient characteristics REF ; an output circuit for outputting the resultant voltage V REF generating a reference voltage V REF ; as well as The startup circuit is used to drive the subsequent circuits to operate out of the degeneracy point during the power-on process of the bandgap reference circuit, and to turn off after the bandgap reference circuit is operating normally.

2. The low-temperature drift, low-power bandgap reference circuit as described in claim 1, characterized in that: The bandgap core circuit includes PTAT circuit for generating a positive temperature coefficient current I PTAT ; as well as A CTAT circuit for generating a negative temperature coefficient current I CTAT .

3. The low-temperature drift, low-power bandgap reference circuit as described in claim 2, characterized in that: The CTAT circuit includes an operational amplifier Amp1, a PMOS transistor M1, and a resistor R4. The source of the PMOS transistor M1 is connected to an external power supply voltage VDD, the drain is grounded through the resistor R4, and the gate is connected to the output terminal of the operational amplifier Amp1. The gate of the PMOS transistor M1 is also electrically connected to its drain through a first phase margin compensation circuit. The positive input end of the operational amplifier Amp1 is electrically connected with the drain of the PMOS tube M1; the negative input end of the operational amplifier Amp1 is electrically connected with the PTAT circuit, and the output end of the operational amplifier Amp1 is used as the output end of the CTAT circuit for outputting the negative temperature coefficient current I CTAT .

4. The low-temperature drift, low-power bandgap reference circuit as described in claim 3, characterized in that: The first phase margin compensation circuit includes a resistor R1 and a capacitor C1 connected in series.

5. The low-temperature drift, low-power bandgap reference circuit as described in claim 3, characterized in that: The PTAT circuit includes an operational amplifier Amp2, a PMOS transistor M2, a PMOS transistor M3, a transistor Q1, a transistor Q2, and a resistor R5; both transistor Q1 and transistor Q2 are bipolar transistors. The source of the PMOS transistor M2 is connected to an external power supply voltage VDD, the drain is electrically connected to the negative input terminal of the operational amplifier Amp2, and the gate is connected to the output terminal of the operational amplifier Amp2; the gate of the PMOS transistor M2 is also electrically connected to its drain through a second phase margin compensation circuit. The source of the PMOS transistor M3 is connected to an external power supply voltage VDD, the drain is electrically connected to the positive input terminal of the operational amplifier Amp2, and the gate is connected to the output terminal of the operational amplifier Amp2; the gate of the PMOS transistor M3 is also electrically connected to its drain through a third phase margin compensation circuit. An output terminal of the operational amplifier Amp2 is used as an output terminal of the PTAT circuit for outputting a positive temperature coefficient current I PTAT A negative input terminal of the operational amplifier Amp2 is electrically connected with a negative input terminal of the operational amplifier Amp1; the negative input terminal of the operational amplifier Amp2 is also electrically connected with an emitter of the transistor Q1; a positive input terminal of the operational amplifier Amp1 is electrically connected with an emitter of the transistor Q2 through the resistor R5; The base and collector of transistor Q1 and the base and collector of transistor Q2 are both grounded.

6. The low-temperature drift, low-power bandgap reference circuit as described in claim 5, characterized in that: The second phase margin compensation circuit includes a resistor R2 and a capacitor C2 connected in series; the third phase margin compensation circuit includes a resistor R3 and a capacitor C3 connected in series.

7. The low-temperature drift, low-power bandgap reference circuit as described in claim 5, characterized in that: The startup circuit includes a PMOS transistor M6, the gate of which is electrically connected to the startup terminal of operational amplifier Amp2, the drain of which is electrically connected to the gate of PMOS transistor M2, and the source of which is electrically connected to the negative input terminals of operational amplifiers Amp1 and Amp2.

8. The low-temperature drift, low-power bandgap reference circuit as described in any one of claims 1 to 7, characterized in that: The current summation circuit comprises a PMOS tube M4, a PMOS tube M5 and a resistor R6, the source of the PMOS tube M4 is connected with a power supply voltage VDD, the gate is electrically connected with the bandgap core circuit, and is used for inputting a positive temperature coefficient current I PTAT ; the source of the PMOS tube M5 is connected with the power supply voltage VDD, the gate is electrically connected with the bandgap core circuit, and is used for inputting a negative temperature coefficient current I CTAT ; the drain of the PMOS tube M4 and the drain of the PMOS tube M5 are both electrically connected with the first end of the resistor R6, the first end of the resistor R6 is also used as an output end of the current summation circuit for outputting a synthesized current, and the second end of the resistor R6 is grounded.

9. The low-temperature drift, low-power bandgap reference circuit as described in claim 8, characterized in that: The resistor R6 is a polycrystalline silicon resistor with zero temperature coefficient.

10. The low-temperature drift, low-power bandgap reference circuit as described in claim 8, characterized in that: The output circuit includes an operational amplifier Amp3, resistors R7 and R8. The positive input terminal of the operational amplifier Amp3 is electrically connected to the first terminal of resistor R6, the output terminal is connected to the first terminal of resistor R8, and the negative input terminal is connected to the second terminal of resistor R8. The second terminal of resistor R8 is grounded through resistor R7.

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