Data writing method, device, equipment, storage medium and program product

Abstract

The application discloses a data writing method, device, equipment, storage medium and program product. The data writing method comprises the following steps: receiving a write request for a target cache line; the write request is used for writing data to a valid byte position of the target cache line; in the case that it is determined that there is at least one invalid byte position in the target cache line based on the write request, the at least one invalid byte position is encoded to obtain an invalid byte code; the invalid byte code comprises a first mask used for determining one invalid byte position in the target cache line; the data is written to the valid byte position, and the first mask is stored; wherein, in the case that the invalid byte position is at least two, the invalid byte code further comprises a second mask; the first mask and all second masks are used for determining all invalid byte positions. In this way, the additional overhead of storing byte masks can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, the technical field of data processing, and particularly relates to a data writing method and device, equipment, a storage medium and a program product. BACKGROUND

[0002] In a computer device, a cache is a high-speed data storage mechanism for temporarily storing frequently accessed data to reduce the number of accesses to a slower storage device (such as a hard disk), thereby improving data access speed and system performance. As a data storage unit, the cache is operated in the granularity of a cache line, but when the cache receives a write request, each write request may not write a complete cache line. A related solution is to store a byte mask corresponding to each cache line to mark which bytes are valid and which bytes are invalid. This storage of a byte mask requires a large additional area overhead. SUMMARY

[0003] Therefore, the embodiments of the present application provide at least a data writing method and device, equipment, a storage medium and a program product.

[0004] The technical solutions of the embodiments of the present application are implemented as follows:

[0005] In one aspect, the embodiments of the present application provide a data writing method, which comprises: receiving a write request for a target cache line; the write request is used to write data to a valid byte position of the target cache line; in the case that it is determined based on the write request that there is at least one invalid byte position in the target cache line, encoding the at least one invalid byte position to obtain an invalid byte code; the invalid byte code comprises a first mask used to determine one invalid byte position in the target cache line; writing the data to the valid byte position and storing the first mask; wherein in the case that the invalid byte position is at least two, the invalid byte code further comprises a second mask; the first mask and all second masks are used to determine all invalid byte positions.

[0006] In another aspect, an embodiment of the present application provides a data writing apparatus, comprising: a receiving module, an encoding module and a writing module; the receiving module is configured to receive a write request for a target cache line; the write request is configured to write data to a valid byte position of the target cache line; the encoding module is configured to encode at least one invalid byte position in the target cache line based on the write request, to obtain an invalid byte encoding; the invalid byte encoding comprises a first mask used to determine one invalid byte position in the target cache line; the writing module is configured to write the data to the valid byte position and store the first mask; wherein, when the invalid byte position is at least two, the invalid byte encoding further comprises a second mask; the first mask and all the second masks are used to determine all the invalid byte positions.

[0007] In another aspect, an embodiment of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor implements part or all steps of the above method when executing the program.

[0008] In another aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all steps of the above method.

[0009] In another aspect, an embodiment of the present application provides a computer program product, comprising a computer program or instructions, and the computer program or instructions are executed by a processor to implement part or all steps of the above method.

[0010] In an embodiment of the present application, the invalid byte encoding corresponding to the target cache line is determined based on the write request, the data is written to the valid byte position, the second mask is written to the invalid byte position of the target cache line, and the first mask is stored. In this way, only one first mask corresponding to an invalid byte position needs to be stored additionally, and the second mask corresponding to other invalid byte positions is written to the invalid byte position of the target cache line. The invalid byte positions in the target cache line can be determined through the first mask and the second mask, thereby effectively reducing the additional area overhead introduced by the storage of the byte mask.

[0011] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the technical solutions of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the technical solutions of the present application.

[0013] Figure 1A is a schematic diagram of a byte mask;

[0014] Figure 1A is a schematic diagram of an implementation process of a data writing method provided by an embodiment of the present application;

[0015] Figure 2 is a schematic diagram of an implementation process of a data writing method provided by an embodiment of the present application Figure 2 ;

[0016] Figure 3 is a schematic diagram of an implementation process of a data writing method provided by an embodiment of the present application Figure 3 ;

[0017] Figure 4 is a schematic diagram of an implementation process of a data writing method provided by an embodiment of the present application Figure 4 ;

[0018] Figure 5 is a schematic diagram of an implementation process of a data writing method provided by an embodiment of the present application Figure 5 ;

[0019] Figure 6 is a schematic diagram of a compression mask provided by an embodiment of the present application;

[0020] Figure 7 is a schematic diagram of a process of writing cache data provided by an embodiment of the present application;

[0021] Figure 8 is a schematic diagram of a component structure of a data writing device provided by an embodiment of the present application;

[0022] Figure 9 is a schematic diagram of a hardware entity of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purposes, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those skilled in the art without making any creative labor are within the scope of protection of the present application.

[0024] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. The terms "first / second / third" referred to are only to distinguish similar objects, and do not represent a specific order of the objects. Understandably, "first / second / third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing the present application only and is not intended to be limiting of the present application.

[0026] The embodiments of the present application provide a method, which can be executed by a processor of an electronic device. The electronic device can be a server, a notebook computer, a tablet computer, a desktop computer, a smart television, a set-top box, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a dedicated messaging device, a portable game device), and the like.

[0027] Figure 1A Fig. 1 is a schematic diagram of a byte mask. As shown in Fig. 1, an initial target cache line includes eight byte positions byte0-byte7, and an initial byte mask is 00000000, indicating that each byte position in the initial target cache line is invalid and no data is written. After receiving a write data request for the target cache line, data is written to byte0 and byte2 of the initial target cache line, and byte0 and byte2 change from invalid byte positions to valid byte positions. Therefore, the bits corresponding to byte0 and byte2 in the byte mask after writing data change from 0 to 1, indicating that byte0 and byte2 in the target cache line after writing data are valid; the remaining byte positions have no data written, and the bits corresponding to the remaining byte positions in the byte mask after writing data remain 0. Figure 1A

[0028] The size of the byte mask will be 1 / 8 of the total size of the target cache line, and the storage of the byte mask and the database of the target cache line need to be stored in a static random access memory (SRAM), so when using the byte mask to record the mask, there will always be an additional area loss of 1 / 8 (each byte is 8 bits (bit), which is equivalent to 8 bits of data corresponding to 1 bit of mask). ​

[0029] In order to reduce the additional area overhead introduced by storing the byte mask, the embodiment of the present application provides a data writing method, which can determine the invalid byte code corresponding to the target cache line based on the write request, write data to the valid byte position, write the second mask to the invalid byte position of the target cache line, and store the first mask. In this way, only one first mask of the invalid byte position needs to be stored, and the second mask of the other invalid byte position is written to the invalid byte position of the target cache line, which can effectively reduce the additional area overhead introduced by storing the byte mask. By determining one invalid byte position of the target cache line through the first mask and the next adjacent invalid byte position through the second mask, the invalid byte position in the target cache line can be accurately determined through the first mask and the second mask.

[0030] Figure 1B The implementation flowchart of the data writing method provided by the embodiment of the present application is shown as Figure 1B The method comprises the following steps S101 to S103:

[0031] Step S101, receiving a write request for a target cache line; the write request is used to write data to the valid byte position of the target cache line.

[0032] The target cache line is a cache line corresponding to the write request in the cache. There are a plurality of cache lines in the cache. After receiving the write request, the write request comprises the address of the target cache line, and the target cache line can be determined from the cache based on the write request.

[0033] The write request is a request for writing cache data, and is used to write data to the valid byte position of the target cache line. In general, each write request does not write a complete cache line, but only writes part of the byte position of the cache line. For example, the cache line comprises eight byte positions byte0 to byte7, and the write request indicates that data is written to byte0 and byte5 of the cache line.

[0034] The number of byte positions in the target cache line can be set according to requirements. For example, the target cache line can comprise eight byte positions byte0 to byte7, or 128 byte positions byte0 to byte127.

[0035] The valid byte position is the byte position in the target cache line where data is written. After receiving the write request, the byte position where data needs to be written can be determined based on the write request, and the byte position where data needs to be written is determined as the valid byte position.

[0036] Step S102, in a case where it is determined based on the write request that there is at least one invalid byte position in the target cache line, encoding the at least one invalid byte position to obtain an invalid byte encoding; the invalid byte encoding includes a first mask used to determine one invalid byte position in the target cache line.

[0037] The invalid byte position refers to a byte position in the target cache line that is not written with data. For example, the target cache line includes 8 byte positions byte0-byte7, the write request indicates writing data to byte0 and byte5 of the target cache line, and therefore byte1-byte4 and byte6 are invalid byte positions.

[0038] In some embodiments, before the write request, all byte positions of the target cache line are invalid byte positions. Based on the write request, the corresponding partial valid byte positions of the write request can be determined, and byte positions of the target cache line other than the partial valid byte positions are determined as invalid byte positions.

[0039] In some embodiments, before the write request, there are partial byte positions in the target cache line that are invalid byte positions. Based on the current partial invalid byte positions, the current valid byte positions of the target cache line can be determined, and in combination with the valid byte positions corresponding to the write request, the final valid byte positions can be obtained. Based on the final valid byte positions, the final invalid byte positions in the target cache line are determined.

[0040] The invalid byte encoding is a byte encoding obtained after encoding the at least one invalid byte position. The invalid byte encoding includes a first mask used to determine one invalid byte position in the target cache line.

[0041] In some embodiments, based on the write request, it is determined that there is one invalid byte position in the target cache line. For example, the target cache line includes 8 byte positions byte0-byte7, based on the write request, byte3 is determined to be an invalid byte position, byte3 is encoded using 4 bits to obtain a first mask 0011.

[0042] In some embodiments, based on the write request, it is determined that there are at least two invalid byte positions in the target cache line. For example, the target cache line includes 8 byte positions byte0-byte7, based on the write request, byte3 and byte5 are determined to be invalid byte positions, byte3 and byte5 are encoded using 4 bits to obtain invalid byte encodings 0011 and 0101. The first mask can be the encoding of any one of the invalid byte positions. The first mask can be 0011 or 0101. Through the first mask, one invalid byte position in the target cache line can be determined.

[0043] Step S103, write the data into the valid byte position and store the first mask.

[0044] In some embodiments, in the case of one invalid byte position, the data is written into the valid byte position and the first mask is stored. Wherein, the valid byte position corresponding to the write request can be determined based on the write request; in the case of one invalid byte position, the encoding of the invalid byte position corresponds to the first mask.

[0045] Wherein, the first mask is stored in a storage area outside the target cache line. Illustratively, the first mask is stored in SRAM.

[0046] Illustratively, the target cache line includes 8 byte positions byte0 to byte7, byte1 to byte7 are determined to be valid byte positions based on the write request, and therefore byte0 is the invalid byte position. Encoding byte0 obtains the first mask 0000. The data is written into the valid byte positions byte1 to byte7, and the first mask 0000 is stored.

[0047] Wherein, in the case of at least two invalid byte positions, the invalid byte encoding further includes a second mask; the first mask and all second masks are used to determine all invalid byte positions.

[0048] In some embodiments, the invalid byte encoding is used to determine all invalid byte positions, that is, the invalid byte positions in the target cache line can be determined by the first mask and the second mask. Illustratively, the first mask is 0100, indicating that byte4 is an invalid byte position, and the second mask 0101 is stored in byte4, indicating that the next invalid byte position adjacent to byte4 is byte5, and so on. All invalid byte positions of the target cache line can be obtained in this way.

[0049] Illustratively, the target cache line includes 8 byte positions byte0 to byte7, byte0 to byte3 are determined to be valid byte positions based on the write request, and therefore byte4 to byte7 are invalid byte positions. Encoding byte4 to byte7 obtains 0100, 0101, 0110 and 0111. In the case of the first mask being 0100, 0101, 0110 and 0111 are second masks. The data is written into the valid byte positions byte0 to byte3, 0101, 0110 and 0111 are written into the corresponding invalid byte positions, and the first mask 0100 is stored.

[0050] In the embodiments of the present application, the invalid byte code corresponding to the target cache line is determined based on the write request, data is written to the valid byte position, the second mask is written to the invalid byte position of the target cache line, and the first mask is stored. In this way, only one first mask of the invalid byte position needs to be stored additionally, the second mask of the other invalid byte position is written to the invalid byte position of the cache line, and the invalid byte position in the target cache line can be determined through the first mask and the second mask, thereby effectively reducing the additional area overhead introduced by the storage of the byte mask.

[0051] In some embodiments, the first mask is used to store a first invalid byte position, and the second mask stored in the first invalid byte position is used to indicate a second invalid byte position, which is the next invalid byte position adjacent to the first invalid byte position.

[0052] Here, when there are at least two invalid byte positions, the first mask and the second mask can be understood as locating all invalid byte positions in the form of a linked list.

[0053] In some possible implementations, the first mask can be used as the first pointer of the linked list, and encodes the position of the first invalid byte (for example, byte0 is encoded as 0000). If there are multiple invalid byte positions, a second mask is stored in each invalid byte position (except the last one). Each second mask acts as a pointer and encodes the value of the next invalid byte position in the linked list.

[0054] For example, assuming that a cache line has 8 bytes (Byte0 to Byte7), after a write request, Byte1, Byte2, and Byte5 are valid bytes (data is written), and Byte0, Byte3, Byte4, Byte6, and Byte7 are invalid bytes, and are encoded as 0000, 0011, 0100, 0110, and 0111 respectively. The position of the first invalid byte (Byte0) is encoded as 0000 (Byte0) as the first mask. In the storage space of the first invalid byte (Byte0), the code 0011 of the next invalid byte (Byte3) is stored, which is the first second mask; in the storage space of the second invalid byte (Byte3), the code 0100 of the next invalid byte (Byte4) is stored, which is the second second mask; in the storage space of the third invalid byte (Byte4), the code 0110 of the next invalid byte (Byte6) is stored, which is the third second mask; and in the storage space of the fourth invalid byte (Byte6), the code 0111 of the next invalid byte (Byte7) is stored, which is the fourth second mask. In this way, all invalid byte positions in the cache line can be determined based on the first mask and the four second masks.

[0055] In some embodiments, the invalid byte encoding further comprises a termination mask, the termination mask stored in a last one of the at least one invalid byte location.

[0056] Here, a last one of the at least one invalid byte location can store a termination mask, which can be a special end-of-chain flag. Illustratively, in the storage space of the last invalid byte (Byte7) in the above example, a special end-of-chain flag (such as 1111, 1000, or other masks different from the second mask) is stored.

[0057] In some embodiments, the first mask is stored in a byte mask bit associated with the target cache line.

[0058] Here, a byte mask bit is an extra external storage space reserved for each cache line to store a corresponding byte mask, which is small and fixed. It can be understood that the byte mask bit is directly associated with a cache line in the cache, i.e., the byte mask bit corresponds to the cache line one-to-one.

[0059] In some embodiments, in a case where it is determined based on the write request that the invalid byte location exists in the target cache line, the byte mask bit is used to store the first mask.

[0060] In some embodiments, in a case where it is determined based on the write request that the invalid byte location does not exist in the target cache line, the byte mask bit is used to store the termination mask.

[0061] Here, in a case where all byte locations of the target cache line are written with valid data, there is no invalid byte location in the cache line. In order to explicitly identify this special state of "all valid", a predefined termination mask (such as 1111, 1000, or other masks different from the second mask) can be written in the "byte mask bit" of the cache line.

[0062] It can be understood that the byte mask bit can directly indicate whether there is an invalid byte in the cache line, i.e., whether there is an invalid byte in the cache line can be determined by determining whether the byte mask bit is a termination mask.

[0063] In some embodiments, the invalid byte encoding comprises N second masks in sequence, and the target cache line comprises N+1 invalid byte locations in sequence, wherein the nth second mask is stored in the nth invalid byte location, n and N are positive integers, and n is less than or equal to N.

[0064] Here, there is a strict correspondence between the number of second masks (N) and the number of invalid byte positions (N+1), and the storage order of the masks is completely consistent with the physical order of the invalid bytes.

[0065] Exemplarily, assuming that a cache line has 8 bytes (Byte0 to Byte7), after a write request, 4 invalid byte positions (N+1=4) are generated in address order as follows: Byte1 (1st), Byte3 (2nd), Byte5 (3rd), and Byte7 (4th). Here, the number of invalid byte positions is 4, so the number of second masks N=3 (i.e., 4-1). Then, three second masks can be obtained as follows:

[0066] The 1st second mask: encodes the address of the 2nd invalid byte (Byte3) and is stored in the 1st invalid byte (Byte1).

[0067] The 2nd second mask: encodes the address of the 3rd invalid byte (Byte5) and is stored in the 2nd invalid byte (Byte3).

[0068] The 3rd second mask: encodes the address of the 4th invalid byte (Byte7) and is stored in the 3rd invalid byte (Byte5).

[0069] At this time, the first mask stored in the byte mask bit points to the head node of the linked list, i.e., the 1st invalid byte (Byte1), and a termination mask is stored in the tail node (4th invalid byte Byte7) of the linked list, indicating the end of the linked list.

[0070] In this way, all invalid byte positions can be accurately located by traversing the chain formed by the first mask and the second masks through an external first mask.

[0071] Figure 2 An implementation flow of a data writing method provided by an embodiment of the present application Figure 2 The method can be executed by a processor of an electronic device. Based on Figure 1B , the data writing method can further include steps S201 to S203, which will be described in combination with the steps shown in Figure 2 .

[0072] Step S201: performing a hit check on the write request.

[0073] In the case that the write request hits the cache, the target cache line corresponding to the write request already exists in the cache, and the write data operation needs to be performed on the basis of the existing target cache line. In the case that the write request does not hit the cache, the target cache line corresponding to the write request does not exist in the cache, and a new target cache line needs to be determined from the cache, and the write data operation needs to be performed on the basis of the new target cache line.

[0074] In some embodiments, the write request has a corresponding address, and the address includes an index, a tag and a block offset. Each cache line in the cache also has a corresponding address, and the corresponding target cache line in the cache can be found through the index in the address of the write request. Whether the corresponding target cache line exists in the cache is determined by judging whether the address tag in the write request is consistent with the address tag of the target cache line, and a hit check result is obtained.

[0075] The hit check result includes that the write request hits the target cache line or the write request does not hit the target cache line.

[0076] In the case that the hit check result indicates that the target cache line is not hit, the valid byte position in the write request is used to determine the invalid byte position in the target cache line.

[0077] Here, in the case that the hit check result indicates that the target cache line is not hit, the corresponding target cache line does not exist in the cache before the write request, and the invalid byte position in the target cache line can be directly determined based on the valid byte position in the write request.

[0078] The target cache line is not hit, which means that the corresponding target cache line does not exist in the cache before the write request, and thus the invalid byte position in the target cache line can be directly determined based on the write request.

[0079] In some embodiments, the write request includes the valid byte position of the data write, and after the valid byte position is obtained, the invalid byte position in the target cache line can be determined.

[0080] For example, the target cache line includes byte0 to byte7, the valid byte position is determined to be byte0 to byte5 based on the write request, and thus the invalid byte position is determined to be byte6 and byte7.

[0081] In the case that the hit check result indicates that the target cache line is not hit, the valid byte position in the write request is used to determine the invalid byte position in the target cache line. In this way, when the target cache line is not hit, the accurate invalid byte position can be determined based on the write request.

[0082] Step S203, in the case that the hit check result represents that the target cache line is hit, determining the invalid byte position in the target cache line based on the valid byte position in the write request and the original invalid byte encoding of the target cache line.

[0083] Here, in the case that the hit check result represents that the target cache line is hit, there is a corresponding target cache line before the write request, so it is necessary to determine the original invalid byte position of the target cache line based on the original invalid byte encoding of the target cache line, and then determine the original valid byte position of the target cache line, and finally, determine the final invalid byte position in combination with the original valid byte position and the valid byte position of the write request.

[0084] Figure 3 An implementation flowchart of a data writing method provided by an embodiment of the present application Figure 3 The method can be executed by a processor of an electronic device. Based on Figure 4 , Figure 4 Step S203 in the method can be updated to steps S301 and S302, which will be described in combination with the steps shown in Figure 3

[0085] Step S301, determining the original valid byte position in the target cache line based on the original invalid byte encoding.

[0086] Wherein, after obtaining the original invalid byte encoding, the original invalid byte position can be determined based on the original invalid byte encoding, and the original valid byte position can be determined based on the original invalid byte position.

[0087] In some embodiments, in the case that the original invalid byte encoding includes an original first mask, at least one original invalid byte position in the target cache line is determined based on the original invalid byte encoding; and the original valid byte position in the target cache line is determined based on the at least one original invalid byte position.

[0088] In some embodiments, in the case that the original invalid byte encoding only includes an original termination mask, it is determined that the target cache line is all original valid byte positions.

[0089] ​Exemplarily, the target cache line includes byte0-byte7, the original invalid byte code includes a first mask 0001, three second masks 0010, 0100, 0101, and a termination mask 1000. Based on the first mask 0001, an invalid byte position byte1 is determined, based on the second mask 0010, an invalid byte position byte2 is determined, based on the second mask 0100, an invalid byte position byte4 is determined, and based on the second mask 0101, an invalid byte position byte5 is determined. Therefore, the original valid byte positions are byte0, byte3, byte6 and byte7.

[0090] In step S302, based on the original valid byte position and the valid byte position in the write request, an invalid byte position in the target cache line is determined.

[0091] The write request includes a valid byte position to which data needs to be written, and after the original valid byte position is obtained, the invalid byte position of the target cache line can be determined.

[0092] Exemplarily, the target cache line includes byte0-byte7, the original valid byte position is byte0 and byte3, and the valid byte position in the write request is byte2 and byte4. Therefore, the invalid byte position of the target cache line is byte1, byte5 and byte6.

[0093] In some embodiments, the original valid byte position and the valid byte position in the write request are consistent, and at this time, the invalid byte position in the target cache line does not need to be recalculated, and the data only needs to be written to the valid byte position.

[0094] In the embodiments of the present application, in the case that the hit check result represents a hit target cache line, the original invalid byte code of the target cache line is read; based on the original invalid byte code, an original valid byte position in the target cache line is determined; and based on the original valid byte position and the valid byte position in the write request, an invalid byte position in the target cache line is determined. In this way, in the case that the target cache line is hit, the final invalid byte position is determined through the original valid byte position, and an accurate invalid byte position can be obtained.

[0095] Figure 3 An implementation flow of a data writing method provided in the embodiments of the present application Figure 4 The method can be executed by a processor of an electronic device. Based on Figure 5 , Figure 5 Step S301 in the method can be updated to steps S401-S402, which will be described in combination with the steps shown in Figure 3

[0096] ​Step S401, in a case that the original invalid byte encoding includes an original first mask, determining at least one original invalid byte position in the target cache line based on the original invalid byte encoding.

[0097] In a case that the original invalid byte encoding includes an original first mask, it indicates that there is at least one original invalid byte position in the target cache line.

[0098] In some embodiments, the original invalid byte encoding includes an original first mask, based on which one original invalid byte position can be determined in the target cache line.

[0099] In some embodiments, the original invalid byte encoding includes an original first mask and at least one original second mask, based on which one original invalid byte position can be determined, and based on which at least one original invalid byte position can be determined again. For example, the original first mask is 0100, the original second masks are 0101 and 0110, 0100 corresponds to byte4, 0101 corresponds to byte5, and 0110 corresponds to byte6, thus the original invalid byte positions are byte4, byte5, and byte6.

[0100] Step S402, determining an original valid byte position in the target cache line based on the at least one original invalid byte position.

[0101] In a case that the at least one original invalid byte position is obtained, the original valid byte position can be determined based on all byte positions of the target cache line and the at least one original invalid byte position.

[0102] For example, the target cache line includes byte0 to byte7, and the at least one original invalid byte position includes byte0 to byte3, thus the original valid byte position is byte4 to byte7.

[0103] In a case that the original invalid byte encoding includes an original first mask, the original valid byte position can be determined through the original invalid byte position, and thus an accurate original valid byte position can be obtained.

[0104] Figure 3 An implementation flow of a data writing method provided in an embodiment of the present application Figure 5 The method can be executed by a processor of an electronic device. Based on Figure 1A , Figure 6 Step S301 in the method can be updated to step S501, which will be explained in combination with steps shown in Figure 6 .

[0105] Step S501, in the case that the original invalid byte encoding only includes the original termination mask, it is determined that all of the target cache line are original valid byte positions.

[0106] The original first mask and the original second mask in the original invalid byte encoding can determine original invalid byte positions, and in the case that the original invalid byte encoding only includes the original termination mask, it can be determined that all of the target cache line are original valid byte positions.

[0107] For example, the target cache line includes byte0-byte7, and the original termination mask is 1000. In the case that only 1000 is read, it is determined that byte0-byte7 of the target cache line are all original valid byte positions.

[0108] In the embodiments of the present application, in the case that the original invalid byte encoding only includes the original termination mask, it is determined that all of the target cache line are original valid byte positions. In this way, based on the original termination mask, the original valid byte positions can be accurately obtained.

[0109] In some embodiments, the encoding of the at least one invalid byte position to obtain the invalid byte encoding includes: determining the number of encoding bits based on the byte length of the target cache line; and encoding the at least one invalid byte position based on the number of encoding bits to obtain the invalid byte encoding.

[0110] The byte length is the number of byte positions of the target cache line. For example, the target cache line includes byte0-byte7, and the byte length is 8.

[0111] In some embodiments, the number of encoding bits is determined by the formula For example, the target cache line includes byte0-byte7, the byte length is 8, and the number of encoding bits is determined to be 4.

[0112] In some embodiments, in the case that the target cache line has an invalid byte position, the invalid byte position is encoded based on the number of encoding bits. For example, the invalid byte position is byte3, and byte3 is encoded to obtain 0011.

[0113] In some embodiments, in the case that the target cache line has no invalid byte position, the invalid byte encoding is a termination mask. The termination mask is encoded based on the number of encoding bits. For example, the number of encoding bits is 4, and the termination mask is 1000.

[0114] In the embodiments of the present application, the number of encoding bits is determined based on the byte length of the target cache line, and then the invalid byte encoding is obtained based on the number of encoding bits. In this way, the accurate invalid byte encoding can be obtained.

[0115] The application further provides a data writing method.

[0116] The cache is a data storage unit, and is operated in a cache data block (cache line, corresponding to the target cache line in the above embodiment) as a granularity. However, when the cache receives write data, each write request does not necessarily write a complete cache data block. The current common technical solution is to additionally store a corresponding byte mask (byte mask) for each cache data block to mark which byte is valid.

[0117] In the related art, when data is written into a cache data block, for an 8-byte cache data block (byte0 to byte7), the number of bit positions of the byte mask is set to 8. When no data is written into the current cache data block, the byte mask is 00000000. The bit positions corresponding to the byte positions where data is written into the cache data block are set to 1, and the remaining bit positions are set to 0. As shown in Figure 7 When data is written into byte0 and byte2, the bit positions corresponding to byte0 and byte2 in the byte mask are set to 1, and the bit positions corresponding to the remaining byte positions are set to 0.

[0118] Figure 8 A compression mask diagram is provided in the embodiments of the application. The embodiments of the application reduce the additional area overhead introduced for storing the cache mask by using the compression mask. When data is written into the cache data block, the embodiments of the application store the mask corresponding to the invalid byte position in a linked list manner, and only need to additionally store the mask of the first invalid byte position (corresponding to the first mask in the above embodiment) in the byte mask. The masks of the subsequent invalid byte positions (corresponding to the second mask in the above embodiment) are stored in the corresponding data bits of the cache data block. A high bit (corresponding to the termination mask in the above embodiment) is additionally set to represent the termination of the linked list, that is, the subsequent data is all valid data. This method is referred to as a compression format, and the original byte mask is referred to as a decompression format.

[0119] As shown in Figure 8As shown, for the initial cache data block cache line of 8 bytes (byte0 to byte7) (corresponding to the target cache line in the above embodiment), the number of bits of the initial byte mask (corresponding to the first mask in the above embodiment) is set to 4. The initial cache data block has no valid data. After writing data into byte0 and byte2 of the cache data block, byte1, byte3 to byte7 in the cache data block are determined to be invalid byte positions. In the form of a linked list, the mask of the first invalid byte position byte1 (corresponding to the first mask in the above embodiment) is stored in the byte mask after writing data, and the position is encoded as 0001 using 4 bits. Based on the byte mask, the first invalid byte position byte1 is determined, the second invalid byte position byte3 is encoded as 0011 using 4 bits, and is stored in the invalid byte position byte1 in the cache data block. The second invalid byte position byte3 is determined based on byte1. In this way, the sixth invalid byte position byte7 is encoded as 0111 using 4 bits, and is stored in the invalid byte position byte6 in the cache data block. An additional 4 bits 1000 (corresponding to the termination mask in the above embodiment) are set to indicate the termination of the linked list, and are stored in the invalid byte position byte7 in the cache data block. The byte masks 0001 to 1000 corresponding to all invalid byte positions are stored in the byte mask and the corresponding invalid byte positions of the cache data block in turn, and the data of the write request is stored in byte0 and byte2, to obtain the compressed format.

[0120] In the byte mask, 0001 is stored, indicating that the byte position byte1 in the cache data block is invalid; 0011 is stored in byte1, indicating that the byte position byte3 in the cache data block is invalid; and so on. 1000 is stored in byte7, indicating that byte7 in the cache data block is the last invalid byte position.

[0121] Figure 9 A flowchart of a process for writing cache data is provided for the embodiments of the present application. The current cache data block has a part that is written into. Taking a cache data block of 8 bytes as an example, the process for writing cache data is as follows:

[0122] Step S701, starting the process for writing cache data;

[0123] Step S702, determining whether the write request hits the target cache line;

[0124] The address matching is performed based on the address of the write request and the address of the target cache line in the cache (corresponding to the hit check in the above embodiment), and an address matching result is obtained; and whether the write request hits the target cache line is determined based on the address matching result. In the case where the address of the write request is consistent with the address of the target cache line in the cache, it is determined that the write request hits the target cache line; and in the case where the address of the write request is inconsistent with the address of the target cache line in the cache, it is determined that the write request does not hit the target cache line.

[0125] Step S703: calculating the compression format according to the current byte mask;

[0126] In the address judgment process, the data after compression byte mask is calculated in parallel. In the case where the write request does not hit the target cache line, the current byte mask is 0000, and the compressed mask data is determined based on the target byte position corresponding to the write request. Exemplarily, the target byte position corresponding to the write request is byte1 and byte3, and therefore the invalid byte positions of the target cache line are byte0, byte2, byte4 to byte7. The calculated mask data (corresponding to the invalid byte encoding in the above embodiment) is 0000→0010→0100→0101→0110→0111→1000. The 0000 in the mask data needs to be stored in the byte mask, and 0010, 0100, 0101, 0110, 0111 and 1000 are sequentially stored in byte0, byte2, byte4 to byte7.

[0127] Step S704: writing the cache data and the corresponding mask data;

[0128] In the case where the write request does not hit the target cache line, the cache data and the mask data of the write request are written into the target cache line and the byte mask based on the compression format calculated in step S703 and the target byte position corresponding to the write request. The cache data is written into the target byte position of the target cache line, the first mask in the mask data is stored in the byte mask, and the other masks in the mask data are sequentially written into the invalid byte positions of the target cache line. Exemplarily, the valid bytes in the target cache line are byte1 and byte3, and the invalid bytes are byte0, byte2, byte4 to byte7. The mask 0000 of the first invalid byte is stored in the byte mask, the mask 0010 of the next invalid byte is stored in byte0 based on the byte mask. In this way, 1000 is stored in byte7.

[0129] Step S705: in the case where the write request hits the target cache line, judging whether the highest bit of the byte mask is 1;

[0130] In the case that the write request hits the target cache line, the address of the target cache line exists in the cache, and at this time, the valid byte position in the target cache line needs to be determined through the byte mask corresponding to the target cache line.

[0131] In the case that the highest bit of the byte mask is 1, the target cache line is full of complete data (all byte positions are valid), and step S704 is executed. Based on the write request, the cache data is written into the target byte position of the target cache line (which can be superimposed on the basis of the original cache data, or replaced with the original cache data). At this time, the mask stored in the byte mask remains unchanged, which is 1000.

[0132] Step S706: In the case that the highest bit of the byte mask is not 1, the original cache data block and the byte mask are read, and the decompression mode is calculated.

[0133] In the case that the highest bit of the byte mask is not 1, part of the byte positions in the target cache line are written with valid data, and part of the byte positions are written with the mask corresponding to invalid bytes. By reading the cache data and the byte mask in the original target cache line, the valid byte position and the invalid byte position in the original target cache line can be determined, and then the decompression mode is obtained. Exemplarily, the cache data in the original target cache line is byte0 (valid), byte1 (valid), byte2 (valid), 0100, 0101, 0110, 0111, 1000, and the original byte mask is 0011. After reading the cache data and the byte mask in the original target cache line, it can be determined that byte0, byte1 and byte2 in the target cache line are valid, and byte3 to byte7 are invalid, that is, the decompression mode is 00000111.

[0134] Step S707: The original decompressed byte mask and the written byte mask are combined to recalculate the compression format.

[0135] Wherein, after obtaining the decompressed byte mask, the valid byte position and the invalid byte position in the current target cache line can be determined. In combination with the target byte position corresponding to the write request, the valid byte position and the invalid byte position in the target cache line after executing the write cache data can be determined. Based on the valid byte position and the invalid byte position in the target cache line, the mask data can be determined, and then the compression format is obtained. Exemplarily, the decompressed byte mask is 00000111, it can be determined that byte0, byte1 and byte2 in the target cache line are valid, and byte3 to byte7 are invalid. In the case that the write request needs to write byte3 and byte7, it is determined that byte0, byte1 and byte2 in the target cache line are valid, byte3 is valid, byte7 is valid, and byte4 to byte6 are invalid. Therefore, the mask data is 0100→0101→0110→1000. The 0100 in the mask data needs to be stored in the byte mask, and 0101, 0110 and 1000 are sequentially stored in byte4 to byte6.

[0136] Step S708: based on the recomputed compression format, write cache data and corresponding mask data.

[0137] Wherein, after determining the compression format, based on the compression format and the target byte corresponding to the write request, the cache data and the mask data of the write request are written into the target cache line and the byte mask. The cache data is written into the target byte position of the target cache line, the first mask in the mask data is stored in the byte mask, and the other masks in the mask data are sequentially written into the invalid byte position of the target cache line.

[0138] The embodiment of the present application can reduce the storage consumption of the byte mask in the cache. Taking an 8-byte cache data block as an example, the original 1 / 8 additional storage is reduced to 1 / 16. If it is a 128-byte cache data block, the original 1 / 8 additional storage is reduced to 1 / 128.

[0139] Wherein, the additional storage of the byte mask calculated by the related scheme is always 1 / 8; the bit number of the additional storage in the embodiment of the present application is Then, the cache data block is converted into the bit number (the byte number multiplied by 8), and the division of the two is the additional consumption of storing the byte mask. Therefore, the longer the cache data block is, the more obvious the benefit is. In the current mainstream graphics processing unit (GPU), a 128-byte cache data block is usually used, and the additional consumption is only 1 / 128.

[0140] The embodiment of the application stores cache data mask in compressed format to reduce additional area overhead; invalid cache data bits are used to store mask information in a linked list manner; when processing write data, compression and decompression operations are needed for the mask.

[0141] Based on the foregoing embodiment, the embodiment of the application provides a data writing device, which comprises units and modules included in the units, and can be implemented by a processor in an electronic device; of course, the device can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0142] Figure 9 The composition structure of the data writing device provided by the embodiment of the application is shown in FIG. 8. ​ As shown in FIG. 8, the data writing device 800 comprises a receiving module 810, an encoding module 820, and a writing module 830.

[0143] The receiving module 810 is configured to receive a write request for a target cache line; the write request is used to write data to a valid byte position of the target cache line.

[0144] The encoding module 820 is configured to, in a case where it is determined based on the write request that there is at least one invalid byte position in the target cache line, encode the at least one invalid byte position to obtain invalid byte encoding; the invalid byte encoding comprises a first mask used to determine one invalid byte position in the target cache line.

[0145] The writing module 830 is configured to write the data to the valid byte position and store the first mask; in a case where the invalid byte position is at least two, the invalid byte encoding further comprises a second mask; the first mask and all second masks are used to determine all invalid byte positions.

[0146] In some embodiments, the first mask is used to store a first invalid byte position, and a second mask stored in the first invalid byte position is used to indicate a second invalid byte position, which is a next invalid byte position adjacent to the first invalid byte position.

[0147] In some embodiments, the invalid byte encoding further includes a termination mask, and the termination mask is stored in a last one of the at least one invalid byte location.

[0148] In some embodiments, the first mask is stored in a byte mask bit associated with the target cache line.

[0149] In some embodiments, in a case that it is determined based on the write request that the invalid byte location does not exist in the target cache line, the byte mask bit is used to store a termination mask.

[0150] In some embodiments, the invalid byte encoding includes N sequential second masks, and the target cache line includes N+1 sequential invalid byte locations, wherein an nth second mask is stored in an nth invalid byte location, n and N are positive integers, and n is less than or equal to N.

[0151] In some embodiments, the receiving module 810 is further configured to perform a hit check on the write request, and in a case that the hit check result indicates that the target cache line is not hit, determine the invalid byte location in the target cache line based on valid byte locations in the write request, and in a case that the hit check result indicates that the target cache line is hit, determine the invalid byte location in the target cache line based on the valid byte locations in the write request and an original invalid byte encoding of the target cache line.

[0152] In some embodiments, the receiving module 810 is further configured to determine, based on the original invalid byte encoding, an original valid byte location in the target cache line, and determine the invalid byte location in the target cache line based on the original valid byte location and the valid byte locations in the write request.

[0153] In some embodiments, the receiving module 810 is further configured to, in a case that the original invalid byte encoding includes an original first mask, determine, based on the original invalid byte encoding, at least one original invalid byte location in the target cache line, and determine an original valid byte location in the target cache line based on the at least one original invalid byte location.

[0154] In some embodiments, the receiving module 810 is further configured to, in a case that the original invalid byte encoding only includes an original termination mask, determine that all of the target cache line are original valid byte locations.

[0155] In some embodiments, the encoding module 820 is further configured to determine a number of encoding bits based on a byte length of the target cache line, and encode the at least one invalid byte location based on the number of encoding bits to obtain the invalid byte encoding.

[0156] The description of the above device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. In some embodiments, the device provided by the embodiments of the present application has functions or includes modules that can be used to perform the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0157] It should be noted that, in the embodiments of the present application, if the above-mentioned method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various media that can store program codes. Thus, the embodiments of the present application are not limited to any particular hardware, software or firmware, or any combination of hardware, software and firmware.

[0158] The embodiments of the present application provide an electronic device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0159] The embodiments of the present application provide a computer-readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all of the steps of the above method. The computer-readable storage medium can be transitory or non-transitory.

[0160] The embodiments of the present application provide a computer program, which includes computer-readable code, and when the computer-readable code is running in an electronic device, a processor in the electronic device executes part or all of the steps of the above method.

[0161] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0162] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0163] ​ This is a hardware entity diagram of an electronic device provided in an embodiment of this application, such as... ​ As shown, the hardware entity of the electronic device 900 includes a processor 901 and a memory 902, wherein the memory 902 stores a computer program that can run on the processor 901, and the processor 901 executes the program to implement the steps in the method of any of the above embodiments.

[0164] The memory 902 stores computer programs that can run on the processor. The memory 902 is configured to store instructions and applications that can be executed by the processor 901. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data and video communication data) in the processor 901 and various modules in the electronic device 900. It can be implemented by flash memory or random access memory (RAM).

[0165] The processor 901 executes the steps of any of the above methods when executing the program. The processor 901 typically controls the overall operation of the electronic device 900.

[0166] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the methods described in any of the above embodiments.

[0167] It should be noted that the above description of the storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present application, please refer to the description of the method embodiments for understanding.

[0168] The processor can be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, or a microprocessor. It can be understood that the electronic device implementing the functions of the processor can also be other devices, and the embodiments of the present application are not limited in this regard.

[0169] The computer storage medium / memory can be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Ferromagnetic Random Access Memory (FRAM), a Flash Memory, a magnetic surface memory, an optical disc, or a Compact Disc Read-Only Memory (CD-ROM), etc. The computer storage medium / memory can also be various terminals including one or any combination of the above storage medium, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc.

[0170] It should be understood that every feature, structure, or characteristic described herein is within a preferred embodiment of the present application. It should be noted that the foregoing embodiments are merely exemplary and are not to be construed as limiting the present application. It should also be noted that features described in the foregoing relate to both structural and method aspects of the application. Accordingly, the terminology in use has a multi-use effect: to the extent there is structural correspondence between a feature described herein and terminology conventionally used to describe corresponding structure in the art, that correspondence is intended. To the extent terminology is used in a manner other than that conventionally used to describe corresponding structure in the art, that terminology is intended to refer to that which is described herein, whether or not there is a corresponding structure in the art which would otherwise be described using that terminology. It is intended that each aspect described herein apply to every embodiment described herein, unless otherwise indicated. It should be understood that any numerical range recited herein includes all values from the lower and upper limits of that range. It should be understood that every maximum numerical limitation given throughout this specification includes every lower numerical limitation, as if each lower numerical limitation is expressly stated. It should be understood that every minimum numerical limitation given throughout this specification includes every higher numerical limitation, as if each higher numerical limitation is expressly stated. It should be understood that every numerical range recited herein includes every combination of the maximum numerical limitation and the minimum numerical limitation if such

[0171] It should be noted that, as used in this document, the terms "comprises", "comprising", or the like are intended to encompass the presence of one or more features, integers, steps, or components described herein, but do not exclude the presence of one or more other features, integers, steps, components, or groups thereof. It should be understood that every maximum numerical limitation given throughout this specification includes every lower numerical limitation, as if such lower numerical limitations were expressly written herein. It should be understood that every minimum numerical limitation given throughout this specification includes every higher numerical limitation, as if such higher numerical limitations were expressly written herein. It should be understood that every numerical range recited herein includes every combination of the maximum numerical limitation and the minimum numerical limitation if such range is expressed to include both.

[0172] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the units is only a logical functional division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interface, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0173] The units described above as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0174] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be separately as one unit, or two or more units can be integrated in one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software function unit. Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by a program instruction related hardware, and the above-mentioned program can be stored in a computer readable storage medium, and the program is executed to perform the steps of the above-mentioned method embodiments; and the above-mentioned storage medium includes a mobile storage device, a read-only memory (ReadOnly Memory, ROM), a magnetic disc or an optical disc and various storage medium capable of storing program codes.

[0175] Alternatively, the integrated unit of the present application, if realized in the form of a software function module and sold or used as an independent product, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part that contributes to the related art can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for making an electronic device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the data writing method described in each embodiment of the present application. And the above-mentioned storage medium includes a mobile storage device, a ROM, a magnetic disc or an optical disc and various storage medium capable of storing program codes.

[0176] The above is only an embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application.

Claims

1. A data write method, characterized by, The data writing method comprises: receiving a write request for a target cache line; the write request is used for writing data to a valid byte position of the target cache line; in a case where it is determined based on the write request that there is at least one invalid byte position in the target cache line, encoding the at least one invalid byte position to obtain an invalid byte encoding; the invalid byte encoding comprises a first mask used for determining one invalid byte position in the target cache line; writing the data to the valid byte position and storing the first mask; wherein, in a case where the invalid byte position is at least two, the invalid byte encoding further comprises a second mask; the first mask and all second masks are used for determining all invalid byte positions, and the second mask is stored in an invalid byte position of the target cache line.

2. The data write method of claim 1, wherein, The first mask is used for storing a first invalid byte position, and a second mask stored in a first invalid byte position is used for indicating a second invalid byte position, which is a next invalid byte position adjacent to the first invalid byte position.

3. The data write method of claim 2, wherein, The invalid byte encoding further comprises a termination mask stored in a last invalid byte position among the at least one invalid byte position.

4. The data write method of claim 1, wherein, The first mask is stored in a byte mask bit associated with the target cache line.

5. The data write method of claim 4, wherein, In a case where it is determined based on the write request that there is no invalid byte position in the target cache line, the byte mask bit is used for storing a termination mask.

6. The data write method of claim 1, wherein, The invalid byte encoding comprises N second masks in sequence, and the target cache line comprises N+1 invalid byte positions in sequence, wherein an nth second mask is stored in an nth invalid byte position, n and N are positive integers, and n is less than or equal to N.

7. The data write method of claim 1, wherein, The data writing method further comprises: performing a hit check on the write request; in a case where a result of the hit check represents a miss of the target cache line, determining an invalid byte position in the target cache line based on a valid byte position in the write request; in a case where the result of the hit check represents a hit of the target cache line, determining an invalid byte position in the target cache line based on the valid byte position in the write request and an original invalid byte encoding of the target cache line.

8. The data write method of claim 7, wherein, The determining of the invalid byte position in the target cache line based on the valid byte position in the write request and the original invalid byte encoding of the target cache line comprises: determining an original valid byte position in the target cache line based on the original invalid byte encoding; determining the invalid byte position in the target cache line based on the original valid byte position and the valid byte position in the write request.

9. The data write method of claim 8, wherein, The determining of the original valid byte position in the target cache line based on the original invalid byte encoding comprises: in a case where the original invalid byte encoding comprises an original first mask, determining at least one original invalid byte position in the target cache line based on the original invalid byte encoding; determining an original valid byte position in the target cache line based on the at least one original invalid byte position.

10. The data write method of claim 8, wherein, The determining of the original valid byte positions in the target cache line based on the original invalid byte encoding comprises: In the case that the original invalid byte encoding only comprises an original termination mask, determining that all of the target cache line are original valid byte positions.

11. The data writing method according to any one of claims 1 to 10, wherein, The encoding of the at least one invalid byte position to obtain an invalid byte encoding comprises: determining the number of encoding bits based on the byte length of the target cache line; encoding the at least one invalid byte position based on the number of encoding bits to obtain an invalid byte encoding.

12. A data writing apparatus, characterized by comprising: The data writing apparatus comprises a receiving module, an encoding module and a writing module; wherein, The receiving module is configured to receive a write request for a target cache line; the write request is configured to write data to a valid byte position of the target cache line; The encoding module is configured to, in the case that it is determined based on the write request that there is at least one invalid byte position in the target cache line, encode the at least one invalid byte position to obtain an invalid byte encoding; the invalid byte encoding comprises a first mask used to determine one invalid byte position in the target cache line; The writing module is configured to write the data to the valid byte position and store the first mask; wherein, in the case that the invalid byte position is at least two, the invalid byte encoding further comprises a second mask; the first mask and all second masks are used to determine all invalid byte positions, and the second mask is stored in the invalid byte position of the target cache line.

13. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, The processor implements the steps in the data writing method of any one of claims 1 to 11 when executing the program.

14. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the steps in the data writing method of any one of claims 1 to 11 when executed by the processor.

15. A computer program product comprising computer programs or instructions, characterized in that, The computer program or instructions implement the steps in the data writing method of any one of claims 1 to 11 when executed by the processor.

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