Interrupt processing method and device, equipment, storage medium and program product

Abstract

The invention relates to the technical field of interrupt processing, and discloses an interrupt processing method and device, equipment, a storage medium and a program product, and the method comprises the steps: setting an interrupt counter and an event counter for all interrupts, and carrying out the initialization; in response to the fact that each interrupt is triggered, entering an interrupt state when the interrupt is not shielded, updating the interrupt counter of the interrupt based on an hourglass mechanism of the interrupt counter, and judging whether the count of the interrupt counter exceeds a first preset threshold value or not after each update; if not, creating an interrupt association event of the interrupt, and updating an event counter of the interrupt; judging whether counting of the interrupted event counter exceeds a second preset threshold value or not; and if not, exiting the interrupt state, processing an interrupt associated event, and updating an interrupt event counter. According to the invention, through a dual monitoring mechanism of the interrupt counter and the event counter, in combination with the hourglass principle and threshold judgment, interrupt storm and resource exhaustion are avoided, and the system is effectively prevented from being abnormal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of interrupt processing, and in particular to an interrupt processing method, device, equipment, storage medium and program product. BACKGROUND

[0002] During the running of a program in hardware, an interrupt may be triggered, and the interrupt priority is higher than the event priority. The software needs to pause the current service and process the interrupt, but the software stays in the interrupt state for too long, which may cause system abnormality. The general processing logic is: after entering the interrupt state, memory is applied to create an interrupt-associated event, and then the interrupt is exited. After exiting, the software enters an event processing function, processes the interrupt-associated event in a non-interrupt state, and releases the memory after the processing is completed.

[0003] However, when the interrupt is triggered frequently, two situations may occur: one situation is that the software continuously stays in the interrupt state and cannot process normal services; the other situation is that the interrupt source continuously generates interrupts or the interrupt cannot be cleared, and new interrupt-associated events are continuously created in the interrupt process, and thus the memory is continuously applied. As a result, the software cannot execute the event processing function, nor can it alarm the outside world, and finally the system will be down due to exhaustion of memory resources. Therefore, how to effectively process the interrupt when the interrupt is triggered frequently to avoid system abnormality is a problem to be solved. SUMMARY

[0004] Therefore, the present application provides an interrupt processing method, device, equipment, storage medium and program product to solve the problem that the interrupt cannot be effectively processed when the interrupt is triggered frequently, resulting in system abnormality.

[0005] In a first aspect, the present application provides an interrupt processing method, which comprises:

[0006] setting and initializing an interrupt counter and an event counter for all interrupts respectively;

[0007] in response to each interrupt being triggered, entering an interrupt state of the interrupt when the interrupt is not shielded, updating the interrupt counter of the interrupt based on a sandglass mechanism of the interrupt counter, and judging whether the count of the interrupt counter exceeds a first preset threshold after each update;

[0008] when the count of the interrupt counter does not exceed the first preset threshold, creating an interrupt-associated event of the interrupt, and updating the event counter of the interrupt;

[0009] judging whether the count of the event counter of the interrupt exceeds a second preset threshold;

[0010] when the count of the event counter does not exceed the second preset threshold, exiting the interrupt state, processing the interrupt-associated event, and updating the event counter of the interrupt.

[0011] The present application sets an interrupt counter and an event counter for each interrupt, implements interrupt processing according to the counting condition, dynamically reflects the triggering frequency of the interrupt based on the sandglass mechanism of the interrupt counter, timely judges the interrupt storm phenomenon, prevents the system from being unable to process normal services due to frequent entry into the interrupt state, creates events in a safe interrupt triggering frequency, and provides data support for memory resource protection based on the counting of the event counter, preventing excessive creation of events from causing memory exhaustion. Through the double monitoring mechanism of the interrupt counter and the event counter, combined with the sandglass principle and threshold judgment, the fine control of the interrupt triggering frequency and the number of created events is realized, the interrupt storm and resource exhaustion are avoided, the system exception is effectively avoided, and the system stability and processing efficiency are balanced.

[0012] In an optional embodiment, in response to each interrupt being triggered, the interrupt state of the interrupt is entered when the interrupt is not masked, the sandglass mechanism of the interrupt counter is used to update the interrupt counter of the interrupt, and after each update, it is judged whether the counting of the interrupt counter exceeds a first preset threshold, including:

[0013] In response to each interrupt being triggered, the counting of the interrupt counter is incremented when the interrupt state of the interrupt is entered when the interrupt is not masked;

[0014] It is judged whether the counting of the interrupt counter exceeds a first preset threshold;

[0015] The counting of the interrupt counter is periodically decremented based on the system clock;

[0016] After each decrement, it is judged whether the counting of the interrupt counter exceeds the first preset threshold.

[0017] The present application increments the counting when the interrupt is triggered, and periodically decrements according to the sandglass mechanism of the system clock, to intuitively represent the actual triggering frequency of the interrupt, which helps to accurately judge whether the system has an interrupt storm.

[0018] In an optional embodiment, after judging whether the counting of the interrupt counter exceeds the first preset threshold, the method further includes:

[0019] When the counting of the interrupt counter exceeds the first preset threshold, the interrupt is masked;

[0020] The counting of the interrupt counter is periodically decremented based on the system clock;

[0021] After each decrement, it is judged whether the counting of the interrupt counter is zero;

[0022] When the counting of the interrupt counter is zero, the response of the interrupt is restored.

[0023] The application can prevent the system resources from being excessively occupied by shielding the interrupt when the interrupt counter exceeds the first preset threshold, avoid the system from being unable to process normal services due to repeatedly entering the interrupt state, periodically decrease the interrupt counter based on the system clock, and restore the response when the count is zero, which indicates that the interrupt triggering has returned to normal frequency, so as to ensure that the system can quickly respond when the interrupt frequency is abnormal and can timely release the limitation after returning to normal, thereby effectively avoiding the system abnormality.

[0024] In an alternative embodiment, before creating the interrupt-associated event of the interrupt, the method further comprises:

[0025] Clearing the interrupt signal of the interrupt;

[0026] Applying for the memory of the interrupt-associated event from the memory resource pool.

[0027] The application can avoid the system from misjudging a new interrupt triggering due to the same interrupt signal not being cleared in time, thereby preventing the system from repeatedly entering the interrupt state, and the memory application can help prevent the memory resource from being exhausted due to frequent event creation.

[0028] In an alternative embodiment, after judging whether the count of the event counter of the interrupt exceeds the second preset threshold, the method further comprises:

[0029] Shielding all interrupts when the count of the event counter of the interrupt exceeds the second preset threshold;

[0030] For each triggered interrupt, exiting the interrupt state of the triggered interrupt, calling the event processing function corresponding to the triggered interrupt, and processing all interrupt-associated events of the triggered interrupt;

[0031] Releasing the memory of the interrupt-associated event and decreasing the count of the event counter of the triggered interrupt in response to each interrupt-associated event being processed;

[0032] Restoring the response of all interrupts when the count of the event counter of the interrupt is less than the second preset threshold.

[0033] The application can shield all interrupts to prevent new events from being created when the event counter exceeds the second preset threshold, avoid the memory resource from being further occupied, prevent the system from being down due to resource exhaustion, centrally process the events to release the resources, dynamically update the event counter, and restore the response of all interrupts when the event counter is less than the second preset threshold, so that the system can process new interrupts again, protect the resources, and avoid excessive shielding from affecting normal services, thereby achieving the balance between resource protection and system function.

[0034] In an alternative embodiment, the calling is triggered to interrupt the corresponding event processing function, processing all interrupt associated events of the triggered interrupt, including:

[0035] All interrupt associated events of the triggered interrupt are sorted according to a preset rule;

[0036] The calling of the event processing function processes all interrupt associated events according to the sorting.

[0037] The present application sorts the interrupt associated events and processes them in sequence to improve the interrupt processing efficiency.

[0038] In a second aspect, the present application provides an interrupt processing device, which comprises:

[0039] The setting module is configured to set interrupt counters and event counters for all interrupts respectively and initialize them;

[0040] The first judging module is configured to, in response to each interrupt being triggered, enter the interrupt state of the interrupt when the interrupt is not shielded, update the interrupt counter of the interrupt based on the hourglass mechanism of the interrupt counter, and judge whether the count of the interrupt counter exceeds a first preset threshold after each update;

[0041] The creating module is configured to, when the count of the interrupt counter does not exceed the first preset threshold, create the interrupt associated event of the interrupt and update the event counter of the interrupt;

[0042] The second judging module is configured to judge whether the count of the event counter of the interrupt exceeds a second preset threshold;

[0043] The first processing module is configured to, when the count of the event counter does not exceed the second preset threshold, exit the interrupt state, process the interrupt associated event, and update the event counter of the interrupt.

[0044] In a third aspect, the present application provides a computer device, which comprises a memory and a processor, the memory and the processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the interrupt processing method of the first aspect or any of the corresponding embodiments thereof.

[0045] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make the computer execute the interrupt processing method of the first aspect or any of the corresponding embodiments thereof.

[0046] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions, and the computer instructions are used to make the computer execute the interrupt processing method of the first aspect or any of the corresponding embodiments thereof. Attached Figure Description

[0047] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0048] Figure 1 This is a flowchart of an interrupt handling method according to an embodiment of the present invention;

[0049] Figure 2 This is a flowchart of interrupt handling based on an interrupt counter according to an embodiment of the present invention;

[0050] Figure 3 This is a flowchart illustrating the operation of an interrupt counter according to an embodiment of the present invention;

[0051] Figure 4 This is a flowchart of interrupt handling based on an event counter according to an embodiment of the present invention;

[0052] Figure 5 This is a flowchart illustrating the operation of an event counter according to an embodiment of the present invention;

[0053] Figure 6 This is a structural block diagram of an interrupt handling device according to an embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] When the interrupt is frequently triggered, two situations can occur: one situation is that the software is continuously in the interrupt state and cannot handle normal business; the other situation is that the interrupt source continuously generates interrupts or the interrupt cannot be cleared, and new interrupt associated events are continuously created in the interrupt process, and then the memory is continuously applied, which causes the software to be unable to execute the event processing function and unable to alarm the outside world, and eventually the system will be down due to exhaustion of memory resources. Therefore, how to effectively handle the frequent triggering of the interrupt to avoid system abnormalities is a problem to be solved. The present application realizes fine control of the interrupt triggering frequency and the number of created events by the double monitoring mechanism of the interrupt counter and the event counter, in combination with the hourglass principle and threshold judgment, avoids interrupt storm and resource exhaustion, effectively avoids system abnormalities, and balances system stability and processing efficiency.

[0057] According to the embodiment of the present application, an interrupt processing method embodiment is provided. It should be noted that the steps shown in the flowchart can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from here.

[0058] In the present embodiment, an interrupt processing method is provided, which can be used in a system including hardware and software, Figure 1 is a flowchart of the interrupt processing method according to the embodiment of the present application, as Figure 1 shown, the flow includes the following steps:

[0059] Step S101, an interrupt counter and an event counter are set for all interrupts respectively and are initialized. Specifically, when the system starts, an interrupt counter and an event counter are configured for each interrupt, and the initial values of the two counters are both set to 0. Among them, the interrupt counter is used to record the number of times the corresponding interrupt is triggered, and the event counter is used to record the number of events created after the corresponding interrupt is triggered. By configuring the two counters, interrupt processing is implemented according to the counting condition, which can prevent the problems of memory resource exhaustion and interrupt storm when the interrupt is frequently triggered.

[0060] Step S102, in response to each interrupt being triggered, the interrupt state of the interrupt is entered when the interrupt is not shielded, the interrupt counter of the interrupt is updated based on the hourglass mechanism of the interrupt counter, and whether the count of the interrupt counter exceeds a first preset threshold is judged after each update. Specifically, a corresponding first preset threshold is set for each interrupt to limit the number of times the interrupt is triggered. In combination with the hourglass mechanism of the interrupt counter, the occurrence of interrupt storm can be avoided, and the system can still run normally in the case of frequent triggering of the interrupt.

[0061] Step S103, when the count of the interrupt counter does not exceed the first preset threshold, creating an interrupt associated event of the interrupt, and updating the event counter of the interrupt. Specifically, when the count of the interrupt counter does not exceed the first preset threshold, it indicates that the triggering frequency of the interrupt is within the range that the system can bear. At this time, the interrupt associated event corresponding to the interrupt is created, and the count of the event counter of the interrupt is incremented. Since the interrupt requires fast in and fast out, if the interrupt state lasts for a long time, it will cause the system to be abnormal, therefore, the system creates an event in the interrupt state, that is, the interrupt associated event, which stores the program content related to processing the interrupt, so that the interrupt can be continued to be processed when the interrupt state is exited.

[0062] Step S104, judging whether the count of the event counter of the interrupt exceeds the second preset threshold. Specifically, since creating the interrupt associated event needs to occupy the memory, the second preset threshold corresponding to each interrupt is set to restrict the number of created events of each interrupt, so as to avoid the memory resource from being exhausted when the interrupt is frequently triggered.

[0063] Step S105, when the count of the event counter does not exceed the second preset threshold, exiting the interrupt state, processing the interrupt associated event, and updating the event counter of the interrupt. Specifically, when the count of the event counter does not exceed the second preset threshold, it indicates that the memory occupied by the events that have been created is within the safe range, at this time, the interrupt associated event of the interrupt is processed, and the count of the event counter of the interrupt is decremented.

[0064] It should be noted that the first preset threshold and the second preset threshold corresponding to each interrupt are set in the embodiment of the present application, so as to realize the targeted interrupt processing.

[0065] The present application sets the interrupt counter and the event counter for each interrupt, implements the interrupt processing according to the count of the interrupt counter, dynamically reflects the triggering frequency of the interrupt based on the hourglass mechanism of the interrupt counter, judges the interrupt storm phenomenon in time, prevents the system from being unable to process the normal business due to frequently entering the interrupt state, creates the event when the interrupt triggering frequency is safe, and provides the data support for the memory resource protection based on the count of the event counter, so as to prevent the memory from being exhausted due to excessive creation of events. Through the double monitoring mechanism of the interrupt counter and the event counter, combined with the hourglass principle and the threshold judgment, the fine control of the interrupt triggering frequency and the number of created events is realized, the interrupt storm and the resource exhaustion are avoided, the system abnormality is effectively avoided, and the system stability and the processing efficiency are balanced.

[0066] In the embodiment, an interrupt processing method is provided, which can be used in the system described above, and specifically includes the following steps:

[0067] Step S201, setting the interrupt counter and the event counter for all interrupts respectively, and initializing. For details, please refer toFigure 1 Step S101 of the illustrated embodiment, which will not be described again here.

[0068] Step S202, in response to each interrupt being triggered, entering the interrupt state of the interrupt when the interrupt is not masked, updating the interrupt counter of the interrupt based on the sandglass mechanism of the interrupt counter, and judging whether the count of the interrupt counter exceeds the first preset threshold after each update.

[0069] Specifically, the above step S202 includes:

[0070] Step S2021, in response to each interrupt being triggered, entering the interrupt state of the interrupt when the interrupt is not masked, incrementing the count of the interrupt counter.

[0071] Step S2022, judging whether the count of the interrupt counter exceeds the first preset threshold.

[0072] Step S2023, periodically decrementing the count of the interrupt counter based on the system clock.

[0073] Step S2024, after each decrement, judging whether the count of the interrupt counter exceeds the first preset threshold.

[0074] Specifically, when an interrupt is triggered, if the interrupt is not masked, the interrupt is normally processed, the interrupt state of the interrupt is entered, and the count of the interrupt counter of the interrupt is incremented by 1 to record the triggering frequency of the interrupt in real time and provide data basis for judging whether an interrupt storm occurs. Then, it is judged whether the count of the interrupt counter exceeds the first preset threshold corresponding to the interrupt to timely judge whether the interrupt is triggered frequently. At the same time, a system clock is set at system startup, the initial timing of the system clock is 0, and the count of the interrupt counter is decremented every time the preset time is increased. For example, the count of the interrupt counter is decremented by 1 every time the system clock is increased by 1 second to simulate the time decay effect. Through the sandglass mechanism of incrementing the count when the interrupt is triggered and periodically decrementing according to the preset time, the actual triggering frequency of the interrupt is intuitively represented, which helps to accurately judge whether an interrupt storm occurs in the system. Moreover, if multiple interrupts are triggered in the system, the sandglass mechanism can independently operate for a single interrupt, and only the specific interrupt triggered frequently is regulated, which does not interfere with the normal response of other interrupts, balancing the system stability and business continuity.

[0075] It should be noted that the process of periodically decrementing the interrupt counter based on the system clock is continuously performed after the interrupt is triggered, that is, after the interrupt counter of the interrupt is started. The minimum value of the count of the interrupt counter is 0, and if it is decremented to 0 again, the count of the interrupt counter is still 0.

[0076] Step S203, when the count of the interrupt counter does not exceed the first preset threshold, creating an interrupt-associated event of the interrupt, and updating the event counter of the interrupt.

[0077] In some optional embodiments, before step S203 creates the interrupt-associated event of the interrupt, the method further comprises:

[0078] Step a1, clearing the interrupt signal of the interrupt.

[0079] Step a2, applying for memory of the interrupt-associated event from a memory resource pool.

[0080] Specifically, if the count of the interrupt counter does not exceed the first preset threshold, it indicates that the triggering frequency of the interrupt is within the range that the system can bear, and the interrupt can be normally processed. First, the interrupt signal of the interrupt is cleared. If it is not cleared in time, the system may mistakenly believe that a new interrupt is triggered, thereby repeatedly entering the interrupt state. Then, the memory required for the interrupt-associated event is applied for from the memory resource pool of the system, so as to create the interrupt-associated event by using the memory. It should be noted that only one interrupt-associated event corresponding to one interrupt can be created each time the interrupt is triggered, and the count of the event counter of the interrupt is increased by 1 each time an interrupt-associated event is created. If the interrupt is triggered multiple times, the corresponding interrupt-associated event can be created after each triggering, and the interrupt can correspond to one or more interrupt-associated events during multiple triggering.

[0081] Step S204, when the count of the interrupt counter exceeds the first preset threshold, masking the interrupt.

[0082] Step S205, periodically decreasing the count of the interrupt counter based on the system clock.

[0083] Step S206, after each decrease, judging whether the count of the interrupt counter is zero.

[0084] Step S207, when the count of the interrupt counter is zero, restoring the response of the interrupt.

[0085] Specifically, when the count of the interrupt counter of a certain interrupt exceeds the corresponding first preset threshold, it indicates that the interrupt is triggered too frequently, forming an interrupt storm, and if the response continues, the system will continuously enter the interrupt state, occupying a large amount of resources and being unable to process normal business. Therefore, the interrupt needs to be temporarily masked to protect the system. After the interrupt is masked, the hardware cannot respond to the triggering of the interrupt again. To avoid the permanent masking affecting the processing of subsequent normal interrupts, the interrupt counter needs to be decreased by the system clock, and the response is automatically restored when the triggering frequency returns to normal. More specifically, if the interrupt is masked, the count will be judged to be zero after each decrease. If the count is zero, the response to the interrupt is restored, and at this time the hardware can normally trigger the interrupt, achieving the balance between suppressing the interrupt storm and normally responding to the interrupt.

[0086] In some optional embodiments, assuming that the serial port interrupt is triggered 10 times within 1 second, and the system clock is counted by 1 every time the system clock increases by 1 second, it can be known that the count of the current interrupt counter is 9, which exceeds the first preset threshold value 5, indicating that the serial port interrupt appears an interrupt storm, and the serial port interrupt is shielded. The periodic decrement based on the system clock is continued, and after each decrement, it is judged whether the count is zero. After 10 seconds, the count of the interrupt counter is decremented to 0, and the serial port interrupt is restored.

[0087] In some optional embodiments, Figure 2 is a flowchart of interrupt processing based on an interrupt counter according to an embodiment of the present application, as Figure 2 shown, a hardware triggered interrupt, and the software judges whether the interrupt is shielded. If the interrupt is not shielded, the interrupt state of the interrupt is entered, and the count of the interrupt counter of the interrupt is added by 1. It is judged whether the count of the interrupt counter exceeds the first preset threshold value corresponding to the interrupt. If it exceeds, the interrupt is shielded. If it does not exceed, the interrupt signal of the interrupt is cleared, the memory of the interrupt associated event is applied from the memory resource pool, and the interrupt associated event of the interrupt is created. Then, the interrupt state is exited, the event processing function of the interrupt is used to process the interrupt associated event, the memory is released after the processing is completed, and the normal business before the interrupt is triggered is continued to be executed. Figure 3 is a working flowchart of an interrupt counter according to an embodiment of the present application, as Figure 3 shown, the system clock is set when the system is started, and the interrupt counter is set for each interrupt. When the interrupt is triggered each time, if the interrupt state is entered, the count of the corresponding interrupt counter is added by 1. At the same time, the count of the interrupt counter of all interrupts is decremented by 1 every time the system clock increases by a preset time. If Figure 2 the interrupt is shielded, the count of the interrupt counter is periodically decremented based on the system clock until it is zero, and the response of the interrupt is restored.

[0088] Step S208, judging whether the count of the event counter of the interrupt exceeds the second preset threshold value. For details, please refer to step S104 of the embodiment shown in Figure 1 , which will not be repeated here.

[0089] Step S209, when the count of the event counter does not exceed the second preset threshold, exit the interrupt state, process the interrupt-associated events, and update the event counter of the interrupt. Specifically, when the count of the event counter does not exceed the second preset threshold, it indicates that the number of interrupt-associated events created by the interrupt is still within the safe range that the system memory can bear. At this time, the software first exits the interrupt state, calls the event processing function corresponding to the interrupt, and processes the associated events in order. After processing each interrupt-associated event, the count of the event counter is decremented by 1 to reflect the remaining number of unprocessed events in real time, ensuring that the count accurately reflects the actual occupation of memory resources.

[0090] Step S2010, when the count of the event counter of the interrupt exceeds the second preset threshold, mask all interrupts.

[0091] Step S2011, for each triggered interrupt, exit the interrupt state of the triggered interrupt, call the event processing function corresponding to the triggered interrupt, and process all interrupt-associated events of the triggered interrupt.

[0092] In some optional embodiments, step S2011 calls the event processing function corresponding to the triggered interrupt to process all interrupt-associated events of the triggered interrupt, including:

[0093] Step b1, sort all interrupt-associated events of the triggered interrupt according to a preset rule.

[0094] Step b2, call the event processing function to process all interrupt-associated events according to the sorting.

[0095] Step S2012, in response to the completion of processing each interrupt-associated event, release the memory of the interrupt-associated event, and decrement the count of the event counter of the triggered interrupt.

[0096] Step S2013, when the count of the event counter of the interrupt is less than the second preset threshold, restore the response of all interrupts.

[0097] Specifically, when the count of the event counter of a certain interrupt A exceeds its corresponding second preset threshold, it indicates that the number of interrupt-associated events currently created is close to the upper limit of the system memory carrying capacity. At this time, in order to avoid running out of memory resources, all interrupts are shielded, and all interrupt-associated events of the interrupts are processed collectively. In particular, the NMI interrupt cannot be shielded, and the interrupt is triggered only when the system has a catastrophic failure. At this time, the system has collapsed, and the interrupt needs to be connected to an external device, such as a CPLD (Complex Programmable Logic Device) or a BMC (Baseboard Management Controller), so that the external device can record the triggering of the interrupt. By closing the global interrupt, the new interrupt trigger cannot enter the interrupt state, avoiding the occupation of memory by continuously creating events, and preventing the system from crashing due to resource exhaustion. After the global interrupt is shielded, for all triggered interrupts that have triggered and are in the interrupt state, each triggered interrupt is caused to exit the interrupt state, and the event processing function corresponding to the triggered interrupt is called to collectively process all interrupt-associated events thereof. After each interrupt-associated event is processed, the memory occupied by the event is released, and the count of the corresponding event counter is reduced by 1. The count of the event counter of the interrupt A is continuously judged, and when the count falls below the second preset threshold, it indicates that the memory resources have recovered to a safe range, the system reopens the global interrupt, and the response ability to all interrupts is restored, realizing the dynamic balance between protecting memory resources and normally processing interrupts.

[0098] More specifically, when each triggered interrupt processes all interrupt-associated events thereof, the interrupt-associated events can be sorted according to a preset rule, such as the creation time, and processed in order. Since the hardware can trigger multiple interrupts at the same time, all interrupts process their respective interrupt-associated events in parallel to improve the interrupt processing efficiency.

[0099] In some optional embodiments, it is assumed that the hardware triggers three interrupts, and the count of the event counter of the serial port interrupt is 5, which exceeds the second preset threshold 3. At this time, all interrupts are shielded. For the three interrupts, the interrupt-associated events are processed in order respectively, and the count is reduced by 1 after each interrupt-associated event is processed, until the count of the event counter of the serial port interrupt is 3, at which time the response of all interrupts is restored.

[0100] In some optional embodiments, Figure 4 is a flowchart of interrupt processing based on an event counter according to an embodiment of the application, as Figure 4As shown, the hardware triggers the interrupt, and if the interrupt is not masked, the software enters the interrupt state of the interrupt. Assuming that the interrupt counter of the interrupt does not exceed the first preset threshold, the interrupt signal of the interrupt is cleared, the memory of the interrupt associated event is applied for from the memory resource pool, the interrupt associated event of the interrupt is created, and the count of the event counter of the interrupt is increased by 1. It is determined whether the count exceeds the second preset threshold. If yes, all interrupts are masked. If no, the interrupt state is exited, the interrupt associated event is processed by using the event processing function of the interrupt, the memory is released after the processing is completed, the count of the event counter is decreased by 1, and the normal business before triggering the interrupt is continued to be executed. Figure 5 is a working flow chart of the event counter according to the embodiment of the application, as shown in Figure 5 As shown, if the count of the event counter of the interrupt A exceeds the second preset threshold, the software masks all interrupts. For each triggered interrupt, all interrupt associated events created therefor are sorted according to a preset rule, and are processed in sequence by using the event processing function. After each interrupt associated event is processed, the count of the event counter is decreased by 1. It is continuously determined whether the count of the event counter of the interrupt A is less than the second preset threshold. If yes, the response of all interrupts is restored.

[0101] The application sets the interrupt counter and the event counter for each interrupt, implements interrupt processing according to the counts thereof, dynamically reflects the triggering frequency of the interrupt based on the hourglass mechanism of the interrupt counter, timely judges the interrupt storm phenomenon, prevents the system from being unable to process the normal business due to frequent entry into the interrupt state, creates the event when the triggering frequency of the interrupt is safe, and provides data support for the memory resource protection based on the count of the event counter, thereby preventing the memory from being exhausted due to excessive creation of the event. Through the double monitoring mechanism of the interrupt counter and the event counter, the fine control of the triggering frequency of the interrupt and the number of created events is realized by combining the hourglass principle and the threshold judgment, the interrupt storm and the resource exhaustion are avoided, the system exception is effectively avoided, and the system stability and the processing efficiency are balanced.

[0102] In the embodiment, an interrupt processing apparatus is also provided, which is used to implement the above-described embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0103] The embodiment provides an interrupt processing apparatus, as shown in Figure 6 The apparatus comprises:

[0104] The setting module 601 is configured to set the interrupt counter and the event counter for all interrupts respectively, and to initialize.

[0105] The first judging module 602 is configured to, in response to each interrupt being triggered, enter an interrupt state of the interrupt when the interrupt is not shielded, update an interrupt counter of the interrupt based on a sandglass mechanism of the interrupt counter, and determine whether the count of the interrupt counter exceeds a first preset threshold after each update.

[0106] The creating module 603 is configured to, when the count of the interrupt counter does not exceed the first preset threshold, create an interrupt-related event of the interrupt, and update an event counter of the interrupt.

[0107] The second judging module 604 is configured to determine whether the count of the event counter of the interrupt exceeds a second preset threshold.

[0108] The first processing module 605 is configured to, when the count of the event counter does not exceed the second preset threshold, exit the interrupt state, process the interrupt-related event, and update the event counter of the interrupt.

[0109] In some optional embodiments, the first judging module 602 comprises:

[0110] The first updating unit is configured to, in response to each interrupt being triggered, enter an interrupt state of the interrupt when the interrupt is not shielded, and make the count of the interrupt counter increase.

[0111] The first judging unit is configured to determine whether the count of the interrupt counter exceeds a first preset threshold.

[0112] The second updating unit is configured to periodically decrease the count of the interrupt counter based on a system clock.

[0113] The second judging unit is configured to, after each decrease, determine whether the count of the interrupt counter exceeds the first preset threshold.

[0114] In some optional embodiments, after the first judging module 602, the apparatus further comprises:

[0115] The first shielding module is configured to shield the interrupt when the count of the interrupt counter exceeds the first preset threshold.

[0116] The first updating module is configured to periodically decrease the count of the interrupt counter based on a system clock.

[0117] The third judging module is configured to, after each decrease, determine whether the count of the interrupt counter is zero.

[0118] The first restoring module is configured to, when the count of the interrupt counter is zero, restore the response of the interrupt.

[0119] In some optional embodiments, before the creating module 603, the apparatus further comprises:

[0120] The clearing module is configured to clear the interrupted interrupt signals.

[0121] The application module is configured to apply for memory of the interrupt-associated events from the memory resource pool.

[0122] In some optional embodiments, after the second judging module 604, the apparatus further comprises:

[0123] The second shielding module is configured to shield all interrupts when the count of the interrupted event counter exceeds the second preset threshold.

[0124] The second processing module is configured to, for each triggered interrupt, exit the interrupt state of the triggered interrupt, call the event processing function corresponding to the triggered interrupt, and process all interrupt-associated events of the triggered interrupt.

[0125] The second updating module is configured to, in response to completion of processing of each interrupt-associated event, release the memory of the interrupt-associated event, and decrease the count of the event counter of the triggered interrupt.

[0126] The second restoring module is configured to, when the count of the interrupted event counter is less than the second preset threshold, restore the response of all interrupts.

[0127] In some optional embodiments, the second processing module comprises:

[0128] The sorting unit is configured to sort all interrupt-associated events of the triggered interrupt according to a preset rule.

[0129] The processing unit is configured to call the event processing function to process all interrupt-associated events according to the sorting.

[0130] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be repeated here.

[0131] The interrupt processing apparatus in the embodiment is presented in the form of functional units. The units herein refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories executing one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.

[0132] The embodiment of the present application further provides a computer device having the above-mentioned Figure 6 interrupt processing apparatus.

[0133] Please refer to Figure 7 , Figure 7 is a structural schematic diagram of a computer device provided by an optional embodiment of the present application, as Figure 7As shown, the computer device includes one or more processors 10, memory 20, and interfaces 30 for external devices such as a keyboard and a mouse and peripheral devices such as disk devices or other storage devices. One or more busses 10 can be used to implement the interface between the various circuits and components of the computer device. It will be appreciated that the bus 10 can be implemented using any one or more of a variety of bus structures, such as a Peripheral Component Interconnect (PCI) bus, a Bluetooth bus, an Industry Standard Architecture (ISA) bus, an Enhanced ISA bus, an Accelerated Graphics Port (AGP) bus, a Video Electronics Standards Association (VESA) local bus, a Micro Channel Architecture (MCA) bus, a Universal Serial Bus (USB), and the like. Figure 7 The processor 10 is used in the embodiments as an example.

[0134] The processor 10 can be a central processing unit, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0135] The memory 20 stores instructions that can be executed by the at least one processor 10, so that the at least one processor 10 can perform the method shown in the above embodiments.

[0136] The memory 20 can include a program region and a data region. The program region can store an operating system and application programs required by at least one function. The data region can store data created by the use of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some alternative embodiments, the memory 20 can optionally include a memory that is remotely arranged with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0137] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned memories.

[0138] The computer device further includes a communication interface 30 for communication with other devices or communication networks.

[0139] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0140] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in a computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way of executing computer program instructions by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0141] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. An interrupt handling method, characterized in that, The method includes: Set and initialize the interrupt counter and event counter for each interrupt separately; In response to each interrupt being triggered, when the interrupt is not masked, the interrupt state of the interrupt is entered. Based on the hourglass mechanism of the interrupt counter, the interrupt counter of the interrupt is updated, and after each update, it is determined whether the count of the interrupt counter exceeds a first preset threshold. When the count of the interrupt counter does not exceed the first preset threshold, an interrupt-associated event for the interrupt is created, and the event counter for the interrupt is updated. Determine whether the count of the interrupted event counter exceeds a second preset threshold; When the count of the event counter does not exceed the second preset threshold, the interrupt state is exited, the interrupt-related event is processed, and the interrupt event counter is updated.

2. The method according to claim 1, characterized in that, The response, upon each interrupt being triggered, enters the interrupt state when the interrupt is not masked, updates the interrupt counter based on the hourglass mechanism of the interrupt counter, and determines whether the interrupt counter count exceeds a first preset threshold after each update, including: In response to each interrupt being triggered, if the interrupt is not masked, the interrupt enters the interrupt state and increments the interrupt counter. Determine whether the count of the interrupt counter exceeds the first preset threshold; The interrupt counter is periodically decremented based on the system clock. After each decrement, it is determined whether the count of the interrupt counter exceeds the first preset threshold.

3. The method according to claim 2, characterized in that, After determining whether the interrupt counter count exceeds the first preset threshold, the method further includes: When the interrupt counter exceeds the first preset threshold, the interrupt is disabled; The interrupt counter is periodically decremented based on the system clock. After each decrement, determine whether the interrupt counter has reached zero; When the interrupt counter reaches zero, the interrupt response is resumed.

4. The method according to claim 1, characterized in that, Before creating the interrupt-associated event for the interrupt, the method further includes: Clear the interrupt signal that caused the interruption; Request memory for the interrupt-related event from the memory resource pool.

5. The method according to claim 4, characterized in that, After determining whether the count of the interrupted event counter exceeds a second preset threshold, the method further includes: When the count of the interrupted event counter exceeds the second preset threshold, all interrupts are blocked; For each triggered interrupt, exit the interrupt state of the triggered interrupt, call the event handling function corresponding to the triggered interrupt, and process all interrupt-related events of the triggered interrupt; In response to the completion of each interrupt-related event processing, the memory of the interrupt-related event is released, and the count of the event counter of the triggered interrupt is decremented; When the count of the interrupted event counter is less than the second preset threshold, the response to all interrupts is restored.

6. The method according to claim 5, characterized in that, The invocation of the event handling function corresponding to the triggered interrupt to process all interrupt-related events of the triggered interrupt includes: Sort all interrupt-related events that have been triggered according to a preset rule; The event handling function is invoked to process all interrupt-related events in order.

7. An interrupt handling device, characterized in that, The device includes: The configuration module is used to set and initialize the interrupt counter and event counter for each interrupt. The first judgment module is used to respond to each interrupt being triggered, enter the interrupt state of the interrupt when the interrupt is not masked, update the interrupt counter of the interrupt based on the hourglass mechanism of the interrupt counter, and determine whether the count of the interrupt counter exceeds a first preset threshold after each update. A creation module is used to create an interrupt-associated event for the interrupt and update the event counter for the interrupt when the count of the interrupt counter does not exceed the first preset threshold. The second judgment module is used to determine whether the count of the interrupted event counter exceeds a second preset threshold. The first processing module is used to exit the interrupt state, process the interrupt-related event, and update the interrupt event counter when the count of the event counter does not exceed the second preset threshold.

8. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the interrupt handling method of any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the interrupt handling method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, Includes computer instructions for causing a computer to execute the interrupt handling method according to any one of claims 1 to 6.

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