Signal analysis method, device and equipment of high-speed protocol and medium
By obtaining the clock signal through linear fitting of the logic sequence and time sequence, and combining techniques such as sliding window and protocol state machine, the problem of low accuracy in high-speed bus signal analysis is solved, and efficient parsing of PCIe bus signals is achieved.
Patent Information
- Application Number
- CN202511100933.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-11-18
AI Technical Summary
Existing signal analysis methods are not very accurate for signals based on high-speed protocols, especially in high-speed bus systems such as PCIe, where it is difficult to achieve efficient and accurate data transmission and control.
By acquiring the signal to be processed and determining the logic sequence and time sequence according to the high-speed protocol, linear fitting is performed to recover the clock signal. Combined with techniques such as sliding window and protocol state machine, efficient parsing of high-speed bus signals is achieved.
It improves the accuracy and speed of high-speed protocol signal analysis, and can effectively analyze complex and high-speed PCIe bus signals.
Smart Images
Figure CN120974155A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal transmission and analysis technology, and in particular to a signal analysis method, apparatus, device and medium for a high-speed protocol. Background Technology
[0002] With the increasing complexity of modern electronic devices, the requirements for data transmission and processing are also constantly improving. As a basic architecture for data transmission, bus technology is widely used in many fields such as computers, communications, automotive electronics, and embedded systems. Bus decoding, as the core part of bus communication, plays a crucial role in the efficient and accurate transmission and control of data, especially in high-speed bus systems such as PCIe.
[0003] Existing signal analysis methods are generally based on oscilloscopes, using edge search and sampling to analyze signals. This method is only suitable for low-speed buses, so most oscilloscopes can only decode low-speed protocols.
[0004] However, existing signal analysis methods suffer from low accuracy in analyzing signals based on high-speed protocols. Summary of the Invention
[0005] This application provides a signal analysis method, apparatus, device, and medium for high-speed protocols, to solve the problem that existing signal analysis methods have low accuracy in analyzing signals based on high-speed protocols.
[0006] Firstly, this application provides a signal analysis method for a high-speed protocol, the method comprising: According to the high-speed protocol, the signal to be processed is acquired, and the logical sequence is determined based on the comparison results between each signal to be processed and the threshold of the target signal. Based on the time points corresponding to each change edge in the logic sequence and the target time width, the target time sequence is determined, and the logic sequence and the target time sequence are linearly fitted to obtain the clock signal. Based on the falling edge of the clock signal, the signal to be processed is acquired to obtain the corresponding logic signal, and the logic signal is identified sequentially according to the time window and the recognition width. When the target identification code is identified, the identification width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted one by one according to the time window and the adjusted identification width to obtain the target logic signal segment; Based on the logic code and information protocol of the high-speed protocol, determine the target information corresponding to the target logic signal segment.
[0007] In some embodiments of this application, a signal to be processed is acquired according to a high-speed protocol, and a logical sequence is determined based on the comparison results between each signal to be processed and a target signal threshold, including: The standard threshold is determined based on the sum of the peak and valley values in the signal to be processed, and the deviation threshold is determined based on the difference. The sum of the standard threshold and the deviation threshold is determined as the highest signal threshold, and the difference between the standard threshold and the deviation threshold is determined as the lowest signal threshold. Based on the highest signal threshold and the lowest signal threshold, the target signal threshold is obtained. The signal strength of each signal to be processed is compared with the highest signal threshold and the lowest signal threshold to obtain the comparison result; If the comparison result shows that the signal to be processed is less than the minimum signal threshold, then the logic value corresponding to the signal to be processed is determined to be a low logic value. If the comparison result shows that the signal to be processed is greater than the highest signal threshold, then the logic value corresponding to the signal to be processed is determined to be a high logic value. If the comparison result is that the signal to be processed is greater than the lowest signal threshold and less than the highest signal threshold, then the logic value corresponding to the signal to be processed is determined to be the logic value of the previous signal to be processed. Based on the logic values corresponding to each signal to be processed, a logic sequence is obtained.
[0008] In some embodiments of this application, a target time series is determined based on the time points corresponding to each change edge in the logical sequence and the target time width, and a clock signal is obtained by linearly fitting the logical sequence and the target time series, including: Calculate the time difference between any two adjacent change edges in the logical sequence to obtain the time width sequence, and determine the target time width by multiplying the time difference with the smallest difference by a preset threshold. Based on the time width sequence and the target time width, the target time sequence is determined, and the logic sequence and the target time sequence are linearly fitted to obtain the clock signal.
[0009] In some embodiments of this application, a target time series is determined based on a time-width sequence and a target time-width sequence, and a clock signal is obtained by linearly fitting the logic sequence and the target time series, including: Based on the difference between any two adjacent time widths in the time width sequence, determine the division values of multiple differences with the target time width to obtain the target time sequence. Then, based on the least squares method, perform linear fitting on the logic sequence and the target time sequence to obtain the target clock period and the target clock deviation value. The clock signal is determined based on the target clock period and the target clock deviation value.
[0010] In some embodiments of this application, the signal to be processed is acquired based on the falling edge of the clock signal to obtain the corresponding logic signal, and the logic signal is identified sequentially according to the time window and the recognition width, including: Collect the target signals to be processed from the signals to be processed corresponding to the falling edge of the change, and determine the corresponding logic signals based on the signal voltage values corresponding to each target signal to be processed; Based on the time window, the logic signal is identified to obtain the logic signal segment with the window width. Then, based on the identification width, the time window is slid successively to obtain multiple logic signal segments identified by the time window.
[0011] In some embodiments of this application, when a target identification code is detected, the identification width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted sequentially according to the time window and the adjusted identification width to obtain the target logic signal segment, including: The recognition width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted one by one according to the time window and the adjusted recognition width to obtain multiple corresponding initial logic signal segments. Based on the preset logical signal mapping relationship, each initial logical signal segment is mapped to the corresponding target logical signal segment.
[0012] In some embodiments of this application, the target information corresponding to the target logical signal segment is determined based on the logic code and information protocol of the high-speed protocol, including: Based on the sequence corresponding to the logic code, determine a preset number of high-order logic bits, and perform an XOR operation on the target logic signal segment and the high-order logic bits to obtain the information to be converted; According to the information protocol, the protocol to be converted is converted to obtain the target information.
[0013] Secondly, this application provides a signal analysis device for a high-speed protocol, the device comprising: The signal acquisition function is used to acquire the signal to be processed according to the high-speed protocol, and to determine the logical sequence based on the comparison results between each signal to be processed and the target signal threshold. The fitting module is used to determine the target time series based on the time points corresponding to each change in the logic sequence and the target time width, and to perform linear fitting between the logic sequence and the target time series to obtain the clock signal; The acquisition module is used to acquire the signal to be processed based on the falling edge of the clock signal, obtain the corresponding logic signal, and identify the logic signal one by one according to the time window and the recognition width. The extraction module is used to adjust the recognition width to the window width of the time window when the target identification code is recognized, and extract the logic signal after the target identification code one by one according to the time window and the adjusted recognition width to obtain the target logic signal segment; The determination module is used to determine the target information corresponding to the target logic signal segment based on the logic code and information protocol of the high-speed protocol.
[0014] Thirdly, this application provides an apparatus, including: a processor, and a memory communicatively connected to the processor; The memory stores the instructions that the computer executes; The processor executes computer execution instructions stored in memory to implement the method of this application.
[0015] Fourthly, this application provides a computer-readable storage medium storing program code, which, when executed by a processor, is used to implement the method of this application.
[0016] This application provides a signal analysis method, apparatus, device, and medium for a high-speed protocol. The method involves: acquiring a signal to be processed according to the high-speed protocol; determining a logical sequence based on the comparison results between each signal to be processed and a target signal threshold; determining a target time sequence based on the time points corresponding to each change edge in the logical sequence and the target time width; linearly fitting the logical sequence and the target time sequence to obtain a clock signal; acquiring the signal to be processed based on the falling edge of the clock signal to obtain the corresponding logical signal; sequentially identifying the logical signal according to a time window and an identification width; when a target identification code is identified, adjusting the identification width to the window width of the time window; and sequentially extracting the logical signal after the target identification code according to the time window and the adjusted identification width to obtain a target logical signal segment; and determining the target information corresponding to the target logical signal segment based on the logic code and information protocol of the high-speed protocol.
[0017] In this way, clock recovery can be performed on signals transmitted via high-speed bus, and signal acquisition can be performed based on the recovered clock. This enables signal acquisition based on a more flexible recovered clock signal, which can handle complex and high-speed protocols, improve the speed and accuracy of protocol analysis, and achieve efficient parsing of high-speed PCIe bus signals by combining various technologies such as sliding window search frame header, signal descrambling, and protocol state machine. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0019] Figure 1A flowchart illustrating a signal analysis method for a high-speed protocol provided in an embodiment of this application; Figure 2 A schematic diagram of a signal analysis method for a high-speed protocol provided in an embodiment of this application; Figure 3 An encoding schematic diagram of a signal analysis method for a high-speed protocol provided in an embodiment of this application; Figure 4 A schematic diagram of a signal analysis method for a high-speed protocol provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a target object identification device provided in an embodiment of this application; Figure 6 This is a structural block diagram of an apparatus for performing a signal analysis method according to a high-speed protocol according to an embodiment of this application. Detailed Implementation
[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0021] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0022] Figure 1 This is a flowchart illustrating a signal analysis method for a high-speed protocol provided in an embodiment of this application. Figure 1 As shown, the signal analysis method for this high-speed protocol may include the following steps: S110. According to the high-speed protocol, acquire the signal to be processed, and determine the logical sequence based on the comparison results between each signal to be processed and the target signal threshold.
[0023] Among them, a high-speed protocol refers to a set of communication rules used in high-speed data transmission scenarios. It defines the data format, transmission rate, timing, error checking, interaction logic, etc., to ensure that the device can communicate reliably under high bandwidth and high frequency conditions. A bus is a physical or logical transmission channel, composed of wires, interfaces, electrical characteristics, etc. It is the hardware carrier for data transmission. The protocol is the data transmission rule on the bus, which specifies how to transmit data through the bus, including data format, rate, interaction process, etc.
[0024] The signal to be processed is a signal transmitted via a high-speed protocol that requires signal analysis. By analyzing the signal to be processed, the information corresponding to the signal can be determined.
[0025] The target signal threshold is used to compare with the signal to be processed, thereby mapping the signal to be processed into the corresponding logic signal.
[0026] The logic sequence is the sequence of logic values corresponding to the signal to be processed. By comparing the signal to be processed with the threshold of the target signal, the signal to be processed is mapped to the corresponding logic value according to different comparison results, thus obtaining the logic sequence.
[0027] Based on this, the signal to be processed transmitted by the high-speed protocol is acquired so that the signal to be processed and the target signal threshold can be compared. Based on the comparison result, each signal to be processed is mapped to the corresponding logical value to obtain a logical sequence. Then, based on the logical sequence, the clock information corresponding to the signal to be processed can be further determined.
[0028] S120. Based on the time points corresponding to each change edge in the logic sequence and the target time width, determine the target time sequence, and perform linear fitting on the logic sequence and the target time sequence to obtain the clock signal.
[0029] The transition edge is the edge of the sequence, which refers to the instant when the signal logic value jumps from one state to another. In a logic sequence composed of 0 and 1, the transition edge includes rising edge and falling edge. Rising edge means that the logic value jumps from 0 to 1, and falling edge means that the logic value jumps from 1 to 0.
[0030] The target time width can be understood as the target symbol width in the logical sequence. A symbol is the basic unit that carries information in digital communication (such as a binary symbol corresponding to 0 or 1), and the symbol width is the length occupied by a symbol on the time axis, representing the time width corresponding to the symbol. The target time width is determined by the time difference between any two adjacent edges in the logical sequence, so that the clock signal can be determined subsequently based on the target time width.
[0031] The target time series is a time width series constructed based on the symbol width. It is a quantitative representation of the theoretical symbol timing changes. Based on the target symbol width, the relative changes in the widths of adjacent symbols are accumulated to characterize the time progression law of symbol transmission under ideal conditions. It provides a theoretical time reference framework for clock calculation, which is equivalent to constructing an ideal symbol time axis.
[0032] Linear fitting is a method that approximates the trend of a data sequence by using a straight line. By finding an optimal straight line that closely approximates the data points in the sequence, it simplifies discrete, potentially noisy data into a single straight line, removes detail interference, and highlights the core trend.
[0033] A clock signal is a clock signal that is restored from a high-speed serial signal (such as a PCIe bus signal) and synchronized with the signal source. During the transmission of high-speed bus signals, the clock information is usually mixed with the data signal rather than transmitted separately. Since the oscilloscope acquires a continuous voltage signal, it is necessary to extract the original clock information from the signal transition edges, symbol width, and other characteristics. This process is called clock recovery, and the obtained clock signal is the recovered clock signal.
[0034] Based on this, the corresponding target time sequence is determined by identifying the time points and target time widths of each transition edge in the logical sequence. The target time sequence is constructed based on the symbol width and is a theoretical quantitative representation of symbol timing changes. It can accumulate the relative changes in the widths of adjacent symbols with the target time width as a benchmark. It can be understood that the target time sequence can reflect the time progression law of symbol transmission under ideal conditions, which is equivalent to constructing an ideal symbol time axis. The logical sequence is the observation value corresponding to the signal edge crossover sequence, that is, the real time point of the signal edge acquired by the oscilloscope. It includes the influence of actual interference factors such as jitter and noise during signal transmission and reflects the actual occurrence time of the signal edge transition. During the clock recovery process, the logical sequence can serve as a real time data sample. Therefore, the combination of the target time sequence and the logical sequence can provide a practical time reference for the least squares method. That is, by fitting the target time sequence and the logical sequence with the least squares method, the corresponding clock signal can be determined, thereby determining the original clock information synchronized with the signal source.
[0035] S130. Acquire the signal to be processed according to the falling edge of the clock signal to obtain the corresponding logic signal, and identify the logic signal one by one according to the time window and the recognition width.
[0036] Among them, the logic signal is the logic value corresponding to the voltage value of the signal. It is used to convert the continuous voltage signal acquired by the oscilloscope into discrete binary logic values, thereby establishing the correspondence between voltage and digital signal. The underlying information transmission of digital circuits is represented in binary (0 / 1). That is, the PCIe bus transmission is essentially a binary data stream. The voltage needs to be converted into the corresponding logic signal 0 / 1 in order to align with the information representation method of the digital system so as to determine the target information carried by the signal.
[0037] A time window is a fixed-length observation interval set during signal processing. It can be moved along the time axis to identify and compare logical signals within the time window.
[0038] The recognition width is the moving width of the time window, which is the distance the time window moves each time it moves along the time axis. It can also be understood as the sliding step size of the time window. The recognition width can be a bit value so that the time window can slide and recognize the logic signal one by one.
[0039] Based on this, by acquiring the signal corresponding to the falling edge of the clock signal in the signal to be processed, the signal voltage is further converted into the corresponding logic value to obtain the logic signal. Then, the logic signal is identified according to the time window, and the time window is slid according to the identification width to identify the corresponding logic signal one by one.
[0040] S140. When the target identification code is identified, the identification width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted sequentially according to the time window and the adjusted identification width to obtain the target logic signal segment.
[0041] The target identification code refers to a pre-determined logical signal segment, which can be understood as an identifier or feature code in a logical signal, and can be a signal frame header.
[0042] The window width is the width of the logic signal within the time window. For example, if the window width of the time window is 10 bits, then the time window will identify 10 bits of data in the logic signal each time.
[0043] The target logic signal segment is the logic signal segment obtained by extracting the logic signal after the target identification code within a time window after the target identification code is identified.
[0044] Please refer to Figure 2 , Figure 2 A schematic diagram of a signal analysis method for a high-speed protocol provided in an embodiment of this application; as shown Figure 2As shown, the PCIe protocol frame needs to find the COMMA code. The COMMA code value is 0xBC, and the corresponding 10-bit value is 0x305 or 0xFA. The COMMA code is searched based on a sliding window. When the element value in the window is 0x305, that is, 1100000101, it means that the PCIe frame header has been found. The position of the frame header is recorded, and the recognition width of the window is adjusted to 10 bits. In this way, each 10-bit logical signal segment after the frame header is identified to obtain the target logical signal segment.
[0045] Based on this, the logic signal is identified through a time window. After the target identification code is identified, the identification width is adjusted to the window width of the time window so that the logic signal after the target identification code can be extracted to obtain multiple target logic signal segments.
[0046] S150. Based on the logic code and information protocol of the high-speed protocol, determine the target information corresponding to the target logic signal segment.
[0047] Among them, the logic code is the characteristic logic code used for signal descrambling; in the PCIe protocol, in order to avoid signal transmission errors caused by consecutive identical bits (such as a long string of "0" or "1"), the transmitting end will scramble the data. Descrambling is the reverse process of scrambling. Its purpose is to recover the original data and provide correct information for subsequent protocol decoding. PCIe scrambling is mainly achieved by XORing the high 8 bits of the linear cyclic shift register value lfsr[15:8] with the logic signal. The logic code is the high 8 bits of the shift register corresponding to the PCIe protocol.
[0048] The information protocol refers to the protocol corresponding to PCIe, which is used to convert signals into corresponding information. According to the PCIe protocol specification, the descrambled raw data is structured and parsed to extract various fields contained in the protocol frame (such as packet type, address, data payload, checksum, etc.), thereby converting it into an understandable format (such as hexadecimal, text description) to obtain the target information.
[0049] Target information refers to the information carried by the transmitted signal, which conforms to the protocol format.
[0050] Based on this, the corresponding protocol code of the high-speed protocol is used to perform the corresponding descrambling operation according to the protocol code and the target logic signal segment, and the descrambling logic signal is converted according to the information protocol to obtain the target information.
[0051] Based on the feasible implementation of S110 described above, this application further provides the following steps: acquiring the signal to be processed according to a high-speed protocol, and determining the logical sequence based on the comparison results of each signal to be processed and the target signal threshold; The standard threshold is determined based on the sum of the peak and valley values in the signal to be processed, and the deviation threshold is determined based on the difference. The sum of the standard threshold and the deviation threshold is determined as the highest signal threshold, and the difference between the standard threshold and the deviation threshold is determined as the lowest signal threshold. Based on the highest signal threshold and the lowest signal threshold, the target signal threshold is obtained. The signal strength of each signal to be processed is compared with the highest signal threshold and the lowest signal threshold to obtain the comparison result; If the comparison result shows that the signal to be processed is less than the minimum signal threshold, then the logic value corresponding to the signal to be processed is determined to be a low logic value. If the comparison result shows that the signal to be processed is greater than the highest signal threshold, then the logic value corresponding to the signal to be processed is determined to be a high logic value. If the comparison result is that the signal to be processed is greater than the lowest signal threshold and less than the highest signal threshold, then the logic value corresponding to the signal to be processed is determined to be the logic value of the previous signal to be processed. Based on the logic values corresponding to each signal to be processed, a logic sequence is obtained.
[0052] The peak signal refers to the highest voltage value detected by the oscilloscope during the signal acquisition period; the valley signal refers to the lowest voltage value detected by the oscilloscope during the signal acquisition period.
[0053] The standard threshold and the deviation threshold are determined based on the peak signal and the valley signal so that they can be used to determine the target signal threshold. In practical applications, the standard threshold deviation can be the average value of the peak signal and the valley signal, and the deviation threshold can be determined by 0.1 times the difference between the peak signal and the valley signal.
[0054] The highest and lowest signal thresholds are used to determine the target signal threshold, which can be understood as a threshold range. The highest signal threshold is the high boundary of the threshold range, and the lowest signal threshold is the low boundary of the threshold range. In practical applications, the highest signal threshold can be the sum of the standard threshold and the deviation threshold, and the lowest signal threshold can be the difference between the standard threshold and the deviation threshold.
[0055] A low logic value is 0, and a high logic value is 1.
[0056] Based on this, by determining the highest and lowest signal thresholds corresponding to the target signal threshold, the signal to be processed is compared with the highest and lowest signal thresholds respectively. Based on the comparison results, i.e. the numerical relationship between the signal to be processed and the highest and lowest signal thresholds, the signal to be processed is determined as the corresponding logical value. The dual threshold design can avoid misjudgment caused by noise and improve the stability of edge recognition.
[0057] Based on the feasible implementation of S120 described above, this application further provides the following steps: determining a target time sequence based on the time points corresponding to each change edge in the logic sequence and the target time width, and performing linear fitting on the logic sequence and the target time sequence to obtain a clock signal, including: Calculate the time difference between any two adjacent change edges in the logical sequence to obtain the time width sequence, and determine the target time width by multiplying the time difference with the smallest difference by a preset threshold. Based on the time width sequence and the target time width, the target time sequence is determined, and the logic sequence and the target time sequence are linearly fitted to obtain the clock signal.
[0058] The preset threshold is a pre-determined threshold used to determine the target time width corresponding to the time difference. The time difference can be understood as the symbol width. In a normal data stream, the maximum time width of a single bit will not be greater than 1.5 times the minimum symbol width. Therefore, the preset threshold can be 1.5.
[0059] Based on this, by determining the corresponding time points of any two adjacent change edges in the logic sequence, the corresponding time difference is calculated, resulting in a time width sequence composed of multiple time differences. The time difference with the smallest value among all time differences is then determined. Based on the product of a preset threshold and the smallest time difference, the target time width is determined. This allows for the subsequent determination of the target time sequence based on the time width sequence and the target time width. Finally, the logic sequence and the target time sequence are linearly fitted to obtain the clock signal.
[0060] Based on the feasible implementation of S120 described above, this application further provides the following steps: determining a target time sequence based on a time width sequence and a target time width, and performing linear fitting on the logic sequence and the target time sequence to obtain a clock signal, including: Based on the difference between any two adjacent time widths in the time width sequence, determine the division values of multiple differences with the target time width to obtain the target time sequence. Then, based on the least squares method, perform linear fitting on the logic sequence and the target time sequence to obtain the target clock period and the target clock deviation value. The clock signal is determined based on the target clock period and the target clock deviation value.
[0061] The target clock period can be understood as the slope of an approximate straight line obtained by linear fitting, which can characterize the periodicity of the clock signal; the target clock deviation value can be understood as the initial deviation in the approximate straight line, which can characterize the phase shift of the clock signal, i.e., the initial time.
[0062] Based on this, by performing linear fitting on the logic sequence and the target time sequence, the periodic information of the clock signal is determined according to the slope of the fitted approximate straight line, and the initial deviation of the clock signal is determined according to the initial phase of the approximate straight line, thus obtaining the clock signal.
[0063] Based on the feasible implementation of S130 described above, this application further provides the following steps: acquiring the signal to be processed based on the falling edge of the clock signal to obtain the corresponding logic signal, and identifying the logic signal sequentially according to the time window and the recognition width; Collect the target signals to be processed from the signals to be processed corresponding to the falling edge of the change, and determine the corresponding logic signals based on the signal voltage values corresponding to each target signal to be processed; Based on the time window, the logic signal is identified to obtain the logic signal segment with the window width. Then, based on the identification width, the time window is slid successively to obtain multiple logic signal segments identified by the time window.
[0064] Among them, the signal voltage value refers to the actual voltage amplitude collected by measuring equipment such as oscilloscopes during the physical transmission of the signal.
[0065] Based on this, the target signal to be processed and its corresponding signal voltage value are collected from the falling edge of the clock signal. Then, the corresponding logic signal is determined based on the signal voltage value. The method of determining the logic sequence corresponding to the signal to be processed can be referred to. By determining the maximum and minimum voltage values among the signal voltage values, each signal voltage value is determined as the corresponding logic signal, so that the logic signal can be identified according to the time window.
[0066] Based on the feasible implementation of S140 described above, this application further provides the following steps: when a target identification code is identified, the identification width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted sequentially according to the time window and the adjusted identification width to obtain the target logic signal segment, including the following steps: The recognition width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted one by one according to the time window and the adjusted recognition width to obtain multiple corresponding initial logic signal segments. Based on the preset logical signal mapping relationship, each initial logical signal segment is mapped to the corresponding target logical signal segment.
[0067] The initial logic signal segment is the signal segment extracted from the logic signal by the time window. Please refer to [reference needed]. Figure 3 , Figure 3 An encoding schematic diagram of a signal analysis method for a high-speed protocol provided in an embodiment of this application; as shown Figure 3 As shown, when there are multiple consecutive logic 1s or logic 0s in a high-speed serial stream, the voltage level can cause signal conversion errors. Therefore, high-speed serial protocols often use 8b / 10b encoding to ensure that the number of "0"s and "1"s in the binary data stream is basically the same, and that there are no multiple consecutive logic 1s or logic 0s. The 8b / 10b encoding method divides 8 bits of data into two groups: three high-significant bits (y) and five low-significant bits (x). The three high-significant bits are denoted as H, G, and F, and the five low-significant bits are denoted as E, D, C, B, and A. The three high bits and five low bits are respectively looked up in tables to correspond to 4-bit and 6-bit data. The mapping relationship is fixed. Therefore, a mapping table is used to implement 8b / 10b decoding. That is, a mapping table is first generated according to the 8b / 10b encoding rules. During the decoding process, the corresponding 8-bit value is looked up in the mapping table according to the 10-bit data in the data stream, thereby realizing 8b / 10b decoding.
[0068] The preset logic signal mapping relationship is a pre-determined logic signal mapping table, which maps a 10-bit logic signal to an 8-bit logic signal.
[0069] Based on this, the logic signal segment identified each time in the time window can be compared with the target identification code. When a logic signal segment that matches the target identification code is found, the identification width of the time window is adjusted to the value corresponding to the window width. Then, the time window can extract the logic signal after the logic signal segment that matches the target identification code one by one according to the adjusted identification width, thereby determining multiple initial logic signal segments. The 10-bit initial logic signal segment is then decoded to obtain the corresponding 8-bit target logic signal segment.
[0070] Based on the feasible implementation of S150 described above, this application further provides the steps of determining the target information corresponding to the target logic signal segment according to the logic code and information protocol of the high-speed protocol, including: Based on the sequence corresponding to the logic code, determine a preset number of high-order logic bits, and perform an XOR operation on the target logic signal segment and the high-order logic bits to obtain the information to be converted; According to the information protocol, the protocol to be converted is converted to obtain the target information.
[0071] The sequence corresponding to the logic code is the bit value of the linear feedback shift register corresponding to the PCIe protocol. The linear feedback shift register generally contains 16 bits, with a preset quantity of 8 bits. The high-order logic code is the high 8 bits of the linear feedback shift register.
[0072] The XOR operation is a binary bitwise operation, usually represented by the symbol "⊕". It performs a calculation on two binary bits. The rule is that when the two bits are the same (both are 0 or both are 1), the result is 0; when the two bits are different (one is 0 and the other is 1), the result is 1.
[0073] The information to be converted is the original information of the signal transmission. The descrambled original data is a string of binary / hexadecimal data stream, which is not the final format of the information. Therefore, information conversion is still required.
[0074] Based on this, by determining the high-order bit value of the linear feedback shift register corresponding to the high-speed protocol, the target logic signal segment is XORed with the high-order bit value. Since data scrambling involves XORing the original information with the high-order bit value once to obtain the target logic signal segment, and then XORing the target logic signal segment with the high-order bit value once more, the original information can be obtained again, thus achieving data descrambling.
[0075] Please refer to Figure 4 , Figure 4 This application provides a schematic diagram of a signal analysis method for a high-speed protocol, as illustrated in the embodiments of this application. Figure 4 As shown, the clock signal of the high-speed bus signal is recovered by constant clock recovery method, then the scrambled signal is obtained by 8b / 10b decoding method, and finally the high-speed bus analysis is realized by descrambling and protocol state machine.
[0076] In some embodiments of this application, the peak and valley signals in the high-speed signal are determined to establish a target signal threshold. This allows each signal to be processed to be converted into a corresponding logic signal, resulting in a logic sequence. The target time sequence is then determined based on the time points corresponding to the changes in the logic signal. A linear fit is then performed between the logic sequence and the target time sequence to obtain a clock signal. This process achieves the following: acquiring the signal to be processed according to the high-speed protocol; determining the logic sequence based on the comparison between each signal to be processed and the target signal threshold; determining the target time sequence based on the time points corresponding to the changes in the logic sequence and the target time width; and performing a linear fit between the logic sequence and the target time sequence to obtain a clock signal. While the bit period (symbol width) of the high-speed PCIe signal is fixed, the oscilloscope acquires a continuous electrical signal, thus enabling clock recovery and obtaining a clock signal. A clock signal synchronized with the signal source is used to acquire the signal to be processed based on the falling edge of the clock signal, obtain the corresponding logic signal, and identify the logic signal sequentially according to the time window and the recognition width. When the target identification code is identified, the recognition width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted sequentially according to the time window and the adjusted recognition width. The extracted 10-bit logic signal is decoded, and according to the preset mapping relationship, the target logic signal segment corresponding to the 10-bit value is obtained. Then, according to the high-order logic code of the linear shift register corresponding to the high-speed protocol, the target logic signal segment and the high-order logic code are XORed to obtain the original information corresponding to the target logic signal segment. The original information is then converted according to the information protocol to obtain the target information, realizing the transmission and analysis of the signal.
[0077] Thus, by combining multiple technologies such as clock recovery, 8B / 10B decoding, sliding window search for frame headers, descrambling, and protocol state machines, multi-algorithm collaborative optimization is achieved, improving signal processing efficiency and enabling efficient parsing of high-speed bus signals. By recovering the original clock signal of high-speed signals, it can handle complex and high-speed protocols, improving the speed and accuracy of protocol analysis.
[0078] Figure 5 This is a schematic diagram of the structure of a high-speed protocol signal analysis device 500 provided in an embodiment of this application. Figure 5 As shown, the signal analysis device 500 for a high-speed protocol includes: a signal acquisition module 510, a fitting module 520, a data acquisition module 530, an extraction module 540, and a determination module 550; wherein: Signal 510 is used to acquire the signal to be processed according to the high-speed protocol, and to determine the logical sequence based on the comparison results between each signal to be processed and the target signal threshold. The fitting module 520 is used to determine the target time series based on the time points corresponding to each change edge in the logic sequence and the target time width, and to perform linear fitting on the logic sequence and the target time series to obtain the clock signal; The acquisition module 530 is used to acquire the signal to be processed based on the falling edge of the clock signal, obtain the corresponding logic signal, and identify the logic signal one by one according to the time window and the recognition width. The extraction module 540 is used to adjust the recognition width to the window width of the time window when the target identification code is recognized, and extract the logic signal after the target identification code one by one according to the time window and the adjusted recognition width to obtain the target logic signal segment; The determination module 550 is used to determine the target information corresponding to the target logic signal segment based on the logic code and information protocol of the high-speed protocol.
[0079] In this embodiment of the application, the acquisition signal 510 can also be specifically used for: The standard threshold is determined based on the sum of the peak and valley values in the signal to be processed, and the deviation threshold is determined based on the difference. The sum of the standard threshold and the deviation threshold is determined as the highest signal threshold, and the difference between the standard threshold and the deviation threshold is determined as the lowest signal threshold. Based on the highest signal threshold and the lowest signal threshold, the target signal threshold is obtained. The signal strength of each signal to be processed is compared with the highest signal threshold and the lowest signal threshold to obtain the comparison result; If the comparison result shows that the signal to be processed is less than the minimum signal threshold, then the logic value corresponding to the signal to be processed is determined to be a low logic value. If the comparison result shows that the signal to be processed is greater than the highest signal threshold, then the logic value corresponding to the signal to be processed is determined to be a high logic value. If the comparison result is that the signal to be processed is greater than the lowest signal threshold and less than the highest signal threshold, then the logic value corresponding to the signal to be processed is determined to be the logic value of the previous signal to be processed. Based on the logic values corresponding to each signal to be processed, a logic sequence is obtained.
[0080] In this embodiment of the application, the fitting module 520 can also be specifically used for: Calculate the time difference between any two adjacent change edges in the logical sequence to obtain the time width sequence, and determine the target time width by multiplying the time difference with the smallest difference by a preset threshold. Based on the time width sequence and the target time width, the target time sequence is determined, and the logic sequence and the target time sequence are linearly fitted to obtain the clock signal.
[0081] In this embodiment of the application, the fitting module 520 can also be specifically used for: Based on the difference between any two adjacent time widths in the time width sequence, determine the division values of multiple differences with the target time width to obtain the target time sequence. Then, based on the least squares method, perform linear fitting on the logic sequence and the target time sequence to obtain the target clock period and the target clock deviation value. The clock signal is determined based on the target clock period and the target clock deviation value.
[0082] In this embodiment of the application, the acquisition module 530 can also be specifically used for: Collect the target signals to be processed from the signals to be processed corresponding to the falling edge of the change, and determine the corresponding logic signals based on the signal voltage values corresponding to each target signal to be processed; Based on the time window, the logic signal is identified to obtain the logic signal segment with the window width. Then, based on the identification width, the time window is slid successively to obtain multiple logic signal segments identified by the time window.
[0083] In this embodiment of the application, the extraction module 540 can also be specifically used for: The recognition width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted one by one according to the time window and the adjusted recognition width to obtain multiple corresponding initial logic signal segments. Based on the preset logical signal mapping relationship, each initial logical signal segment is mapped to the corresponding target logical signal segment.
[0084] In this embodiment of the application, the determining module 550 may also be specifically used for: Based on the sequence corresponding to the logic code, determine a preset number of high-order logic bits, and perform an XOR operation on the target logic signal segment and the high-order logic bits to obtain the information to be converted; According to the information protocol, the protocol to be converted is converted to obtain the target information.
[0085] Figure 6 This is a schematic diagram of the structure of a device for performing a signal analysis method according to a high-speed protocol of this application, provided as an embodiment of the present application. Figure 6 As shown, the device 600 includes: The device 600 may include a processor 601 with one or more processing cores, a memory 602 with one or more computer-readable storage media, a communication component 603, and other components. The processor 601, memory 602, and communication component 603 are connected via a bus 604.
[0086] In the specific implementation process, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to execute the signal analysis method of the high-speed protocol described above.
[0087] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0088] Furthermore, the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0089] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0090] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0091] In some embodiments, a computer program product is also provided, including a computer program or instructions that, when executed by a processor, implement the steps in the signal analysis method of any of the high-speed protocols described above.
[0092] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.
[0093] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.
[0094] Therefore, embodiments of this application provide a computer-readable storage medium storing a plurality of program codes that can be loaded by a processor to execute steps in a signal analysis method for any high-speed protocol provided in embodiments of this application.
[0095] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.
[0096] According to one aspect of this application, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium.
[0097] Since the instructions stored in the storage medium can execute the steps in the signal analysis method of any high-speed protocol provided in the embodiments of this application, the beneficial effects that the signal analysis method of any high-speed protocol provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.
[0098] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the appended claims.
[0099] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.
Claims
1. A signal analysis method for a high-speed protocol, characterized in that, The method includes: According to the high-speed protocol, the signal to be processed is acquired, and the logical sequence is determined based on the comparison results between each signal to be processed and the target signal threshold. Based on the time points corresponding to each change edge in the logical sequence and the target time width, the target time sequence is determined, and the logical sequence and the target time sequence are linearly fitted to obtain the clock signal. The signal to be processed is acquired based on the falling edge of the clock signal to obtain the corresponding logic signal, and the logic signal is identified sequentially according to the time window and the recognition width. When a target identification code is identified, the identification width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted sequentially according to the time window and the adjusted identification width to obtain the target logic signal segment; Based on the logic code and information protocol of the high-speed protocol, the target information corresponding to the target logic signal segment is determined.
2. The method according to claim 1, characterized in that, The step of acquiring the signal to be processed according to the high-speed protocol and determining the logical sequence based on the comparison results between each signal to be processed and the target signal threshold includes: Based on the sum of the peak and valley values in the signal to be processed, a standard threshold is determined, and based on the difference, a deviation threshold is determined. The sum of the standard threshold and the deviation threshold is determined to be the highest signal threshold, and the difference between the standard threshold and the deviation threshold is determined to be the lowest signal threshold. The target signal threshold is obtained based on the highest signal threshold and the lowest signal threshold. The comparison result is obtained by comparing the signal strength of each of the signals to be processed with the highest signal threshold and the lowest signal threshold; If the comparison result indicates that the signal to be processed is less than the minimum signal threshold, then the logic value corresponding to the signal to be processed is determined to be a low logic value. If the comparison result indicates that the signal to be processed is greater than the highest signal threshold, then the logic value corresponding to the signal to be processed is determined to be a high logic value. If the comparison result is that the signal to be processed is greater than the lowest signal threshold and less than the highest signal threshold, then the logical value corresponding to the signal to be processed is determined to be the logical value of the previous signal to be processed. The logical sequence is obtained based on the logical value corresponding to each of the signals to be processed.
3. The method according to claim 1, characterized in that, The step of determining the target time series based on the time points corresponding to each change edge in the logical sequence and the target time width, and performing linear fitting on the logical sequence and the target time series to obtain the clock signal, includes: Based on the time points corresponding to any two adjacent change edges in the logical sequence, the time difference is calculated to obtain the time width sequence, and the target time width is determined by multiplying the time difference with the smallest difference by a preset threshold. Based on the time width sequence and the target time width, the target time sequence is determined, and the logic sequence and the target time sequence are linearly fitted to obtain the clock signal.
4. The method according to claim 3, characterized in that, The step of determining the target time sequence based on the time width sequence and the target time width, and performing linear fitting on the logical sequence and the target time sequence to obtain the clock signal, includes: Based on the difference between any two adjacent time widths in the time width sequence, determine multiple values to divide the difference by the target time width to obtain the target time sequence. Then, perform linear fitting on the logic sequence and the target time sequence using the least squares method to obtain the target clock period and the target clock deviation value. The clock signal is determined based on the target clock period and the target clock deviation value.
5. The method according to claim 1, characterized in that, The step of acquiring the signal to be processed based on the falling edge of the clock signal to obtain the corresponding logic signal, and identifying the logic signal sequentially according to the time window and recognition width, includes: Collect the target signal to be processed from the signal to be processed that corresponds to the falling edge, and determine the corresponding logic signal based on the signal voltage value corresponding to each target signal to be processed; Based on the time window, the logic signal is identified to obtain a logic signal segment of the window width, and based on the identification width, the time window is slid successively to obtain multiple logic signal segments identified by the time window.
6. The method according to claim 1, characterized in that, When a target identification code is detected, the identification width is adjusted to the window width of the time window, and the logic signal following the target identification code is extracted sequentially according to the time window and the adjusted identification width to obtain the target logic signal segment, including: The recognition width is adjusted to the window width of the time window, and the logic signal after the target identification code is extracted sequentially according to the time window and the adjusted recognition width to obtain multiple corresponding initial logic signal segments; According to the preset logical signal mapping relationship, each of the initial logical signal segments is mapped to the corresponding target logical signal segment.
7. The method according to claim 1, characterized in that, The step of determining the target information corresponding to the target logical signal segment based on the logical code and information protocol of the high-speed protocol includes: Based on the sequence corresponding to the logical code, a preset number of high-order logical bits are determined, and an XOR operation is performed on the target logical signal segment and the high-order logical bits to obtain the information to be converted. According to the information protocol, the protocol to be converted is converted to obtain the target information.
8. A signal analysis device for a high-speed protocol, characterized in that, The device includes: The signal acquisition is used to acquire the signal to be processed according to the high-speed protocol, and to determine the logical sequence based on the comparison results between each of the signals to be processed and the target signal threshold. The fitting module is used to determine the target time series based on the time points corresponding to each change edge in the logical sequence and the target time width, and to perform linear fitting on the logical sequence and the target time series to obtain the clock signal; The acquisition module is used to acquire the signal to be processed according to the falling edge of the clock signal to obtain the corresponding logic signal, and to identify the logic signal sequentially according to the time window and the recognition width. The extraction module is used to adjust the recognition width to the window width of the time window when the target identification code is recognized, and extract the logic signal after the target identification code one by one according to the time window and the adjusted recognition width to obtain the target logic signal segment; The determination module is used to determine the target information corresponding to the target logical signal segment based on the logic code and information protocol of the high-speed protocol.
9. A device, characterized in that, include: One or more processors; Memory; One or more programs, wherein the one or more programs are stored in memory and configured to be executed by one or more processors, the one or more programs being configured to perform the method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program code that can be called by a processor to perform the method as described in any one of claims 1 to 7.