Memory device, operating method thereof, and memory system

Abstract

The embodiment of the invention provides a memory device, an operation method thereof and a memory system. The memory device includes: a memory cell array including a plurality of memory cells, a preset number of memory cells forming a codeword; the peripheral circuit is coupled with the storage unit array and is configured to respond to the first command and obtain a corresponding Kth flip result of the at least one code word under the Kth reading voltage; the Kth flipping result comprises the number of bits representing flipping of at least one code word in two reading results under the Kth reading voltage and the (K-1) th reading voltage; a preset difference value exists between the Kth reading voltage and the (K-1) th reading voltage; wherein 1 < = K < = N, and K and N are natural numbers; storing information representing a Kth flip result; and in response to the second command, outputting information representing a Kth flipping result.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular to a memory device and an operating method thereof, and a memory system. BACKGROUND

[0002] With the progress of science and technology and the rapid development of the Internet, people's demand for information data storage and maintenance is becoming higher and higher. Therefore, it is crucial to improve the performance of the memory system. SUMMARY

[0003] Therefore, embodiments of the present application provide a memory device and an operating method thereof, and a memory system.

[0004] In a first aspect, embodiments of the present application provide a memory device, comprising: a memory cell array comprising a plurality of memory cells, a preset number of memory cells forming a code word; a peripheral circuit coupled to the memory cell array and configured to: in response to a first command, obtain a Kth flipping result corresponding to at least one code word under a Kth read voltage; the Kth flipping result comprising a number of bits representing a flipping occurring in the two read results of the at least one code word under the Kth read voltage and a (K-1)th read voltage; the Kth read voltage and the (K-1)th read voltage having a preset difference; wherein 1≤K≤N, K and N are natural numbers; store information representing the Kth flipping result; and in response to a second command, output the information representing the Kth flipping result.

[0005] In some embodiments, the second command is configured by setting a feature command; the peripheral circuit is configured to: store the information representing the Kth flipping result in a reserved field of the setting feature command; and in response to the setting feature command, output the information representing the Kth flipping result according to the information representing the Kth flipping result stored in the reserved field.

[0006] In some embodiments, the peripheral circuit is configured to: store the Kth flipping result in the reserved field according to the Kth flipping result being less than or equal to a preset value; store a modified value of the Kth flipping result in the reserved field according to the Kth flipping result being greater than the preset value; the storage space occupied by the modified value of the Kth flipping result being less than the storage space occupied by the Kth flipping result; and in response to the setting feature command, output the information representing the Kth flipping result according to at least the Kth flipping result or the modified value of the Kth flipping result stored in the reserved field of the setting feature command.

[0007] In some embodiments, the first flipping result to the Nth flipping result are used to represent the threshold voltage distribution of the at least one code word within a range of the first read voltage to the Nth read voltage.

[0008] In some embodiments, the peripheral circuit is configured to: set the flag value stored in the reserved field to a first state according to the Kth flipping result being less than or equal to a preset value; set the flag value stored in the reserved field to a second state according to the Kth flipping result being greater than the preset value; and output information representing the Kth flipping result according to the flag value stored in the reserved field and the Kth flipping result / modified value of the Kth flipping result.

[0009] In some embodiments, the Kth read voltage is a sum of the first read voltage and K step voltages; the reserved field includes a first address area, a second address area, a third address area, and a fourth address area; the first address area is configured to store the first read voltage; the second address area is configured to store the step voltages; the third address area is configured to store the Kth flipping result / modified value of the Kth flipping result; the fourth address area is configured to store the flag value; and the peripheral circuit is configured to output information representing the Kth flipping result according to the Kth flipping result / modified value of the Kth flipping result stored in the third address area and the flag value stored in the fourth address area in response to a set feature command.

[0010] In some embodiments, the voltage range to which the first read voltage to the Nth read voltage belongs is -3V to 6V; and the voltage range of the step voltage is 0.01V to 0.5V.

[0011] In some embodiments, the peripheral circuit is configured to store the (K-1)th flipping result / modified value of the (K-1)th flipping result in the reserved field before obtaining the Kth flipping result corresponding to the at least one codeword under the Kth read voltage; and output information representing the (K-1)th flipping result in response to a set feature command during the process of obtaining the Kth flipping result corresponding to the at least one codeword under the Kth read voltage.

[0012] In some embodiments, the peripheral circuit is configured to obtain flipping results corresponding to the at least one codeword under a plurality of read voltages in response to a third command; the plurality of read voltages include the first read voltage to the Nth read voltage, and the flipping results include the first flipping result to the Nth flipping result; and obtaining the Kth flipping result among the first flipping result to the Nth flipping result includes: reading stored data of the at least one codeword under the Kth read voltage to obtain second read data; performing logical operation on the first read data and the second read data to obtain third read data; the first read data is stored data of the at least one codeword read under the (K-1)th read voltage; and in response to a first command, counting the number of bits representing flipping of the second read data compared with the first read data in the third read data to obtain the Kth flipping result.

[0013] In some embodiments, a time length taken to obtain the second read data in response to the third command is a first time length; a time length taken to obtain the Kth flipping result / the modified value of the Kth flipping result in response to the first command is a second time length; and the second time length is less than the first time length.

[0014] In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store the first read data; the second latch is configured to store the second read data; and the third latch is configured to store the third read data.

[0015] In some embodiments, the peripheral circuit is configured to: compare the Kth flipping result with a preset value to obtain a comparison result; and determine, according to the comparison result, whether to store the Kth flipping result / the modified value of the Kth flipping result in a preset field; and the peripheral circuit further includes: a fourth latch; and the fourth latch is configured to store the Kth flipping result in the preset field and output the Kth flipping result.

[0016] In some embodiments, the peripheral circuit is configured to: in response to the third command, sequentially obtain the first flipping result to the Nth flipping result, and for the Kth flipping result among the first flipping result to the Nth flipping result: apply a corresponding read voltage to a word line coupled with the at least one codeword according to the Kth read voltage; store second read data of the at least one codeword sensed at the Kth read voltage in the second latch; perform an exclusive-OR operation on the first read data stored in the first latch at the (K-1)th read voltage and the second read data stored in the second latch at the Kth read voltage to generate third read data, and store the third read data in the third latch; and transmit the second read data stored in the second latch at the Kth read voltage to the first latch; in response to the first command, before the second read data sensed at the Kth read voltage, generate the (K-1)th flipping result / the modified value of the (K-1)th flipping result according to the third read data, and store the (K-1)th flipping result / the modified value of the (K-1)th flipping result in the preset field; and in response to the setting feature command, in the process of obtaining the Kth flipping result, transmit information representing the (K-1)th flipping result stored in the preset field to the fourth latch.

[0017] In some embodiments, the memory device includes a NAND type memory.

[0018] In a second aspect, embodiments of the present application provide a memory system, including: one or more memory devices of any of the first aspect; and a memory controller coupled with the memory device and configured to control the memory device.

[0019] In some embodiments, the memory controller is configured to: send a first command and a second command; the first command indicates to obtain a Kth flipping result corresponding to the at least one codeword at a Kth read voltage; the second command indicates to output information representing the Kth flipping result; the memory device is configured to: receive the first command, obtain information representing the first flipping result to the Nth flipping result; receive the second command, output the information representing the first flipping result to the Nth flipping result; and send the obtained information representing the Kth flipping result to the memory controller; the memory controller is further configured to: generate information representing a threshold voltage distribution of the at least one codeword at the Kth read voltage using the information representing the Kth flipping result and the Kth read voltage.

[0020] In some embodiments, the memory controller is configured to: send a third command, the third command indicating to obtain third read data; the memory device is configured to: in response to the third command, obtain flipping results corresponding to the at least one codeword at a plurality of read voltages respectively; the plurality of read voltages comprises the first read voltage to the Nth read voltage, and the flipping results comprise the first flipping result to the Nth flipping result; obtaining the Kth flipping result in the first flipping result to the Nth flipping result comprises: reading stored data of the at least one codeword at the Kth read voltage to obtain second read data; performing a logical operation on the first read data and the second read data to obtain the third read data; the first read data is stored data of the at least one codeword read at the (K-1)th read voltage; in response to the first command, counting a number of bits representing flipping of the second read data relative to the first read data in the third read data to obtain the Kth flipping result; the memory controller is further configured to: generate information representing a threshold voltage distribution of the at least one codeword in a range of the first read voltage to the Nth read voltage using the information representing the first flipping result to the Nth flipping result and the first read voltage to the Nth read voltage.

[0021] In a third aspect, embodiments of the present application provide an operation method of a memory device, the operation method comprising: in response to a first command, obtaining a Kth flipping result corresponding to at least one codeword formed by a preset number of storage units in the memory device at a Kth read voltage respectively; the Kth flipping result comprising a number of bits representing flipping of read results of the at least one codeword at the Kth read voltage and at a (K-1)th read voltage; the Kth read voltage and the (K-1)th read voltage have a preset difference; wherein 1≤K≤N, K and N are natural numbers; storing information representing the Kth flipping result; in response to a second command, outputting the information representing the Kth flipping result.

[0022] In some embodiments, the operation method comprises: storing information representing the Kth flipping result in a reserved field of the set feature command; and outputting information representing the Kth flipping result according to the information representing the Kth flipping result stored in the reserved field in response to the set feature command; wherein the second command is configured by the set feature command.

[0023] In some embodiments, the operation method comprises: storing the Kth flipping result in the reserved field according to the Kth flipping result being less than or equal to a preset value; storing a modified value of the Kth flipping result in the reserved field according to the Kth flipping result being greater than the preset value; the modified value of the Kth flipping result occupying a storage space smaller than that of the Kth flipping result; and outputting information representing the Kth flipping result according to at least the Kth flipping result or the modified value of the Kth flipping result stored in the reserved field of the set feature command in response to the set feature command.

[0024] In some embodiments, the operation method comprises: setting a flag value stored in the reserved field to a first state according to the Kth flipping result being less than or equal to a preset value; setting the flag value stored in the reserved field to a second state according to the Kth flipping result being greater than the preset value; and outputting information representing the Kth flipping result according to the flag value stored in the reserved field and the Kth flipping result / modified value of the Kth flipping result.

[0025] In some embodiments, the operation method comprises: outputting information representing the Kth flipping result according to the Kth flipping result / modified value of the Kth flipping result stored in a third address area of the reserved field and a flag value stored in a fourth address area of the reserved field in response to the set feature command; wherein the Kth read voltage is a sum of a first read voltage and K step voltages; the first address area of the reserved field stores the first read voltage; the second address area of the reserved field stores the step voltages; the third address area of the reserved field stores the Kth flipping result / modified value of the Kth flipping result; and the fourth address area of the reserved field stores the flag value.

[0026] In some embodiments, the operation method comprises: storing the (K-1)th flipping result / modified value of the (K-1)th flipping result in the reserved field before obtaining the Kth flipping result corresponding to the at least one code word under the Kth read voltage; and outputting information representing the (K-1)th flipping result in response to the set feature command during the process of obtaining the Kth flipping result corresponding to the at least one code word under the Kth read voltage.

[0027] In some embodiments, the operation method comprises: in response to the third command, obtaining the flipping results of the at least one code word corresponding to a plurality of read voltages respectively; the plurality of read voltages comprise a first read voltage to an Nth read voltage, and the flipping results comprise a first flipping result to an Nth flipping result; wherein obtaining a Kth flipping result in the first flipping result to the Nth flipping result comprises: reading the stored data of the at least one code word at the Kth read voltage to obtain second read data; performing logical operation on the first read data and the second read data to obtain third read data; the first read data is the stored data of the at least one code word read at the (K-1)th read voltage; and in response to the first command, counting the number of bits in the third read data representing the flipping of the second read data compared with the first read data to obtain the Kth flipping result.

[0028] In some embodiments, the operation method comprises: in response to the third command, obtaining the flipping results of the at least one code word corresponding to a plurality of read voltages respectively; the plurality of read voltages comprise a first read voltage to an Nth read voltage, and the flipping results comprise a first flipping result to an Nth flipping result; wherein obtaining a Kth flipping result in the first flipping result to the Nth flipping result comprises: reading the stored data of the at least one code word at the Kth read voltage to obtain second read data; performing logical operation on the first read data and the second read data to obtain third read data; the first read data is the stored data of the at least one code word read at the (K-1)th read voltage; and in response to the first command, counting the number of bits in the third read data representing the flipping of the second read data compared with the first read data to obtain the Kth flipping result.

[0029] In some embodiments, the operation method comprises: in response to the third command, obtaining the flipping results of the at least one code word corresponding to a plurality of read voltages respectively; the plurality of read voltages comprise a first read voltage to an Nth read voltage, and the flipping results comprise a first flipping result to an Nth flipping result; wherein obtaining a Kth flipping result in the first flipping result to the Nth flipping result comprises: reading the stored data of the at least one code word at the Kth read voltage to obtain second read data; performing logical operation on the first read data and the second read data to obtain third read data; the first read data is the stored data of the at least one code word read at the (K-1)th read voltage; and in response to the first command, counting the number of bits in the third read data representing the flipping of the second read data compared with the first read data to obtain the Kth flipping result. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0031] Figure 2A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0032] Figure 2B schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present application;

[0033] Figure 3 schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0034] Figure 4 schematic diagram of a cross section of a memory cell array including NAND type memory strings according to an embodiment of the present application;

[0035] Figure 5 schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0036] Figure 6 schematic diagram of an exemplary constituent structure having a memory system according to an embodiment of the present application;

[0037] Figure 7 flowchart of a process of acquiring information of a Kth flipping result of a memory device according to an embodiment of the present application Figure 1 ;

[0038] Figure 8 flowchart of a process of acquiring information of a Kth flipping result of a memory device according to an embodiment of the present application

[0039] Figure 9 flowchart of a process of acquiring information of a Kth flipping result of a memory device according to an embodiment of the present application Figure 3 ;

[0040] Figure 10 flowchart of a process of acquiring information of a Kth flipping result of a memory device according to an embodiment of the present application Figure 4 ;

[0041] Figure 11 block diagram of a memory system according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0043] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of the specific details. In other instances, well-known

[0044] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0045] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms since such terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

[0046] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] For a thorough understanding of the present application, reference will be made to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0049] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND type memory, and for the convenience of understanding, the three-dimensional NAND type memory is taken as an example for description.

[0050] Figure 1 A block diagram of an exemplary system 100 having a memory device in accordance with some aspects of the present application is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Argument Reality (AR) device, or any other suitable electronic device having a memory. As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 2. The host 108 can be a processor (e.g., a Central Processing Unit (CPU)) or a System of Chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 108 can be configured to send data to or receive data from the memory device 104. Figure 1

[0051] ​According to some embodiments, a memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104, and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0052] In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Muti Media Card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0053] The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is further configured to process error correction codes with respect to data read from or written to the memory device 104.

[0054] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0055] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0056] In such Figure 2A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0057] In such Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1SSD connector 208. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0058] In some embodiments, each block of storage can be coupled to a plurality of word lines, and each word line can be coupled to a plurality of storage cells that form a physical page.

[0059] Figure 3 A schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry is shown in accordance with some aspects of the present application. The memory device 300 can be an example of the memory device 104 in Figure 1 The memory device 300 can include a storage cell array 301 and peripheral circuitry 302 coupled to the storage cell array 301. By way of example, the storage cell array 301 is described as a three-dimensional NAND type storage cell array, where the storage cells 306 are NAND type storage cells provided in an array of storage strings 308, each of which extends vertically above a substrate (not shown). In some embodiments, each storage string 308 includes a plurality of storage cells 306 coupled in series and stacked vertically. Each storage cell 306 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons captured within a region of the storage cell 306. Each storage cell 306 can be a floating gate type of storage cell that includes a floating gate transistor, or a charge trap type of storage cell that includes a charge trapping transistor.

[0060] In some embodiments, each storage unit 306 is a single-level cell (SLC) that has two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each storage unit 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell, a fourth nominal storage value can be used for the erased state.

[0061] It is noted that the storage states referred to herein are also referred to as storage states of the storage units of the present disclosure. Different storage units have different numbers of storage states. For example, a SLC type storage unit has two storage states (i.e., two memory states), which include one programmed state and one erased state. For another example, a MLC type storage unit has four storage states, which include one erased state and three programmed states. For yet another example, a TLC type storage unit has eight storage states, which include one erased state and seven programmed states. In some embodiments, a QLC type storage unit has sixteen storage states, which include one erased state and fifteen programmed states.

[0062] As Figure 3As shown in FIG. 3, each memory string 308 can include a bottom select transistor (BSG) 310 (also referred to as a source side select transistor) at its source end and a top select transistor (TSG) 312 (also referred to as a drain side select transistor) at its drain end. The BSG 310 and the TSG 312 can be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0 V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0 V) to the respective BSG 310 via one or more BSG lines 315.

[0063] As Figure 3 As shown in FIG. 3, the memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same face as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20 V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable fraction of any suitable number of memory blocks or memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled through word lines 318 that select which row of memory cells 306 is affected by read and program operations.

[0064] Referring to Figure 3 each of the plurality of memory cells 306 is coupled to a respective word line 318, each memory string 308 is coupled to a respective bit line 316 through a respective select transistor (e.g., a top select transistor (TSG) 312).

[0065] Figure 4 A cross-sectional schematic of an exemplary memory cell array 301 including a memory string 308, for example in NAND, is shown in accordance with some aspects of the present application. As shown, the NAND memory cell array 301 can include a stack structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412, wherein the channel structure and each gate layer form a memory cell, and the channel structure and the plurality of gate layers in the stack structure 410 form a memory string 308. The gate layers 411 and the insulating layers 412 can be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412. Figure 4

[0066] The constituent material of the gate layers 411 can include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate surrounding a memory cell. The gate layers 411 at the top of the stack structure 410 can laterally extend as upper select gate lines, the gate layers 411 at the bottom of the stack structure 410 can laterally extend as lower select gate lines, and the gate layers 411 laterally extending between the upper select gate lines and the lower select gate lines can serve as word line layers.

[0067] In some embodiments, the stack structure 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0068] ​In some embodiments, the storage string 308 includes a channel structure that extends vertically through the stack structure 410. In some implementations, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge-trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0069] Referring back to Figure 3 , the peripheral circuitry 302 can be coupled to the array of storage cells 301 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the array of storage cells 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target storage cell 306 via the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some example peripheral circuitry is shown, including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus 518. It should be understood that additional peripheral circuitry not shown in FIG. 5 can also be included in some examples. Figure 5

[0070] ​The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed to the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying bit line voltages obtained from the voltage generator 510.

[0071] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages obtained from the voltage generator 510. In some implementations, the row decoder / word line driver 508 can also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform program operations on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and obtain word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0072] Control logic 512 can be coupled to and configured to control the operation of each of the other portions of the peripheral circuitry described above. Registers 514 can be coupled to control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuitry. Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic 512, and to buffer and relay status information received from control logic 512 to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and act as a data I / O interface and data buffer to buffer and relay data to or from memory cell array 301.

[0073] Reference Figure 6 In some embodiments, the memory system 102 is coupled with a host and performs various feedbacks in response to instructions from the host. The memory system 102 can include a memory controller 106 for controlling a memory device 104 to perform read, write, erase, etc. operations, and the memory controller 106 can also be coupled with the memory device 104 in any suitable manner.

[0074] The memory controller 106 can include a host interface (I / F) 1061, a memory interface (I / F) 1062, a processor 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, and a bus 1060. The host interface 1061 is a connection interface between the host 108 and the memory controller 106, and allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104, and is used to implement data transmission between the memory controller 106 and the memory device 104. The processor 1063 is used to control the memory system 106 as a whole, and the specific steps described above regarding the memory controller are mainly performed and completed by the processor 1063 here. In some embodiments, the processor 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), etc. The ROM 1069 generally contains firmware or firmware program code of the memory controller 106, which is used to initialize and operate the components of the memory controller, and the RAM 1070 is generally used to buffer data. The error correction module 1064 can further include an encoding part and a decoding part; the encoding part is used to encode the data to be stored to obtain check data, and the decoding part is used to decode the check data to detect and correct possible error data during data transmission.

[0075] The garbage collection module 1065 is used to read out valid data on some storage blocks, rewrite them, and then mark the storage blocks to obtain new spare storage blocks after the storage space of the memory device reaches a certain threshold. The general implementation of garbage collection can be divided into three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to a target storage block. At this time, all data in the source storage block become invalid data, and the source storage block is marked and can be used as a new spare storage block. The wear leveling module 1066 is used to keep the wear (number of erasures) of each storage block in the memory system balanced through data statistics and algorithms. The general implementation of wear leveling can be divided into two steps: selecting a source storage block where cold data is located; and reading valid data on the source storage block and writing it to a storage block with a relatively large number of erasures, at which time the valid data in the source storage block becomes invalid data and is marked.

[0076] Reference Figure 7In some example embodiments, the peripheral circuit is configured to perform the following steps: S701, in response to the read command, sequentially obtaining the 0th to 1st read result, the 1st to 2nd read result, …, the (N-1)th to Nth read result, and flipping the (K-1)th to Kth read result among the 0th to 1st read result, the 1st to 2nd read result, …, the (N-1)th to Nth read result; S702, applying the Kth read voltage to the word line coupled with the at least one code word according to the Kth read voltage; S703, storing the sensed data of the at least one code word at the Kth read voltage in the sense latch DS; S704, performing XOR operation on the sensed data at the (K-1)th read voltage stored in the L latch DL and the sensed data at the Kth read voltage stored in the sense latch DS to generate an XOR result, i.e., the (K-1)th to Kth flipping result, and storing the (K-1)th to Kth flipping result in the second data latch D2; S705, transferring the data stored in the sense latch DS to the L latch DL, at which time the data stored in the L latch DL is the sensed data at the Kth read voltage; S706, after transferring the data stored in the sense latch DS to the L latch DL, setting the (K+1)th read voltage according to the Kth read voltage and the step voltage before applying the corresponding (K+1)th read voltage to the word line coupled with the at least one code word; and S707, transferring the (K-2)th to (K-1)th read result stored in the second data latch D2 to the cache latch DC; S708, during the period from storing the sensed data of the at least one code word at the Kth read voltage in the sense latch DS to transferring the data stored in the sense latch DS to the L latch DL, the data of the (K-2)th to (K-1)th read result (e.g., the data amount is 18 KB) can be output from the data port DQ, S709, and transferred to the outside of the memory device for data processing to obtain the Kth flipping result. Here, the first flipping result to the Nth flipping result are used to represent the threshold voltage (Vt) distribution of the at least one code word within the range of the first read voltage to the Nth read voltage.

[0077] It should be noted that when K = 1, for the first read, the first flipping result is not obtained during the period of applying the first read voltage to the word line coupled with the at least one code word, and the cache latch DC stores a default value / set value, e.g., both are “0”; the 0th read result stored in the L latch DL during the period of obtaining the first read result is the default value / set value (e.g., both are “0”). When K ≥ 2, for sequential reading, e.g., the second read, the first flipping result is obtained during the period of applying the second read voltage to the word line coupled with the at least one code word, and the cache latch DC stores the first flipping result; the first read result stored in the L latch DL during the period of obtaining the second read result.

[0078] Threshold voltage (Vt) distribution read is used to draw threshold voltage distribution state of memory cells in three-dimensional NAND type memory; threshold voltage (Vt) distribution read protocol is similar to sequential cache read, except for read voltage and page address; threshold voltage (Vt) distribution read needs to do more page buffer operations, sensing data from the last read is stored in cache latch DC, and sensing data of the current read is stored in the second data latch D2. For each read voltage read, all data stored in the cache latch DC is output from the input / output (IO) port, for example, all data of at least one codeword, at least one codeword is based on data of one physical page, for example, data amount size is 18KB, all data of at least one codeword takes too much time in the transmission process, for example, too much time on a low-speed test platform; more time is needed to process these output data before drawing the threshold voltage (Vt) distribution.

[0079] Therefore, embodiments of the present application provide a memory device and an operating method thereof, and a memory system.

[0080] In a first aspect, embodiments of the present application provide a memory device, which refers to Figure 8 The memory device includes: a memory cell array including a plurality of memory cells, a preset number of memory cells forming one codeword; a peripheral circuit coupled with the memory cell array and configured to perform the following steps: S808, in response to a first command, obtaining a Kth flipping result corresponding to at least one codeword under a Kth read voltage; the Kth flipping result includes the number of bits representing the flipping of the read results of at least one codeword under the Kth read voltage and the (K-1)th read voltage; the Kth read voltage and the (K-1)th read voltage have a preset difference; wherein 1≤K≤N, K and N are natural numbers; storing information representing the Kth flipping result; S809, in response to a second command, outputting information representing the Kth flipping result.

[0081] It should be noted that, Figure 8 、 Figure 9 and Figure 10 The Kth read process is shown, the (K-1)th flipping result is obtained, the information representing the (K-1)th flipping result is stored, and the specific process of outputting the information representing the (K-1)th flipping result. Here and hereinafter, the specific process of obtaining, storing and outputting the Kth flipping result can be understood with reference to the specific process of obtaining, storing and outputting the (K-1)th flipping result shown in Figure 8 、 Figure 9 and Figure 10 .

[0082] Here, the structure of the memory device refers to the foregoing Figure 3The details are not described here.

[0083] In some embodiments, the memory device includes an array of memory cells, the array of memory cells including a plurality of memory cells, a preset number of memory cells forming a code word (CW).

[0084] In some embodiments, a code word includes a number of memory cells, and the number of memory cells included in a code word is the same as the number of memory cells included in one time of encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of memory cells included in a code word can be less than or equal to the number of memory cells coupled by a physical page, such as the number of memory cells included in a code word being 1 / 4 of the number of memory cells coupled by a physical page. In some specific embodiments, a code word can include a number of memory cells ranging from 2 4 to 2 12 . For example, a code word can include 2 4 , 2 8 , or 2 12 memory cells.

[0085] In general, different memory systems can select different sizes of code words to meet their performance, reliability, and storage requirements.

[0086] It should be noted that in practice, a code word will have some additional reserved space for management and error correction, so the actual number of memory cells required may be slightly more than the calculation result above.

[0087] It can be understood that a code word can include a plurality of memory cells, and the number of memory cells included in a code word can be adjusted according to actual conditions.

[0088] In some embodiments, in the process of reading the memory device, one read operation reads out the data of one physical page, and when the number of memory cells included in a code word is less than the number of memory cells coupled by a physical page, the code word is the unit that can be executed when obtaining the Kth flipping result, but it is not excluded that it is a plurality of code words. That is, at least one code word corresponding to the Kth flipping result under the current read voltage can be obtained here. For example, a physical page can include 4 code words, and the page buffer hardware operation can count the fail bit count (FBC) of the 4 code words respectively at one time, and then the FBC of the four code words is added to obtain the FBC of a physical page, and the subsequent calculation uses the added value. It can be understood that the Kth flipping result here can be based on the data of a physical page, and a physical page can include a plurality of code words.

[0089] It should be noted that the read result of the at least one code word at the Kth read voltage (hereinafter can be referred to as the "Kth read result") can be understood as follows: in the storage cells included in the at least one code word, the read result of the storage cell with a threshold voltage (Vt) less than the Kth read voltage is "1", and the read result of the storage cell with a threshold voltage (Vt) greater than or equal to the Kth read voltage is "0". By counting the data with a read result of "1" in the Kth read result, the number of storage cells with a threshold voltage (Vt) less than the Kth read voltage can be obtained. The result of the flip in the read result of the at least one code word at the Kth read voltage and the (K-1)th read voltage (hereinafter can be referred to as the "(K-1)th to Kth read result") can be understood as follows: in the storage cells included in the at least one code word, the read result of the storage cell with a threshold voltage (Vt) less than the Kth read voltage and greater than or equal to the (K-1)th read voltage is "1", the read result of the storage cell with a threshold voltage (Vt) greater than or equal to the Kth read voltage is "0", and the read result of the storage cell with a threshold voltage (Vt) less than the (K-1)th read voltage is "0". By counting the data with a read result of "1" in the (K-1)th to Kth read result, the number of storage cells with a threshold voltage (Vt) less than the Kth read voltage and greater than or equal to the (K-1)th read voltage can be obtained, that is, the number of bits that flip in the read result of the at least one code word at the Kth read voltage and the (K-1)th read voltage can be obtained.

[0090] It should be noted that when K=1, the read result of the at least one code word at the (K-1)th read voltage is the zeroth read result, and the zeroth read result can be a default value / set value, for example, the zeroth read result can be "0". When K=1, the first flip result is the number of bits that flip in the read result of the at least one code word at the first read voltage and the zeroth read voltage, that is, since the zeroth read result is a default value / set value (for example, all "0"), the first flip result can be understood as the number of read results of the at least one code word at the first read voltage being "1".

[0091] Here and below, the information representing the Kth flip result output in response to the second command includes the Kth flip result. In this way, since the data amount of the Kth flip result is less than the data amount of the (K-1)th to Kth read result, transmission time can be saved. For example, the data amount of the at least one code word can be 18KB, the data amount of the (K-1)th to Kth read result is the same as the data amount of the at least one code word, and the data amount of the Kth flip result can be 4B, the data amount of the Kth flip result is less than the data amount of the (K-1)th to Kth read result, and compared with transmitting the (K-1)th to Kth read result, transmitting the Kth flip result can save transmission time.

[0092] In some embodiments, the preset difference values can be the same or different. Illustratively, the preset difference values are the same, i.e., the preset difference value is one step voltage, that is, the Kth read voltage is different from the (K-1)th read voltage by one step voltage. The setting of the first read voltage or the starting voltage, and the setting of the step voltage will be described in detail later, and will not be described here.

[0093] Reference Figure 9 In some embodiments, the first command can be implemented by setting a Voltage Frequency Converter (VFC) mode of the memory device. Illustratively, the peripheral circuit is configured to count the number of (K-1)th to Kth read results as "1" using the VFC, and the number is used to represent the Kth flipping result.

[0094] Reference Figure 9 In some embodiments, the second command is configured by a set feature command; the peripheral circuit is configured to perform the following steps: S808, storing information representing the Kth flipping result in a reserved field of the set feature command; S809, in response to the set feature command, outputting information representing the Kth flipping result according to the information representing the Kth flipping result stored in the reserved field.

[0095] In the embodiments of the present application, the second command is configured by a set feature command, that is, the second command can be hidden in the set feature command, and the information representing the Kth flipping result is stored in the reserved field of the set feature command, and the information representing the Kth flipping result is outputted in response to the set feature command, which does not damage the basic feature function of the set feature command, and can also achieve the storage and output of the information of the Kth flipping result.

[0096] Reference Figure 9 In some embodiments, the peripheral circuit is configured to perform the following steps: S8081, S8083 and S8084, according to the Kth flipping result being less than or equal to a preset value, storing the Kth flipping result in the reserved field; S8081, S8082 and S8084, according to the Kth flipping result being greater than the preset value, storing a modified value of the Kth flipping result in the reserved field; the storage space occupied by the modified value of the Kth flipping result is less than the storage space occupied by the Kth flipping result; S809, in response to the set feature command, outputting information representing the Kth flipping result according to at least the Kth flipping result or the modified value of the Kth flipping result stored in the reserved field of the set feature command.

[0097] In some embodiments, the preset value can be an empirical value; or can be a default value configured when the memory device is shipped, which is obtained through a large number of simulation experiments before the memory device is shipped.

[0098] In some embodiments, the modified value of the Kth flipping result can be a product of the Kth flipping result and a modification coefficient. The modification coefficient can be a default value / set value. Exemplarily, the modification coefficient can be a number greater than 0 and less than 1.

[0099] In some embodiments, according to that the Kth flipping result is less than or equal to a preset value, the Kth flipping result is stored in the reserved field, and in response to the set feature command, the Kth flipping result is outputted at least according to the Kth flipping result stored in the reserved field of the set feature command; or, according to that the Kth flipping result is greater than the preset value, a modified value of the Kth flipping result is stored in the reserved field, and in response to the set feature command, the Kth flipping result is outputted at least according to the modified value of the Kth flipping result stored in the reserved field of the set feature command and the modification coefficient. Exemplarily, the preset value can be 256 (corresponding to 9-bit binary number 100000000), and the modification coefficient can be 1 / 5. When the Kth flipping result is 257 (corresponding to 9-bit binary number 100000001) greater than the preset value, the modified value of the Kth flipping result is 257*(1 / 5), and 257*(1 / 5) is rounded to 51 (corresponding to 6-bit binary number 110011). The modified value 51 of the Kth flipping result is stored in the reserved field, and the 6-bit storage space occupied by the modified value 51 of the Kth flipping result is less than the 11-bit storage space occupied by the Kth flipping result 257. In response to the set feature command, the Kth flipping result 51 / (1 / 5) = 255 (corresponding to 8-bit binary number 11111111) is outputted at least according to the modified value 51 of the Kth flipping result and the modification coefficient 1 / 5; or, the preset value can be 256 (corresponding to 9-bit binary number 100000000), and when the Kth flipping result is 256 (corresponding to 9-bit binary number 100000000) equal to the preset value, the Kth flipping result 256 is stored in the reserved field. In response to the set feature command, the Kth flipping result 256 (corresponding to 9-bit binary number 100000000) is outputted at least according to the Kth flipping result 256. In the case that the Kth flipping result is greater than the preset value, the accuracy of the counting value is slightly lost, for example, in the case that the Kth flipping result is 257 greater than the preset value 256, the modified value of the Kth flipping result stored in the reserved field is 51, and the Kth flipping result 51 / (1 / 5) = 255 is outputted. Compared with the Kth flipping result 257 obtained by the VFC, the Kth flipping result 255 loses the accuracy of 2 counting values. In the case that the Kth flipping result is greater than the preset value, the accuracy of the counting value is slightly lost, which does not affect the threshold voltage distribution diagram, for example, which can be well applied to the threshold voltage distribution diagram with logarithmic coordinates on the Y-axis.

[0100] Reference Figure 9In some embodiments, the first flipping result to the Nth flipping result are used to represent the threshold voltage distribution of the at least one code word in the first reading voltage to the Nth reading voltage range.

[0101] Exemplarily, when K = 1, for the first reading, the first reading result is obtained, and the first flipping result is not obtained; when K ≥ 2, for the sequential reading, for example, the second reading, the first flipping result and the second reading result are obtained, the first flipping result is the number of the first reading result and the zeroth reading result being “1”, which can represent the number of the storage cells whose threshold voltage (Vt) is less than the first reading voltage in the storage cells included in the at least one code word; for the third reading, the second flipping result and the third reading result are obtained, the second flipping result is the number of the first reading result and the second reading result being “1”, which can represent the number of the storage cells whose threshold voltage (Vt) is less than the second reading voltage and greater than or equal to the first reading voltage in the storage cells included in the at least one code word; and the like is sequentially deduced until the first flipping result to the Nth flipping result are obtained. In this way, the distribution of the threshold voltage of the storage cells included in the at least one code word at the first reading voltage to the Nth reading voltage can be obtained according to the first flipping result to the Nth flipping result.

[0102] Reference Figure 9 In some embodiments, the peripheral circuit is configured to: S8081, S8083 and S8084, set the flag value stored in the reserved field to the first state according to the Kth flipping result being less than or equal to the preset value; S8081, S8082 and S8084, set the flag value stored in the reserved field to the second state according to the Kth flipping result being greater than the preset value; and S809, output the information representing the Kth flipping result according to the flag value stored in the reserved field and the Kth flipping result / the modified value of the Kth flipping result.

[0103] Exemplarily, according to the Kth flipping result being less than or equal to a preset value, the flag value stored in the reserved field is set to the second state, for example, the flag value c_vfc_maxcountX5=0 is set, the Kth flipping result is obtained, and then the flag value set to the second state and the Kth flipping result are stored in the reserved field of the set feature command. In response to the set feature command, according to the flag value stored in the reserved field of the set feature command being set to the second state and the Kth flipping result, the Kth flipping result is output. Or, according to the Kth flipping result being greater than the preset value, the flag value stored in the reserved field is set to the first state, for example, the flag value c_vfc_maxcountX5=1 is set, the modified value of the Kth flipping result is obtained, and then the flag value set to the first state and the modified value of the Kth flipping result are stored in the reserved field of the set feature command. In response to the set feature command, according to the flag value stored in the reserved field of the set feature command being set to the first state and the modified value of the Kth flipping result, the Kth flipping result is output.

[0104] Reference Figure 9 In some embodiments, the Kth read voltage is a sum of the first read voltage and K step voltages; the reserved field includes a first address area, a second address area, a third address area, and a fourth address area; the first address area is configured to store the first read voltage; the second address area is configured to store the step voltage; the third address area is configured to store the Kth flipping result / modified value of the Kth flipping result; the fourth address area is configured to store the flag value; and the peripheral circuit is configured to, in response to the set feature command, output information representing the Kth flipping result according to the Kth flipping result / modified value of the Kth flipping result stored in the third address area and the flag value stored in the fourth address area.

[0105] In some embodiments, the end voltage can be controlled by the number of times of step voltage adjustment. Exemplarily, the first read voltage (or initial voltage) can be -1V, the step voltage can be 0.1V, N=56, and the first read voltage -1V is adjusted by 55 times of step voltage to obtain the fifty-sixth read voltage 4.5V, which is also referred to as the end voltage.

[0106] In the embodiments of the present application, the fourth address area and the third address area of the reserved field can be used to store the flag value and the Kth flipping result / modified value of the Kth flipping result, respectively, without occupying additional storage space, and information representing the Kth flipping result can be output in response to the set feature command according to the Kth flipping result / modified value of the Kth flipping result stored in the third address area and the flag value stored in the fourth address area. The basic feature function of the set feature command can not be damaged, and the storage and output of the information of the Kth flipping result can be realized.

[0107] Reference Figure 9In some embodiments, the voltage range to which the first read voltage to the Nth read voltage belongs is -3V to 6V; the voltage range of the step voltage is 0.01V to 0.5V. The voltage range to which the first read voltage to the Nth read voltage belongs is -1V to 4.5V, -2V to 5.0V, or -3V to 5.5V; the voltage range of the step voltage is 0.05V, 0.1V, 0.2V, 0.3V, or 0.4V.

[0108] In some embodiments, with the voltage range to which the first read voltage to the Nth read voltage belongs being fixed, the smaller the step voltage, the more times the step voltage is adjusted (i.e. the larger N), and the more details of the threshold voltage distribution of the at least one code word in the first read voltage to the Nth read voltage range.

[0109] For example, the voltage range is -1V to 4.5V, the step voltage can be 0.5V, N = 12, the first read voltage -1V is adjusted by 11 times of step voltage to obtain the twelfth read voltage 4.5V, at this time the twelfth read voltage 4.5V is also called the end voltage; the step voltage can be 0.05V, N = 111, the first read voltage -1V is adjusted by 110 times of step voltage to obtain the one hundred and twelfth read voltage 4.5V, at this time the one hundred and twelfth read voltage 4.5V is also called the end voltage. Compared with 12 times of threshold voltage distribution data when the step voltage can be 0.5V, 111 times of threshold voltage distribution data when the step voltage can be 0.05V, the more details of the threshold voltage distribution.

[0110] In some embodiments, with the step voltage being fixed, the larger the voltage range to which the first read voltage to the Nth read voltage belongs, the more times the step voltage is adjusted (i.e. the larger N), and the more details of the threshold voltage distribution of the at least one code word in the first read voltage to the Nth read voltage range.

[0111] For example, the step voltage can be 0.1V, the voltage range is -1V to 4.5V, N = 56, the first read voltage -1V is adjusted by 55 times of step voltage to obtain the fifty-sixth read voltage 4.5V, at this time the fifty-sixth read voltage 4.5V is also called the end voltage; the voltage range is -3V to 6V, N = 91, the first read voltage -1V is adjusted by 90 times of step voltage to obtain the ninety-first read voltage 4.5V, at this time the ninety-first read voltage 4.5V is also called the end voltage. Compared with 56 times of threshold voltage distribution data when the voltage range is -1V to 4.5V, 91 times of threshold voltage distribution data when the voltage range is -3V to 6V, the more details of the threshold voltage distribution.

[0112] Reference Figure 9In some embodiments, the peripheral circuit is configured to: store the (K-1)th flipping result / the modified value of the (K-1)th flipping result in the reserved field before obtaining the Kth flipping result corresponding to the at least one code word under the Kth read voltage; and output the information of the (K-1)th flipping result in response to the set feature command during the process of obtaining the Kth flipping result corresponding to the at least one code word under the Kth read voltage.

[0113] In some embodiments, during the Kth reading process (refer to Figure 9 Steps S802 to S805), the (K-1)th flipping result can be obtained and stored according to the VFC, and the (K-1)th flipping result can also be output according to the set feature command. Illustratively, during the word line / bit line setting stage of the at least one code word under the Kth read voltage, for example, during the stage of applying the corresponding driving voltage to the word line / bit line (refer to Figure 9 Step S802), the (K-1)th flipping result / the modified value of the (K-1)th flipping result is obtained and stored according to the VFC; after the word line / bit line setting of the at least one code word under the Kth read voltage is completed, i.e., after the process of obtaining the (K-1)th to Kth reading results (refer to Figure 9 Steps S803 to S805), the (K-1)th flipping result is output in response to the set feature command.

[0114] Refer to Figure 9 In some embodiments, the peripheral circuit is configured to perform the following steps: S801, in response to a third command, obtain flipping results corresponding to the at least one code word under a plurality of read voltages respectively; the plurality of read voltages include a first read voltage to an Nth read voltage, and the flipping results include a first flipping result to an Nth flipping result; wherein obtaining the Kth flipping result in the first flipping result to the Nth flipping result includes: S803, reading the stored data of the at least one code word under the Kth read voltage to obtain second reading data; S804, performing logical operation on the first reading data and the second reading data to obtain third reading data; the first reading data is the stored data of the at least one code word read under the (K-1)th read voltage; and S808, in response to a first command, counting the number of bits in the third reading data representing the flipping of the second reading data compared with the first reading data to obtain the Kth flipping result.

[0115] It should be noted that when K = 1, for the first reading, the first read data is a default value / set value, for example, all "0", the second read data is the stored data of the at least one code word read at the first read voltage, and the third read data is the zeroth to first read result; when K≥2, for sequential reading, for example, the second reading, the first read data is the stored data of the at least one code word read at the first read voltage, the second read data is the stored data of the at least one code word read at the second read voltage, the third read data is the first to second read result, and so on, for the Kth reading, the first read data is the stored data of the at least one code word read at the (K-1)th read voltage, i.e., the (K-1)th read result, the second read data is the stored data of the at least one code word read at the Kth read voltage, i.e., the Kth read result, and the third read data is the result of the at least one code word in the two read results at the Kth read voltage and the (K-1)th read voltage, i.e., the (K-1)th to Kth read result.

[0116] In some embodiments, the third command comprises a read command. The third command can be a read cache random command, or a read cache sequential command. Here and below, the third command is taken as an example of a read cache sequential command.

[0117] Exemplarily, when K = 1, for the first reading, the word line / bit line of the at least one code word is set at the first read voltage; the stored data of the at least one code word is read at the first read voltage to obtain the first read result; the first read result and the zeroth read result are subjected to an exclusive OR operation to obtain the zeroth to first read result; the first read result is used to overwrite the zeroth read result; wherein the zeroth read result is a default value / set value; when K≥2, for sequential reading, for example, the second reading, the word line / bit line of the at least one code word is set at the second read voltage, and in response to the first command, the number of bits in the zeroth to first read result representing the flipping of the first read result compared with the zeroth read result is counted to obtain the first flipping result, and the first flipping result / amended value of the first flipping result is stored; the stored data of the at least one code word is read at the second read voltage to obtain the second read result; the second read result and the first read result are subjected to an exclusive OR operation to obtain the first to second read result; the second read result is used to overwrite the first read result; in response to the second command, the first flipping result is output according to the stored first flipping result / amended value of the first flipping result; and so on, until the first flipping result to the Nth flipping result is output.

[0118] In some embodiments, when K = 1, for the first reading, the flag value is set to a first state, for example, the flag value c_vfc_maxcountX5 = 1 is set; when K ≥ 2, for the sequential reading, for example, the second reading, the first flipping result is obtained, and according to the first flipping result being less than or equal to a preset value and the flag value c_vfc_maxcountX5 = 1, the flag value stored in the reserved field is set to a second state, for example, the flag value c_vfc_maxcountX5 = 0 is set; or, according to the first flipping result being greater than the preset value and the flag value c_vfc_maxcountX5 = 0, the flag value stored in the reserved field is set to the first state, for example, the flag value c_vfc_maxcountX5 = 1 is set; in turn, the Kth flipping result and the flag value in the second state are obtained and stored, or the Kth flipping result and the flag value in the first state are obtained and stored, until the first flipping result to the Nth flipping result and the flag values corresponding to the first flipping result to the Nth flipping result are obtained.

[0119] Reference Figure 9 In some embodiments, the time length taken to obtain the second reading data in response to the third command is a first time length; the time length taken to obtain the Kth flipping result / the modified value of the Kth flipping result in response to the first command is a second time length; and the second time length is less than the first time length.

[0120] As Figure 9 indicated, the time length for executing the first command can be parallel to the time length for the Kth reading, that is, the process of obtaining the (K-2)th flipping result / the modified value of the (K-1)th flipping result in response to the first command can be hidden in the process of obtaining the (K-1)th reading result to the Kth reading result in response to the third command. For example, when K = 2, the process of obtaining the first flipping result / the modified value of the first flipping result in response to the first command can be hidden in the word line / bit line setting stage at the second reading voltage in the process of obtaining the first reading result to the second reading result in response to the third command.

[0121] In the embodiments of the present application, the execution process of the first command can be hidden in the execution process of the third command, which can not damage the basic characteristic function of the third command (for example, the sequential reading buffer command), and can also realize the acquisition and storage of the information of the Kth flipping result.

[0122] In some embodiments, the page buffer of the memory device can include a sense latch DS (also referred to as a sense read latch DS), at least one data latch, an L latch DL, and a cache latch DC. Illustratively, the page buffer of a QLC type memory device can include the sense latch DS, four data latches, the L latch DL, and the cache latch DC, the four data latches being a first data latch D1, a second data latch D2, a third data latch D3, and a fourth data latch DX. The sense latch DS can store data from a lower page, a middle page, an upper page, or an extra page measured (or read) on a bit line, the data of the lower page, the middle page, the upper page, or the extra page stored in the sense latch DS being transmitted to the first data latch D1, the second data latch D2, the third data latch D3, or the fourth data latch DX, respectively; the first data latch D1, the second data latch D2, the third data latch D3, and the fourth data latch DX can be used to store data of the lower page, the middle page, the upper page, and the extra page of the memory device, respectively; the L latch DL can be used to store FBC data, such as storing the (K-1)th to the Kth read results; the cache latch DC can be used to store data outputted to the outside of the page buffer / inputted to the page buffer, such as storing the Kth flip results outputted, the Kth flip results being outputted to the cache latch DC in response to a set features command, the Kth flip results / a modified value of the Kth flip results stored in a reserved field of the set features command, the data stored in the cache latch DC can be transmitted from a data port DQ to the outside of the memory device.

[0123] Reference Figure 10 In some embodiments, the peripheral circuit includes a first latch, a second latch, and a third latch; the first latch is configured to store first read data; the second latch is configured to store second read data; and the third latch is configured to store third read data.

[0124] Here and below, the first latch, the second latch, the third latch can be respectively understood as a data latch (for example, a second data latch D2), a sense latch DS, and an L latch DL. Exemplarily, when K = 1, for the first reading, the second data latch D2 stores a default value / set value, for example, both are "0", the sense latch DS stores a first reading result, and the L latch DL stores an exclusive-OR result of the data stored by the second data latch D2 and the data stored by the sense latch DS. After obtaining the exclusive-OR result, the first reading result stored by the sense latch DS is transmitted to the second data latch D2, and at this time, the second data latch D2 stores the first reading result. When K ≥ 2, for sequential reading, for example, the second reading, the second data latch D2 stores the first reading result, the sense latch DS stores the second reading result, and the L latch DL stores an exclusive-OR result of the data stored by the second data latch D2 and the data stored by the sense latch DS. After obtaining the exclusive-OR result, the second reading result stored by the sense latch DS is transmitted to the second data latch D2, and at this time, the second data latch D2 stores the second reading result. By analogy, the second data latch D2 stores the (K-1)th reading result, the sense latch DS stores the Kth reading result, and the L latch DL stores an exclusive-OR result of the data stored by the second data latch D2 and the data stored by the sense latch DS, that is, the (K-1)th to Kth reading result. After obtaining the (K-1)th to Kth reading result, the Kth reading result stored by the sense latch DS is transmitted to the second data latch D2, and at this time, the second data latch D2 stores the Kth reading result.

[0125] Reference Figure 10 In some embodiments, the peripheral circuit is configured to: compare the Kth flip result with a preset value to obtain a comparison result; and determine, according to the comparison result, whether to store the Kth flip result / modified value of the Kth flip result in the preset field. The peripheral circuit further comprises a fourth latch. The fourth latch is configured to perform: S807, store the Kth flip result in the preset field, and output the Kth flip result.

[0126] Here and below, the fourth latch can be understood as a cache latch DC. Exemplarily, the cache latch DC stores the output Kth flip result. The cache latch DC is configured to output the Kth flip result to the cache latch DC according to the Kth flip result / modified value of the Kth flip result stored in the reserved field of the set feature command in response to the set feature command.

[0127] Reference Figure 10In some embodiments, the peripheral circuit is configured to perform the following: S801, in response to the third command, sequentially obtain the first flipping result to the Nth flipping result, for the Kth flipping result among the first flipping result to the Nth flipping result; S802, according to the Kth read voltage, apply a corresponding read voltage to the word line coupled with the at least one code word; S803, store the second read data of the at least one code word sensed at the Kth read voltage in the second latch; S804, perform an exclusive-OR operation on the first read data stored in the first latch at the (K-1)th read voltage and the second read data stored in the second latch at the Kth read voltage, generate the third read data, and store the third read data in the third latch; S805, transmit the second read data stored in the second latch at the Kth read voltage to the first latch; S808, in response to the first command, before the second read data sensed at the Kth read voltage, generate the (K-1)th flipping result / amended value of the (K-1)th flipping result according to the third read data, and store the (K-1)th flipping result / amended value of the (K-1)th flipping result in the preset field; S809, in response to the setting feature command, in the process of obtaining the Kth flipping result, transmit the information representing the (K-1)th flipping result stored in the preset field to the fourth latch.

[0128] Exemplarily, when K = 1, for the first reading, the second data latch D2 stores a default value / set value, for example, both are “0”; a corresponding first read voltage is applied to the word line coupled with the at least one code word; the first read result of the at least one code word at the first read voltage is stored in the sensing latch DS; the data stored in the second data latch D2 is subjected to an exclusive-OR operation with the data stored in the sensing latch DS, an exclusive-OR result is generated, and the exclusive-OR result is stored in the L latch DL; the first read result stored in the sensing latch DS is transmitted to the second data latch D2, and at this time the second data latch D2 stores the first read result. When K ≥ 2, for sequential reading, for example, the second reading, a corresponding second read voltage is applied to the word line coupled with the at least one code word; in the stage (e.g. Figure 10 the step S802) set by the second read voltage, in response to the first command, the first flipping result / amended value of the first flipping result is generated according to the exclusive-OR result stored in the L latch DL, and the first flipping result / amended value of the first flipping result is stored in the preset field; in response to the setting feature command, in the process (e.g. Figure 10In the steps S803-S805, the information representing the first flipping result stored in the preset field is transmitted to the cache latch DC, and the data stored in the cache latch DC is the first flipping result. The first flipping result stored in the cache latch DC is used for transmission to the outside of the memory device, and the first flipping result is used to represent the threshold voltage distribution of the at least one code word under the first read voltage. By analogy, the first flipping result to the Nth flipping result are output. In this way, according to the first flipping result to the Nth flipping result obtained in the memory device and the first read voltage to the Nth read voltage corresponding thereto, the threshold voltage distribution of the at least one code word in the range of the first read voltage to the Nth read voltage can be obtained outside the memory device.

[0129] In the embodiments of the present application, the output of the first flipping result to the Kth flipping result obtained in the memory device can skip the input / output (IO) port, and the data output time is saved by responding to the setting feature command output.

[0130] Reference Figure 11 In some embodiments, the peripheral circuit is configured to perform the following steps: S806, after transmitting the Kth read result stored in the sensing latch DS under the Kth read voltage to the second data latch D2, setting the (K+1)th read voltage according to the Kth read voltage and the step voltage before the (K+1)th read, and S807, storing the (K-1)th to Kth read results to the cache latch DC.

[0131] Exemplarily, when K = 1, for the first read, the second data latch D2 stores a default value / set value, for example, both are "0"; a corresponding first read voltage is applied to the word line to which the at least one codeword is coupled; a first read result of the at least one codeword under the first read voltage is stored in the sensing latch DS; the data stored in the second data latch D2 is XORed with the data stored in the sensing latch DS to generate an XOR result, and the XOR result is stored in the L latch DL; the first read result stored in the sensing latch DS is transmitted to the second data latch D2, and at this time the second data latch D2 stores the first read result; after the first read result stored in the sensing latch DS is transmitted to the second data latch D2, a second read voltage is set according to the first read voltage and the step voltage before the second read, and the zeroth to first read results are stored in the cache latch DC; wherein the second read voltage can be used to be applied to the word line to which the at least one codeword is coupled in the second read; wherein for the first read, the cache latch DC stores a default value / set value, for example, both are "0"; by analogy, when K ≥ 2, for the sequential read, for example, the second read, after the cache latch DC is ready, the zeroth to first read results stored in the cache latch DC are output to the outside of the memory device until the zeroth to first read results, the first to second read results, …, the (N-1)th to N read results are output. In this way, according to the zeroth to first read results, the first to second read results, …, the (N-1)th to N read results obtained in the memory device, the first flip result, the second flip result, …, the Nth flip result can be obtained according to the zeroth to first read results, the first to second read results, …, the (N-1)th to N read results outside the memory device, and according to the first flip result to the Nth flip result and the first read voltage to the Nth read voltage corresponding thereto obtained outside the memory device, the threshold voltage distribution of the at least one codeword in the range of the first read voltage to the Nth read voltage can be obtained.

[0132] In some embodiments, the (K-1)th to Kth read results stored in the cache latch DC can be output to the outside of the memory device after the cache latch DC is ready by a read enable (RE) command.

[0133] In the embodiments of the present application, the zeroth to first read results, the first to second read results, the (N-1)th to Nth read results obtained in the memory device can be output to the outside of the memory device through the input / output (IO) port, that is, the acquisition, storage and output of the first to Kth flipping results obtained in the memory device do not affect the function of the zeroth to first read results, the first to second read results, the (N-1)th to Nth read results obtained in the memory device being output to the outside of the memory device through the input / output (IO) port.

[0134] In some embodiments, the memory device includes a NAND type memory.

[0135] In the embodiments of the present application, since the amount of data of the Kth flipping result of the at least one codeword obtained by the memory device is less than the amount of data of the result of flipping in the two read results of the at least one codeword at the Kth read voltage and the (K-1)th read voltage, compared with the result of transmitting the result of flipping in the two read results of the at least one codeword at the Kth read voltage and the (K-1)th read voltage, transmitting the Kth flipping result can save transmission time.

[0136] In a second aspect, the embodiments of the present application provide a memory system, referring to Figure 6 The memory system 102 includes one or more memory devices 104 of any one provided in the first aspect, and a memory controller 106 coupled to the memory device 104 and controlling the memory device 104.

[0137] Here, the structure of the memory system is described with reference to the foregoing Figure 6 which will not be repeated here.

[0138] As shown in Figure 11 and Figure 11 In some embodiments, the memory system 102 is coupled to a host and performs various feedback in response to instructions of the host. The memory system 102 can include a memory controller 106 and a memory device 104, the memory controller 106 being configured to control the memory device 104 to perform read, write, erase and other operations, and the memory controller 106 and the memory device 104 can also be coupled in any suitable manner.

[0139] Referring to Figure 11In some embodiments, the memory controller is configured to: send a first command and a second command; the first command indicates to obtain a Kth flipping result corresponding to the at least one codeword at a Kth read voltage; the second command indicates to output information representing the Kth flipping result; the memory device is configured to: receive the first command, obtain information representing the first flipping result to the Nth flipping result; receive the second command, output the information representing the first flipping result to the Nth flipping result; and send the obtained information representing the Kth flipping result to the memory controller; the memory controller is further configured to: generate information representing a threshold voltage distribution of the at least one codeword at the Kth read voltage using the information representing the Kth flipping result and the Kth read voltage.

[0140] Reference ​ In some embodiments, the memory controller is configured to: send a third command, the third command indicating to obtain third read data; the memory device is configured to: in response to the third command, obtain flipping results corresponding to the at least one codeword at a plurality of read voltages respectively; the plurality of read voltages comprises the first read voltage to the Nth read voltage, and the flipping results comprise the first flipping result to the Nth flipping result; obtaining a Kth flipping result in the first flipping result to the Nth flipping result comprises: reading stored data of the at least one codeword at a Kth read voltage to obtain second read data; performing a logical operation on the first read data and the second read data to obtain the third read data; the first read data is stored data of the at least one codeword read at a (K-1)th read voltage; in response to the first command, counting a number of bits representing flipping of the second read data relative to the first read data in the third read data to obtain the Kth flipping result; the memory controller is further configured to: generate information representing a threshold voltage distribution of the at least one codeword in a range of the first read voltage to the Nth read voltage using the information representing the first flipping result to the Nth flipping result and the first read voltage to the Nth read voltage.

[0141] In a third aspect, embodiments of the present disclosure provide an operation method of a memory device, the operation method comprising: in response to a first command, obtaining a Kth flipping result corresponding to at least one codeword formed by a preset number of storage units in the memory device at a Kth read voltage; the Kth flipping result comprising a number of bits representing flipping of a result of reading the at least one codeword at the Kth read voltage and a result of reading the at least one codeword at a (K-1)th read voltage; the Kth read voltage and the (K-1)th read voltage having a preset difference; wherein 1≤K≤N, K and N are natural numbers; storing information representing the Kth flipping result; in response to a second command, outputting the information representing the Kth flipping result.

[0142] In some embodiments, the operation method comprises: storing information representing the Kth flipping result in a reserved field of the set feature command; and outputting information representing the Kth flipping result according to the information representing the Kth flipping result stored in the reserved field in response to the set feature command; wherein the second command is configured by the set feature command.

[0143] In some embodiments, the operation method comprises: storing the Kth flipping result in the reserved field according to the Kth flipping result being less than or equal to a preset value; storing a modified value of the Kth flipping result in the reserved field according to the Kth flipping result being greater than the preset value; the modified value of the Kth flipping result occupying a storage space smaller than that of the Kth flipping result; and outputting information representing the Kth flipping result according to at least the Kth flipping result or the modified value of the Kth flipping result stored in the reserved field of the set feature command in response to the set feature command.

[0144] In some embodiments, the operation method comprises: setting a flag value stored in the reserved field to a first state according to the Kth flipping result being less than or equal to a preset value; setting the flag value stored in the reserved field to a second state according to the Kth flipping result being greater than the preset value; and outputting information representing the Kth flipping result according to the flag value stored in the reserved field and the Kth flipping result / modified value of the Kth flipping result.

[0145] In some embodiments, the operation method comprises: outputting information representing the Kth flipping result according to the Kth flipping result / modified value of the Kth flipping result stored in a third address area of the reserved field and a flag value stored in a fourth address area of the reserved field in response to the set feature command; wherein the Kth read voltage is a sum of a first read voltage and K step voltages; the first address area of the reserved field stores the first read voltage; the second address area of the reserved field stores the step voltage; the third address area of the reserved field stores the Kth flipping result / modified value of the Kth flipping result; and the fourth address area of the reserved field stores the flag value.

[0146] In some embodiments, the operation method comprises: storing the (K-1)th flipping result / modified value of the (K-1)th flipping result in the reserved field before obtaining the Kth flipping result corresponding to the at least one code word under the Kth read voltage; and outputting information representing the (K-1)th flipping result in response to the set feature command during the process of obtaining the Kth flipping result corresponding to the at least one code word under the Kth read voltage.

[0147] In some embodiments, the operation method comprises: in response to the third command, acquiring flip results corresponding to the at least one code word under a plurality of read voltages respectively; the plurality of read voltages comprise a first read voltage to an Nth read voltage, and the flip results comprise a first flip result to an Nth flip result; wherein acquiring a Kth flip result in the first flip result to the Nth flip result comprises: reading stored data of the at least one code word under the Kth read voltage to obtain second read data; performing logical operation on the first read data and the second read data to obtain third read data; the first read data is stored data of the at least one code word read under the (K-1)th read voltage; and in response to the first command, counting the number of bits in the third read data representing the flip of the second read data compared with the first read data to obtain the Kth flip result.

[0148] In some embodiments, the operation method comprises: in response to the third command, acquiring the first flip result to the Nth flip result in sequence, for a Kth flip result in the first flip result to the Nth flip result; applying a corresponding read voltage to a word line coupled with the at least one code word according to the Kth read voltage; storing second read data of the at least one code word sensed under the Kth read voltage in a second latch of a peripheral circuit of the memory device; performing exclusive-OR operation on the first read data stored in a first latch of the peripheral circuit under the (K-1)th read voltage and the second read data stored in a second latch under the Kth read voltage to generate third read data and store the third read data in a third latch of the peripheral circuit; transmitting the second read data stored in the second latch under the Kth read voltage to the first latch; in response to the first command, generating a (K-1)th flip result / amended value of the (K-1)th flip result according to the third read data before the second read data sensed under the Kth read voltage, and storing the (K-1)th flip result / amended value of the (K-1)th flip result in a preset field; and in response to a setting feature command, transmitting information representing the (K-1)th flip result stored in the preset field to a fourth latch of the peripheral circuit in the process of acquiring the Kth flip result.

[0149] The memory device used by the operation method of the memory device provided by the embodiments of the present application is the same as or similar to the memory device in each embodiment of the first aspect described above. For technical features not disclosed in detail in the embodiments of the present application, please refer to the memory device in each embodiment of the first aspect described above for understanding, which will not be described here again.

[0150] It should be understood that the term "in one embodiment" or "in an embodiment" as used throughout this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the application. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the processes described above does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application. The sequence of the above embodiments of the application is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0151] The above only describes the preferred embodiments of the application, and does not limit the protection scope of the application, and any equivalent structural transformation made according to the content of the specification and drawings of the application, or direct / indirect application in other related technical fields within the concept of the application is included in the protection scope of the application.

Claims

1. A memory device, characterized in that, include: A storage cell array includes multiple storage cells, and a predetermined number of the storage cells form a codeword; The peripheral circuitry, coupled to the memory cell array, is configured as follows: In response to a first command, the Kth flip result of at least one codeword at the Kth read voltage is obtained; the Kth flip result includes the number of bits that are flipped in the two read results at the Kth read voltage and the (K-1)th read voltage; there is a preset difference between the Kth read voltage and the (K-1)th read voltage; where 1≤K≤N, and K and N are natural numbers; Store information characterizing the Kth flip result; In response to the second command, information characterizing the result of the Kth flip is output.

2. The memory device according to claim 1, characterized in that, The second command is configured via a feature setting command; the peripheral circuit is configured as follows: Information characterizing the Kth flip result is stored in the reserved field of the setting feature command; In response to the setting feature command, information representing the Kth flip result is output based on the information representing the Kth flip result stored in the reserved field.

3. The memory device according to claim 2, characterized in that, The peripheral circuit is configured as follows: If the Kth flip result is less than or equal to a preset value, the Kth flip result is stored in the reserved field. If the Kth flip result is greater than the preset value, a correction value for the Kth flip result is stored in the reserved field; the storage space occupied by the correction value for the Kth flip result is less than the storage space occupied by the Kth flip result. In response to the setting feature command, information characterizing the Kth flip result is output, based at least on the Kth flip result stored in the reserved field of the setting feature command or the correction value of the Kth flip result.

4. The memory device according to claim 3, characterized in that, The first flip result to the Nth flip result are used to characterize the threshold voltage distribution of at least one of the codewords within the range of the first read voltage to the Nth read voltage.

5. The memory device according to claim 3, characterized in that, The peripheral circuit is configured as follows: If the Kth flip result is less than or equal to the preset value, the flag value stored in the reserved field is set to the first state; If the Kth flip result is greater than the preset value, the flag value stored in the reserved field is set to the second state; Based on the flag value stored in the reserved field and the correction value of the Kth flip result / the Kth flip result, output information characterizing the Kth flip result.

6. The memory device according to claim 5, characterized in that, The Kth read voltage is the sum of the first read voltage and the K step voltages; The reserved fields include a first address area, a second address area, a third address area, and a fourth address area; The first address area is configured to store the first read voltage; The second address area is configured to store the step voltage; The third address area is configured to store the Kth flip result / the correction value of the Kth flip result; The fourth address area is configured to store the flag value; The peripheral circuit is configured to: in response to the setting feature command, output information characterizing the Kth flip result based on the Kth flip result / correction value of the Kth flip result stored in the third address area and the flag value stored in the fourth address area.

7. The memory device according to claim 6, characterized in that, The voltage range from the first read voltage to the Nth read voltage is -3V to 6V; the voltage range of the step voltage is 0.01V to 0.5V.

8. The memory device according to claim 3, characterized in that, The peripheral circuit is configured as follows: Before obtaining the Kth flip result corresponding to at least one codeword at the Kth read voltage, the (K-1)th flip result / the correction value of the (K-1)th flip result is stored in the reserved field; During the process of acquiring the Kth flip result corresponding to at least one codeword at the Kth read voltage, in response to the setting feature command, the information of the (K-1)th flip result is output.

9. The memory device according to claim 3, characterized in that, The peripheral circuit is configured as follows: In response to the third command, at least one codeword is acquired under multiple read voltages, including a first read voltage to an Nth read voltage, and the flip results include a first flip result to an Nth flip result; wherein, acquiring the Kth flip result among the first flip results to the Nth flip results includes: At least one codeword's stored data is read under the Kth read voltage to obtain second read data; logical operations are performed on the first read data and the second read data to obtain third read data; the first read data is stored data of at least one codeword read under the (K-1)th read voltage; In response to the first command, the number of bits in the third read data that represent the flipping of the second read data compared to the first read data is counted to obtain the Kth flip result.

10. The memory device according to claim 9, characterized in that, The time elapsed after obtaining the second read data in response to the third command is the first time elapsed; the time elapsed after obtaining the Kth flip result / the correction value of the Kth flip result in response to the first command is the second time elapsed; wherein, the second time elapsed is less than the first time elapsed.

11. The memory device according to claim 9, characterized in that, The peripheral circuit includes: a first latch, a second latch, and a third latch; The first latch is configured to store the first read data; The second latch is configured to store the second read data; The third latch is configured to store the third read data.

12. The memory device according to claim 11, characterized in that, The peripheral circuit is configured as follows: The Kth flip result is compared with the preset value to obtain the comparison result; Based on the comparison result, determine the correction value of the Kth flip result / the Kth flip result to be stored in the preset field; The peripheral circuit also includes: a fourth latch; The fourth latch is configured to store the Kth flip result in the preset field and output the Kth flip result.

13. The memory device according to claim 12, characterized in that, The peripheral circuit is configured as follows: In response to the third command, the first flip result to the Nth flip result are obtained sequentially, and the Kth flip result among the first flip result to the Nth flip result is selected. According to the Kth read voltage, a corresponding read voltage is applied to at least one word line coupled to the codeword; The second read data sensed by the at least one codeword under the Kth read voltage is stored in the second latch; The first read data stored in the first latch at the (K-1)th read voltage and the second read data stored in the second latch at the Kth read voltage are XORed to generate the third read data, which is then stored in the third latch; the second read data stored in the second latch at the Kth read voltage is then transferred to the first latch. In response to the first command, before the second read data sensed at the Kth read voltage, a correction value of the (K-1)th flip result / the (K-1)th flip result is generated based on the third read data, and the correction value of the (K-1)th flip result / the (K-1)th flip result is stored in the preset field; In response to the setting feature command, during the process of obtaining the Kth flip result, the information representing the (K-1)th flip result stored in the preset field is transmitted to the fourth latch.

14. The memory device according to any one of claims 1 to 13, characterized in that, The memory device includes NAND flash memory.

15. A memory system, characterized in that, include: One or more memory devices as described in any one of claims 1 to 13; as well as A memory controller is coupled to and controls the memory device.

16. The memory system according to claim 15, characterized in that, The memory controller is configured to: send a first command and a second command; the first command instructs to acquire the Kth flip result corresponding to at least one codeword at the Kth read voltage; the second command instructs to output information characterizing the Kth flip result; The memory device is configured to: receive the first command and acquire information characterizing the first flip result to the Nth flip result; Receive the second command and output information characterizing the first flip result to the Nth flip result; And send the acquired information characterizing the Kth flip result to the memory controller; The memory controller is further configured to: generate information characterizing the threshold voltage distribution of the Kth read voltage of at least one of the codewords, using information characterizing the Kth flip result and the Kth read voltage.

17. The memory system according to claim 16, characterized in that, The memory controller is configured to send a third command, the third command instructing the acquisition of third read data; The memory device is configured to: In response to the third command, at least one codeword is acquired for each of the multiple read voltages; the multiple read voltages include a first read voltage to an Nth read voltage, and the flip results include a first flip result to an Nth flip result. Obtaining the Kth flip result from the first flip result to the Nth flip result includes: At least one codeword's stored data is read under the Kth read voltage to obtain second read data; logical operations are performed on the first read data and the second read data to obtain third read data; the first read data is stored data of at least one codeword read under the (K-1)th read voltage; In response to the first command, the number of bits in the third read data that represent the flipping of the second read data compared to the first read data is counted to obtain the Kth flip result; The memory controller is further configured to: generate information characterizing the threshold voltage distribution of at least one of the codewords within the range of the first read voltage to the Nth read voltage, using information characterizing the first flip result to the Nth flip result, and the first read voltage to the Nth read voltage.

18. A method of operating a memory device, characterized in that, include: In response to a first command, the Kth flip result corresponding to at least one codeword formed by a predetermined number of storage cells in the memory device at the Kth read voltage is obtained respectively; the Kth flip result includes the number of bits that are flipped in the two read results at the Kth read voltage and the (K-1)th read voltage; there is a predetermined difference between the Kth read voltage and the (K-1)th read voltage; wherein, 1≤K≤N, and K and N are natural numbers; Store information characterizing the Kth flip result; In response to the second command, information characterizing the result of the Kth flip is output.

19. The operating method according to claim 18, characterized in that, The operation method includes: The information characterizing the Kth flip result is stored in the reserved field of the feature setting command; In response to the setting feature command, information representing the Kth flip result is output based on the information representing the Kth flip result stored in the reserved field; The second command is configured through a feature setting command.

20. The operating method according to claim 19, characterized in that, The operation method includes: If the Kth flip result is less than or equal to a preset value, the Kth flip result is stored in the reserved field. If the Kth flip result is greater than the preset value, a correction value for the Kth flip result is stored in the reserved field; the storage space occupied by the correction value for the Kth flip result is less than the storage space occupied by the Kth flip result. In response to the setting feature command, information characterizing the Kth flip result is output, based at least on the Kth flip result stored in the reserved field of the setting feature command or the correction value of the Kth flip result.

21. The operating method according to claim 20, characterized in that, The operation method includes: If the Kth flip result is less than or equal to the preset value, the flag value stored in the reserved field is set to the first state; If the Kth flip result is greater than the preset value, the flag value stored in the reserved field is set to the second state; Based on the flag value stored in the reserved field and the correction value of the Kth flip result / the Kth flip result, output information characterizing the Kth flip result.

22. The operating method according to claim 21, characterized in that, The operation method includes: in response to the setting feature command, outputting information characterizing the Kth flip result based on the Kth flip result / correction value of the Kth flip result stored in the third address area of ​​the reserved field and the flag value stored in the fourth address area of ​​the reserved field; Wherein, the Kth read voltage is the sum of the first read voltage and the K step voltages; the first address area of ​​the reserved field stores the first read voltage; the second address area of ​​the reserved field stores the step voltage; the third address area of ​​the reserved field stores the Kth flip result / the correction value of the Kth flip result; and the fourth address area of ​​the reserved field stores the flag value.

23. The operating method according to claim 20, characterized in that, The operation method includes: Before obtaining the Kth flip result corresponding to at least one codeword at the Kth read voltage, the (K-1)th flip result / the correction value of the (K-1)th flip result is stored in the reserved field; During the process of acquiring the Kth flip result corresponding to at least one codeword at the Kth read voltage, in response to the setting feature command, the information of the (K-1)th flip result is output.

24. The operating method according to claim 20, characterized in that, The operation method includes: In response to the third command, at least one codeword is acquired under multiple read voltages, including a first read voltage to an Nth read voltage, and the flip results include a first flip result to an Nth flip result; wherein, acquiring the Kth flip result among the first flip results to the Nth flip results includes: At least one codeword's stored data is read under the Kth read voltage to obtain second read data; logical operations are performed on the first read data and the second read data to obtain third read data; the first read data is stored data of at least one codeword read under the (K-1)th read voltage; In response to the first command, the number of bits in the third read data that represent the flipping of the second read data compared to the first read data is counted to obtain the Kth flip result.

25. The operating method according to claim 24, characterized in that, The operation method includes: In response to the third command, the first flip result to the Nth flip result are obtained sequentially, and the Kth flip result among the first flip result to the Nth flip result is selected. According to the Kth read voltage, a corresponding read voltage is applied to at least one word line coupled to the codeword; the second read data sensed by the at least one codeword under the Kth read voltage is stored in a second latch of the peripheral circuit of the memory device; the first read data stored in the first latch of the peripheral circuit under the (K-1)th read voltage and the second read data stored in the second latch under the Kth read voltage are XORed to generate the third read data, which is stored in a third latch of the peripheral circuit; the second read data stored in the second latch under the Kth read voltage is transferred to the first latch; In response to the first command, before the second read data sensed at the Kth read voltage, a correction value of the (K-1)th flip result / the (K-1)th flip result is generated based on the third read data, and the correction value of the (K-1)th flip result / the (K-1)th flip result is stored in the preset field; In response to the setting feature command, during the process of obtaining the Kth flip result, the information representing the (K-1)th flip result stored in the preset field is transmitted to the fourth latch of the peripheral circuit.

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