Storage system, electronic product, and operation method of storage system

Abstract

The invention discloses a storage system, an electronic product and an operation method of the storage system, and belongs to the technical field of storage. In the embodiment of the invention, the current test circuit is packaged in the memory system comprising the memory, so that the current on the pin of the memory is directly tested through the current test circuit. Therefore, on one hand, the current of the memory can be tested anytime and anywhere without building a test board, and the test process is simple and is not limited by the environment. And on the other hand, the current test circuit can test the current on the pins of the memory at any time, so that the current data of the memory can be monitored in real time in the working process of the memory, and the accuracy of power consumption evaluation is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage system, an electronic product, and a method for operating the storage system. Background Technology

[0002] Currently, to assess memory power consumption, the memory current can be tested, and the power consumption can be evaluated based on the tested current and the rated operating voltage. In related technologies, a test bench can be set up, including an oscilloscope, to test the memory current. However, this testing method is complex due to the need for a test bench; furthermore, the oscilloscope can only test the memory current over a few specific, intermittent time periods, thus affecting the accuracy of the power consumption assessment. Summary of the Invention

[0003] This application provides a storage system, an electronic product, and a method for operating the storage system. The technical solution is as follows:

[0004] On one hand, a storage system is provided, the storage system including a first memory and a current testing circuit, the first memory having a first pin, the current testing circuit having a first test terminal and a data output terminal, the first test terminal being connected to the first pin;

[0005] The first pin is used to supply power to the first memory through the first power supply circuit;

[0006] The current testing circuit is used to collect the current on the first pin during the operation of the first memory, and output the current on the first pin through the data output terminal.

[0007] Optionally, the first pin includes a plurality of first sub-pins, the first test terminal includes a plurality of first sub-test terminals, each first sub-test terminal is connected to a first sub-pin, and the current test circuit also has a control terminal;

[0008] The current testing circuit is also used to receive control commands through the controlled terminal, the control commands being used to indicate that the current on the target first sub-pin among the plurality of first sub-pins needs to be collected;

[0009] The current testing circuit is also used to collect the current on the first sub-pin of the target in response to the control command.

[0010] Optionally, the control command carries a bit sequence, the bit sequence including multiple bits corresponding one-to-one with the plurality of first sub-pins;

[0011] The value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence besides the target bit are the second bit values. The target bit is the bit corresponding to the target first sub-pin.

[0012] Optionally, the current testing circuit includes an analog signal acquisition circuit and an analog-to-digital conversion circuit. The input terminal of the analog signal acquisition circuit is connected to the first test terminal, the output terminal of the analog signal acquisition circuit is connected to the input terminal of the analog-to-digital conversion circuit, and the output terminal of the analog-to-digital conversion circuit is connected to the data output terminal.

[0013] The analog signal acquisition circuit is used to acquire the current on the first pin and obtain an analog current signal;

[0014] The analog-to-digital converter circuit is used to convert the analog current signal into a digital current signal.

[0015] Optionally, the current testing circuit further includes a buffer, the output terminal of the analog-to-digital conversion circuit is connected to the input terminal of the buffer, and the output terminal of the buffer is connected to the data output terminal;

[0016] The buffer is used to buffer the digital current signal;

[0017] The buffer is further configured to output the current digital signal to the data output terminal in response to a data read command received at the output terminal of the buffer.

[0018] Optionally, the output of the buffer communicates with the data output via an I2C serial communication bus.

[0019] Optionally, the first pin includes a plurality of first sub-pins, the first test terminal includes a plurality of first sub-test terminals, the plurality of first sub-test terminals are connected to the plurality of first sub-pins in a one-to-one correspondence, the analog signal acquisition circuit includes a plurality of current sensors that correspond to the plurality of first sub-pins in a one-to-one correspondence, the input terminal of each current sensor is connected to the corresponding first sub-pin through a first sub-test terminal, and the output terminal of each current sensor is connected to the input terminal of the analog-to-digital conversion circuit;

[0020] Each current sensor is used to collect the current on the corresponding first sub-pin.

[0021] Optionally, the current testing circuit further includes a control terminal, and the analog signal acquisition circuit further includes a sensing control circuit. The sensing control circuit has multiple control terminals and one input terminal. The multiple control terminals of the sensing control circuit are respectively connected to the control terminals of the multiple current sensors, and the input terminal of the sensing control circuit is connected to the control terminal of the current testing circuit.

[0022] The sensing control circuit is used to control each of the plurality of current sensors to turn on or off in response to a control command received at the input terminal of the sensing control circuit.

[0023] Optionally, the storage system further includes a second memory having a second pin, and the current test circuit further includes a second test terminal connected to the second pin;

[0024] The second pin is used to supply power to the second memory through the second power supply circuit;

[0025] The current testing circuit is also used to collect the current on the second pin during the operation of the second memory, and output the current on the second pin through the data output terminal.

[0026] Optionally, the first memory includes non-volatile memory, and the second memory includes volatile memory.

[0027] On the other hand, an electronic product is provided, the electronic product comprising:

[0028] The storage system described in any of the foregoing aspects;

[0029] And a host coupled to the storage system and configured to control the storage system.

[0030] On the other hand, a method for operating a storage system is provided, the storage system including a first memory and a current testing circuit, the first memory having a first pin;

[0031] The method includes:

[0032] The current testing circuit receives a current signal, which is used to indicate the current on the first pin.

[0033] The current testing circuit sends test data based on the current signal, and the test data includes current data used to indicate the current on the first pin.

[0034] Optionally, the first pin includes a plurality of first sub-pins;

[0035] Before the current testing circuit receives the current signal, the method further includes:

[0036] The current testing circuit receives a control command, which indicates that the current on the target first sub-pin among the plurality of first sub-pins needs to be collected.

[0037] The current testing circuit receives current signals and includes:

[0038] The current testing circuit receives a target current signal, which is used to indicate the current on the first sub-pin of the target.

[0039] The test data includes target current data used to indicate the current on the first sub-pin of the target.

[0040] Optionally, the control command carries a bit sequence, the bit sequence including multiple bits corresponding one-to-one with the plurality of first sub-pins;

[0041] The value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence besides the target bit are the second bit values. The target bit is the bit corresponding to the target first sub-pin.

[0042] Optionally, the current test circuit includes a buffer for storing the test data;

[0043] The current testing circuit sends test data based on the current signal, including:

[0044] The buffer receives data read instructions;

[0045] In response to the data read instruction, the buffer sends the test data.

[0046] On the other hand, a method for operating a storage system is provided, the storage system including a first memory and a current testing circuit, the first memory having a first pin;

[0047] The method includes:

[0048] The host receives test data from the current test circuit, the test data including current data used to indicate the current on the first pin.

[0049] Optionally, the first pin includes a plurality of first sub-pins;

[0050] Before the host receives test data from the current testing circuit, the method further includes:

[0051] The host sends a control command to the current testing circuit, the control command being used to indicate that the current on the target first sub-pin among the plurality of first sub-pins needs to be collected;

[0052] The test data includes current data used to indicate the current on the first sub-pin of the target.

[0053] Optionally, the control command carries a bit sequence, the bit sequence including multiple bits corresponding one-to-one with the plurality of first sub-pins;

[0054] The value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence besides the target bit are the second bit values. The target bit is the bit corresponding to the target first sub-pin.

[0055] Optionally, before the host receives test data from the current test circuit, the method further includes:

[0056] The host sends a data read command to the buffer in the current test circuit, and the buffer stores the test data.

[0057] In this embodiment, a current testing circuit is encapsulated within the storage system, including the memory, to directly test the current on the memory pins. This eliminates the need for a test bench, allowing for real-time testing of the memory current without environmental limitations. Furthermore, since the current testing circuit can continuously monitor the memory pins, it enables real-time monitoring of the memory's current data during operation, thereby improving the accuracy of power consumption assessment. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a schematic diagram of a storage system provided in an embodiment of this application;

[0060] Figure 2 This is a schematic diagram of a memory card provided in an embodiment of this application;

[0061] Figure 3 This is a schematic diagram of another memory card provided in an embodiment of this application;

[0062] Figure 4 This is a schematic diagram of another memory card provided in an embodiment of this application;

[0063] Figure 5 This is a schematic diagram of a peripheral circuit provided in an embodiment of this application;

[0064] Figure 6This is a schematic diagram of the architecture of a storage system including a current testing circuit, provided in an embodiment of this application;

[0065] Figure 7 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0066] Figure 8 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0067] Figure 9 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0068] Figure 10 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0069] Figure 11 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0070] Figure 12 This is a schematic diagram of an SRAM storing current data in a rolling manner, provided in an embodiment of this application;

[0071] Figure 13 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0072] Figure 14 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0073] Figure 15 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0074] Figure 16 This is a schematic diagram of another storage system architecture including a current testing circuit provided in an embodiment of this application;

[0075] Figure 17 This is a schematic diagram of the structure of an electronic product provided in an embodiment of this application;

[0076] Figure 18 This is a flowchart illustrating an operation method of a storage system provided in an embodiment of this application;

[0077] Figure 19 This is a flowchart of an operation method for another storage system provided in an embodiment of this application. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0079] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application. For example... Figure 1 As shown, the storage system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100.

[0080] Controller 200 can be configured to control operations performed by memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions related to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. Optionally, controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to memory 100. Controller 200 can also perform any other suitable functions, such as formatting memory 100.

[0081] The controller 200 can also communicate with external devices according to a specific communication protocol. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. Interface protocols may include Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Development Environment (IDE), FireWire, etc.

[0082] In some embodiments, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices may be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In such a scenario, such as... Figure 1 As shown, the storage system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage the data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0083] In other embodiments, the controller 200, and one or more memories 100, can be integrated into various types of storage devices.

[0084] As an example, such as Figure 2 As shown, the controller 200 and a single memory 100 can be integrated into the memory card 400. The memory card 400 may include PCMCIA (PC) cards, CompactFlash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 400 may also include a connector 410 for coupling the memory card 400 to the host.

[0085] As another example, such as Figure 3 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 500. The solid-state drive 500 may also include a connector 510 for coupling the solid-state drive 500 to the host. The storage capacity and / or operating speed of the solid-state drive 500 is greater than that of the memory card 400.

[0086] also, Figures 1 to 3 The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0087] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application. Figure 4 As shown, the memory 100 includes:

[0088] Storage array 110, which includes multiple rows of storage cells;

[0089] Multiple word lines 120 are coupled to multiple rows of memory cells;

[0090] Peripheral circuitry 130 is coupled to a plurality of word lines 120 and configured to perform a verification operation or a programming operation on a selected memory cell line among a plurality of memory cell lines, wherein the selected memory cell line is a memory cell line coupled to the selected word line, wherein, in order to perform the verification operation or programming operation, peripheral circuitry 130 is configured to perform the memory operation method provided in the embodiments of this application.

[0091] Storage array 110 can be a NAND flash memory storage array. For example... Figure 1 As shown, the NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, each memory string 111 extending vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 that are coupled in series and stacked vertically.

[0092] like Figure 4 As shown, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called the bottom select gate (BSG) or source selector, and the drain select gate is also called the top select gate (TSG) or drain selector. The source select gate 113 and the drain select gate 114 can be configured to activate the selected memory string 111 during read and program operations.

[0093] In some embodiments, the drain selection gate 114 of each memory string 111 is coupled to a corresponding bit line 115, and data can be read from or written to the bit line 115 via an output bus (not shown).

[0094] In some embodiments, each memory string 111 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0095] like Figure 4 As shown, the storage string 111 can be organized into multiple blocks 140. For any one of the multiple blocks 140, the block 140 can have a source line (SL) 118. The sources of all storage strings 111 in the block 140 are coupled through the source line 118. The source line is also called the common source line or array common source (ACS).

[0096] It should be noted that the source line 118 is used for grounding, so as to enable the source of each memory cell in the memory string in block 140 to be grounded in some subsequent operations.

[0097] Each block 140 is the basic data unit used for the erase operation, meaning that all memory cells 112 on the same block 140 are erased simultaneously. To erase memory cells 112 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line of the selected block.

[0098] It should be understood that, in other embodiments, erasure operations may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level with any suitable number of blocks or blocks.

[0099] like Figure 4 As shown, the same layer of storage cells 112 of adjacent storage strings 111 in the same block 140 can be coupled through word lines 120. Word lines 120 are used to select which layer of storage cells 112 in the block 140 is affected by read and program operations.

[0100] Return to reference Figure 4The peripheral circuitry 130 can be coupled to the memory array 110 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116. The peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 110 by applying voltage and / or current signals to and sensing voltage and / or current signals from the memory cells 112 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116.

[0101] Peripheral circuitry 130 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry 130 is shown, including a page buffer / sensor amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0102] Page buffer / sensor amplifier 131 can be configured to read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic unit 135. For example, page buffer / sensor amplifier 131 can store a page of programming data (write data) to be programmed into a page 130 of memory array 110. Page buffer / sensor amplifier 131 can also perform a verification operation to ensure that data has been correctly programmed into memory cell 112 coupled to selected word line 120. Page buffer / sensor amplifier 131 can also sense a low-power signal from bit line 115, which represents a data bit stored in memory cell 112, and amplify a small voltage swing to a recognizable logic level during read operations.

[0103] The column decoder / bit line driver 132 can be configured to be controlled by the control logic unit 135 and to select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134.

[0104] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135 and to select / deselect block 140 of the memory array 110 and to select / deselect word lines 120 of block 140. The row decoder / word line driver 133 can also be configured to drive word lines 120 using word line voltages (VWL) generated from a voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive SSG lines 117 and DSG lines 116. As described in detail below, the row decoder / word line driver 133 is configured to perform erase operations on memory cells 112 coupled to one or more selected word lines 120.

[0105] Voltage generator 134 can be configured to be controlled by control logic unit 135 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 110.

[0106] The control logic unit 135 can be coupled to various circuits in the peripheral circuitry described above and is configured to control the operation of each circuit.

[0107] Register 136 can be coupled to control logic unit 135. The register may include a status register, a command register, and an address register to store status information, command opcodes (OP codes), and command addresses for controlling the operation of each circuit in the peripheral circuitry.

[0108] Interface (I / F) 137 can be coupled to control logic unit 135 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 135, as well as to buffer status information received from control logic unit 135 and relay it to the host. Interface 137 can also be coupled to column decoder / bit line driver 132 via data bus 138 and act as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0109] The above description of the memory-related hardware embodiments has similar beneficial effects to the method embodiments described below. For technical details not disclosed in the memory-related hardware embodiments, please refer to the description of the method embodiments in this application for understanding.

[0110] It should be noted that, Figures 4-5 The memory shown is an example of a memory involved in an embodiment of this application. The memory involved in the embodiments of this application is not limited to this. Figures 4-5 The structure of the memory is shown.

[0111] In some scenarios, the current on memory pins can be tested by setting up a test bench, and the power consumption of the memory can then be evaluated based on the measured current. This test bench includes an oscilloscope. However, this testing method is complex due to the need to set up a test bench, limiting the testing environment. Furthermore, the oscilloscope's operating principle is as follows: after acquiring and displaying data for a recent period (e.g., 2 seconds), it needs to be reset (which takes several seconds), and then the data acquired during those 2 seconds needs to be stored (which takes another ten seconds). Only after storing the data will it acquire and display data for the next 2 seconds. This means the oscilloscope cannot capture data within the two consecutive 2-second intervals. Therefore, the oscilloscope can only test the current on the memory pins during a few intermittent time periods, thus affecting the accuracy of the power consumption assessment.

[0112] Based on this, this application provides a storage system in which a current testing circuit is encapsulated within the storage system, including the memory, to directly test the current on the memory pins. This eliminates the need for a test bench, allowing for real-time testing of the memory current, simplifying the process and removing environmental limitations. Furthermore, since the current testing circuit can continuously monitor the memory pins, it enables real-time monitoring of the memory's current data during operation, thereby improving the accuracy of power consumption assessment.

[0113] The storage system provided in the embodiments of this application will be described in detail below.

[0114] Figure 6 This is a schematic diagram of the architecture of a storage system including a current testing circuit, provided in an embodiment of this application. Figure 6 As shown, the storage system includes a first memory and a current testing circuit. The first memory has a first pin, and the current testing circuit has a first test terminal and a data output terminal. The first test terminal is connected to the first pin.

[0115] The first pin is used to supply power to the first memory through the first power supply circuit; the current test circuit is used to collect the current on the first pin during the operation of the first memory and output the current on the first pin through the data output terminal.

[0116] Since the first pin is used to supply power to the first memory through the first power supply circuit, the first pin is also called the first power pin. The first power supply circuit can be integrated inside the memory system, or alternatively, the first power supply circuit can be deployed outside the memory system.

[0117] like Figure 6As shown, the current tested by the current testing circuit can be directly output to the external host through the data output terminal. Thus, during the operation of the storage system, the external host can read the current data tested by the current testing circuit at any time through the data output terminal, thereby realizing real-time monitoring of the current data of the memory during the operation of the memory, and improving the accuracy of the power consumption assessment of the memory.

[0118] In addition, the storage system including the first memory and the current test circuit can be understood as follows: the first memory and the current test circuit are packaged on the same board, so as to realize the current test circuit is packaged inside the storage system including the memory.

[0119] For example, the first memory includes non-volatile memory, such as flash memory like NAND. In this scenario, Figure 6 The storage system shown can be eMMC (embedded multimedia card) or UFS (universal flash storage). That is, in the embodiments of this application, the current testing circuit can be packaged inside the eMMC or UFS to enable testing of the NAND current anytime and anywhere.

[0120] For example, the first memory may include volatile memory, such as DRAM (dynamic random access memory). In this scenario, Figure 6 The storage system shown can be DDR SDRAM (double data rate synchronous dynamic random access memory). That is, in this embodiment, the current testing circuit can be packaged inside the DDR SDRAM to enable testing of the DRAM current anytime and anywhere.

[0121] In some embodiments, such as Figure 7 As shown, the first pin includes multiple first sub-pins, the first test terminal includes multiple first sub-test terminals, each first sub-test terminal is connected to a first sub-pin, and the current test circuit also has a control terminal.

[0122] The current testing circuit is also used to receive control commands through the control terminal. The control commands are used to indicate that the current on the target first sub-pin among multiple first sub-pins needs to be collected. The current testing circuit is also used to collect the current on the target first sub-pin in response to the control commands.

[0123] Since the first memory typically has multiple pins, in some scenarios it may be necessary to test the current on certain specific pins. In the embodiments of this application, such as... Figure 7 As shown, the external host can control the current testing circuit through the control terminal to test the current on a specific pin (i.e., the target first sub-pin).

[0124] The target first sub-pin can be one of multiple first sub-pins, or multiple first sub-pins.

[0125] For example, in a scenario where the first memory is NAND, the multiple first sub-pins may include a VCC pin, a VCCQ pin, and a VCCQ2 pin. The VCC pin is used to power the storage medium in the first memory; the VCCQ pin is used to power the input / output circuits in the first memory and the controller that controls the first memory; and the VCCQ2 pin is used to power the front-end interface in the first memory and other low-voltage modules.

[0126] When the target first sub-pin includes the NAND VCC pin, the current on the NAND VCC pin can be measured using the current testing circuit provided in this application embodiment. When the target first sub-pin includes the NAND VCCQ pin, the current on the NAND VCCQ pin can be measured using the current testing circuit provided in this application embodiment. When the target first sub-pin includes the NAND VCCQ2 pin, the current on the NAND VCCQ2 pin can be measured using the current testing circuit provided in this application embodiment.

[0127] For example, in a scenario where the first memory is DRAM, the multiple first sub-pins may include the VDD1 pin, VDD2H pin, VDD2L pin, and VDDQ pin. The VDD1 pin is used to power the core circuitry, such as logic circuitry, in the first memory; the VDD2H and VDD2L pins are used to power auxiliary circuitry, such as internal address, clock, and control signal generation circuitry, in the first memory; and the VDDQ pin is used to power the input / output circuitry in the first memory.

[0128] When the target first sub-pin includes the VDD1 pin of the DRAM, the current on the VDD1 pin of the DRAM can be measured using the current testing circuit provided in this application embodiment. When the target first sub-pin includes the VDD2H pin of the DRAM, the current on the VDD2H pin of the DRAM can be measured using the current testing circuit provided in this application embodiment. When the target first sub-pin includes the VDD2L pin of the DRAM, the current on the VDD2L pin of the DRAM can be measured using the current testing circuit provided in this application embodiment. When the target first sub-pin includes the VDDQ pin of the DRAM, the current on the VDDQ pin of the DRAM can be measured using the current testing circuit provided in this application embodiment.

[0129] Additionally, for example, the control instruction carries a bit sequence, which includes multiple bits corresponding one-to-one with multiple first sub-pins; the value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence are the second bit values, wherein the target bit is the bit corresponding to the target first sub-pin.

[0130] In this way, the external host can control the current testing circuit to test the current on a specific pin of the first memory by sending a simple bit sequence to the current testing circuit through the control terminal. The solution is simple to implement and does not require complex hardware costs.

[0131] The target bit can be a single bit in a bit sequence or multiple bits in a bit sequence. This current testing circuit can support testing the current on certain specific pins or testing the current on all pins.

[0132] The first bit value is typically 1, and the second bit value is typically 0. For example, in a scenario where the first memory is NAND, multiple first sub-pins may include a VCC pin, a VCCQ pin, and a VCCQ2 pin. The bit sequence may then include three bits, each corresponding to one of the VCC, VCCQ, and VCCQ2 pins. If the bit sequence is 001, it indicates that a current testing circuit is needed to test the current on the VCCQ2 pin. If the bit sequence is 011, it indicates that a current testing circuit is needed to test the current on both the VCCQ and VCCQ2 pins. If the bit sequence is 111, it indicates that a current testing circuit is needed to test the current on all three pins: VCC, VCCQ, and VCCQ2.

[0133] Optionally, the first bit value can be 0 and the second bit value can be 1, which will not be explained in detail here.

[0134] The internal structure of the current testing circuit inside the storage system provided in the embodiments of this application will be described in detail below.

[0135] In some embodiments, such as Figure 8 As shown, the current testing circuit includes an analog signal acquisition circuit and an analog-to-digital conversion circuit. The input terminal of the analog signal acquisition circuit is connected to the first test terminal, the output terminal of the analog signal acquisition circuit is connected to the input terminal of the analog-to-digital conversion circuit, and the output terminal of the analog-to-digital conversion circuit is connected to the data output terminal.

[0136] The analog signal acquisition circuit is used to acquire the current on the first pin and obtain the analog current signal; the analog-to-digital conversion circuit is used to convert the analog current signal into a digital current signal.

[0137] The analog signal acquisition circuit and analog-to-digital conversion circuit can directly convert the acquired analog current signal into a digital current signal, so that the digital circuit signal can be output to the external host through the data output terminal.

[0138] Furthermore, in some embodiments, such as Figure 9 As shown, the current testing circuit also includes a buffer. The output of the analog-to-digital converter is connected to the input of the buffer, and the output of the buffer is connected to the data output. The buffer is used to buffer the digital current signal; it also responds to a data read command received at its output by outputting the digital current signal to the data output.

[0139] By using a buffer, the analog-to-digital converter circuit can first store the converted current digital signal in the buffer. This way, the external host can read the current digital signal, i.e., the current data, from the buffer as needed, thereby improving the flexibility of current testing.

[0140] Optionally, in scenarios without a buffer, the analog-to-digital converter circuit can output the converted digital current signal to an external host in real time via its data output terminal, where the external host stores the received digital current signal. This scenario requires the external host to maintain a constant communication connection with the data output terminal of the current testing circuit during its operation.

[0141] For example, the output of the register communicates with the data output via I2C (inter-integrated circuit). In some scenarios, it may be necessary to test the current on multiple sub-pins. In such cases, I2C communication allows the register to transmit the digital current signals of the multiple sub-pins in parallel to an external host.

[0142] Specifically, the buffer transmits the digital current signals of multiple sub-pins to the external host in parallel. This means that different digital current signals are transmitted to the external host in different time segments, thereby realizing the parallel transmission of multiple digital current signals to the external host.

[0143] With I2C communication, only one pin needs to be set on the buffer to connect to the data output terminal. Therefore, I2C communication can reduce the number of pins between the buffer and the data output terminal, thereby reducing the hardware cost of the current test circuit.

[0144] For example, in Figure 8 or Figure 9 In the scenario shown, such as Figure 10As shown, the first pin includes multiple first sub-pins, and the first test terminal includes multiple first sub-test terminals. Each first sub-test terminal is connected to one of the multiple first sub-pins in a one-to-one correspondence. The analog signal acquisition circuit includes multiple current sensors, each corresponding to one of the multiple first sub-pins. The input terminal of each current sensor is connected to its corresponding first sub-pin through a first sub-test terminal, and the output terminal of each current sensor is connected to the input terminal of the analog-to-digital conversion circuit. Each current sensor is used to acquire the current on its corresponding first sub-pin.

[0145] By configuring different current sensors on different sub-pins, the current on each sub-pin can be collected separately. This method is simple to implement and can reduce the hardware cost of the current testing circuit.

[0146] Furthermore, such as Figure 11 As shown, the analog signal acquisition circuit also includes a sensing control circuit, which has multiple control terminals and one input terminal. The multiple control terminals of the sensing control circuit are respectively connected to the control terminals of multiple current sensors, and the input terminal of the sensing control circuit is connected to the control terminal of the current testing circuit.

[0147] The sensing control circuit is used to control each current sensor among the multiple current sensors to turn on or off in response to the control command received at the input terminal of the sensing control circuit.

[0148] The sensing control circuit allows users to selectively collect current from certain specific sub-pins via an external host, improving the application flexibility of the current acquisition circuit.

[0149] like Figure 11 As shown, the external host can input control commands to the sensing control circuit through the control terminal to control a specific current sensor to turn on, thereby collecting the current on a specific sub-pin.

[0150] For example, the control instruction carries a bit sequence, which includes multiple bits that correspond one-to-one with multiple first sub-pins; the value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence are the second bit values, wherein the target bit is the bit corresponding to the target first sub-pin.

[0151] Regarding the target bit, the explanation of the first bit value and the second bit value can be found in the aforementioned embodiments, and will not be repeated here.

[0152] For any given bit, if the bit value is the first bit value, it indicates that the current sensor connected to the corresponding first sub-pin is turned on, thereby enabling the current on the corresponding first sub-pin to be sampled. If the bit value is the second bit value, it indicates that the current sensor connected to the corresponding first sub-pin is turned off, thereby preventing the current on the corresponding first sub-pin from being sampled.

[0153] The first bit value is typically 1, and the second bit value is typically 0. For example, in a scenario where the first memory is NAND, multiple first sub-pins may include a VCC pin, a VCCQ pin, and a VCCQ2 pin. The bit sequence may then include three bits, each corresponding to one of the VCC, VCCQ, and VCCQ2 pins. If the bit sequence is 001, it indicates that the current sensor connected to the VCCQ2 pin in the current testing circuit needs to be turned on to test the current on the VCCQ2 pin. If the bit sequence is 011, it indicates that both current sensors connected to the VCCQ and VCCQ2 pins in the current testing circuit need to be turned on to test the current on those two pins. If the bit sequence is 111, it indicates that all three current sensors connected to the VCC, VCCQ, and VCCQ2 pins in the current testing circuit need to be turned on to test the current on those three pins.

[0154] Alternatively, the sensor control circuit can be implemented using a 3-to-8 decoder. Other decoders can also be used, which will not be illustrated here.

[0155] Analog-to-digital conversion circuits can be implemented, for example, using an ADC (analog-to-digital converter). This application does not limit the specific structure of the ADC. Furthermore, in scenarios where the analog signal acquisition circuit includes multiple current sensors, the analog-to-digital conversion circuit may include multiple ADCs connected to each of the multiple current sensors to improve data acquisition efficiency.

[0156] The buffer can be implemented using SRAM (static random access memory). Considering that the storage speed requirement for the buffer is not high in this embodiment, other lower-cost storage media, such as NOR flash, can also be used as the buffer. Optionally, to further reduce the hardware cost of the current testing circuit, a portion of the storage space in the first memory can be allocated to implement the buffer function.

[0157] In addition, in scenarios where the buffer is SRAM, the way SRAM stores the digital current signal, i.e., the current data, can be in a rolling manner. Figure 12 This is a schematic diagram illustrating how SRAM stores current data in a rolling manner, as provided in an embodiment of this application. Figure 12 As shown, the blocks marked [4] / [5] / [6] / [7] / [8] represent offset addresses, each occupying 3 bytes, with a maximum value of 0xFFFFFF. Among them, the offset addresses with values ​​from 2 to 15015017 are omitted in the block marked [6].

[0158] The digital current signal converted from the analog-to-digital converter circuit, i.e., the current data, starts from the position where offset = 0. Figure 12 The storage starts from the square marked [4] and continues sequentially. When the storage reaches the position of offset = 15015019, it will switch to the position of offset = 0 to continue storing, overwriting the existing data instead of clearing it.

[0159] In scenarios where SRAM uses a rolling read operation to store current data, the external host can set a read cycle that is less than or equal to the time required for the SRAM to store one round of data. The time required for the SRAM to store one round of data can be understood as the time it takes for the SRAM to start storing data at a certain offset address and then to store data again at that offset address. The external host periodically reads current data from the SRAM according to this read cycle. This ensures that the user can obtain the current data tested by the current testing circuit for all the time periods.

[0160] Alternatively, the external host can also forgo setting the aforementioned read cycle and instead read current data from SRAM in response to user requests. In this scenario, due to rolling storage, the user can obtain current data tested by the current testing circuit within a recent period.

[0161] It should be noted that, Figure 12 The method of storing current data shown is for illustrative purposes only, and the embodiments of this application do not limit the method of storing current data in the buffer.

[0162] The above description uses an example of a storage system containing only one memory module. Alternatively, in other embodiments, such as... Figure 13 As shown, the storage system also includes a second memory with a second pin, and the current test circuit also has a second test terminal connected to the second pin.

[0163] The second pin is used to supply power to the second memory through the second power supply circuit; the current test circuit is also used to collect the current on the second pin during the operation of the second memory and output the current on the second pin through the data output terminal.

[0164] The first power supply circuit and the second power supply circuit can be integrated together or deployed in different locations. This application does not limit this.

[0165] For example, the first memory includes non-volatile memory, and the second memory includes volatile memory.

[0166] For example, the first memory is NAND, and the second memory is DRAM. In this scenario... Figure 13 The storage system shown can be a uMCP (UFS-based multichip package). That is, in this embodiment, the current testing circuit can be packaged inside the uMCP to enable testing of the current on the pins of the NAND and DRAM inside the uMCP anytime and anywhere.

[0167] The explanations regarding the second pin, the second test terminal, and the second power supply circuit can be found in the previous sections on the first pin, the first test terminal, and the first power supply circuit, and will not be repeated here. Furthermore, the specific method by which the current testing circuit tests the current at the second pin of the second memory can also be found in the previous section on the specific method by which the current testing circuit tests the current at the first pin of the first memory, and will not be repeated here.

[0168] In some embodiments, such as Figure 14 As shown, the first pin includes multiple first sub-pins, and the first test terminal includes multiple first sub-test terminals, each of which is connected to a first sub-pin. The second pin includes multiple second sub-pins, and the second test terminal includes multiple second sub-test terminals, each of which is connected to a second pin. The current testing circuit also has a control terminal.

[0169] The current testing circuit is also used to receive control commands through the control terminal. The control commands are used to indicate that the current on the target sub-pin among multiple first sub-pins and multiple second sub-pins needs to be collected. The current testing circuit is also used to collect the current on the target sub-pin in response to the control commands.

[0170] exist Figure 13 In the scenario shown, the current testing circuit can simultaneously test the current on the pins of the first and second memory. However, in some scenarios, it may be necessary to test the current on certain specific pins. Therefore, in this embodiment, as shown... Figure 14As shown, the external host can control the current testing circuit through the control terminal to test the current on a specific pin (i.e., the target sub-pin).

[0171] For example, in a scenario where the first memory is NAND and the second memory is DRAM, multiple first sub-pins may include VCC pin, VCCQ pin, and VCCQ2 pin, and multiple second sub-pins may include VDD1 pin, VDD2H pin, VDD2L pin, and VDDQ pin. An external host can control a current testing circuit to test the current on a target sub-pin among these seven sub-pins using control commands.

[0172] For example, the control instruction carries a bit sequence, which includes multiple bits corresponding one-to-one with multiple first sub-pins and multiple second sub-pins; the value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence are the second bit values, and the target bit is the bit corresponding to the target sub-pin.

[0173] In this way, the external host can send a simple bit sequence to the current test circuit through the control terminal to control the current test circuit to test the current on specific pins of the first and second memories. The solution is simple to implement and does not require complex hardware costs.

[0174] The explanations of the target bit, the second bit value, and the second bit value can also be found in the aforementioned embodiments, and will not be repeated here.

[0175] The first bit value is typically 1, and the second bit value is typically 0. For example, in a scenario where the first memory is NAND and the second memory is DRAM, multiple first sub-pins include the VCC pin, VCCQ pin, and VCCQ2 pin, and multiple second sub-pins include the VDD1 pin, VDD2H pin, VDD2L pin, and VDDQ pin. The bit sequence is then a byte consisting of eight bits, where the first seven bits correspond to the VCC pin, VCCQ pin, VCCQ2 pin, VDD1 pin, VDD2H pin, VDD2L pin, and VDDQ pin, respectively, and the last bit is a reserved bit.

[0176] If the bit sequence is 00100010, it indicates that a current testing circuit is needed to test the current on the VCCQ2 pin of the NAND flash memory and the VDDQ pin of the DRAM. If the bit sequence is 01100110, it indicates that a current testing circuit is needed to test the current on the VCCQ and VCCQ2 pins of the NAND flash memory, and the VDD2L and VDDQ pins of the DRAM. Other examples of bit sequences will not be illustrated here.

[0177] The following is based on Figure 9Taking the current testing circuit shown as an example... Figure 14 The current testing circuit shown is further illustrated by an example.

[0178] like Figure 15 As shown, the current testing circuit includes an analog signal acquisition circuit, an analog-to-digital converter circuit, and a buffer. The input terminal of the analog signal acquisition circuit is connected to multiple first sub-test terminals and multiple second sub-test terminals respectively. The output terminal of the analog signal acquisition circuit is connected to the input terminal of the analog-to-digital converter circuit. The output terminal of the analog-to-digital converter circuit is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the data output terminal.

[0179] The analog signal acquisition circuit is used to acquire the current on the first and second sub-pins to obtain the analog current signal; the analog-to-digital converter circuit is used to convert the analog current signal into a digital current signal. The buffer is used to buffer the digital current signal; the buffer is also used to output the digital current signal to the data output terminal in response to the data read command received at the output terminal of the buffer.

[0180] For information on the internal connections and related functions of the analog signal acquisition circuit, analog-to-digital conversion circuit, and buffer, please refer to the aforementioned documentation. Figure 11 The embodiments shown will not be described in detail here.

[0181] In addition, Figures 13 to 15 In the storage system shown, the components in the newly added current test circuit can be powered by a separate power supply circuit, namely the third power supply circuit. Alternatively, the components in the current test circuit can be powered by the current on the first pin or the second pin. This application embodiment does not limit this.

[0182] The following example demonstrates the deployment of a current testing circuit in a uMCP. Figure 13 The current testing circuit shown is further illustrated with an example. For example... Figure 16 As shown, the storage system example is uMCP, the first memory example is UFS including NAND, and the second memory example is DRAM. Regarding... Figure 16 The connection relationships between the various components can be referred to in the aforementioned embodiments, and will not be repeated here. Additionally, Figure 16 The code is marked with 6 markers [1]-[6]. The following is a summary of the code. Figure 16 The following explanations will be provided for these six markers.

[0183] [1] indicates that the analog signal acquisition circuit detects the power pins from the second memory (such as DRAM), including the four pins VDD1 / VDD2H / VDD2L / VDDQ. The analog signal acquisition circuit supports selecting to measure one of the power pins individually, or selecting to measure all the power pins simultaneously. It should be noted that [1] does not represent one line, but rather includes four power lines. The analog signal acquisition circuit can select to measure the current on one or more of the power lines individually, and the specific power line to be tested is controlled by [6].

[0184] [2] indicates that the analog signal acquisition circuit detects the power supply pins of the first memory (such as UFS including NAND), including the three pins VCC / VCCQ / VCCQ2. The analog signal acquisition circuit supports selecting to measure one of the power supply pins individually, or selecting to measure all the power supply pins simultaneously. It should be noted that [2] does not represent one line, but rather includes three power lines. The analog signal acquisition circuit can select to measure the current on one or more of the power lines individually, and the specific power line whose current is measured is controlled by [6].

[0185] [3] indicates that power is supplied to the analog signal acquisition circuit and components such as SRAM in the current test circuit. Figure 16 In this case, the connecting line marked [3] is connected to a solder ball in the storage system (e.g., uMCP), which is used to access the external power supply circuit. Alternatively, a power supply pin can be connected inside the storage system (e.g., uMCP) from the second memory (e.g., DRAM) and the first memory (e.g., UFS) respectively as the power supply circuit for analog signal acquisition current and SRAM. In this scenario, if the voltage on the power supply pin does not reach the specified operating voltage value of the component in the current test circuit, an LDO (low dropout regulator) can be added between the power supply pin and the component in the current test circuit to convert the voltage on the power supply pin to the specified operating voltage value required by the component.

[0186] For example, the operating voltage of SRAM is specified as 1.2V.

[0187] [4] indicates that the analog signal acquisition circuit converts the detected analog current signal into a digital current signal, that is, the current data is stored in SRAM. Table 1 is a parameter diagram of a digital current signal provided in the embodiments of this application.

[0188] Table 1

[0189] Parameter name Parameter values Does it support adjustment? Precision range 1 microamp (μA) Not supported Current range 1μA-5A Not supported Sampling interval 666 nanoseconds (ns) - 5 milliseconds (ms) support

[0190] As shown in Table 1, when the ADC converts the analog current signal into a digital current signal, the accuracy range of the converted current data is controlled to be 1μA, and the range of the converted current data is controlled to be 1μA-5A. The sampling interval used during the conversion can be between 666ns and 5 milliseconds. The specific sampling interval can be configured by the user, that is, the sampling interval of the ADC can be adjusted.

[0191] For example, the ADC provides an interface for users to configure the sampling interval. Through this interface, users can configure the specific value of the sampling interval, which will not be described in detail here.

[0192] [5] indicates that the current data of the SRAM is output to a solder ball in the storage system (such as uMCP), which is the data output terminal, and then transmitted to the external host. The current data is transmitted in I2C communication mode, which aims to reduce the number of pins between the SRAM and the data output terminal.

[0193] [6] indicates the control command input by the external host through the control terminal. The control command is 1 byte. Each bit in the byte corresponds to a power supply pin. The value of each bit indicates whether the current test of the corresponding power supply pin is enabled. A bit value of 1 indicates that the current test of the corresponding power supply pin is enabled, that is, the current on the corresponding power supply pin is tested. A bit value of 0 indicates that the current test of the corresponding power supply pin is not enabled, that is, the current on the corresponding power supply pin is not tested.

[0194] Table 2 is a schematic table of the format of a control instruction provided in an embodiment of this application.

[0195] Table 2

[0196]

[0197] As shown in Table 2, the control instruction is a single byte. In this byte, the 0th bit corresponds to the VCCQ2 pin of the first memory (e.g., UFS), the 1st bit corresponds to the VCCQ pin of the first memory (e.g., UFS), the 2nd bit corresponds to the VCC pin of the first memory (e.g., UFS), the 3rd bit corresponds to the VDDQ pin of the second memory (e.g., DRAM), the 4th bit corresponds to the VDD2L pin of the second memory (e.g., DRAM), the 5th bit corresponds to the VDD2H pin of the second memory (e.g., DRAM), and the 6th bit corresponds to the VDD1 pin of the second memory (e.g., DRAM).

[0198] In summary, the storage system provided in this application embodiment has the following functions:

[0199] (1) By adding a current testing circuit inside the package of the storage system, the current on the memory pins can be collected during normal operation of the storage system. This allows for testing the memory current anytime and anywhere without the need to build a test bench. The testing process is simple and not limited by the environment. It also reduces testing costs.

[0200] (2) Since the current test circuit can test the current on the pins of the memory at any time, it can monitor the current data of the memory in real time during the operation of the memory. This not only improves the efficiency of collecting current data, but also improves the accuracy of the collected current data.

[0201] (3) Since the current data of the memory can be monitored in real time during the operation of the memory, the tested current data can more realistically reflect the working status of the memory, thus facilitating the analysis of the behavior and power consumption of the memory system.

[0202] In addition, this application also provides an electronic product. Figure 17 This is a schematic diagram of the structure of an electronic product provided in an embodiment of this application. For example... Figure 17 As shown, the electronic product includes a storage system and a host coupled to the storage system and configured to control the storage system.

[0203] in, Figure 17 The storage system in the middle can be Figure 6-16 The storage system described in any of the above.

[0204] Furthermore, embodiments of this application also provide an operation method for a storage system, the storage system including a first memory and a current testing circuit, the first memory having a first pin. For example... Figure 18 As shown, the method includes the following steps.

[0205] Step 1801: The current test circuit receives a current signal, which is used to indicate the current on the first pin.

[0206] The current signal in step 1801 can be specifically understood as the analog current signal on the first pin acquired by the current test circuit.

[0207] Step 1802: The current test circuit sends test data based on the current signal. The test data includes current data used to indicate the current on the first pin.

[0208] For details on how the current testing circuit transmits test data based on the current signal, please refer to the aforementioned... Figures 7-11 The relevant content will not be repeated here.

[0209] In some embodiments, the first pin includes a plurality of first sub-pins; before the current testing circuit receives the current signal, the current testing circuit receives a control command, which is used to indicate that the current on the target first sub-pin among the plurality of first sub-pins needs to be collected.

[0210] In this scenario, the current testing circuit can receive the current signal in the following way: the current testing circuit receives the target current signal, which is used to indicate the current on the first sub-pin of the target; wherein, the test data includes the target current data used to indicate the current on the first sub-pin of the target.

[0211] For example, the control instruction carries a bit sequence, which includes multiple bits that correspond one-to-one with multiple first sub-pins; the value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence are the second bit values, wherein the target bit is the bit corresponding to the target first sub-pin.

[0212] The relevant content regarding control commands can also be found in the foregoing embodiments, and will not be repeated here.

[0213] In some embodiments, the current test circuit includes a buffer for storing test data. In this scenario, the current test circuit can transmit test data based on a current signal in the following manner: the buffer receives a data read instruction; in response to the data read instruction, the buffer transmits the test data.

[0214] The details regarding the cache can also be found in the aforementioned embodiments, and will not be repeated here.

[0215] Furthermore, embodiments of this application also provide another method for operating a storage system, the storage system including a first memory and a current testing circuit, the first memory having a first pin. For example... Figure 19 As shown, the method includes the following steps.

[0216] Step 1901: The host receives test data from the current test circuit, including current data used to indicate the current on the first pin.

[0217] In some embodiments, the first pin includes a plurality of first sub-pins. In this scenario, before the host receives test data from the current test circuit, the host sends a control command to the current test circuit. The control command is used to indicate that the current on a target first sub-pin among the plurality of first sub-pins needs to be collected; wherein, the test data includes current data used to indicate the current on the target first sub-pin.

[0218] For example, the control instruction carries a bit sequence, which includes multiple bits that correspond one-to-one with multiple first sub-pins; the value of the target bit in the bit sequence is the first bit value, and the values ​​of the other bits in the bit sequence are the second bit values, wherein the target bit is the bit corresponding to the target first sub-pin.

[0219] In some embodiments, before the host receives test data from the current test circuit, the host sends a data read instruction to a buffer in the current test circuit, which stores the test data.

[0220] Figure 18 and Figure 19 The implementation of the method shown has been described in detail in the foregoing embodiments and will not be repeated here.

[0221] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is understood that "first," "second," etc., may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0222] It should be understood that the phrase "some embodiments" throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0223] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0224] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage system, characterized by, The storage system comprises a first memory and a current test circuit, the first memory has a first pin, the current test circuit has a first test end and a data output end, and the first test end is connected with the first pin; The first pin is used for supplying power for the first memory through a first power supply circuit; The current test circuit is used for collecting the current on the first pin during the working process of the first memory and outputting the current on the first pin through the data output end.

2. The storage system of claim 1, wherein, The first pin comprises a plurality of first sub-pins, the first test end comprises a plurality of first sub-test ends, each first sub-test end is connected with a first sub-pin, and the current test circuit further has a control end; The current test circuit is further used for receiving a control instruction through the control end, and the control instruction is used for indicating that the current on a target first sub-pin in the plurality of first sub-pins needs to be collected; The current test circuit is further used for collecting the current on the target first sub-pin in response to the control instruction.

3. The storage system of claim 2, wherein, The control instruction carries a bit sequence, and the bit sequence comprises a plurality of bit positions corresponding to the plurality of first sub-pins one by one; The value of a target bit position in the bit sequence is a first bit value, the values of bit positions other than the target bit position in the bit sequence are second bit values, and the target bit position is a bit position corresponding to the target first sub-pin.

4. The storage system of claim 1, wherein, The current test circuit comprises an analog signal collection circuit and an analog-to-digital conversion circuit, an input end of the analog signal collection circuit is connected with the first test end, an output end of the analog signal collection circuit is connected with an input end of the analog-to-digital conversion circuit, and an output end of the analog-to-digital conversion circuit is connected with the data output end; The analog signal collection circuit is used for collecting the current on the first pin to obtain an analog current signal; The analog-to-digital conversion circuit is used for converting the analog current signal into a digital current signal.

5. The storage system of claim 4, wherein, The current test circuit further comprises a buffer, an output end of the analog-to-digital conversion circuit is connected with an input end of the buffer, and an output end of the buffer is connected with the data output end; The buffer is used for buffering the digital current signal; The buffer is further used for outputting the digital current signal to the data output end in response to a data reading instruction received by the output end of the buffer.

6. The storage system of claim 5, wherein, The output end of the buffer and the data output end communicate through a serial communication bus I2C.

7. The storage system of claim 4, wherein, The first pin comprises a plurality of first sub-pins, the first test end comprises a plurality of first sub-test ends, the plurality of first sub-test ends are connected with the plurality of first sub-pins one by one, the analog signal collection circuit comprises a plurality of current sensors corresponding to the plurality of first sub-pins one by one, an input end of each current sensor in the plurality of current sensors is connected with a corresponding first sub-pin through a first sub-test end, and an output end of each current sensor is connected with an input end of the analog-to-digital conversion circuit; Each current sensor is used for collecting the current on the corresponding first sub-pin.

8. The storage system of claim 7, wherein, The current test circuit also has a control end, and the analog signal acquisition circuit further includes a sensing control circuit having a plurality of control ends and an input end, the plurality of control ends of the sensing control circuit being connected with the control ends of the plurality of current sensors respectively, and the input end of the sensing control circuit being connected with the control end of the current test circuit; The sensing control circuit is configured to control each of the plurality of current sensors to be turned on or turned off in response to a control instruction received by the input end of the sensing control circuit.

9. The storage system of any one of claims 1-8, wherein, The storage system further includes a second memory having a second pin, and the current test circuit further has a second test end connected with the second pin; The second pin is configured to supply power to the second memory through a second power supply circuit. The current test circuit is further configured to acquire a current on the second pin during operation of the second memory and output the current on the second pin through the data output end.

10. The storage system of claim 9, wherein, The first memory includes a non-volatile memory, and the second memory includes a volatile memory.

11. An electronic product, characterized by comprising: The electronic product includes: The storage system of any one of claims 1-10; and a host coupled to the storage system and configured to control the storage system.

12. An operating method of a storage system characterized by, The storage system includes a first memory having a first pin and a current test circuit; The method includes: The current test circuit receives a current signal, the current signal being used to indicate a current on the first pin; The current test circuit sends test data based on the current signal, the test data including current data used to indicate the current on the first pin.

13. The method of claim 12, wherein, The first pin includes a plurality of first sub-pins; Before the current test circuit receives the current signal, the method further includes: The current test circuit receives a control instruction, the control instruction being used to indicate that a current on a target first sub-pin of the plurality of first sub-pins needs to be acquired; The current test circuit receives a current signal, including: The current test circuit receives a target current signal, the target current signal being used to indicate the current on the target first sub-pin; The test data includes target current data used to indicate the current on the target first sub-pin.

14. The method of claim 13, wherein, The control instruction carries a bit sequence, the bit sequence including a plurality of bit positions corresponding to the plurality of first sub-pins one by one; A target bit position in the bit sequence has a first bit value, and other bit positions in the bit sequence have a second bit value, the target bit position being a bit position corresponding to the target first sub-pin.

15. The method of claim 12, wherein, The current test circuit includes a buffer configured to store the test data; The current test circuit sends test data based on the current signal, including: The buffer receives a data read instruction; In response to the data read instruction, the buffer sends the test data.

16. An operating method of a storage system characterized by, The storage system includes a first memory having a first pin and a current test circuit; The method includes: The host receives test data from the current test circuit, the test data including current data for indicating current on the first pin.

17. The method of claim 16, wherein, The first pin includes a plurality of first sub-pins; Before the host receives the test data from the current test circuit, the method further includes: The host sends a control instruction to the current test circuit, the control instruction being used to indicate that current on a target first sub-pin in the plurality of first sub-pins needs to be collected; The test data includes current data for indicating current on the target first sub-pin.

18. The method of claim 17, wherein, The control instruction carries a bit sequence, the bit sequence including a plurality of bit positions corresponding to the plurality of first sub-pins one by one; A target bit position in the bit sequence has a first bit value, and other bit positions in the bit sequence except the target bit position have a second bit value, the target bit position being a bit position corresponding to the target first sub-pin.

19. The method of any one of claims 16-18, wherein, Before the host receives the test data from the current test circuit, the method further includes: The host sends a data read instruction to a buffer in the current test circuit, the buffer storing the test data.

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