Semiconductor package and method of forming same

Abstract

The invention provides a semiconductor package and a method of forming the same. A semiconductor package includes a through electrode within a substrate. The wiring structure is disposed on the substrate and includes a die pad and a protective insulating layer. The protrusion pattern is disposed on the protective insulating layer. The front bonding insulating layer is disposed on the wiring structure. A protrusion pattern is disposed within the front bonding insulating layer. A front bonding pad is disposed within the front bonding insulating layer and is connected to the chip pad.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a semiconductor package including a through electrode and a method of forming the same. BACKGROUND

[0002] Semiconductor chips formed on a semiconductor wafer are separated using a scribe process. The scribe process includes, for example, cutting the wafer along a central line of a scribe lane. In response to a demand for high integration of semiconductor packages, a technology for stacking semiconductor chips is being developed. The stacked semiconductor chips are electrically connected through through silicon vias (TSVs) and bonding pads. SUMMARY

[0003] A semiconductor package according to an embodiment of the present disclosure can include a through electrode within a substrate. A wiring structure can be disposed on the substrate and can include a chip pad and a protection insulating layer. A bump pattern can be disposed on the protection insulating layer. A front bonding insulating layer can be disposed on the wiring structure. The bump pattern can be disposed within the front bonding insulating layer. A front bonding pad can be disposed within the front bonding insulating layer and can be connected to the chip pad.

[0004] A semiconductor package according to an embodiment of the present disclosure can include a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip can include a first substrate, a first through electrode in the first substrate, a first wiring structure disposed on the first substrate and including a first chip pad and a first protection insulating layer, a first bump pattern on the first protection insulating layer, a first front bonding insulating layer on the first wiring structure, and a first front bonding pad disposed within the first front bonding insulating layer and connected to the first chip pad. The second semiconductor chip can include a second substrate, a second wiring structure disposed on the second substrate and including a second chip pad and a second protection insulating layer, a second bump pattern on the second protection insulating layer, a second front bonding insulating layer on the second wiring structure, and a second front bonding pad disposed within the second front bonding insulating layer and connected to the second chip pad. The first bump pattern can be disposed within the first front bonding insulating layer. The second bump pattern can be disposed within the second front bonding insulating layer.

[0005] A semiconductor package according to an embodiment of the present disclosure can include a wiring structure disposed on a substrate and including a chip pad and a protection insulating layer. A bump pattern can be disposed on the protection insulating layer. A front bonding insulating layer can be disposed on the wiring structure. The bump pattern can be disposed within the front bonding insulating layer. A front bonding pad can be disposed within the front bonding insulating layer and can be connected to the chip pad.

[0006] A method of forming a semiconductor package according to embodiments of the disclosure can include forming a substrate having a wiring structure. The method can include forming a recess that penetrates the wiring structure. The method can include forming a front side bonding insulating layer on the wiring structure after forming the recess. The method can include cutting the front side bonding insulating layer and the substrate using a dicing process.

[0007] A semiconductor package according to embodiments of the disclosure can include a substrate, a wiring structure disposed on the substrate and including a protective insulating layer, an insulating layer disposed on a first surface and a second surface of the wiring structure, wherein the second surface extends away from the first surface, and a protrusion pattern disposed on the protective insulating layer and within the insulating layer, wherein the insulating layer is cut during a dicing process. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional view of a semiconductor package according to embodiments of the disclosure.

[0009] Figures 2 to 6 is a partial view of a section of a semiconductor package illustrating embodiments of the disclosure.

[0010] Figure 7 is a cross-sectional view of a semiconductor package according to embodiments of the disclosure.

[0011] Figure 8 is a flowchart illustrating a method of forming a semiconductor package according to embodiments of the disclosure.

[0012] Figure 9 is a plan view of a substrate including a semiconductor chip according to embodiments of the disclosure.

[0013] Figure 10 is a partial view of a section of a substrate including a semiconductor chip illustrating embodiments of the disclosure.

[0014] Figures 11 to 26 is a cross-sectional view of a semiconductor package formed using a method according to embodiments of the disclosure. DETAILED DESCRIPTION

[0015] Embodiments of the disclosure are described in detail with reference to the attached drawings. The detailed description of the embodiments of the disclosure is provided as examples in order to convey the essence of the concepts disclosed in this application. The scope of the disclosure is not limited to the examples or embodiments described in this specification, but extends to any modifications within the spirit of the concepts disclosed in this application.

[0016] Cross-hatching in all the drawings indicates corresponding or similar elements in the various figures, not necessarily by their relative spatial relationship. Terms such as "vertical", "horizontal", "top", "bottom", "over", "on", "side", "interior", "upper", "uppermost", "lower", "higher", "front", "rear", "row", "column", "horizontal", and other terms that imply relative spatial relationships or orientations are used for the purpose of convenience and reference in the description or reference to the drawings, and are not intended to be limiting.

[0017] When an element is identified as "connected", "coupled", or "linked" to another element, it can be directly connected, coupled, or linked to the other element, or it can be connected, coupled, or linked through at least one intervening element. When two elements are identified as "directly connected", "directly coupled", or "directly linked", one is connected, coupled, or linked to the other without any intervening elements.

[0018] When using temporal relative terms such as "after", "before", etc. to describe the relationship between two processes, the two processes or operations can be non-continuous or non-sequential processes or operations, with or without intermediate processes between the two processes or operations. When the temporal relative terms are used in conjunction with "directly" or "immediately" for two processes, the two processes are executed continuously or sequentially.

[0019] Embodiments of the present disclosure include semiconductor packages with through electrodes and methods of forming the same.

[0020] Figure 1 A cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. Figures 2 to 6 A partial view of a section 10 (e.g., Figure 1 shown by the dashed box in FIG. 1).

[0021] Referring to Figure 1 , a semiconductor package according to an embodiment of the present disclosure includes a semiconductor chip 100. The semiconductor chip 100 includes a substrate 21, a wiring structure 31, a through electrode 39, a protrusion pattern 41, a front side bonding pad 43, a front side bonding insulating layer 45, a back side insulating layer 52, a back side bonding pad 53, and a back side bonding insulating layer 55. The semiconductor chip 100 includes an active region AR and an outer region OR. The outer region OR is continuous along an outer periphery of the active region AR. The wiring structure 31 includes a guard ring 34 that serves as an indication to separate the active region AR and the outer region OR. Referring to Figure 9 and Figure 10 The guard ring 34, the active region AR, and the outer region OR are described.

[0022] The substrate 21 includes a first surface 23 opposite the second surface 24. The first surface 23 is referred to as a front surface of the substrate 21, and the second surface 24 is referred to as a back surface of the substrate 21. The substrate 21 extends across the active area AR and the outer side area OR. The wiring structure 31 includes a circuit insulating layer 32, horizontal / vertical wires 33, a protection ring 34, chip pads 35, and a protection insulating layer 36. The semiconductor chip 100 can include various types of active / passive elements, such as transistors and / or capacitors, inside the substrate 21, extending between the substrate 21 and the wiring structure 31, and / or inside the wiring structure 31. In embodiments, the semiconductor chip 100 includes a memory, a processor, or a combination thereof. The semiconductor chip 100 can include a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), a resistive random access memory (RRAM), or a combination thereof.

[0023] The wiring structure 31 is disposed on the first surface 23 of the substrate 21. In embodiments, a horizontal width of the wiring structure 31 is less than a horizontal width of the substrate 21. The through electrode 39 penetrates the substrate 21 in a vertical direction. The through electrode 39 is connected to the wiring structure 31. In embodiments, one end of the through electrode 39 penetrates into the circuit insulating layer 32 and contacts the horizontal / vertical wires 33.

[0024] The front side bonding insulating layer 45 is disposed on the wiring structure 31. The front side bonding pads 43 are disposed within the front side bonding insulating layer 45. A top surface of the front side bonding insulating layer 45 is formed in substantially the same plane as a top surface of the front side bonding pads 43. The front side bonding pads 43 contact the chip pads 35 within the wiring structure 31. The front side bonding pads 43 are electrically connected to the horizontal / vertical wires 33 through the chip pads 35.

[0025] A protrusion pattern 41 is disposed on the protection insulating layer 36 of the wiring structure 31. The protrusion pattern 41 is covered, disposed, or embedded within the front side bonding insulating layer 45. The protrusion pattern 41 is disposed near or at an edge of the wiring structure 31. The protrusion pattern 41 is disposed within the outer side area OR. In embodiments, a distance between the edge of the wiring structure 31 and the protrusion pattern 41 is less than a distance between the edge of the wiring structure 31 and the chip pads 35. The distance between the edge of the wiring structure 31 and the protrusion pattern 41 is less than a distance between the edge of the wiring structure 31 and the front side bonding pads 43.

[0026] The front side bonding insulating layer 45 extends downward along the side surface of the wiring structure 31. In an embodiment, the front side bonding insulating layer 45 completely surrounds or covers the side surface of the wiring structure 31. One end of the front side bonding insulating layer 45 is disposed near or adjacent to the boundary between the substrate 21 and the wiring structure 31. In an embodiment, the one end of the front side bonding insulating layer 45 contacts the surface at the boundary or interface between the substrate 21 and the wiring structure 31.

[0027] The back side insulating layer 52 and the back side bonding insulating layer 55 are disposed in sequence on the second surface 24 of the substrate 21. The back side bonding pad 53 is in contact with the back side insulating layer 52. The back side bonding pad 53 is disposed within the back side bonding insulating layer 55. The lower surface of the back side bonding insulating layer 55 and the back side bonding pad 53 are in contact with the second surface 24 of the substrate 21. Figure 1 In an example, the back side bonding pad 53 and the through electrode 39 are formed in substantially the same plane. One end of the through electrode 39 penetrates the back side insulating layer 52 and is in contact with the back side bonding pad 53.

[0028] In an embodiment, the side surfaces of the back side bonding insulating layer 55, the back side insulating layer 52, the substrate 21, and the front side bonding insulating layer 45 are vertically aligned. The side surfaces of the back side bonding insulating layer 55, the back side insulating layer 52, the substrate 21, and the front side bonding insulating layer 45 are formed in substantially the same plane. In an example where the side surface of the wiring structure 31 is completely covered by the front side bonding insulating layer 45, the side surface of the wiring structure 31 is not exposed. Each of the back side bonding insulating layer 55, the back side insulating layer 52, the substrate 21, and the front side bonding insulating layer 45 has substantially the same horizontal width.

[0029] Referring to Figure 2 , the protrusion pattern 41 is disposed on the protective insulating layer 36. In an embodiment, the protrusion pattern 41 is disposed within the outer side region OR. Due to the front side bonding insulating layer 45, the protrusion pattern 41 is not exposed to the environment outside the semiconductor package. In the present example, the protrusion pattern 41 is completely covered, disposed, or buried within the front side bonding insulating layer 45. The front side bonding insulating layer 45 includes a first surface 45S1 and a second surface 45S2 facing in opposite directions. The first surface 45S1 of the front side bonding insulating layer 45 is in contact with the wiring structure 31. The second surface 45S2 of the front side bonding insulating layer 45 can be relatively distant from the wiring structure 31. In an embodiment, the protrusion pattern 41 is formed between the wiring structure 31 and the second surface 45S2 of the front side bonding insulating layer 45. The protrusion pattern 41 is disposed, located, or confined between the wiring structure 31 and the second surface 45S2 of the front side bonding insulating layer 45. The protrusion pattern 41 can include a material different from that of the front side bonding insulating layer 45. The material composition of the protrusion pattern 41 will be described with reference to Figure 16 .

[0030] The outer region OR is provided with a groove 31G that penetrates the wiring structure 31, which will be described with reference to Figure 16 The detail. The front bonding insulating layer 45 extends inside the groove 31G or fills the groove 31G. The front bonding insulating layer 45 is in contact with the side surface of the wiring structure 31. The bottom of the front bonding insulating layer 45 can be in contact with the substrate 21. In an embodiment, the boundary between the front bonding insulating layer 45 and the substrate 21 is substantially in the same plane as the boundary between the wiring structure 31 and the substrate 21, as shown in the example of Figure 2 and Figure 6 The side surface of the substrate 21 and the side surface of the front bonding insulating layer 45 are vertically aligned, as shown in the example of Figures 1 to 6 The side surface of the substrate 21 and the side surface of the front bonding insulating layer 45 are formed in substantially the same plane.

[0031] The front bonding insulating layer 45 includes a single layer or two or more layers of material. The front bonding insulating layer 45 can include at least two or more materials selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), and boron (B). The front bonding insulating layer 45 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), a low-k dielectric, a high-k dielectric, or a combination thereof.

[0032] The upper surface or top of the front bonding pad 43 is formed in substantially the same plane as the second surface 45S2 of the front bonding insulating layer 45. In an embodiment, the front bonding insulating layer 45 includes a first or lower bonding insulating layer 45A and a second or upper bonding insulating layer 45B. The lower bonding insulating layer 45A is disposed on the protective insulating layer 36 and the protrusion pattern 41. In this example, the lower bonding insulating layer 45A covers the upper surface and the side surface of the protrusion pattern 41.

[0033] The lower bonding insulating layer 45A surrounds the side surface of the front bonding pad 43. The lower bonding insulating layer 45A contacts the upper surface of the protective insulating layer 36. In this example, the lower bonding insulating layer 45A completely covers the upper surface and the side surface of the protrusion pattern 41. The lower bonding insulating layer 45A extends inside the groove 31G. The lower bonding insulating layer 45A contacts the side surface of the protective insulating layer 36, the side surface of the circuit insulating layer 32, and the substrate 21. The lower bonding insulating layer 45A prevents the material of the front bonding pad 43 (e.g., a conductive material such as copper) from spreading or diffusing. The upper surface of the lower bonding insulating layer 45A can include a non-flat structure. The upper bonding insulating layer 45B is disposed on the lower bonding insulating layer 45A. The lower bonding insulating layer 45A extends between the upper bonding insulating layer 45B and the front bonding pad 43. The top of the front bonding pad 43, the top of the lower bonding insulating layer 45A, and the top of the upper bonding insulating layer 45B are formed in substantially the same plane.

[0034] The upper junction insulating layer 45B includes a material having better gap filling properties and insulating properties than the lower junction insulating layer 45A. The lower junction insulating layer 45A can include nitride, such as silicon nitride. The upper junction insulating layer 45B can include silicon oxide (e.g., thermal oxide, or silicon oxide formed by plasma enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS), etc.), silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), or a combination thereof. In an embodiment, the upper junction insulating layer 45B includes silicon oxide or silicon carbon nitride (SiCN).

[0035] The through electrode 39 penetrates the substrate 21 and the circuit insulating layer 32 vertically, and contacts the horizontal / vertical wiring 33. A spacer 38 is formed on a side surface of the through electrode 39. The spacer 38 surrounds the side surface of the through electrode 39. The through electrode 39 is insulated from the substrate 21 by the spacer 38.

[0036] The chip pad 35 is disposed on the circuit insulating layer 32. The chip pad 35 is electrically connected to the horizontal / vertical wiring 33. The protective insulating layer 36 covers or is disposed on the circuit insulating layer 32, and covers or is disposed on an edge or an outer periphery of the chip pad 35.

[0037] The protective insulating layer 36 includes a single layer or two or more layers of material. The protective insulating layer 36 can include at least two materials selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), and boron (B). Each of the circuit insulating layer 32, the protective insulating layer 36, and the spacer 38 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), a low-k dielectric material, a high-k dielectric material, or a combination thereof.

[0038] In an embodiment, the protective insulating layer 36 can include a lower protective insulating layer 36A and an upper protective insulating layer 36B. The upper protective insulating layer 36B is formed on the lower protective insulating layer 36A. The lower protective insulating layer 36A can include a material having better gap filling properties and insulating properties than the upper protective insulating layer 36B. The lower protective insulating layer 36A can include silicon oxide formed using TEOS (tetraethyl orthosilicate). The upper protective insulating layer 36B can include a material having better moisture resistance than the lower protective insulating layer 36A. The upper protective insulating layer 36B can include a material capable of compensating for stress caused by the lower protective insulating layer 36A. The upper protective insulating layer 36B can include silicon nitride.

[0039] The front side bonding pad 43 is disposed on the protective insulating layer 36. The front side bonding pad 43 penetrates the protective insulating layer 36 and contacts the chip pad 35. During patterning of the protective insulating layer 36, the top surface of the chip pad 35 is partially recessed by over-etching. A central region of the top surface of the chip pad 35 is recessed to a lower height than the outer periphery. The bottom of the front side bonding pad 43 can extend to a lower height than the top of the chip pad 35. The thickness of the chip pad 35 in the contact region between the chip pad 35 and the front side bonding pad 43 is less than or thinner than the thickness of the chip pad 35 in the overlap region between the chip pad 35 and the protective insulating layer 36. Thus, the thickness of the chip pad 35 in the contact region between the chip pad 35 and the front side bonding pad 43 is less than the thickness of the chip pad 35 at the outermost periphery of the chip pad 35. In embodiments, the front side bonding pad 43 includes a first barrier layer 43B, a first seed layer 43S, and a first conductive layer 43C.

[0040] Referring to Figure 3 , the recess 31G2 penetrates the wiring structure 31 completely in the vertical direction and extends into the substrate 21. The lower end of the front side bonding insulating layer 45 extends into the substrate 21. The boundary between the bottom of the front side bonding insulating layer 45 and the substrate 21 is disposed at a lower height than the boundary between the wiring structure 31 and the substrate 21.

[0041] Referring to Figure 4 , the recess 31G3 is formed and terminates within the wiring structure 31. A portion of the circuit insulating layer 32 remains between the bottom of the recess 31G3 and the substrate 21. The bottom of the front side bonding insulating layer 45 is disposed at a height above the boundary between the wiring structure 31 and the substrate 21. The circuit insulating layer 32 of the wiring structure 31 extends between the bottom of the front side bonding insulating layer 45 and the first surface 23 of the substrate 21. In this example, the side surface of the substrate 21, the side surface of the circuit insulating layer 32, and the side surface of the front side bonding insulating layer 45 are vertically aligned. The side surface of the substrate 21, the side surface of the circuit insulating layer 32, and the side surface of the front side bonding insulating layer 45 are formed in substantially the same plane.

[0042] Referring to Figure 5 , the side surface of the substrate 21, the side surface of the circuit insulating layer 32, the side surface of the protective insulating layer 36, and the side surface of the front side bonding insulating layer 45 are vertically aligned. The side surface of the substrate 21, the side surface of the circuit insulating layer 32, the side surface of the protective insulating layer 36, and the side surface of the front side bonding insulating layer 45 are formed in substantially the same plane. Referring to Figure 25 exposure of the side surface of the substrate 21, the side surface of the circuit insulating layer 32, the side surface of the protective insulating layer 36, and the side surface of the front side bonding insulating layer 45 is described.

[0043] Referring to Figure 6The front side bonding insulating layer 45 can include a single layer. The protrusion pattern 41 can be completely covered, disposed, or embedded within the front side bonding insulating layer 45. The upper surface of the front side bonding pad 43 is formed in substantially the same plane as the second surface 45S2 of the front side bonding insulating layer 45.

[0044] Figure 7 A cross-sectional view of a semiconductor package according to an embodiment of the disclosure. In an embodiment, the semiconductor package includes a package-on-package or a multi-chip package.

[0045] Referring to Figure 7 The semiconductor package according to an embodiment of the disclosure includes a first semiconductor chip 101, a second semiconductor chip 201, a third semiconductor chip 301, and a fourth semiconductor chip 401 stacked in sequence on a base structure 921. For example, each of the semiconductor chips 101, 201, 301, and 401 can have a similar configuration as described, for example, with reference to Figure 1 A connection terminal 923 is disposed between the first semiconductor chip 101 and the base structure 921. An encapsulation layer 926 covering the semiconductor chips 101, 201, 301, and 401 is disposed on the base structure 921.

[0046] The first semiconductor chip 101 includes a first substrate 121, a first wiring structure 131, a first through electrode 139, a first protrusion pattern 141, a first front side bonding pad 143, a first front side bonding insulating layer 145, a first back side insulating layer 152, a first back side bonding pad 153, and a first back side bonding insulating layer 155. The first substrate 121, the first wiring structure 131, the first through electrode 139, the first protrusion pattern 141, the first front side bonding pad 143, the first front side bonding insulating layer 145, the first back side insulating layer 152, the first back side bonding pad 153, and the first back side bonding insulating layer 155 can respectively have similar configurations as the substrate 21, the wiring structure 31, the through electrode 39, the protrusion pattern 41, the front side bonding pad 43, the front side bonding insulating layer 45, the back side insulating layer 52, the back side bonding pad 53, and the back side bonding insulating layer 55 described, for example, with reference to Figures 1 to 6

[0047] The first wiring structure 131 includes a first circuit insulating layer 132, a first horizontal / vertical wiring 133, a first protection ring 134, a first chip pad 135, and a first protection insulating layer 136. The first circuit insulating layer 132, the first horizontal / vertical wiring 133, the first protection ring 134, the first chip pad 135, and the first protection insulating layer 136 can respectively have similar configurations as the circuit insulating layer 32, the horizontal / vertical wiring 33, the protection ring 34, the chip pad 35, and the protection insulating layer 36 described, for example, with reference to Figures 1 to 6 ​​

[0048] The first protective insulating layer 136 includes a first lower protective insulating layer 136A and a first upper protective insulating layer 136B. The first lower protective insulating layer 136A and the first upper protective insulating layer 136B can have similar configurations to, for example, the lower protective insulating layer 36A and the upper protective insulating layer 36B described with reference to FIG. 2, respectively. Figures 1 to 6 The first front bonding insulating layer 145 includes a first lower bonding insulating layer 145A and a first upper bonding insulating layer 145B. The first lower bonding insulating layer 145A and the first upper bonding insulating layer 145B can have similar configurations to, for example, the lower bonding insulating layer 45A and the upper bonding insulating layer 45B described with reference to FIG. 3, respectively. Figures 1 to 6 The first front bonding insulating layer 145 includes a first lower bonding insulating layer 145A and a first upper bonding insulating layer 145B. The first lower bonding insulating layer 145A and the first upper bonding insulating layer 145B can have similar configurations to, for example, the lower bonding insulating layer 45A and the upper bonding insulating layer 45B described with reference to FIG. 3, respectively.

[0049] The second semiconductor chip 201 includes a second substrate 221, a second wiring structure 231, a second through electrode 239, a second protrusion pattern 241, a second front bonding pad 243, a second front bonding insulating layer 245, a second back insulating layer 252, a second back bonding pad 253, and a second back bonding insulating layer 255. The second substrate 221, the second wiring structure 231, the second through electrode 239, the second protrusion pattern 241, the second front bonding pad 243, the second front bonding insulating layer 245, the second back insulating layer 252, the second back bonding pad 253, and the second back bonding insulating layer 255 can have similar configurations to, for example, the substrate 21, the wiring structure 31, the through electrode 39, the protrusion pattern 41, the front bonding pad 43, the front bonding insulating layer 45, the back insulating layer 52, the back bonding pad 53, and the back bonding insulating layer 55 described with reference to FIG. 2, respectively. Figures 1 to 6 The second semiconductor chip 201 includes a second substrate 221, a second wiring structure 231, a second through electrode 239, a second protrusion pattern 241, a second front bonding pad 243, a second front bonding insulating layer 245, a second back insulating layer 252, a second back bonding pad 253, and a second back bonding insulating layer 255. The second substrate 221, the second wiring structure 231, the second through electrode 239, the second protrusion pattern 241, the second front bonding pad 243, the second front bonding insulating layer 245, the second back insulating layer 252, the second back bonding pad 253, and the second back bonding insulating layer 255 can have similar configurations to, for example, the substrate 21, the wiring structure 31, the through electrode 39, the protrusion pattern 41, the front bonding pad 43, the front bonding insulating layer 45, the back insulating layer 52, the back bonding pad 53, and the back bonding insulating layer 55 described with reference to FIG. 2, respectively.

[0050] The second wiring structure 231 includes a second circuit insulating layer 232, a second horizontal / vertical wiring 233, a second protection ring 234, a second chip pad 235, and a second protective insulating layer 236. The second circuit insulating layer 232, the second horizontal / vertical wiring 233, the second protection ring 234, the second chip pad 235, and the second protective insulating layer 236 can have similar configurations to, for example, the circuit insulating layer 32, the horizontal / vertical wiring 33, the protection ring 34, the chip pad 35, and the protective insulating layer 36 described with reference to FIG. 2, respectively. Figures 1 to 6 The second wiring structure 231 includes a second circuit insulating layer 232, a second horizontal / vertical wiring 233, a second protection ring 234, a second chip pad 235, and a second protective insulating layer 236. The second circuit insulating layer 232, the second horizontal / vertical wiring 233, the second protection ring 234, the second chip pad 235, and the second protective insulating layer 236 can have similar configurations to, for example, the circuit insulating layer 32, the horizontal / vertical wiring 33, the protection ring 34, the chip pad 35, and the protective insulating layer 36 described with reference to FIG. 2, respectively.

[0051] The second protective insulating layer 236 includes a second lower protective insulating layer 236A and a second upper protective insulating layer 236B. The second lower protective insulating layer 236A and the second upper protective insulating layer 236B can have similar configurations to, for example, the lower protective insulating layer 36A and the upper protective insulating layer 36B described with reference to FIG. 2, respectively. Figures 1 to 6The lower and upper protective insulating layers 36A and 36B are similarly configured. The second front bonding insulating layer 245 includes a second lower bonding insulating layer 245A and a second upper bonding insulating layer 245B. The second lower and upper bonding insulating layers 245A and 245B can respectively have similar configurations to, for example, the lower and upper bonding insulating layers 45A and 45B described with reference to FIG. 4. Figures 1 to 6 The lower and upper bonding insulating layers 45A and 45B are similarly configured.

[0052] The third semiconductor chip 301 includes a third substrate 321, a third wiring structure 331, a third through electrode 339, a third bump pattern 341, a third front bonding pad 343, a third front bonding insulating layer 345, a third back insulating layer 352, a third back bonding pad 353, and a third back bonding insulating layer 355. The third substrate 321, the third wiring structure 331, the third through electrode 339, the third bump pattern 341, the third front bonding pad 343, the third front bonding insulating layer 345, the third back insulating layer 352, the third back bonding pad 353, and the third back bonding insulating layer 355 can respectively have similar configurations to, for example, the substrate 21, the wiring structure 31, the through electrode 39, the bump pattern 41, the front bonding pad 43, the front bonding insulating layer 45, the back insulating layer 52, the back bonding pad 53, and the back bonding insulating layer 55 described with reference to FIG. 5. Figures 1 to 6 The substrate 21, the wiring structure 31, the through electrode 39, the bump pattern 41, the front bonding pad 43, the front bonding insulating layer 45, the back insulating layer 52, the back bonding pad 53, and the back bonding insulating layer 55 are similarly configured.

[0053] The third wiring structure 331 includes a third circuit insulating layer 332, a third horizontal / vertical wiring 333, a third guard ring 334, a third chip pad 335, and a third protective insulating layer 336. The third circuit insulating layer 332, the third horizontal / vertical wiring 333, the third guard ring 334, the third chip pad 335, and the third protective insulating layer 336 can respectively have similar configurations to, for example, the circuit insulating layer 32, the horizontal / vertical wiring 33, the guard ring 34, the chip pad 35, and the protective insulating layer 36 described with reference to FIG. 6. Figures 1 to 6 The circuit insulating layer 32, the horizontal / vertical wiring 33, the guard ring 34, the chip pad 35, and the protective insulating layer 36 are similarly configured.

[0054] The third protective insulating layer 336 includes a third lower protective insulating layer 336A and a third upper protective insulating layer 336B. The third lower and upper protective insulating layers 336A and 336B can respectively have similar configurations to, for example, the lower and upper protective insulating layers 36A and 36B described with reference to FIG. 7. Figures 1 to 6 The lower and upper protective insulating layers 36A and 36B are similarly configured. The third front bonding insulating layer 345 includes a third lower bonding insulating layer 345A and a third upper bonding insulating layer 345B. The third lower and upper bonding insulating layers 345A and 345B can respectively have similar configurations to, for example, the lower and upper bonding insulating layers 45A and 45B described with reference to FIG. 4. Figures 1 to 6 The lower and upper bonding insulating layers 45A and 45B are similarly configured.

[0055] The topmost semiconductor chip or the fourth semiconductor chip 401 can have a similar configuration, which does not include Figure 1 Some components of the semiconductor chip 100 shown are illustrated (e.g., through electrode 39, back insulating layer 52, back bonding pad 53, and back bonding insulating layer 55). In an embodiment, the thickness of the uppermost semiconductor chip / fourth semiconductor chip 401 is greater than the thickness of each of semiconductor chips 101, 201, and 301. In an embodiment, the uppermost semiconductor chip / fourth semiconductor chip 401 may have the same thickness as... Figure 1 The semiconductor chip 100 shown has a similar configuration. The thickness of the topmost semiconductor chip / fourth semiconductor chip 401 can be substantially the same as the thickness of each of semiconductor chips 101, 201 and 301.

[0056] The fourth semiconductor chip 401 includes a fourth substrate 421, a fourth wiring structure 431, a fourth protrusion pattern 441, a fourth front-side bonding pad 443, and a fourth front-side bonding insulating layer 445. The fourth substrate 421, the fourth wiring structure 431, the fourth protrusion pattern 441, the fourth front-side bonding pad 443, and the fourth front-side bonding insulating layer 445 may each have, for example, the features described above. Figures 1 to 6 The substrate 21, wiring structure 31, protrusion pattern 41, front bonding pad 43 and front bonding insulating layer 45 are similarly configured.

[0057] The fourth wiring structure 431 includes a fourth circuit insulating layer 432, a fourth horizontal / vertical wiring 433, a fourth guard ring 434, a fourth chip pad 435, and a fourth protective insulating layer 436. The fourth circuit insulating layer 432, the fourth horizontal / vertical wiring 433, the fourth guard ring 434, the fourth chip pad 435, and the fourth protective insulating layer 436 may each have, for example, the features described above. Figures 1 to 6 The circuit insulating layer 32, horizontal / vertical wiring 33, guard ring 34, chip pad 35 and protective insulating layer 36 are configured similarly.

[0058] The fourth protective insulation layer 436 includes a fourth lower protective insulation layer 436A and a fourth upper protective insulation layer 436B. The fourth lower protective insulation layer 436A and the fourth upper protective insulation layer 436B may each have, for example, the characteristics described above. Figures 1 to 6 The lower protective insulating layer 36A and the upper protective insulating layer 36B have similar configurations. The fourth front bonding insulating layer 445 includes a fourth lower bonding insulating layer 445A and a fourth upper bonding insulating layer 445B. The fourth lower bonding insulating layer 445A and the fourth upper bonding insulating layer 445B may each have the same configuration as, for example, as shown in the reference. Figures 1 to 6 The lower bonding insulating layer 45A and the upper bonding insulating layer 45B have similar configurations.

[0059] The base structure 921 includes any substrate used in the semiconductor field. In an embodiment, the base structure 921 includes a base chip, an interposer, or a combination thereof. The connection terminals 923 are formed between the first face bonding pads 143 of the first semiconductor chip 101 and the base structure 921. The first semiconductor chip 101 is electrically connected to the base structure 921 through the first face bonding pads 143. The connection terminals 923 can include conductive bumps, solder balls, conductive pins, or a combination thereof.

[0060] The second semiconductor chip 201 is bonded to the first semiconductor chip 101. The second face bonding insulating layer 245 of the second semiconductor chip 201 is bonded to the first back bonding insulating layer 155 of the first semiconductor chip 101. The second face bonding pads 243 are bonded to the first back bonding pads 153 of the first semiconductor chip 101. The second protrusion pattern 241 of the second semiconductor chip 201 can be covered, disposed, or embedded within the second face bonding insulating layer 245. In an embodiment, the second face bonding insulating layer 245 of the second semiconductor chip 201 directly contacts the first back bonding insulating layer 155 of the first semiconductor chip 101. In an embodiment, the second face bonding pads 243 of the second semiconductor chip 201 directly contact the first back bonding pads 153 of the first semiconductor chip 101.

[0061] In an embodiment, since the second protrusion pattern 241 is covered, disposed, or embedded within the second face bonding insulating layer 245, the interface between the second face bonding insulating layer 245 and the first back bonding insulating layer 155 remains flat. Accordingly, the bonding force between the second face bonding insulating layer 245 and the first back bonding insulating layer 155 can be strengthened. Since the interface between the second face bonding insulating layer 245 and the first back bonding insulating layer 155 remains flat, the bonding defects, such as delamination, warpage, unbonding, or void, between the first semiconductor chip 101 and the second semiconductor chip 201 can be prevented.

[0062] The third semiconductor chip 301 is bonded to the second semiconductor chip 201 in a manner similar to the manner in which the first semiconductor chip 101 is bonded to the second semiconductor chip 201. A third front bonding insulating layer 345 of the third semiconductor chip 301 is bonded to the second back bonding insulating layer 255 of the second semiconductor chip 201. Third front bonding pads 343 of the third semiconductor chip 301 are bonded to the second back bonding pads 253 of the second semiconductor chip 201. Third protrusion patterns 341 of the third semiconductor chip 301 are covered, disposed, or embedded within the third front bonding insulating layer 345. In embodiments, the third front bonding insulating layer 345 of the third semiconductor chip 301 directly contacts the second back bonding insulating layer 255 of the second semiconductor chip 201. In embodiments, the third front bonding pads 343 of the third semiconductor chip 301 directly contact the second back bonding pads 253 of the second semiconductor chip 201.

[0063] In embodiments, since the third protrusion patterns 341 are covered, disposed, or embedded within the third front bonding insulating layer 345, an interface between the third front bonding insulating layer 345 and the second back bonding insulating layer 255 remains flat. As a result, the bonding force between the third front bonding insulating layer 345 and the second back bonding insulating layer 255 can be strengthened. Since the interface between the third front bonding insulating layer 345 and the second back bonding insulating layer 255 remains flat, bonding defects, such as delamination, warpage, unbonding, or voids, between the second semiconductor chip 201 and the third semiconductor chip 301 can be prevented.

[0064] The fourth semiconductor chip 401 is bonded to the third semiconductor chip 301 in a manner similar to the manner in which the second semiconductor chip 201 is bonded to the third semiconductor chip 301. A fourth front bonding insulating layer 445 of the fourth semiconductor chip 401 is bonded to a third back bonding insulating layer 355 of the third semiconductor chip 301. Fourth front bonding pads 443 of the fourth semiconductor chip 401 are bonded to third back bonding pads 353 of the third semiconductor chip 301. Fourth protrusion patterns 441 of the fourth semiconductor chip 401 are covered, disposed, or embedded within the fourth front bonding insulating layer 445. In embodiments, the fourth front bonding insulating layer 445 of the fourth semiconductor chip 401 directly contacts the third back bonding insulating layer 355 of the third semiconductor chip 301. In embodiments, the fourth front bonding pads 443 of the fourth semiconductor chip 401 directly contact the third back bonding pads 353 of the third semiconductor chip 301. One or more additional semiconductor chips can be bonded between the third semiconductor chip 301 and the uppermost semiconductor chip (in this example, the fourth semiconductor chip 401).

[0065] In an embodiment, since the fourth protrusion pattern 441 is covered, disposed, or embedded in the fourth front side bonding insulating layer 445, the interface between the fourth front side bonding insulating layer 445 and the third back side bonding insulating layer 355 remains flat. Thus, the bonding force between the fourth front side bonding insulating layer 445 and the third back side bonding insulating layer 355 can be strengthened. Since the interface between the fourth front side bonding insulating layer 445 and the third back side bonding insulating layer 355 remains flat, the bonding defects, such as peeling, warpage, unbonding, or void, between the third semiconductor chip 301 and the fourth semiconductor chip 401 can be prevented.

[0066] The encapsulation layer 926 includes epoxy molding compound. The encapsulation layer 926 covers the side surfaces of the semiconductor chips 101, 201, 301, and 401 and extends between the first semiconductor chip 101 and the base structure 921. The connection terminal 923 penetrates the encapsulation layer 926 and contacts the first semiconductor chip 101 and the base structure 921. The second surface 424 of the topmost semiconductor chip / fourth semiconductor chip 401 is formed in substantially the same plane as the upper surface of the encapsulation layer 926. In an embodiment, the second surface 424 of the topmost semiconductor chip / fourth semiconductor chip 401 is exposed. In an embodiment, the encapsulation layer 926 can be formed to cover the second surface 424 of the topmost semiconductor chip / fourth semiconductor chip 401.

[0067] Figure 8 A flowchart illustrating a method of forming a semiconductor package according to an embodiment of the disclosure is shown. Figure 9 A plan view of a substrate 21 including a plurality of semiconductor chips 100, and Figure 10 A partial view of a section 11 is shown to illustrate Figure 9 A cross-sectional view of a semiconductor package according to an embodiment of the disclosure is shown. Figures 11 to 25 A cross-sectional view of a semiconductor package according to an embodiment of the disclosure is shown. Figure 10 A cross-sectional view of a semiconductor package according to an embodiment of the disclosure is shown. Figure 26 A cross-sectional view of a semiconductor package according to an embodiment of the disclosure is shown.

[0068] Referring to Figure 8 A method of forming a semiconductor package according to an embodiment of the disclosure includes forming a substrate B810 including a wiring structure on a first surface, forming front side bonding pads B820 on the wiring structure, forming a groove B830, forming a front side bonding insulating layer B840, forming back side bonding pads and a back side bonding insulating layer B850 on a second surface of the substrate, separating semiconductor chips B860 using a dicing process, and stacking the semiconductor chips B870.

[0069] Referring to Figure 9 and Figure 10The plurality of active regions AR are arranged in the substrate 21 in the row direction and the column direction. The outer region OR is located or formed between consecutive active regions among the plurality of active regions AR. As Figure 10 shown in the example of FIG. 1 1, a guard ring 34 is formed within the active region AR. The guard ring 34 can be overlaid, disposed, buried, or embedded adjacent to or at or near the boundary between the active region AR and the outer region OR. In embodiments, the guard ring 34 is an indication for distinguishing the active region AR and the outer region OR. The guard ring outlines the boundary between the active region AR and the outer region OR. The boundary between the active region AR and the outer region OR is outlined by the guard ring 34. The active region AR is bounded by the guard ring 34. The outer region OR is the region between consecutive guard rings 34 (e.g., the guard ring 34 of an active region AR and the guard ring 34 of the nearest or adjacent active region AR). The guard ring 34 can be formed along the edge of the active region AR. In a plan view, the guard ring 34 can completely surround the active region AR. The outer region OR includes a scribe lane for dicing or separating the semiconductor chip 100 from the substrate 21.

[0070] In embodiments, for example, as shown in Figures 1 to 7 the guard ring 34 can include a plurality of patterns at the same height as the horizontal / vertical wiring 33 and the chip pad 35. The guard ring 34 can completely penetrate the circuit insulating layer 32. A first or lower end of the guard ring 34 can contact the substrate 21. A second or top end of the guard ring 34 can extend into the protection insulating layer 36. An upper surface of the guard ring 34 is formed in substantially the same plane as an upper or outer surface of the chip pad 35. The guard ring 34 can include the same material as the horizontal / vertical wiring 33 and the chip pad 35.

[0071] Referring to Figure 8 and Figure 11 , the substrate 21 B810 is formed on the first surface 23 including the wiring structure 31. The wiring structure 31 includes the circuit insulating layer 32, the horizontal / vertical wiring 33, the guard ring 34, the chip pad 35, and the protection insulating layer 36. The through electrode 39 extends in the vertical direction within the substrate 21 and contacts the horizontal / vertical wiring 33. As shown in the example of Figure 2 , the spacer 38 is included along the side surface of the through electrode 39.

[0072] The substrate 21 can include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The substrate 21 can include a III-V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate 21 can include single crystalline silicon, polycrystalline silicon, amorphous silicon, single crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0073] The circuit insulation layer 32 can cover the active region AR and the outer region OR of the substrate 21. The circuit insulation layer 32 includes the horizontal / vertical wiring 33 and the guard ring 34 therein. The horizontal / vertical wiring 33 and the guard ring 34 are disposed in the active region AR. The guard ring 34 is disposed adjacent to or in the vicinity of the boundary between the active region AR and the outer region OR. In an embodiment, the wiring structure 31 further includes other components, such as alignment keys, cursor keys, dummy patterns, test patterns, etc., located within the outer region OR.

[0074] The chip pad 35 is disposed in the active region AR on the circuit insulation layer 32. The chip pad 35 is connected to the horizontal / vertical wiring 33. The protective insulation layer 36 covers the circuit insulation layer 32 and covers the surface of the chip pad 35. Forming the protective insulation layer 36 can include a thin film forming process and a patterning process. While performing the patterning process to form an opening that exposes the central region of the chip pad 35, the upper surface of the chip pad 35 is etched and partially recessed, as shown in the example of Figure 2 .

[0075] The through electrode 39 is disposed in the active region AR. The through electrode 39 is exemplified as being formed by a via-middle process, but the through electrode 39 can also be formed by a via-first process or a via-last process.

[0076] The circuit insulation layer 32 includes a single layer or two or more layers of material. The circuit insulation layer 32 can include at least two materials selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), and boron (B). The circuit insulation layer 32 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), low-k dielectric, high-k dielectric, or a combination thereof.

[0077] In an embodiment, the protective insulation layer 36 includes a lower protective insulation layer 36A and an upper protective insulation layer 36B. In the present example, the upper protective insulation layer 36B is formed on the lower protective insulation layer 36A.

[0078] Each of the horizontal / vertical wiring 33, the guard ring 34, the chip pad 35, and the through electrode 39 includes a single layer or two or more layers of materials. Each of the horizontal / vertical wiring 33, the guard ring 34, the chip pad 35, and the through electrode 39 can include a metal, a metal silicide, a metal nitride, a metal oxide, polysilicon, conductive carbon, or a combination thereof. Each of the horizontal / vertical wiring 33, the guard ring 34, the chip pad 35, and the through electrode 39 can include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), silver (Ag), platinum (Pt), ruthenium (Ru), gold (Au), aluminum (Al), copper (Cu), tin (Sn), or a combination thereof. In an embodiment, the chip pad 35 can include aluminum (Al).

[0079] Referring to Figure 12 A first barrier layer 43B and a first seed layer 43S are sequentially stacked on the wiring structure 31. The first barrier layer 43B and the first seed layer 43S can be formed by a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or a combination thereof. Figure 12 In an example, the first barrier layer 43B directly contacts the chip pad 35. The first barrier layer 43B can include titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The first seed layer 43S can include copper.

[0080] Referring to Figure 13 A mask pattern 43M is formed on a portion of the first seed layer 43S. The mask pattern 43M can include a photoresist pattern.

[0081] Referring to Figure 14 A first conductive layer 43C is formed on the first seed layer 43S. The first conductive layer 43C can include a metal, a metal nitride, or a combination thereof. The first conductive layer 43C can include copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), silver (Ag), platinum (Pt), ruthenium (Ru), gold (Au), aluminum (Al), tin (Sn), or a combination thereof. In an embodiment, the first conductive layer 43C includes a copper layer formed using an electrolytic plating method.

[0082] Referring to Figure 8 and Figure 15 A face bonding pad 43B820 is formed by removing the mask pattern 43M and partially removing the first barrier layer 43B and the first seed layer 43S. For example, the first barrier layer 43B and the first seed layer 43S can be removed together with the mask pattern 43M, and can be removed from the same area as the mask pattern 43M on the upper protection insulating layer 36B. The face bonding pad 43 includes, as an example, a copper layer 43C, a tantalum nitride layer 43N, a titanium tungsten layer 43W, a titanium layer 43Ti, and a titanium nitride layer 43TiN, which are sequentially stacked. Figure 2The first barrier layer 43B, the first seed layer 43S, and the first conductive layer 43C are shown stacked in that order. The frontside bonding pad 43 contacts the chip pad 35. The frontside bonding pad 43 is disposed in the active region AR.

[0083] Referring to Figure 8 and Figure 16 , the groove 31G penetrates the wiring structure 31B 830 within the outer region OR. The groove 31G is formed along or centered on a centerline of the outer region OR. The horizontal width of the groove 31G is narrower than the width of the outer region OR. In forming the groove 31G, a section of the wiring structure 31 within the outer region OR can be removed. In embodiments, the groove 31G is formed using a laser slotting process.

[0084] In embodiments, the process B 830 of forming the groove 31G is performed after performing the process B 820 of forming the frontside bonding pad 43. During the process of forming the groove 31G, structures such as test patterns, alignment keys, etc. within the outer region OR can be damaged, and due to the process of forming the groove 31G, a protrusion pattern 41 is created or formed on the passivation layer 36 from the detached sections of these structures. The protrusion pattern 41 can be disposed on or attached to the passivation layer 36 near or adjacent to the groove 31G. In embodiments, the protrusion pattern 41 is formed on the passivation layer 36 within the outer region OR. The bottom of the protrusion pattern 41 is formed at a lower height than the top of the frontside bonding pad 43. The bottom of the protrusion pattern 41 is formed at a higher height than the top of the chip pad 35. The protrusion pattern 41 can have an irregular or uneven shape and can extend along the length of both sides of the groove 31G.

[0085] The protrusion pattern 41 can include a metal, a metal silicide, a metal nitride, a metal oxide, polysilicon, conductive carbon, an inorganic material, or a combination thereof. In embodiments, the protrusion pattern 41 includes a metal, such as copper, aluminum, tungsten, or titanium. The protrusion pattern 41 can include metal spurs. In the present example, the protrusion pattern 41 includes the same material as the structures (e.g., test patterns, alignment keys, etc.) within the outer region OR.

[0086] The bottom of the groove 31G is formed at a horizontal location adjacent to the boundary between the substrate 21 and the wiring structure 31, as shown in Figure 16 . The groove 31G can be formed at different depths, as shown in Figures 2 to 6 . The bottom of the groove 31G can be formed at substantially the same horizontal location as the boundary between the substrate 21 and the circuit insulating layer 32, for example Figure 2 . The bottom of the groove 31G2 can be formed at a lower height than the bottom surface of the circuit insulating layer 32, for example Figure 3As shown, the groove 31G2 penetrates the wiring structure 31 completely and extends into the substrate 21. The bottom of the groove 31G3 can be formed at a height higher than a bottom surface of the circuit insulating layer 32, for example Figure 4 As shown.

[0087] Referring to Figure 17 A front side bonding insulating layer 45B 840 is formed on the wiring structure 31 covering the front side bonding pads 43 and the protrusion pattern 41. The protrusion pattern 41 can be covered, disposed or embedded within the front side bonding insulating layer 45. The front side bonding insulating layer 45 can fill the entire groove 31G.

[0088] In an embodiment, the front side bonding insulating layer 45 includes a lower bonding insulating layer 45A and an upper bonding insulating layer 45B. The upper bonding insulating layer 45B is formed on the lower bonding insulating layer 45A. The lower bonding insulating layer 45A covers the upper and side surfaces of the front side bonding pads 43 and the protrusion pattern 41. The lower bonding insulating layer 45A extends inside the groove 31G. The lower bonding insulating layer 45A contacts the side of the wiring structure 31.

[0089] In an embodiment, the protrusion pattern 41 is formed before performing a process of forming the front side bonding insulating layer 45. The protrusion pattern 41 includes a material different from that of the front side bonding insulating layer 45.

[0090] Referring to Figure 8 and Figure 18 The process B 840 of forming the front side bonding insulating layer 45 includes a process of partially removing the front side bonding insulating layer 45 to expose the upper surface of the front side bonding pads 43 using a planarization process. The front side bonding insulating layer 45 and the upper surface of the front side bonding pads 43 are formed in substantially the same plane. The planarization process including the partial removal of the front side bonding insulating layer 45 to expose the upper surface of the front side bonding pads 43 can include a chemical mechanical polishing (CMP) process, an etch back process or a combination thereof.

[0091] In an embodiment, the lower bonding insulating layer 45A covers the protrusion pattern 41 and surrounds the side of the front side bonding pads 43. The lower bonding insulating layer 45A can extend between the front side bonding pads 43 and the upper bonding insulating layer 45B. The uppermost surface of the front side bonding pads 43, the uppermost surface of the lower bonding insulating layer 45A and the uppermost surface of the upper bonding insulating layer 45B are formed in substantially the same plane.

[0092] In an embodiment, the process B820 of forming the front side bonding pad 43, the process B830 of forming the recess 31G, and the process B840 of forming the front side bonding insulating layer 45 are sequentially performed. For example, after performing the process B820 of forming the front side bonding pad 43, the process B830 of forming the recess 31G is performed. After performing the process B830 of forming the recess 31G, the process B840 of forming the front side bonding insulating layer 45 is performed.

[0093] Referring to Figure 19 The substrate 21 including the front side bonding insulating layer 45 and the front side bonding pad 43 is disposed or loaded on the carrier CAR. A first buffer layer BF1 is formed between the carrier CAR and the front side bonding insulating layer 45 and between the carrier CAR and the front side bonding pad 43. The second surface 24 of the substrate 21 is exposed.

[0094] Referring to Figure 20 The substrate 21 is partially removed to expose the through electrode 39. The second surface 24 of the substrate 21 is recessed to be lower than a height of a top of the through electrode 39.

[0095] Referring to Figure 21 A back side insulating layer 52 is formed on the second surface 24 of the substrate 21. The back side insulating layer 52 is formed such that an upper surface of the through electrode 39 is exposed. In an embodiment, the upper surface of the back side insulating layer 52 and the upper surface of the through electrode 39 are exposed in substantially the same plane.

[0096] Referring to Figure 8 and Figure 22 A back side bonding pad 53 and a back side bonding insulating layer 55 are formed on the second surface 24 of the substrate 21 B850. The back side bonding insulating layer 55 covers the back side insulating layer 52. The back side bonding pad 53 is disposed within the back side bonding insulating layer 55. Each of the back side bonding pads 53 is aligned on or centered on the through electrode 39 and disposed in the active region AR. The back side bonding pad 53 is in contact with the through electrode 39. An upper surface of the back side bonding pad 53 and an upper surface of the back side bonding insulating layer 55 are exposed in substantially the same plane.

[0097] The backside landing pad 53 can include a metal, a metal nitride, or a combination thereof. In an embodiment, the backside landing pad 53 includes a second barrier layer 53B, a second seed layer 53S, and a second conductive layer 53C stacked in that order. The second barrier layer 53B contacts the through electrode 39. The second barrier layer 53B can include titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The second seed layer 53S can include copper. The second conductive layer 53C can include copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), silver (Ag), platinum (Pt), ruthenium (Ru), gold (Au), aluminum (Al), tin (Sn), or a combination thereof. In an embodiment, the second conductive layer 53C includes the same material as the first conductive layer 43C. The second conductive layer 53C can include a copper layer formed using an electrolytic plating method.

[0098] Each of the backside insulating layer 52 and the backside landing insulating layer 55 includes a single layer or two or more layers of material. Each of the backside insulating layer 52 and the backside landing insulating layer 55 can include at least two materials selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), and boron (B). Each of the backside insulating layer 52 and the backside landing insulating layer 55 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), a low-K dielectric material, a high-K dielectric material, or a combination thereof. In an embodiment, the backside landing insulating layer 55 can include the same material as the frontside landing insulating layer 45. The backside landing insulating layer 55 can include silicon oxide or silicon carbon nitride (SiCN).

[0099] Referring to Figure 23 A second buffer layer BF2 is formed on the backside landing pad 53 and the backside landing insulating layer 55. The second buffer layer BF2 can include a layer of elastic material, such as a laminated tape.

[0100] Referring to Figure 24 The frontside landing insulating layer 45 and the frontside landing pad 43 are exposed by removing the carrier CAR and the first buffer layer BF1.

[0101] Referring to Figure 8 and Figure 25The semiconductor chip 100B860 is separated using a dicing process. Optionally, the second buffer layer BF2 is removed. The dicing process may include laser stealth dicing, laser dicing, plasma dicing, blade sawing, or a combination thereof. In this embodiment, the dicing process includes laser stealth dicing. Simultaneously with the dicing process, the front bonding insulating layer 45, the substrate 21, the back insulating layer 52, and the back bonding insulating layer 55 are cut vertically.

[0102] The area cut by the dicing process is along... Figure 10 The centerline of the outer region OR is shown. The horizontal width of the area cut by the dicing process is narrower than the width of the outer region OR. The area cut by the dicing process is located above the groove 31G in the vertical direction. In this embodiment, the horizontal width of the area cut by the dicing process is narrower than the width of the groove 31G, and the front bonding insulating layer 45 within the groove 31G is partially retained after the dicing process.

[0103] In this implementation, the horizontal width of the area cut by the dicing process is greater than the width of the groove 31G. For example... Figure 5 As shown, the side surfaces of the substrate 21, the circuit insulating layer 32, the protective insulating layer 36, and the front bonding insulating layer 45 are exposed. The side surfaces of the substrate 21, the circuit insulating layer 32, the protective insulating layer 36, and the front bonding insulating layer 45 are formed in substantially the same plane.

[0104] According to this disclosure, by forming as referenced Figure 16 The groove 31G is used to remove part or all of the wiring structure 31 disposed in the outer region OR. The wiring structure 31 in the outer region OR includes multiple structures, such as test patterns, alignment keys, vernier keys, dummy patterns, etc., which are made of various materials. The wiring structure 31 includes materials different from those of the substrate 21 and the front bonding insulating layer 45. In an embodiment, the wiring structure 31 in the outer region OR may include a metal, and the substrate 21, circuit insulating layer 32, protective insulating layer 36, and front bonding insulating layer 45 may include non-metallic inorganic materials. Non-metallic inorganic materials are brittle materials that may crack and are easily cut as stress is generated during the dicing process. Since metals are ductile materials, plastic deformation may occur even when stress is applied, which may prevent separation or leave residues during the dicing process. Since the wiring structure 31 in the area to be diced is removed while the groove 31G is formed before the dicing process, defects such as failure of the semiconductor chip 100 to separate during the dicing process due to plastic deformation of the wiring structure 31 can be prevented.

[0105] Reference Figure 8 and Figure 26The second to fourth semiconductor chips 201, 301, and 401 are stacked in order on the first semiconductor chip or the lowermost semiconductor chip 101 B870. Each of the semiconductor chips 101, 201, 301, and 401 can include the same configuration, for example, with reference to Figures 1 to 25 the configuration described above.

[0106] In an embodiment, the second semiconductor chip 201 is bonded to the first semiconductor chip 101. The first semiconductor chip 101 is aligned with the second semiconductor chip 201. The second front bonding insulating layer 245 of the second semiconductor chip 201 contacts the first back bonding insulating layer 155 of the first semiconductor chip 101. The first back bonding insulating layer 155 is aligned with the second front bonding insulating layer 245. The second front bonding pad 243 of the second semiconductor chip 201 contacts the first back bonding pad 153 of the first semiconductor chip 101. The first back bonding pad 153 is aligned with the second front bonding pad 243. The first through electrode 139, the first back bonding pad 153, and the second front bonding pad 243 are aligned in the vertical direction. In an embodiment, the first back bonding pad 153 is aligned with the first through electrode 139, and the second front bonding pad 243 is aligned with the first back bonding pad 153.

[0107] The third semiconductor chip 301 is bonded to the second semiconductor chip 201. The second semiconductor chip 201 is aligned with the third semiconductor chip 301. The third front bonding insulating layer 345 of the third semiconductor chip 301 contacts the second back bonding insulating layer 255 of the second semiconductor chip 201. The third front bonding pad 343 of the third semiconductor chip 301 contacts the second back bonding pad 253 of the second semiconductor chip 201. The second through electrode 239, the second back bonding pad 253, and the third front bonding pad 343 are aligned in the vertical direction.

[0108] The fourth semiconductor chip 401 is bonded to the third semiconductor chip 301. The third semiconductor chip 301 is aligned with the fourth semiconductor chip 401. The fourth front bonding insulating layer 445 of the fourth semiconductor chip 401 contacts the third back bonding insulating layer 355 of the third semiconductor chip 301. The fourth front bonding pad 443 of the fourth semiconductor chip 401 contacts the third back bonding pad 353 of the third semiconductor chip 301. The third through electrode 339, the third back bonding pad 353, and the fourth front bonding pad 443 are aligned in the vertical direction. One or more other semiconductor chips can be additionally bonded between the third semiconductor chip 301 and the uppermost semiconductor chip (the fourth semiconductor chip 401 in this example).

[0109] With reference to Figure 7According to the method of forming a semiconductor package according to the present disclosure, the semiconductor chips 101, 201, 301, and 401 can be sequentially bonded on the base structure 921.

[0110] The first semiconductor chip 101 is mounted on the base structure 921. A connection terminal 923 is formed between the first front surface bonding pad 143 of the first semiconductor chip 101 and the base structure 921. The semiconductor chips 201, 301, and 401 are bonded to the first semiconductor chip 101 in a similar manner as described with reference to the semiconductor chip 101. Figure 26

[0111] The concepts are disclosed in connection with the examples and embodiments as described above. Those skilled in the art will understand that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure. The embodiments disclosed in the present application should be considered in a descriptive sense only and not for purposes of limitation. Therefore, the scope of the present disclosure is not limited to the described embodiments. All changes, modifications and equivalents fall within the scope of the claims and their equivalents.

[0112] Cross Reference to Related Applications

[0113] This application claims priority to Korean Patent Application No. 10-2024-0063828, filed on May 16, 2024, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.​

Claims

1. A semiconductor package, the semiconductor package comprising: substrate; A through electrode, wherein the through electrode is located within the substrate; A wiring structure disposed on the substrate and including chip pads and a protective insulating layer; A raised pattern, the raised pattern being on the protective insulating layer; A front bonding insulation layer is provided on the wiring structure, and the protrusion pattern is disposed within the front bonding insulation layer. as well as A front bonding pad is disposed within the front bonding insulating layer and connected to the chip pad.

2. The semiconductor package according to claim 1, wherein, The front-side bonding insulation layer includes a first surface in contact with the wiring structure and a second surface opposite to the first surface. The protruding pattern is disposed between the wiring structure and the second surface.

3. The semiconductor package according to claim 2, wherein, One surface of the front bonding pad is disposed in the same plane as the second surface of the front bonding insulation layer.

4. The semiconductor package according to claim 1, wherein, The distance between the edge of the wiring structure and the protrusion pattern is less than the distance between the edge of the wiring structure and the chip pad.

5. The semiconductor package according to claim 1, wherein, The wiring structure also includes a protective ring that delineates the boundary between the active region and the outer region. The protruding pattern is disposed in the outer region.

6. The semiconductor package according to claim 1, wherein, The front-side bonding insulating layer includes: A first bonding insulating layer is applied to the protective insulating layer and the raised pattern; and A second bonding insulating layer is applied on the first bonding insulating layer; The first bonding insulating layer covers the second surface and side surface of the protrusion pattern; The first bonding insulating layer extends between the front bonding pad and the second bonding insulating layer.

7. The semiconductor package according to claim 6, wherein, The surfaces of the front bonding pads, the first bonding insulating layer, and the second bonding insulating layer are formed in the same plane.

8. The semiconductor package according to claim 1, wherein, The width of the front bonding insulating layer is the same as the width of the substrate.

9. The semiconductor package according to claim 1, wherein, The width of the wiring structure is smaller than the width of the substrate. The front bonding insulation layer extends along the side surface of the wiring structure.

10. The semiconductor package according to claim 1, wherein, One end of the front-side bonding insulating layer contacts the substrate.

11. The semiconductor package according to claim 1, wherein, The side surface of the substrate and the side surface of the front bonding insulating layer are formed in the same plane.

12. The semiconductor package according to claim 1, wherein, The raised pattern includes a material different from the material of the front-side bonding insulation layer.

13. The semiconductor package according to claim 1, wherein, The substrate includes a first surface opposite to the second surface, and the wiring structure is disposed on the first surface. The semiconductor package further includes: A back insulating layer, the back insulating layer being on the second surface of the substrate; A back-side bonding insulating layer, wherein the back-side bonding insulating layer is disposed on the back-side insulating layer; and A back bonding pad is disposed within the back bonding insulation layer and connected to the through electrode.

14. The semiconductor package of claim 13, wherein, The side surface of the back bonding insulating layer, the side surface of the substrate, and the side surface of the front bonding insulating layer are formed in the same plane.

15. The semiconductor package according to claim 1, wherein, The protective insulating layer is disposed on the edge of the chip pad. The front bonding pad penetrates the protective insulating layer and contacts the chip bonding pad. Wherein, the thickness of the chip pad in the contact area between the chip pad and the front bonding pad is less than the thickness of the chip pad at the outermost periphery of the chip pad.

16. A semiconductor package, the semiconductor package comprising: First semiconductor chip; as well as A second semiconductor chip, which is bonded to the first semiconductor chip. The first semiconductor chip includes: First substrate; The first through electrode is located in the first substrate; A first wiring structure is disposed on the first substrate and includes a first chip pad and a first protective insulating layer. A first raised pattern is present on the first protective insulating layer; A first front-side bonding insulating layer, the first front-side bonding insulating layer being on the first wiring structure, and the first protrusion pattern being disposed within the first front-side bonding insulating layer; and The first front bonding pad is disposed within the first front bonding insulating layer and connected to the first chip pad. The second semiconductor chip includes: Second substrate; The second wiring structure is disposed on the second substrate and includes a second chip pad and a second protective insulating layer. The second raised pattern is on the second protective insulating layer; A second front-side bonding insulating layer, the second front-side bonding insulating layer being on the second wiring structure, the second protrusion pattern being disposed within the second front-side bonding insulating layer; and The second front bonding pad is disposed within the second front bonding insulating layer and connected to the second chip pad.

17. The semiconductor package of claim 16, wherein, The first substrate includes a first surface opposite to the second surface, and the first wiring structure is disposed on the first surface. The first semiconductor chip further includes: A first back insulating layer is disposed on the second surface; A first back-side bonding insulating layer, wherein the first back-side bonding insulating layer is disposed on the first back-side insulating layer; and The first back-side bonding pad is disposed within the first back-side bonding insulating layer and connected to the first through electrode. The second front bonding insulating layer is bonded to the first back bonding insulating layer. The second front bonding pad is bonded to the first back bonding pad.

18. The semiconductor package of claim 17, wherein, The first back-side bonding pad is aligned with the first through electrode. The second front bonding pad is aligned with the first back bonding pad.

19. The semiconductor package of claim 17, wherein, The first back-side bonding insulation layer is aligned with the second front-side bonding insulation layer.

20. A semiconductor package, the semiconductor package comprising: substrate; A wiring structure disposed on the substrate and including chip pads and a protective insulating layer; A raised pattern, the raised pattern being on the protective insulating layer; A front bonding insulation layer is provided on the wiring structure, and the protrusion pattern is disposed within the front bonding insulation layer. as well as A front bonding pad is disposed within the front bonding insulating layer and connected to the chip pad.

21. A method for forming a semiconductor package, the method comprising the following steps: Forming a substrate including a wiring structure; Forming a groove that penetrates the wiring structure; After the groove is formed, a front-side bonding insulation layer is formed on the wiring structure; as well as The front bonding insulating layer and the substrate are cut using a dicing process.

22. The method according to claim 21, wherein, The step of forming the groove is performed using a laser grooving process.

23. The method of claim 21, further comprising forming a protruding pattern disposed within the front bonding insulating layer.

24. The method according to claim 23, further comprising the following step: A through electrode is formed within the substrate; and A front bonding pad is formed within the front bonding insulating layer; Wherein, one surface of the front bonding pad and one surface of the front bonding insulating layer are formed in the same plane.

25. The method according to claim 24, wherein, The step of forming the groove is performed after the step of forming the front bonding pad.

26. The method according to claim 24, wherein, The front-side bonding insulating layer includes: A first bonding insulating layer is applied to the wiring structure and the raised pattern; and A second bonding insulating layer is applied on the first bonding insulating layer; The first bonding insulating layer covers the second surface and side surface of the protrusion pattern; The first bonding insulating layer extends between the front bonding pad and the second bonding insulating layer.

27. The method according to claim 26, wherein, The surfaces of the front bonding pads, the first bonding insulating layer, and the second bonding insulating layer are formed in the same plane.

28. The method according to claim 21, wherein, The front-side bonding insulating layer extends inside the groove.

29. A semiconductor package, the semiconductor package comprising: substrate; A wiring structure disposed on the substrate and including a protective insulating layer; An insulating layer is disposed on a first surface and a second surface of the wiring structure, wherein the second surface extends away from the first surface; and A raised pattern, the raised pattern being disposed on and within the protective insulating layer; The insulating layer is cut during the dicing process.

Images