Chipset heat dissipation device

Abstract

The embodiment of the invention provides a chipset heat dissipation device, the chipset heat dissipation device comprises a packaging shell, a packaging substrate and one or more chipsets, the chipsets are located on the packaging substrate, and the chipsets are located in a space formed by the packaging shell and the packaging substrate, each chip group comprises one or more stacked core particles, a first micro-channel for communicating the adjacent core particles and a plurality of radial second micro-channels taking the first micro-channel as an intersection point are arranged at the central position of each core particle, the packaging shell comprises a coolant inlet and a coolant outlet, and the coolant inlet is communicated with the coolant outlet. The coolant inlet is communicated with the first micro-channel, and the coolant outlet is communicated with the second micro-channel. Through the embodiment of the invention, a shorter flow path length of the cooling liquid is realized, so that the fluid resistance is effectively reduced, and a higher heat transfer rate can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip technology, in particular to a chip set heat dissipation device. BACKGROUND

[0002] With the advancement of semiconductor technology, the continuous reduction of transistor size means that the heat density rises rapidly, and the power density can reach 100-300 w / cm2, even locally exceeding 1 kW / cm2. For 3DIC, the heat dissipation problem has gradually become a serious challenge, because the stacking of multiple chips increases the total power per unit area, resulting in increased heat, and there is no effective heat dissipation channel. After wafer thinning, heat aggregation occurs in the chip, resulting in hot spots.

[0003] Current chip heat dissipation is usually achieved by providing a microchannel from one side to the other side of the chip, so that the cooling liquid flows in from one side and out from the other side. However, the above-mentioned heat dissipation method still has the problem of low heat dissipation efficiency. SUMMARY

[0004] In view of the above problems, a chip set heat dissipation device is provided to overcome the above problems or at least partially solve the above problems, comprising:

[0005] A chip set heat dissipation device, comprising: a package shell, a package substrate, and one or more chip sets, the chip sets being located on the package substrate, and the chip sets being in a space formed by the package shell and the package substrate, each chip set comprising one or more stacked chips, each chip having a first microchannel provided at a central position for communication with an adjacent chip, and a plurality of radial second microchannels intersecting at the first microchannel, the package shell comprising a coolant inlet and a coolant outlet, the coolant inlet being in communication with the first microchannel, and the coolant outlet being in communication with the second microchannel.

[0006] Optionally, the first microchannel of the non-bottom chip in each chip set is a central through channel, and the first microchannel of the bottom chip in each chip set is a central non-through channel.

[0007] Optionally, the coolant inlet is connected to a guide channel, and the guide channel is connected to the first microchannel.

[0008] Optionally, the second microchannel is connected to a chip edge channel, and the chip edge channel is connected to the coolant outlet.

[0009] Optionally, the first microchannel and the second microchannel are provided with a sealing ring.

[0010] Optionally, the chip set heat dissipation device uses single-phase or dual-phase cooling.

[0011] Optionally, when the chipset heat dissipating device adopts dual-phase cooling, the coolant outlet is connected with the inlet of a condenser, and the outlet of the condenser is connected with the coolant inlet.

[0012] Optionally, the second microchannels of the core pellets are angularly offset layer by layer.

[0013] Optionally, the cross-sectional geometry of the second microchannels is any of the following:

[0014] rectangular, semicircular, triangular.

[0015] Optionally, the chipset heat dissipating device further comprises transistors, metal windings and through-silicon vias, and the positions of the transistors, the metal windings and the through-silicon vias are determined according to the positions of the first microchannels and the second microchannels.

[0016] The embodiments of the present application have the following advantages:

[0017] In the embodiments of the present application, the first microchannels and the second microchannels are arranged at the center positions of the stacked core pellets, so that the flow path length of the coolant is shortened, the fluid resistance is effectively reduced, and a higher heat transfer rate can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the description of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a structural schematic diagram of a chipset heat dissipating device in the prior art;

[0020] Figure 2 is a structural schematic diagram of a chipset heat dissipating device provided by an embodiment of the present application;

[0021] Figure 3 is a three-dimensional view in an embodiment of the present application;

[0022] Figure 4 is a three-dimensional stacking schematic diagram in an embodiment of the present application;

[0023] Figure 5 is a silicon wafer cross-sectional schematic of a core pellet in an embodiment of the present application;

[0024] Figure 6 is a structural schematic diagram of a heat dissipating device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the above objectives, features and advantages of the present application more clear and easily understandable, the following further describes the present application in conjunction with the accompanying drawings and specific embodiments. Obviously, the described examples are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0026] Three-dimensional integrated circuit (3D Integrated Circuit, 3DIC) is an advanced semiconductor design and packaging technology, which allows performance, power consumption, and area advantages to be achieved through vertical stacking of Chiplets on a single package. In a 3DIC, different Chiplets can be interconnected through through-silicon vias. 3DIC is a key technology to break through the bottleneck of System on Chip (SoC) integration and performance in the post-Moore era, and will play an important role in data centers and various fields such as automobiles and PCs to meet the growing demand for high efficiency and high performance computing power of emerging businesses.

[0027] With the advancement of semiconductor technology, the continuous reduction in transistor size means that the heat density is rapidly rising, with a power density of 100-300 w / cm2, and even locally exceeding 1 kW / cm2. For 3DIC, the heat dissipation problem has gradually become a serious challenge, because the stacking of multiple Chiplets further increases the total power consumption per unit area, generating more heat, and there is no effective heat dissipation channel. Thinning of the wafer can cause heat to accumulate in the chip, resulting in hot spots.

[0028] In practical applications, heat dissipation can be considered from two aspects: packaging-level thermal design and external heat dissipation measures. Among them, the packaging-level thermal design can include optimizing the packaging structure and applying packaging-level cooling technology, such as adding copper heat sinks, aluminum packaging covers, etc. External heat dissipation measures include air cooling, liquid cooling, and phase change cooling, etc. Traditional chip cooling relies on the heat dissipation fins on the top of the chip package for heat dissipation, which cannot cool the Chiplets in the middle or bottom of the stack.

[0029] For three-dimensional integrated circuits, one solution is to use embedded cooling based on micro-channel technology, allowing the coolant to flow between stacked chip layers to remove heat. Microchannels refer to channels with a cross-sectional length in the order of microns. By etching microchannels on the back of the wafer, the coolant can pass through each chip in the 3D stack, effectively relieving the heat generated by the middle and bottom Chiplets. For example, Figure 1As shown, it is a 3D schematic diagram of an edge-to-edge parallel line microchannel heat dissipation design, the stacked chip groups are distributed with parallel microchannels, the coolant enters the microchannels from one side of the parallel line and flows out from the other side of the parallel line.

[0030] The heat dissipation method has the problems of small channel size and relatively long flow path, resulting in low heat dissipation efficiency.

[0031] In the embodiment of the present application, the first microchannel is arranged at the middle position of the stacked chip groups, and the second microchannel is arranged radially with the first microchannel as the intersection point, so that the coolant can be input from the first microchannel and then flow out from the second microchannel, thereby shortening the flow path and improving the heat dissipation efficiency.

[0032] Reference Figure 2 As shown in the structure schematic diagram of the chip group heat dissipation device provided by the embodiment of the present application, the chip group heat dissipation device 200 comprises a packaging shell 201, a packaging substrate 202, and one or more chip groups 203, the chip groups are located on the packaging substrate, and the chip groups are located in the space formed by the packaging shell and the packaging substrate, each chip group comprises one or more stacked chip grains 11, as shown, the chip grains are stacked in three layers to form a chip grain group, each chip grain can be provided with a first microchannel 12 and a second microchannel 13, wherein the center position of the chip grain can be provided with the first microchannel 12 for communication between adjacent chip grains, the second microchannel 13 is a plurality of radial channels with the first microchannel as the intersection point, the radius of the first microchannel is greater than the radius of the second microchannel, the packaging shell can comprise a coolant inlet 14 and a coolant outlet 15, the coolant inlet is in communication with the first microchannel, and the coolant outlet is in communication with the second microchannel.

[0033] Based on the above structure in the embodiment of the present application, the packaging shell 201 and the packaging substrate 202 form a closed space, and the chip groups are located in the closed space, and then when the coolant is pumped into the closed space from the coolant inlet of the packaging shell, it flows into the first microchannel of the chip group, and then flows out from the radial second microchannel by the first microchannel, and then flows out from the coolant outlet of the packaging shell, the coolant can carry away the heat generated by the chip grains of the chip group during the working process through the above path, thereby achieving chip heat dissipation.

[0034] In the embodiment of the present application, the coolant flows from the middle position of the chip grain to the edge of the chip grain, which is shorter than the flow path of the parallel microchannel coolant flowing from one side to the other side on the chip grain, thereby effectively reducing the fluid resistance and achieving a higher heat transfer rate.

[0035] In practical applications, 3D stacking yield and cost control requirements also need to be considered when setting the chip. In practice, a mixed packaging method of 3D and 2D / 2.5D can be used, that is, the package can contain multiple groups of 3D stacked chips laid in a plane (multiple groups of 3D stacked chips are interconnected on the packaging substrate or Interposer in a 2D / 2.5D manner), so the heat dissipation design also needs to consider the actual packaging situation. The chip heat dissipation device in the embodiment of the present application can support 3D and 2D / 2.5D mixed stacking heat dissipation, that is, the chip group can be a single chip, or a 3D chip group composed of multiple chips, or a mixed stacking of 3D chip groups, for example, a mixed stacking of a 3D chip group composed of 6 chips and a 3D chip group composed of 4 chips. In the embodiment of the present application, each chip group is located on a 2D packaging substrate.

[0036] Referring to Figure 3 In the embodiment of the present application, a three-dimensional view, the package shell includes a coolant inlet and a coolant outlet, and the package shell covers the packaging substrate to form a closed space.

[0037] In an embodiment of the present application, the first microchannel of the non-bottom chip in each chip group is a central through channel, and the first microchannel of the bottom chip in each chip group is a central non-through channel. Thus, the cooling liquid can enter from the central through channel and flow out from the edge of the chip.

[0038] In an embodiment of the present application, in each chip group, the second microchannel of the chip can be angularly offset layer by layer.

[0039] In the embodiment of the present application, the microchannel length is significantly shortened, which can provide higher heat dissipation efficiency. The simplest radial straight microchannel structure can be used in the present application as an example, but in practical applications, other radial microchannel structure designs (such as a central spiral line) and different layer radial microchannels with layer-by-layer angular offset can also be used. For example, the first microchannel position of each layer of chips corresponds one-to-one, and the second microchannel position can be offset at a preset angle, which can be set according to actual requirements. Figure 4 FIG. 2 shows a three-dimensional stacking schematic diagram in an embodiment of the present application.

[0040] In an embodiment of the present application, the cross-sectional geometry of the second microchannel is any of the following shapes:

[0041] Rectangle, semicircle, triangle.

[0042] In practical applications, the first microchannel is located at the center position, and the channels of the second microchannel can be set according to actual needs. In the stacked core particles, a plurality of radial second microchannels made on the back surface of the core particle silicon wafer can be formed by deep reactive ion etching, wherein the depth and height dimensions are typically 100-200 um, and the cross-sectional geometry of the second microchannel can be rectangular, semicircular, triangular, etc. according to different manufacturing processes and technologies.

[0043] In an embodiment of the present application, the chip set heat dissipation device can further include a transistor, a metal winding and a through silicon via, and the positions of the transistor, the metal winding and the through silicon via are determined according to the positions of the first microchannel and the second microchannel.

[0044] In practical applications, in order to adapt to the heat dissipation design of the present application, the core particle needs to be improved as follows during the design of the front-end circuit:

[0045] (1) When there is a center through channel core particle (except for the bottommost core particle), the transistor placement (Place) and metal winding (Route) can be set to avoid the center channel hole area.

[0046] (2) The position of the TSV (Through-Silicon Via, through silicon via) can be placed to avoid the area where the microchannel channel is located.

[0047] In the design of microfluidic chips (Microfluidic Chip) or other similar devices, the position of the TSV (Through-Silicon Via, through silicon via) needs to be paid special attention, especially to avoid the area where the microchannel channel (Microchannel) is located. This is because the function and structure of TSV and microchannel may interfere with each other, affecting the performance and reliability of the device.

[0048] In practical applications, the TSV (Through-Silicon Via, through silicon via) is a vertical conductive channel through the silicon wafer, and the microchannel is a channel for fluid transmission. If the TSV is placed in the microchannel area, the manufacturing complexity will be increased, and the reliability will be reduced, so that the positions of the transistor, the metal winding and the through silicon via can be determined based on the positions of the first microchannel and the second microchannel.

[0049] In an embodiment of the present application, the first microchannel and the second microchannel are provided with a sealing ring.

[0050] In practical applications, the first microchannel and the second microchannel can isolate the fluid from the electrical interconnection by setting a sealing ring. Ensure the safety of the chip.

[0051] Reference Figure 5Figure 1 shows a cross-sectional view of a chiplet in an embodiment of the present application. The left side (a) shows a through-center channel, which is a first microchannel between non-bottom chiplets. The right side (b) shows a center channel that does not go through, which is a non-bottom chiplet. The chiplet can include a bonding layer, a substrate, and a back end of line (BEOL).

[0052] The bonding layer can be used to connect different chiplets or chiplets to a substrate, ensuring electrical and mechanical connections. Common techniques include micro bumps, hybrid bonding, etc.

[0053] The substrate can provide physical support and electrical connections for the chiplet. The material can be silicon, organic material, or ceramic, depending on the application requirements.

[0054] The back end of line is used to form interconnect structures and packaging after wafer fabrication is complete. It includes multilayer metal interconnects, dielectric layers, vias, etc., ensuring signal transmission within the chiplet and to other chiplets.

[0055] The back end of line (BEOL) is the main heat source, which includes transistor devices and multiple metal layers. Each metal layer (typically a few hundred nanometers thick) contains a large number of metal interconnects for signal transmission, surrounded by low-K insulating material to reduce parasitic capacitance between metal lines, thereby reducing signal transmission delay. Through-hole structures (Vias) filled with metal connect different metal layers in the vertical direction.

[0056] In an embodiment of the present application, the coolant inlet is connected to a guide channel, which is connected to the first microchannel.

[0057] In an embodiment of the present application, the second microchannel is connected to a chiplet edge channel, which is connected to the coolant outlet, so that the coolant flows out of the second microchannel and then enters the chiplet edge channel, and then flows out of the coolant outlet of the package shell.

[0058] In an embodiment of the present application, the chiplet cooling device uses single-phase or two-phase cooling.

[0059] In the field of chip cooling, from the perspective of the coolant, it can be divided into single-phase cooling and two-phase cooling technology. Single-phase cooling technology mainly relies on the heat conduction and convection of the liquid to absorb heat, and then transfers the heat of the cooled object to a heat exchanger or other device, and then dissipates the heat through external heat dissipation means. The cooling liquid remains in a liquid state throughout the process and does not undergo phase change. The heat capacity and thermal conductivity of the liquid are relatively high, which can achieve good cooling effect, but the heat dissipation efficiency is relatively low compared with two-phase cooling. Two-phase cooling uses the phase change between gas and liquid to achieve heat transfer. When the coolant absorbs heat, it changes from liquid to gas through boiling, and the gaseous coolant is transported to the cooling device and then reverts to liquid through heat dissipation, and then recirculates to the cooling part to continue to absorb heat. Due to the use of latent heat of phase change, the heat dissipation efficiency is very high, which is suitable for high-power density equipment cooling requirements. Considering the advantages of two-phase cooling technology in heat transfer principle and great potential, however, in the existing parallel microchannels, due to the small channel size and relatively long flow path, there are flow boiling instability (such as channel bubbles, etc.), which hinders its application in actual 3DIC heat sinks. In the embodiment of the present application, the flow path is shortened, so that single-phase or two-phase technology can be adapted to achieve rapid cooling of the chip.

[0060] In an embodiment of the present application, when the chip set cooling device adopts two-phase cooling, the coolant outlet is connected to the inlet of the condenser, and the outlet of the condenser is connected to the inlet of the coolant.

[0061] In practical applications, different coolants can be used for different cooling technologies. For example, a phase change coolant can be selected to perform two-phase phase change cooling technology in the chip cooling device, and then when the coolant enters the first microchannel and the second microchannel of the chip, it absorbs heat and changes from liquid to gas, and then flows out from the package shell outlet in the form of a liquid-gas mixture, enters the external condenser, and is converted into a liquid after being pumped into the shell coolant inlet.

[0062] Referring to Figure 6 , a schematic diagram of a heat dissipation device structure in an embodiment of the present application is shown. The chip cooling device can include a package shell, a package substrate, a chip set, a printed circuit board (PCB), a solder ball, an insulating filler, a bump, a sealing ring, and a cooling agent inlet and a cooling agent outlet on the shell, as shown in Figure 6As shown in the middle, two groups of chipsets are shown, which are stacked with 6 layers of core particles and 4 layers of core particles respectively. Among them, a through center hole (i.e. a first microchannel) is arranged in the middle of the core particles, and a radial microchannel with the center as the intersection point is arranged in the core particles. Then, the coolant is pumped into the through center hole from the coolant inlet, and then flows out from the edge of the core particles, and then flows out from the coolant outlet, that is, the coolant can flow in the direction indicated by the arrow in the figure.

[0063] Among them, the chip tin ball is a key component in integrated circuit packaging, mainly used for electrical and mechanical connection between the chip and the substrate. The material can be tin-lead alloy, lead-free solder, other alloys.

[0064] The insulating filler is a material used to fill the gap between the chip and the substrate, mainly used to enhance mechanical strength and reliability.

[0065] The bump is a micro connection point between the chip and the substrate, used for electrical and mechanical connection.

[0066] The sealing ring is an annular structure used to protect the internal structure of the chip from the external environment.

[0067] In practical applications, the insulating filler and the bump are usually used together. In flip-chip packaging, the bump provides electrical connection, and the insulating filler enhances mechanical reliability. The sealing ring and the insulating filler can jointly protect the internal structure of the chip, preventing failure caused by environmental factors. In high-density packaging (such as 3D IC), the three work together to ensure electrical performance, mechanical strength and long-term reliability.

[0068] In the embodiment of the present application, two types of core particles (center through channel, center non-through channel) can be combined to form a group of top center injection, multi-layer edge outflow of coolant fluid channels, effectively reducing the microchannel path length, bringing a series of advantages such as high heat dissipation efficiency and two-phase cooling friendly.

[0069] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0070] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device or computer program product. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0071] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more of the flowcharts and / or block diagrams. Figure 1 one or more of the flowcharts and / or block diagrams.

[0072] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowcharts and / or block diagrams. Figure 1 one or more of the flowcharts and / or block diagrams. Figure 1 one or more of the flowcharts and / or block diagrams.

[0073] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, such that a series of operational steps are carried out on the computer or other programmable terminal devices to produce a computer implemented process so that the instructions executed on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more of the flowcharts and / or block diagrams. Figure 1 one or more of the flowcharts and / or block diagrams.

[0074] Although preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to the described embodiments without departing from the inventive concepts disclosed in the present application. Accordingly, the appended claims are intended to cover all such modifications and variations as falling within the scope of the present application.

[0075] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying that there is any such actual relationship or order between these entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or terminal device including a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or terminal device. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or terminal device including the element.

[0076] The above provides a chip set heat dissipation device, and the principle and implementation manner of the present application are described by applying specific examples in the present application. The above example is only used to help understand the method and core idea of the present application. Meanwhile, for the general skilled in the art, the specific implementation manner and application range can be changed according to the idea of the present application. In summary, the content of the present application should not be understood as a limitation.

Claims

1. A chipset heat dissipation device, characterized in that, The chipset heat dissipation device includes: a package housing, a package substrate, and one or more chipsets. The chipsets are located on the package substrate and are situated within the space formed by the package housing and the package substrate. Each chipset includes one or more stacked chips. Each chipet has a first microchannel at its center for connecting adjacent chips, and multiple radial second microchannels intersecting at the first microchannel. The package housing includes a coolant inlet and a coolant outlet. The coolant inlet communicates with the first microchannel, and the coolant outlet communicates with the second microchannel.

2. The chipset heat dissipation device according to claim 1, characterized in that, In each chipset, the first microchannel of the non-bottom chip is the central through-channel, and the first microchannel of the bottom chip is the central non-through-channel.

3. The chipset heat dissipation device according to claim 1, characterized in that, The coolant inlet is connected to a guide channel, which is connected to the first microchannel.

4. The chipset heat dissipation device according to claim 1, characterized in that, The second microchannel is connected to the core edge channel, and the core edge channel is connected to the coolant outlet.

5. The chipset heat dissipation device according to claim 1, characterized in that, The first microchannel and the second microchannel are provided with sealing rings.

6. The chipset heat dissipation device according to claim 1, characterized in that, The chipset heat dissipation device adopts single-phase or dual-phase cooling.

7. The chipset heat dissipation device according to claim 1, characterized in that, When the chipset heat dissipation device adopts two-phase cooling, the coolant outlet is connected to the condenser inlet, and the condenser outlet is connected to the coolant inlet.

8. The chipset heat dissipation device according to claim 1, characterized in that, The second microchannel of the core particle is shifted at an angle layer by layer.

9. The chipset heat dissipation device according to claim 1, characterized in that, The cross-sectional geometry of the second microchannel can be any of the following shapes: Rectangle, semicircle, triangle.

10. The chipset heat dissipation device according to claim 1, characterized in that, The chipset heat dissipation device also includes transistors, metal wires, and through-silicon vias. The positions of the transistors, the metal wires, and the through-silicon vias are determined based on the positions of the first microchannel and the second microchannel.

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