Semiconductor packaging device and forming method thereof

Abstract

The invention provides a semiconductor packaging device and a forming method thereof. The semiconductor packaging device comprises a carrier plate; and a first wafer stack disposed on the carrier plate. The first wafer stack includes a first wafer in contact with the carrier plate and a second wafer disposed on the first wafer. The first wafer comprises a first through silicon lead hole arranged on the side wall of the first wafer, and the second wafer comprises a second through silicon lead hole arranged on the side wall of the second wafer. The semiconductor package device further includes a first conductive layer extending from a surface of the first through silicon lead hole to a surface of the second through silicon lead hole. The first conductive layer electrically connects the first wafer and the second wafer.

Description

Technical Field

[0001] This application relates to semiconductor packaging devices and methods for forming the same, and particularly to through-silicon vias (TSVs) and methods for forming them. Background Technology

[0002] To enable wafers to be stacked on top of each other and electrically connected, the back surface of the substrate is typically ground to expose through-silicon vias formed within the substrate. In the packaging process, when stacked wafers are bonded to a carrier substrate, the area occupied on the substrate can be saved (e.g., only the area of ​​dynamic random access memory is required), thus enabling packaged devices with higher functional density. However, these steps are costly and time-consuming. Therefore, several challenges remain to be overcome regarding semiconductor packaging devices and manufacturing technologies. Summary of the Invention

[0003] This application provides a semiconductor packaging apparatus, including: a carrier substrate and a first wafer stack disposed on the carrier substrate. The first wafer stack includes: a first wafer in contact with the carrier substrate and a second wafer disposed on the first wafer. The first wafer includes a first through-silicon via disposed on a sidewall of the first wafer, and the second wafer includes a second through-silicon via disposed on a sidewall of the second wafer. The semiconductor packaging apparatus further includes a first conductive layer extending from the surface of the first through-silicon via to the surface of the second through-silicon via. The first conductive layer electrically connects the first wafer and the second wafer.

[0004] This application provides a method for forming a semiconductor packaging device, including: providing a first wafer and providing a second wafer. The first wafer includes: a first substrate; a first seal ring structure and a second seal ring structure embedded within the first substrate; a plurality of first bonding pads disposed on the first substrate; and a first through-silicon via and a second through-silicon via embedded within the first substrate. The first seal ring structure laterally surrounds a first group of the first bonding pads, and the second seal ring structure laterally surrounds a second group of the first bonding pads. The first through-silicon via and the second through-silicon via are located outside the first seal ring structure and the second seal ring structure, respectively. The second wafer includes: a second substrate; a third seal ring structure and a fourth seal ring structure embedded within the second substrate; a plurality of second bonding pads disposed on the second substrate; the third through-silicon via and the fourth through-silicon via embedded within the second substrate; and a dielectric layer covering the second bonding pads. The third seal ring structure laterally surrounds a first group of the second bonding pads, and the fourth seal ring structure laterally surrounds a second group of the second bonding pads. The third and fourth through-silicon vias are located outside the third and fourth sealing ring structures, respectively. The method for forming a semiconductor packaging device further includes: performing a singulation process on a first wafer to form a first wafer and a second wafer, wherein the first and second through-silicon vias are exposed from the sidewalls of the first and second wafers, respectively; performing a singulation process on the second wafer to form a third wafer and a fourth wafer, wherein the third and fourth through-silicon vias are exposed from the sidewalls of the third and fourth wafers, respectively; sequentially stacking the first and third wafers on a carrier substrate; sequentially stacking the second and fourth wafers on the carrier substrate; forming a first conductive layer to electrically connect the first through-silicon via of the first wafer to the third through-silicon via of the third wafer; and forming a second conductive layer to electrically connect the second through-silicon via of the second wafer to the fourth through-silicon via of the fourth wafer. Attached Figure Description

[0005] Figures 1A-1B , Figures 2A-2B , Figures 3A-3D and Figures 4-11 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor packaging device, according to some embodiments of this application.

[0006] Glossary

[0007] 10,20: Wafers

[0008] 10A, 10B, 20A, 20B: Chips

[0009] 100: Base

[0010] 120: Sealing ring structure

[0011] 140: Through-silicon via

[0012] 220: Line Layer

[0013] 240: Solder pad

[0014] 300: Passivation layer

[0015] 400: Dielectric layer

[0016] 1000,1000': Semiconductor packaging device

[0017] 1000A, 1000B: Chip Stacking

[0018] 1100: Carrier board

[0019] 1200: Adhesive layer

[0020] 1220: Supporting structure

[0021] 1240: Adhesive layer

[0022] 1300, 1500: Conductive layer

[0023] 1400: Molded compound

[0024] 1450: Opening

[0025] 1600: Bump Structure

[0026] 1620: Column Structure

[0027] 1640: Welded ball

[0028] C: Cavity Detailed Implementation

[0029] This application illustrates an innovative design for a semiconductor packaging device using through-silicon vias (TSVs) combined with a conductive layer. Instead of placing the TSVs within the circuit area of ​​the wafer and combining them with bump structures and pads, the TSVs can be formed on the sidewalls of the wafer (i.e., outside the circuit area), eliminating the need for bump structures and pads. Since the wafer is formed through a single-crystallization process, the location of the TSVs corresponds to the dicing street / scribe line on the wafer. After vertical stacking of the wafers, conductive material can be grown on the exposed surface of the TSVs on the sidewalls of each wafer. As growth time increases, the conductive material expands vertically, allowing the conductive material on the TSVs of each wafer to interconnect, establishing an electrical connection between the upper and lower wafers. This improves the cost and cycle time of the semiconductor packaging device and enhances its performance.

[0030] Figures 1A-1B , Figures 2A-2B , Figures 3A-3D and Figures 4-8 This is a cross-sectional schematic diagram illustrating an intermediate stage in forming a semiconductor packaging device 1000, according to some embodiments of this application. The semiconductor packaging device 1000 may include a stack of wafers formed from different wafers. In this embodiment, only a portion of the circuit structure of the exemplary wafer is shown.

[0031] Reference Figures 1A-1B Initially, wafers 10 and 20 can be provided. The initial structure of wafers 10 and 20 includes a substrate 100, a sealing ring structure 120, a through-silicon via 140, a wiring layer 220, a solder pad 240, and a passivation layer 300. Compared to wafer 10, wafer 20 additionally includes a dielectric layer 400. Wafer 20 (or the wafer subsequently formed from wafer 20) is planned as the top component in the wafer stack of the semiconductor packaging device 1000.

[0032] The substrate 100 may be, for example, a wafer or a die, and may be a semiconductor-on-insulator (SOI) substrate. The SOI substrate may include a substrate, a buried oxide (BOX) layer disposed on the substrate, and a semiconductor layer disposed on the buried oxide layer. For example, the buried oxide layer may be silicon dioxide.

[0033] The substrate 100 may include isolation structures to define active regions and electrically isolate active region components within or above the substrate 100. Examples of isolation structures may include shallow trench isolation structures, deep trench isolation structures, or localized silicon oxide structures. Forming the isolation structure may include, for example, forming an insulating layer on the surface of the substrate 100, selectively etching the insulating layer and the substrate 100 to form trenches extending from the surface of the substrate 100 into the substrate 100, wherein the trenches are located between adjacent active regions. Next, forming the isolation structure may include growing a nitrogen-rich substrate (such as silicon oxynitride or other similar materials) along the trenches, and then filling the trenches with an insulating material (such as silicon dioxide, silicon nitride, silicon oxynitride, or other similar materials) using a deposition process. Subsequently, the insulating material in the trenches is annealed, and the substrate 100 is planarized to remove excess insulating material, making the insulating material in the trenches flush with the top surface of the substrate 100.

[0034] Refer to Figures 1A-1BA sealing ring structure 120 can be formed within the substrate 100 of wafers 10 and 20. From the top view, the sealing ring structure 120 is a continuous ring structure that laterally surrounds the circuit area to be subsequently single-crystallized into each wafer. The sealing ring structure 120 is disposed along the periphery of the predetermined circuit area of ​​the wafer and serves as a protective element to prevent chipping during the single-crystallization dicing process from extending into the circuit area of ​​the wafer. In other words, the sealing ring structure 120 is located between the predetermined dicing area and the predetermined circuit area of ​​the wafer. Since each subsequent wafer 10 and 20 will be single-crystallized into two wafers (detailed below), each wafer 10 and 20 includes two sealing ring structures 120. From the top view, the width of the sealing ring structure 120 can be between 4 μm and 6 μm, for example, 5 μm. Furthermore, the spacing between adjacent sealing ring structures 120 (i.e., the dicing size) can be between 80 μm and 150 μm.

[0035] The material of the sealing ring structure 120 may include amorphous silicon, polycrystalline silicon, poly-germanium, poly-SiGe, metal nitrides (such as titanium nitride, tantalum nitride, tungsten nitride, or titanium aluminum nitride), metals, other similar materials, combinations thereof, or multiple layers thereof.

[0036] Reference Figures 1A-1B Through-silicon vias 140 can be formed within the substrate 100 of wafers 10 and 20. The through-silicon via 140 can be located outside the continuous ring structure of the sealing ring structure 120. The through-silicon via 140 is provided in a dicing zone, rather than a circuit zone of the wafer. From a top view, the through-silicon via 140 can have any suitable geometry. For example, the through-silicon via 140 can be cylindrical. The horizontal dimension (e.g., diameter) of the through-silicon via 140 can be between 10 μm and 20 μm. The vertical dimension (e.g., height) of the through-silicon via 140 can be between 50 μm and 150 μm. The material and formation method of the through-silicon via 140 can be similar to those of the sealing ring structure 120; after forming a hole in the substrate 100 using a patterning process, copper can be used to fill the hole to form the through-silicon via 140.

[0037] According to some embodiments, the through-silicon via 140 can be disposed in the dicing zone. During single crystallization, a selective dicing process can be used to partially expose the through-silicon via 140. Since the dicing process is required anyway, no additional cost or cycle time is added. That is, after the wafer stacking is completed, the through-silicon via 140 on each wafer sidewall is vertically connected using a conductive layer (described in detail below). Therefore, the bump pads and bump structures originally in the circuitry zone of the wafer can be omitted, and an adhesive layer (described in detail below) is used for vertical connection between wafers. This configuration also frees up additional space in the circuitry zone of the wafer, allowing more components to be integrated into the wafer and increasing functional density. In addition, the additional bump structures disposed on the top surface of the wafer stack do not need to correspond to the position of the through-silicon via 140, so no additional interposer is required to bond to the printed circuit board.

[0038] Still refer to Figures 1A-1B A circuit layer 220 can be formed on the substrate 100 of wafers 10 and 20. The circuit layer 220 can extend laterally from the circuit predetermined area of ​​the wafer to the dicing predetermined area. The circuit layer 220 can electrically connect the through silicon via 140 to the subsequently formed bonding pad 240. The circuit layer 220 can traverse and cover the sealing ring structure 120 and can reach the through silicon via 140. The thickness of the circuit layer 220 can be between 1 μm and 3 μm. The material and formation method of the circuit layer 220 can be similar to those of the sealing ring structure 120, and the details are not repeated.

[0039] Reference Figures 1A-1B Bond pads 240 can be formed on the substrate 100 of wafers 10 and 20. Bond pads 240 can be arranged in a predetermined circuit area of ​​the wafer and can be situated on the circuit layer 220. A sealing ring structure 120 can be laterally positioned between the through-silicon via 140 and the bond pads 240. Bond pads 240 can serve as wire bonding for, for example, back-end of line (BEOL) processes. The circuit layer 220 can be vertically disposed between the substrate 100 and the bond pads 240, and the circuit layer 220 can extend from below the bond pads 240 to above the through-silicon via 140. Since wafers 10 and 20 each include two sealing ring structures 120, the bond pads 240 can be divided into two groups, each laterally surrounded by one of the two sealing ring structures 120. It should be understood that various active and / or passive components (as described above) can be formed in wafers 10 and 20, which are not shown for simplicity. The thickness of the solder pad 240 can be between 1 μm and 5 μm. Viewed from above, the horizontal dimensions of the solder pad 240 can be between 50 μm × 50 μm and 80 μm × 80 μm, for example, a design with 75 μm × 75 μm. The material and forming method of the solder pad 240 can be similar to those of the sealing ring structure 120.

[0040] Refer toFigures 1A-1B A passivation layer 300 can be formed on the substrate 100 of wafers 10 and 20. The passivation layer 300 can cover the substrate 100, the circuit layer 220, and the solder pads 240. The passivation layer 300 provides mechanical protection and electrical insulation to the underlying structure. The thickness of the passivation layer 300 can be between 1 μm and 2 μm. The material of the passivation layer 300 can include silicon oxide, silicon oxynitride, silicon carbonitride, tetraethoxysilane (TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phosphosilicate glass (BPSG), fused silica glass, phospho-silicate glass, boron-doped silicate glass, or other similar materials), low-dielectric-constant dielectric materials, or other suitable dielectric materials. After planarization, the solder pads 240 can be flush with the top surface of the passivation layer 300.

[0041] Reference Figures 1A-1B A dielectric layer 400 can be formed on the passivation layer 300 of wafer 20. As previously mentioned, in order to connect the wafer stack to other components (such as printed circuit boards), a bump structure 1600 (described in detail below) needs to be provided on the top surface of the wafer stack. The dielectric layer 400 can serve as a redistribution layer (RDL) or an interlayer dielectric (ILD) connecting the bonding pad 240 and the bump structure 1600. As described above, wafer 20 (or the wafer subsequently formed from wafer 20) is planned as the topmost component in the wafer stack of the semiconductor packaging device 1000, therefore wafer 20 needs to additionally include a dielectric layer 400. The thickness of the dielectric layer 400 can be between 1 μm and 2 μm. The material of the dielectric layer 400 can include silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxynitride carbide, polyimide, or other suitable dielectric materials. The method for forming dielectric layer 400 is similar to that for passivation layer 300.

[0042] Reference Figures 2A-2B The substrate 100 of wafers 10 and 20 can be thinned. Depending on the application and design requirements, the substrate 100 can be thinned from its back side to the desired thickness, for example, exposing the lower surface of the through-silicon via 140. The substrate 100 of wafers 10 and 20 can be thinned using Taiko grinding, non-Taiko grinding, or other similar methods. After thinning, an etching process can be performed to give the ground back side of the substrate 100 a flatter surface.

[0043] Reference Figures 3A-3D The thinned wafers 10 and 20 can be subjected to a single-crystallization process. This process can be performed using blade sawing, die break dicing, laser dicing, plasma dicing, stealth dicing, or other similar methods. For stealth dicing, multiple holes can be drilled along the dicing path, and then the wafer is expanded to break the wafer at the holes. A mask can be used in conjunction with plasma dicing for single-crystallization. Because plasma dicing is selective, it can cut the material (e.g., silicon) of the substrate 100 within a predetermined dicing path area without substantially damaging the material (e.g., copper) of the through-silicon via 140. Using a mask further ensures the precision of the single-crystallization process, exposing the cylindrical portion of the through-silicon via 140 away from the sealing ring structure 120, while the cylindrical portion of the through-silicon via 140 near the sealing ring structure 120 remains covered by the material of the substrate 100.

[0044] In some embodiments, wafer 10 is single-crystallized into wafers 10A and 10B, and wafer 20 is single-crystallized into wafers 20A and 20B. Each of wafers 10A, 10B, 20A, and 20B includes a substrate 100, a sealing ring structure 120 laterally surrounding a circuit region of the wafer within the substrate 100, through-silicon vias 140 on both sides outside the sealing ring structure 120, a circuit layer 220 extending from within the sealing ring structure 120 to outside the sealing ring structure 120 on the substrate 100, bonding pads 240 on the circuit layer 220, and a passivation layer 300 covering the circuit layer 220 and the bonding pads 240. Furthermore, each of wafers 20A and 20B additionally includes a dielectric layer 400 on the passivation layer 300. Through-silicon vias 140 are located on the sidewalls of each of wafers 10A, 10B, 20A, and 20B, eliminating the need for bump pads and bump structures, thereby improving the cost and cycle time of semiconductor packaging devices and enhancing their performance.

[0045] Reference Figure 4A carrier board 1100 can be provided, and wafers 10A, 10B, 20A, and 20B can be stacked on the carrier board 1100. Wafers 10A and 20A can be sequentially stacked on the carrier board 1100 to form a wafer stack 1000A, and wafers 10B and 20B can be sequentially stacked on the carrier board 1100 to form a wafer stack 1000B. Although wafer stacks 1000A and 1000B are illustrated with two wafers each, any number of wafer stacks can be mounted on the carrier board 1100, and each wafer stack can have any number of wafers, as long as the topmost wafer in each stack is additionally provided with a dielectric layer 400. According to some embodiments, an adhesive layer 1200 replaces conventional bump pads and bump structures. The adhesive layer 1200 can be used to attach wafer 10A of wafer stack 1000A and wafer 10B of wafer stack 1000B to the surface of the carrier substrate 1100, and the adhesive layer 1200 can also be used to attach wafer 20A of wafer stack 1000A and wafer 20B of wafer stack 1000B to the top surfaces of wafer 10A and wafer 10B, respectively. Compared to bump pads and bump structures, using the adhesive layer 1200 simplifies the process. The adhesive layer 1200 includes a support structure 1220 and an adhesive layer 1240.

[0046] Refer to Figure 4 The carrier 1100 may include an insulating material without any circuitry. The carrier 1100 is used solely for mounting wafer stacks 1000A and 1000B. The carrier 1100 may be a laminate. For example, the carrier 1100 may include multiple metal layers and multiple dielectric layers arranged in an alternating configuration, and has wire holes through the dielectric layers coupling the individual metal layers, allowing its lower surface to be electrically connected to other components. The thickness of the carrier 1100 may be between 50 μm and 200 μm.

[0047] Reference Figure 4The adhesive layer 1200 can be vertically located between the carrier 1100 and wafer 10A, between the carrier 1100 and wafer 10B, between wafer 10A and wafer 20A, and between wafer 10B and wafer 20B. The support structure 1220 of the adhesive layer 1200 may include spacer paste, and the adhesive layer 1240 of the adhesive layer 1200 may include die attach film (DAF). The support structure 1220 of the adhesive layer 1200 supports and maintains the space between the carrier 1100 and the wafer or between wafers, while the adhesive layer 1240 of the adhesive layer 1200 ensures adhesion between the carrier 1100 and the wafer or between wafers. In other words, the adhesive layer 1200 ensures that wafers 10A, 10B, 20A, and 20B all have a uniform height. If the adhesive layer 1200 does not include the support structure 1220, the stacked wafers can easily develop height differences. The material of the support structure 1220 of the adhesive layer 1200 may include glass fiber, silica, other similar materials, or combinations thereof. The material of the adhesive layer 1240 of the adhesive layer 1200 may include epoxy resin, a hardener, other similar materials, or combinations thereof. The adhesive layer 1200 may be formed by dispensing or spin-on coating.

[0048] Reference Figure 5 A conductive layer 1300 is formed on the exposed surface of the through-silicon via 140 on each sidewall of wafers 10A, 10B, 20A, and 20B. The conductive layer 1300 can extend continuously in the vertical direction. Therefore, the conductive layer 1300 can extend from the exposed surface of the through-silicon via 140 of wafer 10A to the exposed surface of the through-silicon via 140 of wafer 20A, and the conductive layer 1300 can extend from the exposed surface of the through-silicon via 140 of wafer 10B to the exposed surface of the through-silicon via 140 of wafer 20B. The conductive layer 1300 can electrically connect wafers 10A and 20A in wafer stack 1000A, and electrically connect wafers 10B and 20B in wafer stack 1000B. Alternatively, the conductive layer 1300 can be considered as wire bonding, attaching to the exposed surfaces of the through-silicon vias 140 on the upper and lower sidewalls of the wafer stack. The thickness of the conductive layer 1300 can be between 10 μm and 20 μm. The material and formation method of the conductive layer 1300 can be similar to those of the sealing ring structure 120, and the conductive layer 1300 can be formed using nickel-palladium-gold or nickel-gold by electroless plating. Because nickel has good corrosion resistance, it can serve as a protective layer to enhance the corrosion resistance of gold.

[0049] According to some embodiments of this application, the exposed surface of the through-silicon via 140 can be used as a dielectric (including copper) to perform chemical substitution (i.e., redox reaction) to grow nickel-palladium-gold or nickel-gold. Contrary to common understanding, the semiconductor packaging device 1000 of this application intentionally allows the metal materials on the through-silicon vias 140 of the upper and lower wafers to contact each other, enabling the wafer stack to conduct electricity and establish an electrical connection. Because the through-silicon vias 140 are located on the sidewalls of wafers 10A, 10B, 20A, and 20B, the relatively low precision and reliability of the deposited metal layer will not affect the performance of the semiconductor packaging device 1000.

[0050] To allow the conductive layer 1300 to expand more effectively in the vertical direction, the upper and lower surfaces of each through-silicon via 140 can be fully exposed. Therefore, the metallic material of the conductive layer 1300 can expand upwards and downwards from the upper and lower surfaces of the through-silicon vias 140, respectively. Furthermore, to prevent the metallic material of the conductive layer 1300 from accidentally growing on the exposed metal surfaces of the pads 240, it is necessary to ensure that the pads 240 of the intermediate wafers in wafer stacks 1000A and 1000B are covered by the adhesive layer 1200, and that the pads 240 of the topmost wafers in wafer stacks 1000A and 1000B are covered by the dielectric layer 400. After the conductive layer 1300 is formed, cavities C can be defined between wafers 10A and 20A, and between wafers 10B and 20B. In other embodiments, the growth of the conductive layer 1300 may completely fill the cavities C.

[0051] Reference Figure 6A molding compound 1400 can be formed on a carrier substrate 1100. The molding compound 1400 covers wafer stacks 1000A and 1000B and fills cavities C (if present). It should be understood that the structures of wafer stacks 1000A and 1000B are inherently fragile. The molding compound 1400 protects wafer stacks 1000A and 1000B from mechanical stress, facilitating subsequent operations. Furthermore, the top surface of the dielectric layer 400 can be exposed by a planarization process (e.g., chemical mechanical polishing). After the planarization process, the dielectric layer 400 can be flush with the top surface of the molding compound 1400, and the molding compound 1400 can laterally surround wafer stacks 1000A and 1000B (including wafers 10A, 10B, 20A, and 20B). The molding compound 1400 can be formed using hot pressing, compression, or injection methods. The height of the molding compound 1400 can be between 0.5 mm and 1.5 mm. Generally, the material of the molding compound 1400 can be a plastic compound, which may include epoxy resin, phenolic curing agents, silicone, catalysts, pigments, or mold release agents.

[0052] Reference Figure 7 Bump structures 1600 can be formed on wafer stacks 1000A and 1000B. The bump structures 1600 extend through the dielectric layer 400. According to some embodiments, the bump structures 1600 can be used to connect the semiconductor package device 1000 to other components (such as a printed circuit board). The bump structures 1600 can be connected to solder pads 240 via the dielectric layer 400. It should be understood that the number of bump structures 1600 is independent of the number of solder pads 240. Although only one bump structure 1600 is shown on each of wafer stacks 1000A and 1000B, this embodiment is not limited thereto. For example, any number of bump structures 1600 can be provided on wafer stacks 1000A and 1000B. The horizontal dimensions of the bump structures 1600 can be between 80μm × 80μm and 400μm × 400μm, for example, a design of 250μm × 250μm. The bump structure 1600 may include column structure 1620 and welded ball 1640.

[0053] In some embodiments, a pillar structure 1620 may be formed through the dielectric layer 400 and may reside on the passivation layer 300. The pillar structure 1620 may be connected to the solder pads 240 via the dielectric layer 400. The pillar structure 1620 may be a conductive component connecting the wafer stack 1000A / wafer stack 1000B to the subsequently formed solder balls 1640. From the top view, the pillar structure 1620 may be formed in any suitable geometry. Due to application or design requirements, the pillar structure 1620 may have straight or sloping sidewalls. The material of the pillar structure 1620 may include any suitable metal or alloy described above, such as copper, copper-nickel-gold alloys, other similar materials, or combinations thereof. The pillar structure 1620 may be formed by any suitable process (such as electroplating or other similar methods).

[0054] Solder balls 1640 can be disposed on the pillar structure 1620. The solder balls 1640 can be used to connect the semiconductor package device 1000 to other components (such as printed circuit boards). The material of the solder balls 1640 may include any suitable metals mentioned above, such as tin, gold, silver, lead, other similar materials, combinations thereof, or alloys thereof. The solder balls 1640 can be thermally bonded to the pillar structure 1620 using an adhesive bonding machine, followed by a reflow soldering process.

[0055] Reference Figure 8 The semiconductor packaging device 1000 can undergo a single-crystallization process. Wafer stack 1000A and wafer stack 1000B can be separated by any of the aforementioned suitable processes (not limited to selective plasma dicing). Each packaged wafer after single-crystallization has a single wafer stack. Alignment detection methods can be used to ensure that the dicing streets / marks set during single-crystallization avoid critical components of the semiconductor packaging device 1000, such as wafer stacks 1000A and 1000B. In embodiments using dicing streets, the width of the dicing streets can be between 80 μm and 100 μm.

[0056] The single-crystallized wafer stacks 1000A and 1000B can be used for subsequent processes. It should be understood that suitable packaging processes can be performed before or after single-crystallization. Suitable types of packaging processes include wafer-level chip scale package (WLCSP), transistor outline (TO), small outline integrated circuit (SOIC), quadflat package (QFP), dual flat non-leaded (DFN), quad flat non-leaded (QFN), and ball grid array (BGA).

[0057] Figures 9-11 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor package 1000' according to some embodiments. Compared to the semiconductor package 1000, the semiconductor package 1000' includes forming a conductive layer 1500 in a molding compound 1400. The features of the wafer stack 1000A (including wafer 10A and wafer 20A), wafer stack 1000B (including wafer 10B and wafer 20B), carrier 1100, adhesive layer 1200 (including support structure 1220 and adhesive layer 1240), conductive layer 1300, molding compound 1400, and bump structure 1600 (including pillar structure 1620 and solder ball 1640) are similar to... Figure 8 The features shown are similar.

[0058] Reference Figure 9 Compared to Figure 6 An opening 1450 can be further formed in the molding compound 1400. For simplicity, this is omitted. Figures 1A-1B , Figures 2A-2B , Figures 3A-3D and Figures 4-5 The steps are as follows. Opening 1450 can be filled by conductive layer 1500 in subsequent fabrication processes. It should be understood that conductive layer 1500 needs to be in physical contact with conductive layer 1300. Therefore, opening 1450 can penetrate the entire molding compound 1400 to expose the surface of carrier plate 1100, thereby ensuring that conductive layer 1500 can effectively make physical contact with conductive layer 1300. The horizontal dimension of opening 1450 can be between 60 μm and 150 μm. To ensure physical contact between conductive layer 1500 and conductive layer 1300, opening 1450 needs to expose conductive layer 1300 without significantly damaging conductive layer 1300. Therefore, it can be used with... Figures 3A-3DThe same selective plasma segmentation is used in conjunction with a mask to ensure the accuracy of the opening 1450's location. In other words, the opening 1450 cuts through the material of the molding compound 1400 (e.g., EMC (Epoxy Molding Compound)) without substantially damaging the material of the conductive layer 1300 (e.g., nickel-palladium-gold or nickel-gold). More specifically, the portion of the conductive layer 1300 away from the through-silicon via 140 is exposed, while the portion of the conductive layer 1300 near the through-silicon via 140 remains covered by the molding compound 1400.

[0059] Reference Figure 10 A conductive layer 1500 can be formed in the opening 1450. Alternatively, the conductive layer 1500 can be formed through the molding compound 1400. The conductive layer 1500 physically contacts the conductive layer 1300. The configuration of the conductive layer 1500 further enhances the electrical connection between wafer 10A and wafer 20A, and between wafer 10B and wafer 20B. As previously mentioned, the selective growth of the electroless plating used in the conductive layer 1300 is less controllable, and therefore the thickness of the conductive layer 1300 may be too large or too small. If the thickness of the conductive layer 1300 is too small, it will cause excessive impedance of the semiconductor package during operation. Therefore, the conductive layer 1500 can improve the potential impedance of the semiconductor package during operation. Since the conductive layer 1500 can cover the overall outline of the opening 1450, the size of the conductive layer 1500 can be similar to the size of the opening 1450. The material and formation method of the conductive layer 1500 can be similar to those of the sealing ring structure 120, and the details will not be repeated here. The conductive layer 1500 can also be made of silver paste. The deposition of metallic materials and the deposition of silver paste can have different throughputs. Filling the opening 1450 with silver paste requires less processing time compared to using metallic materials. Furthermore, planarization processes (such as chemical mechanical polishing) can be performed to make the molding compound 1400 flush with the top surface of the conductive layer 1500.

[0060] Reference Figure 11 Compared to Figure 8 The semiconductor packaging device 1000' can undergo a single-crystalization process to disconnect wafer stack 1000A from wafer stack 1000B. (For simplicity, details are omitted.) Figure 7 The steps involve scribe lines. Alignment detection methods can be used to ensure that the scribe lines / cuts during single-crystallization avoid critical components of the semiconductor packaging device 1000', such as wafer stacks 1000A and 1000B. In embodiments using scribe lines, the width of the scribe lines can be between 80 μm and 100 μm. The single-crystallized wafer stacks 1000A and 1000B can then be used for subsequent processes. Any suitable packaging process described above can be performed before or after single-crystallization.

[0061] This application discloses a semiconductor packaging device that includes an innovative design of through-silicon vias (TSVs) combined with a conductive layer. Traditional fabrication processes place TSVs within the circuitry of a wafer and couple them to bump structures on the upper surface and bump pads on the lower surface. Because the bumping process easily causes warping of the thinned substrate, the wafer must first be bonded to glass, which is then detached. The connection between the bump structure and bump pads, as well as the use of glass, increases the overall cost and timeframe of the fabrication process. This application's semiconductor packaging device forms TSVs on the sidewalls of the wafer, eliminating the need for bump structures and bump pads. This frees up circuitry space on the wafer, allowing more components to be integrated, thereby increasing functional density. When TSVs are positioned on the sidewalls of the wafer, conductive material can be grown on the surface of each TSV. As growth time increases, the conductive material expands vertically, allowing the conductive material on each TSV to interconnect, thus establishing an electrical connection between the upper and lower wafers. It can improve the cost and cycle time of semiconductor packaging devices, and enhance the performance of semiconductor packaging devices.

[0062] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Based on the embodiments of this application, other processes and structures can be designed or modified to achieve the same purpose or advantages as the embodiments described herein. Various changes, substitutions, and replacements can be made without departing from the spirit and scope of this application.

Claims

1. A semiconductor packaging device, characterized in that, include: One carrier board; A first wafer stack, disposed on the carrier board, includes: A first wafer, in contact with the carrier substrate, wherein the first wafer includes a first through-silicon via disposed on a sidewall of the first wafer; and A second wafer, disposed on the first wafer, wherein the second wafer includes a second through-silicon via disposed on a sidewall of the second wafer; and A first conductive layer extends from the surface of the first through-silicon via to the surface of the second through-silicon via, wherein the first conductive layer electrically connects the first wafer and the second wafer.

2. The semiconductor packaging apparatus as claimed in claim 1, characterized in that, The first chip further includes: One base; Multiple solder pads are disposed on the substrate; A sealing ring structure is embedded in the substrate, wherein the sealing ring structure is laterally located between the first through-silicon via and the bonding pad; and A circuit layer is disposed between the substrate and the pad, wherein the circuit layer extends from below the pad to above the first through-silicon via, and wherein the circuit layer covers the sealing ring structure.

3. The semiconductor packaging apparatus as claimed in claim 1, characterized in that, The second wafer is attached to the first wafer using an adhesive layer.

4. The semiconductor packaging apparatus as claimed in claim 1, characterized in that, Including: A molding compound, disposed on the carrier plate and laterally surrounding the first wafer stack; and A second conductive layer is disposed through the molding compound and in physical contact with the first conductive layer.

5. The semiconductor packaging apparatus as claimed in claim 1, characterized in that, It also includes a bump structure disposed on the top surface of the second wafer.

6. A method for forming a semiconductor packaging device, characterized in that, include: Provide a first wafer, comprising: A first base; A first sealing ring structure and a second sealing ring structure are embedded in the first substrate; A plurality of first solder pads are disposed on the first substrate, wherein a first sealing ring structure laterally surrounds a first group of the first solder pads, and a second sealing ring structure laterally surrounds a second group of the first solder pads; and A first through silicon lead hole and a second through silicon lead hole are embedded in the first substrate, wherein the first through silicon lead hole and the second through silicon lead hole are located outside the first sealing ring structure and the second sealing ring structure, respectively; Provide a second wafer, comprising: A second basement; A third sealing ring structure and a fourth sealing ring structure are embedded in the second substrate; A plurality of second solder pads are disposed on the second substrate, wherein a third sealing ring structure laterally surrounds a first group of the second solder pads, and a fourth sealing ring structure laterally surrounds a second group of the second solder pads; A third through-silicon via and a fourth through-silicon via are embedded in the second substrate, wherein the third through-silicon via and the fourth through-silicon via are located outside the third sealing ring structure and the fourth sealing ring structure, respectively; and A dielectric layer covers the second solder pad; The first wafer is subjected to a single crystallization process to form a first wafer and a second wafer, wherein the first through-silicon via and the second through-silicon via are exposed from the sidewall of the first wafer and the sidewall of the second wafer, respectively. The second wafer is subjected to a single crystallization process to form a third wafer and a fourth wafer, wherein the third through-silicon via and the fourth through-silicon via are exposed from the sidewall of the third wafer and the sidewall of the fourth wafer, respectively. The first wafer and the third wafer are stacked sequentially on a carrier plate; The second wafer and the fourth wafer are stacked sequentially on the carrier plate; A first conductive layer is formed to electrically connect the first through-silicon via of the first wafer to the third through-silicon via of the third wafer; and A second conductive layer is formed to electrically connect the second through-silicon via of the second wafer to the fourth through-silicon via of the fourth wafer.

7. The method for forming a semiconductor packaging apparatus as described in claim 6, characterized in that, The first conductive layer is extended vertically from the first through-silicon via to the third through-silicon via by electroless electroplating, and the second conductive layer is extended vertically from the second through-silicon via to the fourth through-silicon via.

8. The method for forming a semiconductor packaging apparatus as described in claim 6, characterized in that, It further includes forming an adhesive layer between the first wafer and the third wafer, and between the second wafer and the fourth wafer.

9. The method for forming a semiconductor packaging apparatus as described in claim 6, characterized in that, Including: A molding compound is formed on the carrier and laterally surrounds the first wafer, the second wafer, the third wafer, and the fourth wafer; Multiple openings are formed through the molding compound, wherein the openings expose the first conductive layer and the second conductive layer; and A third conductive layer and a fourth conductive layer are filled into the opening to physically contact the first conductive layer and the second conductive layer, respectively.

10. The method for forming a semiconductor packaging apparatus as claimed in claim 6, characterized in that, Furthermore, before performing a single-crystallization process on the first wafer and the second wafer, the first substrate of the first wafer and the second substrate of the second wafer are thinned, wherein the first through-silicon via and the second through-silicon via are exposed from the bottom surface of the thinned first substrate, and the third through-silicon via and the fourth through-silicon via are exposed from the bottom surface of the thinned second substrate.

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