Semiconductor package

Abstract

A semiconductor package (10) comprises an encapsulant (11), the encapsulant (11) comprising a peripheral side wall (11.1) having at least one recess (11.2) therein, where the recess (11.2) comprises an inner bottom surface (11.2 A) and a side surface (11.2 B) extending between the inner bottom surface (11.2 A) and an outer surface (11.1 A) of the peripheral side wall (11.1) of the encapsulant (11), and where the recess (11.2) comprises a side surface (11.2 B) extending between the inner bottom surface (11.2 A) and the outer surface (11.1 A) of the peripheral side wall (11.1) of the encapsulant (11). At least one lead (12) extends from the inner bottom surface (11.2 A) into the recess (11.2), the lead (12) being spaced apart from the side wall (11.2 B) of the recess (11.2).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor package, a method of manufacturing thereof, a semiconductor device module, and a system comprising the semiconductor package. BACKGROUND

[0002] Power density is an important driver for the industry. Related to this are performance, size, and reliability. Different packaging solutions are manifold and have to meet the needs of specific applications.

[0003] In the past years, a number of activities have been performed regarding embedding of passive components and active semiconductor dies into a printed circuit board, PCB, or other packaging carrier system. Some low voltage use cases have found their way into production as embedding offers additional value compared to module or discrete packaging solutions, such as tightness (power density), short lead length, good thermal management, and significantly improved power cycling capability. These benefits are also seen as attractive for power applications with high voltages up to 1200 V and especially for fast switching applications greater than 30 kHz.

[0004] Due to the short lead length, semiconductor chips embedded in a PCB are accompanied by excellent cooling capability and very low parasitic inductance. This allows high power density and efficiency in system design. Especially for fast switching devices such as SiC MOS, GaN, IGBT and diodes, CoolMOS and SFET, this advantage is used to achieve outstanding performance.

[0005] In particular, a package with embedded power semiconductor chips can generate a considerable amount of heat during operation. This can limit reliability and performance. Efficient removal of heat from the package can be achieved by a heat sink or the like. At the same time, electrical reliability of the package is required.

[0006] For these and other reasons, the present disclosure is needed. SUMMARY

[0007] In particular, high voltage applications such as electric vehicles, electric vehicle charging, uninterruptible power supplies, and the like require dedicated designs to enable use in environments of high electric fields and high temperatures. The present disclosure for chip embedding provides a solution for such high voltage use cases.

[0008] A first aspect of the present disclosure relates to a semiconductor package comprising an enclosure comprising a peripheral sidewall having at least one recess therein, wherein the recess comprises an inner bottom surface and a side surface extending between the inner bottom surface and an outer surface of the peripheral sidewall of the enclosure, and wherein at least one lead extends from the inner bottom surface into the recess, the lead being spaced apart from the side surface of the recess.

[0009] A second aspect of the present disclosure relates to a method of manufacturing a semiconductor package, the method comprising: providing a leadframe comprising a die pad and a plurality of leads; attaching a semiconductor transistor die to the die pad; applying an encapsulant to the leadframe and the semiconductor transistor die such that the encapsulant comprises a peripheral sidewall having at least one recess therein, wherein the peripheral sidewall comprises an outer surface transverse to the recess, an inner surface at a bottom of the recess, and a side surface between the outer surface and the inner surface, wherein the encapsulant is applied such that at least one lead of the plurality of leads extends from the inner surface into the recess, the lead being spaced apart from the side surface of the recess; and cutting an outer end of the lead.

[0010] A third aspect of the present disclosure relates to a semiconductor device module, the semiconductor device module comprising a package carrier comprising an opening, wherein a semiconductor package according to the first aspect is arranged in the opening.

[0011] A fourth aspect of the present disclosure relates to a semiconductor package comprising an encapsulant, the encapsulant comprising: a first surface and a second surface opposite the first surface; and a sloped peripheral sidewall connecting the first surface and the second surface; wherein the sloped peripheral sidewall comprises a corner portion, wherein the corner portion is rounded, preferably with a radius not less than 0.8 mm. This aspect is compatible with all preceding aspects and all embodiments thereof.

[0012] A fifth aspect of the present disclosure relates to a method of manufacturing a semiconductor package, the method comprising: providing a leadframe comprising a die pad and a plurality of leads; attaching a semiconductor transistor die to the die pad; providing an encapsulant to the leadframe and the semiconductor transistor die such that the encapsulant comprises a sloped peripheral sidewall; and providing the encapsulant such that the sloped peripheral sidewall comprises a corner portion, wherein the corner portion is rounded with a radius not less than 0.8 mm. This aspect is compatible with all preceding aspects and all embodiments thereof.

[0013] A sixth aspect of this disclosure relates to a semiconductor package comprising: an encapsulation; a lead frame including die pads and a plurality of leads; the die pads having a first main surface and a second main surface opposite to the first main surface, wherein the second main surface of the die pads is exposed to the outside of the package on a lower surface of the encapsulation; a plurality of via pads, wherein the via pads are exposed from an upper surface of the encapsulation and embedded in the encapsulation; wherein the ratio of the lateral extension of the second main surface of the die pads in a direction between the via pads exposed on the lower surface of the encapsulation to the distance between the via pads on the upper surface of the encapsulation is at most 0.55. This aspect is compatible with all the foregoing aspects and all embodiments thereof.

[0014] A seventh aspect of this disclosure relates to a system comprising: a semiconductor package of any of the foregoing aspects (and embodiments thereof); a core layer having a cavity, wherein the semiconductor package is embedded in the cavity; a first material layer comprising pre-impregnated fibers covering a lower surface of the core layer and contacting a lower surface of the semiconductor package; and a second material layer comprising pre-impregnated fibers covering an upper surface of the core layer opposite to the lower surface of the core layer and contacting the upper surface of the semiconductor package, wherein the core layer is a printed circuit board (PCB).

[0015] Those skilled in the art will recognize the additional features and advantages after reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0016] The present disclosure is shown in the accompanying drawings by way of example and not by way of limitation, wherein similar reference numerals refer to similar or identical elements. The elements in the drawings are not necessarily drawn to scale relative to each other. Features of the various illustrated examples can be combined unless they are mutually exclusive.

[0017] Figure 1 A top view of a semiconductor package is shown, and a magnified view of the recess and the leads contained therein is shown in the marked circles.

[0018] Figures 2A-2C It shows Figure 1 The semiconductor package is shown in the following views: bottom view (A), top perspective view (B), and bottom perspective view (C).

[0019] Figure 3 It shows Figure 1 A top view of the lead frame design for a semiconductor package.

[0020] Figure 4 It shows including Figure 1 A cross-sectional side view of a semiconductor device module in a semiconductor package.

[0021] Figure 5 Another embodiment of the disclosure is shown from a top side perspective.

[0022] Figure 6 A side view of an embodiment of Figure 5 and Figure 6 is shown.

[0023] Figure 7 An embodiment of Figure 5 is shown from a bottom side perspective. DETAILED DESCRIPTION

[0024] The embodiments described herein provide the following.

[0025] An embodiment of the semiconductor package according to the first aspect, no lead extends beyond the outer surface of the side wall of the encapsulation. In particular, the outer surface of the lead is coplanar with or retracted from the plane of the outer surface of the encapsulation.

[0026] An embodiment of the semiconductor package according to the first aspect, the semiconductor package comprises a plurality of recesses, each recess containing at least one lead, and the shape of each of the recesses and the leads contained therein is similar to at least one recess and the leads contained therein. A recess containing two or more leads can be provided. This will be shown in detail in the embodiments below.

[0027] An embodiment of the semiconductor package according to the first aspect, the semiconductor package comprises a plurality of recesses, wherein the recesses are located in opposite side walls of the encapsulation.

[0028] An embodiment of the semiconductor package according to the first aspect, the semiconductor package further comprises a semiconductor transistor die comprising a drain terminal, a source terminal, a gate terminal, and optionally, a source / sense terminal. In particular, it can be provided that, in a first side wall of the encapsulation, a recess is arranged comprising leads connected to the source terminal (source lead), the gate terminal (gate lead), and optionally, the source / sense terminal (source / sense lead), and in a second side wall of the encapsulation opposite the first side wall, at least one recess is arranged comprising at least one lead connected to the drain terminal (drain lead). This will be shown in detail in the embodiments below.

[0029] An embodiment of the semiconductor package according to the first aspect, two source leads are arranged in two different recesses.

[0030] An embodiment of the semiconductor package according to the first aspect, two drain leads are arranged in two different recesses.

[0031] An embodiment of the semiconductor package according to the first aspect, the gate lead and the source / sense lead are arranged in one common recess.

[0032] According to an embodiment of the semiconductor package of the first aspect, the semiconductor package further comprises a plurality of via pads, wherein the drain lead is connected with a first via pad, the source lead is connected with a second via pad, the gate lead is connected with a third via pad, and the source / sense lead is connected with a fourth via pad. The via pads can be embedded in the encapsulation and exposed from an upper surface of the encapsulation.

[0033] According to an embodiment of the semiconductor package of the first aspect, the semiconductor package further comprises a lead frame comprising a die pad and leads. According to a further embodiment thereof, the semiconductor transistor die is arranged on a first main face of the die pad, wherein a second main face of the die pad opposite to the first main face is exposed to the outside. This can be exploited on the customer side by applying the semiconductor package to a heat sink for efficient heat dissipation. This will be shown in detail in the embodiments below.

[0034] According to an embodiment of the semiconductor package of the first aspect, the semiconductor transistor die comprises one or more of the following: a vertical semiconductor transistor die, a semiconductor power transistor die, an IGBT die, a MOSFET die, a JFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die or a GaN transistor die.

[0035] According to an embodiment of the method of the second aspect, the outer ends of the leads are cut such that no lead extends beyond an outer surface of the package side wall. In particular, the cutting can be performed such that an outer surface of the leads is coplanar with or is set back from a plane of an outer surface of the encapsulation.

[0036] According to an embodiment of the method of the second aspect, the cutting of the outer ends of the leads is performed by one of punching, sawing or laser cutting.

[0037] According to an embodiment of the method of the second aspect, the encapsulation is applied such that one main face of the die pad is exposed to the outside.

[0038] According to an embodiment of the semiconductor device module of the third aspect, the package carrier is a printed circuit board, in particular comprising a core layer of FR3 or FR4 material. On both sides of the core layer, a lamination layer can be applied which fills the space between the side of the opening of the semiconductor package and the core layer.

[0039] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure can be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0040] It is to be understood that features of the various example embodiments described herein can be combined with each other, unless specifically noted otherwise.

[0041] As employed in this specification, the terms "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" do not mean that the elements or layers must be in direct contact with each other; intervening elements or layers can be disposed between the elements that are "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled," respectively. However, according to the present disclosure, the aforementioned terms can optionally also have the specific meaning that the elements or layers are in direct contact with each other, i.e., that intervening elements or layers are not respectively disposed between the elements that are "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled."

[0042] Further, the word "over" used in relation to a part, element or material layer that forms or is located "over" a surface can be used herein to mean that the part, element or material layer is indirectly located (e.g., placed, formed, deposited, etc.) on the implied surface with one or more additional parts, elements or layers arranged between the implied surface and the part, element or material layer. However, the word "over" used in relation to a part, element or material layer that forms or is located "over" a surface can optionally also have the specific meaning that the part, element or material layer is directly located (e.g., placed, formed, deposited, etc.) on the implied surface (e.g., in direct contact with the implied surface).

[0043] Examples of semiconductor packages can use various types of transistor devices. Examples can use vertical transistor devices, where those structures can be provided in a form in which at least one electrical contact element is arranged on a first main face of a semiconductor die and at least one other electrical contact element is arranged on a second main face opposite to the main face of the semiconductor die, such as MOS transistor structures or IGBT (insulated gate bipolar transistor) structures.

[0044] According to embodiments of the semiconductor package, the semiconductor transistor die is a semiconductor power transistor die. Here, the term "power semiconductor transistor die" can refer to a semiconductor die that provides at least one of a high voltage blocking or a high current carrying capability. The power semiconductor die can be configured for high currents with maximum current values of several amperes, such as for example 10 A, 250 A, 600 A, 1000 A, or maximum current values of up to or even exceeding 1000 A. Similarly, voltages associated with such current values can have values of several volts to several tens or hundreds or even thousands of volts, with voltage values of 1200 V and 1700 V / 2000 V / 3.3 kV and higher being of significance.

[0045] Examples of the semiconductor package can include an encapsulant or an encapsulation material in which the semiconductor transistor die and the semiconductor driver die are embedded. The encapsulation material can be any electrically insulating material, such as any kind of molding material, any kind of resin material, or any kind of epoxy resin material. The encapsulation material can also be a polymeric material, a polyimide material, a thermoplastic material, a silicone material, a ceramic material, and a glass material. The encapsulation material can also include any of the above materials and further include a filler material embedded therein, such as a thermally conductive additive, such as thermally conductive particles made of, for example, AIO, BNi, AlNi, SiN, diamond, any other thermally conductive particle, or a non-thermally conductive filler, such as SiO, SiO2, glass, or the like.

[0046] Figure 1 A top view of the semiconductor package is shown, and an enlarged view of the recess and the lead contained therein is shown in the marked circle.

[0047] More specifically, Figure 1 A semiconductor package 10 is shown that includes an encapsulant 11 that includes a peripheral sidewall 11.1 that includes a plurality of recesses 11.2, 11.3, 11.4, and 11.5 therein. The first recess 11.2 includes an inner bottom surface 11.2A and a side surface 11.2B that extends between the inner bottom surface 11.2A and an outer surface 11.1A of the peripheral sidewall 11.1 of the encapsulant 11. A first lead 12 extends into the recess 11.2 from the inner bottom surface 11.2A, the first lead 12 being spaced apart from the sidewall 11.2B of the first recess 11.2. The other recesses 11.3, 11.4, and 11.5 are formed in a similar manner as the first recess 11.2.

[0048] The semiconductor package 10 of the present embodiments includes a semiconductor transistor die 20 and a semiconductor driver die 30 that are embedded in an encapsulant 11. The semiconductor transistor die 20 is a power semiconductor transistor die that is configured for high currents with maximum current values of several amperes, such as for example 10 A, 250 A, 600 A, 1000 A, or maximum current values of up to or even exceeding 1000 A. Similarly, voltages associated with such current values can have values of several volts to several tens or hundreds or even thousands of volts, with voltage values of 1200 V and 1700 V / 2000 V / 3.3 kV and higher being of significance. Figure 1A power semiconductor, in particular an IGBT die, comprising a source contact, a drain contact, a gate contact, and a source / sense contact. The source contact is connected with a source lead, the gate contact is connected with a gate lead, and the source / sense contact is connected with a source / sense lead. The recesses 11.2, 11.3, 11.4, and 11.5 and the respective leads 12 to 17 contained therein are arranged in opposite upper and lower side walls of the encapsulation 11.

[0049] As Figure 1 indicated, the upper side wall comprises a first recess 11.2 and a second recess 11.3 and the respective first drain lead 12 and second drain lead 13 contained therein. The second recess 11.3 and the second drain lead 13 are configured in the same way as the first recess 11.2 and the first drain lead 12. The first drain lead 12 and the second drain lead 13 are connected with the first via pad 5. As Figure 1 indicated, the lower side wall comprises a third recess 11.4 and a fourth recess 11.5 within the dashed line limits. The third recess 11.4 comprises a first source lead 14. The fourth recess 11.5 comprises a second source lead 15, a gate lead 16, and a source / sense lead 17. Here is given a configuration in which the source / sense lead 17 is spaced apart from the left side wall of the fourth recess 11.5, the gate lead 16 and the source / sense lead 17 are spaced apart from each other, and the second source lead 15 is spaced apart from the right side wall of the fourth recess 11.5. The first source lead 14 and the second source lead 15 are connected with the second via pad 6. The gate lead 16 is connected with the third via pad 7, and the source / sense lead 17 is connected with the fourth via pad 8. The via pads 5 to 8 enable contact through vias. When using via pads, the number of leads to the via pads can be increased, and the main current can flow via the via pads.

[0050] It is noted that in all first to fourth recesses 11.2 to 11.5, the outer surface of the respective lead 12 to 17 is set back from the plane of the outer surface 11.1A of the encapsulation 11. Alternatively, the outer surface of the lead can also be coplanar with the plane of the outer surface of the encapsulation. Both alternatives are good prerequisites for chip embedding.

[0051] In Figure 1 the embodiment shown, the leads connected to the source contact, the gate contact, and optionally the source / sense contact can be arranged in the same recess (11.5). Within the recess (11.5), the leads can be distributed evenly. However, the leads can also be distributed unevenly, i.e. grouped together. For example, the gate contact can be grouped together with the source / sense contact. Both contacts can be spaced apart from the source contact, but still arranged in the same recess.

[0052] As will be shown later, the semiconductor transistor die is mounted with its drain contact to the die pad of the leadframe, and the die pad is connected with the first drain lead 12 and the second drain lead 13.

[0053] It should also be noted that the semiconductor package 10 comprises a rounded edge, in particular with a radius R = 0.25 / 0.5 / 1.0 / 2.0 / 4.0 mm. This has also proven to be advantageous for the chip-inlay. The reason for the rounding is a milling process which creates a cavity in the core material during the PCB process.

[0054] Figures 2A-2C Fig. 1 shows a top view (A), a top perspective view (B) and a bottom perspective view (C) of a semiconductor package according to the present application. Figure 1

[0055] More specifically, Figure 2A Fig. 2 shows a back surface of the die pad 21.1 of the leadframe exposed on the main back surface of the semiconductor package 10. It allows mounting a heat sink on the customer side, which will be shown in more detail in Figure 4 Fig. 3. The lowermost edge of the die pad has a significant larger distance to the lowermost edge of the semiconductor package 10 in order to avoid or at least minimize a creepage or even a short circuit current between the source contact and the drain contact.

[0056] Figure 2B Fig. 4 shows a cross-sectional view of the semiconductor package 10 according to the present application. Figure 2C Fig. 5 shows a cross-sectional view of the semiconductor package 10 according to the present application for illustrating further details of the semiconductor package 10. A possible feature is that the sidewall 11.1A of the encapsulation 11 can be beveled to facilitate the insertion of the semiconductor package 10 into an opening of a PCB during the manufacturing of the semiconductor module. The beveling is performed in such a way that the area of the lower side with the drain pads is slightly smaller than the area of the upper side with the source pads. As can be seen in Fig. 6, the beveling results in a triangular shape of the side surface in the recess 12-17. It is also possible to perform the beveling in such a way that the shape of the side surface is trapezoidal or polygonal, which will be described in further detail below. Figure 2B

[0057] The openings 18.1 and 18.2 are so-called mold ears and are created by the molding process and do not need to be explained further here.

[0058] Figure 3 Fig. 7 shows a top view of the leadframe design of the semiconductor package according to the present application. Figure 1

[0059] More specifically, Figure 3 Fig. 8 shows a top view of the leadframe design of the semiconductor package according to the present application. Figure 1 Figures 2A-2C ​​​​semiconductor package, but this time the encapsulant is omitted, giving a free view of the semiconductor transistor die and leadframe design. The leadframe 20 of the semiconductor package 10 comprises the die pad 21.1 and the leads 12 to 17, which correspond to the leads 12 to 17 as shown in Figure 1 The semiconductor transistor die 22 comprises an upper surface with a source pad 22.1, a gate pad 22.2, and a source / sense pad 22.3. A plurality of wire loops 24 connect the source pad 22.1 with an upper metal layer, which in turn is connected with the source leads 14 and 15. Details thereof are shown in the semiconductor device module as shown in Figure 4

[0060] It should be noted that instead of wire loops 24, other front side connectors can also be used. In particular, a plurality of metal pillars, e.g. of copper, can be used to connect the source pad with the upper metal layer.

[0061] The embodiments described so far have shown the following configuration: where the source contact is provided on the upper main surface of the semiconductor transistor die and the drain contact is provided on the lower main surface of the semiconductor transistor die. It should be noted that this configuration can also be reversed, with the drain contact on the upper surface and the source contact on the lower surface, an arrangement referred to as "source down".

[0062] Figure 4 A cross-sectional side view of a semiconductor device module is shown comprising Figure 1 a semiconductor package.

[0063] More specifically, the semiconductor device module 100 as shown in Figure 4 comprises a printed circuit board (PCB) 110, which essentially consists of a core layer comprising an opening 111, wherein a semiconductor package 10, such as shown and described in the previous embodiments, is provided in the opening 111. The core layer of the PCB 110 can be made of, e.g., FR3 or FR4 material. Instead of a PCB, other types of packaging carriers can also be used.

[0064] In the illustration of Figure 4 the down-set portions 21.2 and 21.3 of the leadframe 21 are also shown, which lead from the level of the die pad 21.1 and the level of the conductive wires connecting the source and gate contacts to the via pads 5 to 8, which have been shown and described in connection with Figure 1 and Figures 2A-2C

[0065] ​​The semiconductor device module can further comprise a lamination layer 112 on the upper side of the core layer 112, which also fills the gap between the sidewall of the semiconductor package 10 and the sidewall of the opening 111 of the core layer after application.

[0066] On the customer side, the arrangement consisting of the semiconductor package and the PCB can be connected to a suitable heat sink 115 via a thermally conductive layer 113, typically a TIM layer (thermal interface layer) and a further metal layer, in particular made of copper.

[0067] The semiconductor device module can further be designed as a power inlay, i.e. such that it can be inserted into and connected with another device. Such other device can for example be any kind of substrate or PCB.

[0068] Figures 1-3 and Figure 5 A semiconductor package 10 according to the fourth aspect of the present disclosure is shown. The semiconductor package 10 comprises an encapsulation 11. The encapsulation 11 comprises a first surface 11.6 and a second surface 11.7. The second surface 11.7 can also be referred to as back surface. The first surface 11.6 is arranged opposite to the second surface 11.7. The peripheral sidewall 11.1 of the package can be beveled, i.e. chamfered, and can comprise a rounded corner portion 11.1B. The radius of the corner portion 11.1B can be not less than 0.8 mm. A radius of at least 0.8 mm enables the package to be inserted into a recess of a substrate which also has a rounded corner (see also Figure 4 ), wherein the rounded corner portion of the recess in the substrate can be obtained by mechanical machining using a tool with a radius of not less than 0.8 mm. Due to the rounded corner portion 11.1B of the package 10, it is easy to insert the semiconductor package 10 into the corresponding mechanically machined recess in the substrate.

[0069] The radius of the corner portion 11.1B can also be in the range between 0.8 mm and 1.6 mm. The larger the radius, the better the manufacturability of the corresponding recess in the substrate by mechanical machining, i.e. by using a larger mechanical machining tool.

[0070] It is to be noted that any aspect and embodiment described in the following with reference to the figures is considered to be compatible with any of the preceding aspects and embodiments.

[0071] Figure 6 With regard to the preceding figures, in particular Figures 1-3 and Figure 5Side view of the described embodiment. The peripheral sidewall 11.1, and in particular its outer surface 11.1A, has a first inclined portion 501 and a second inclined portion 502. The first inclined portion 501 can have a first inclination, and the second inclined portion 502 can have a second inclination different from the first inclination. The first and second inclined portions form an apex 503 at the upper surface 11.1A of the peripheral sidewall 11.1. The apex 503 can be at a parting line of 500 pm, which corresponds to the thickness of the leadframe. In this embodiment, the cross-section of the recess with the two inclined portions can be polygonal.

[0072] The inclination of the inclined portions 501, 502 relative to a line perpendicular to the upper surface of the package 10 can be at most 4°. The encapsulant 11 can form a package body. Keeping the inclination as low as possible can be advantageous to reduce the dead space between the surface of the peripheral sidewall of the package body and the respective sidewall of the recess of the substrate in which the package 10 can be embedded.

[0073] The second inclined portion 502 can be larger than the first inclined portion 501. That is, the second inclined portion 502 can have a longer extension along the surface of the peripheral sidewall than the first inclined portion 501. Thus, the apex 503 can be closer to the first surface 11.6 of the encapsulant 11 than to the second surface 11.7 of the encapsulant 11. The second inclined portion 502 can be connected to the second surface 11.7, and the first inclined portion can be connected to the first surface 11.6. The second inclined portion 502 can be connected to the first inclined portion 501 at the apex 503 formed thereby.

[0074] In embodiments compatible with all the foregoing and described embodiments, the thickness (a) of the package body corresponds to the distance between the first surface 11.6 and the second surface 11.7 of the encapsulant, as shown in Figure 6 As shown in Figure 5 The lateral extension (b) of the package body corresponds to the total distance between the portions of the peripheral sidewalls opposite each other where the recesses with leads are arranged. The package body can have a rectangular footprint with a longer side and a shorter side. Typically, the peripheral sidewalls where the recesses with leads are arranged are located on the shorter side, and are spaced apart from each other by the longer side. Thus, the lateral extension referred to herein typically refers to the extension of the longer side of the rectangular footprint of the package body.

[0075] In embodiments, the ratio (b) / (a) between the lateral extension (b) and the thickness (a) of the package body is between 9.0 and 9.5. In particular, the ratio can be 9.19.

[0076] Figures 1-6A semiconductor package is shown that is manufactured according to a method comprising: providing a leadframe comprising a die pad and a plurality of leads, attaching a semiconductor transistor die to the die pad, providing an encapsulant to the leadframe and the semiconductor transistor die such that the encapsulant comprises a sloped peripheral sidewall, providing the encapsulant such that the sloped peripheral sidewall comprises a corner portion, wherein the corner portion is rounded with a radius that is not less than 0.8 mm.

[0077] Figure 5 、 6 and 7 show embodiments of a semiconductor package according to the sixth aspect of the disclosure. The semiconductor package 10 comprises an encapsulant 11 and a leadframe 20. The leadframe comprises a die pad 21 and a plurality of leads 12-17. The die pad has a first major face and a second major face opposite to the first major face. The second major face of the die pad 21 can be exposed to the outside of the package at a lower surface 11.7 of the encapsulant 11. The semiconductor package can further comprise a plurality of via pads 5, 6, 7, 8. The via pads 5, 6, 7, 8 can be exposed at an upper surface 11.6 of the encapsulant 11 and can be embedded in the encapsulant 11.

[0078] The ratio (c) / (d) of the lateral extension (c) of the second major face 21.1 of the die pad in a direction between the via pads exposed at the upper surface 11.6 of the encapsulant and the distance (d) between the via pads at the upper surface 11.6 of the encapsulant can be at most 0.55. This ratio represents or can be interpreted as a measure for the lateral extension of the die pad inside the encapsulant 11. At the above ratio, the die pad 20 and the exposed portion of the die pad 21.1 have their maximum lateral extension and thus their maximum capability to transfer heat from the semiconductor chip inside the encapsulant 11 via the die pad to the outside of the package 10. This is also shown in Figure 4 .

[0079] The exposed second major face of the die pad 21.1 can be configured to fit to a heat sink 115 as exemplarily shown in Figure 4 . The heat sink 115 can be any other device capable of receiving heat via the exposed second major face of the die pad 21.1. The heat sink 115 can be suitable for liquid cooling and can be part of an external cooling system. Alternatively, the exposed second major face 21.1 of the die pad 20 can be configured to be attached to a thermal via (not shown). This can be the case in particular in configurations where the package 10 is embedded in another substrate 110 and needs to be contacted by another encapsulating upper and / or lower layer.

[0080] In embodiments of the semiconductor package 10 of any of the preceding embodiments or aspects, the exposed via pads 5, 6, 7, 8 can be configured to be connected to thermal and / or electrical vias 116 as shown in Figure 4 .

[0081] like Figure 5 , Figure 7 , Figure 1 , Figure 2C and Figure 3 As shown, the lateral dimensions of via pads 5, 6, 7, and 8 can be between 0.62 mm and 0.7 mm. In this configuration, vias can be attached along the via pads in a staggered (i.e., zigzag) arrangement.

[0082] Exposed via pads, leads, and exposed die pads can be coated with an adhesion promoter. Examples of possible adhesion promoters include A2, acrylic resins, chromates, titanates, and silanes. Using an adhesion promoter can significantly improve the bonding between the exposed metal surfaces of the package and the auxiliary components, thereby ensuring a strong and durable bond.

[0083] Furthermore, to improve the bonding strength of the semiconductor package in the embedded state, the molding compound (i.e., the encapsulant 11) may have a surface roughness of at least 5 μm. The embedded state can be a state in which the semiconductor package is inserted into and sealed within a substrate, such as... Figure 4 As illustrated in the example, the surface roughness can be in the range of 5 μm to 10 μm.

[0084] Figure 4 It shows including Figures 1-3 and Figures 5-7 A cross-sectional side view of a semiconductor device module in a semiconductor package. In addition to the aspects already described. Figure 4 A system for a semiconductor package 10, which may include any of the foregoing embodiments and aspects of this disclosure, is illustrated. The system includes a core layer 110. The core layer 110 may have a cavity in which the semiconductor package 10 is embedded. The core layer 110, together with the semiconductor package 10, may be covered by a first material layer 113 comprising pre-impregnated fibers, i.e., composed of a pre-impregnated material. The first material layer 113 may cover the lower surface of the core layer and contact the lower surface 11.7 of the semiconductor package 10. A second material layer 112, comprising pre-impregnated fibers, may cover the upper surface of the core layer 110. The upper surface of the core layer 110 may be opposite the lower surface of the core layer 110. The second material layer 112, i.e., a second pre-impregnated material, may contact the upper surface 11.6 of the semiconductor package 10. The core layer 110 may be a printed circuit board (PCB).

[0085] During embedding, i.e. the manufacturing process of the system, the semiconductor package is inserted into the recess of the core layer 110. The lower surface of the core layer 110 and the lower surface of the package are covered with the first material layer 113, i.e. with the first prepreg material. The upper surface of the core layer 110 and the upper surface of the package are then covered with the second material layer 112, i.e. with the second prepreg material. In a pressing step, pressure can be applied to the first material layer 113 and the second material layer 112. In this pressing step, the resin stored in the prepreg material layers is pressed out and penetrates into possible gaps between the peripheral side walls of the package and the corresponding peripheral side walls of the core layer 110, i.e. the side walls of the recess. Thereby, the space between the side walls of the package and the core layer is filled with resin. Due to the slight inclination of the peripheral side surface of the package 10 and the apex, dead zones without filled resin, i.e. spaces between the side walls of the package and the core layer, are reduced. After a possible curing step, vias 116 can be provided through the second material layer 112 to contact the via pads.

[0086] Furthermore, although particular features or aspects of embodiments of the disclosure can have been disclosed in only one of the several embodiments, such features or aspects can be combined with one or more other features or aspects of other embodiments, as to an applicant can be desirous and advantageous for any given or particular application. Still further, the use of the terms "including", "containing", "comprising", "having" or other variations such terms in the detailed description or in any claims is not intended to exclude any components, features, structures, or methodologies not expressly recited. Furthermore, it is to be understood that embodiments of the disclosure can be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits, or programmatic devices. Also, the term "exemplary" is merely meant to mean an example, not the best or optimal. It should be further understood that the features and / or elements depicted in the figures are shown with particular dimensions for the sake of simplicity and ease of understanding and that actual dimensions can differ substantially from those depicted in the figures.

[0087] Although specific embodiments have been shown and described herein, it is understood that a variety of alternatives and / or equivalents exist for the particular embodiments shown and described herein and that the present disclosure is intended to cover any alternatives or modifications as is within the scope of the claims. The application is intended to encompass any modifications or variations of the specific embodiments discussed herein. Accordingly, the disclosure is intended to be limited only by the scope of the claims and their equivalents.

[0088] Although specific examples have been shown and described herein, it will be understood that a variety of alternatives and / or equivalents exist for the particular examples shown and described herein and that the present disclosure is intended to cover any alternatives or modifications as is within the scope of the claims. The application is intended to encompass any modifications or variations of the specific examples discussed herein. Accordingly, the present disclosure is intended to be limited only by the scope of the claims and their equivalents.

[0089] It should be noted that the methods and apparatus outlined in this document, including preferred embodiments thereof, can be used independently or in combination with other methods and apparatus disclosed in this document. Further, features outlined in the context of the apparatus are applicable to corresponding methods, and vice versa. Moreover, all aspects of the methods and apparatus outlined in this document can be combined in any combination. In particular, features of the claims can be combined in any manner.

[0090] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the application and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in this document have the purpose of illustrating the principles of the proposed methods and systems only and are not intended to limit the scope of the application to such specific examples and embodiments. Furthermore, all statements as to the manner of exercising the application, as well as those with respect to its particular examples, are intended to encompass equivalents thereof.

Claims

1. A semiconductor package (10), comprising: Encapsulation (11), including a peripheral sidewall (11.1) having at least one recess (11.2) therein, The recess (11.2) includes an inner bottom surface (11.2A) and a side surface (11.2B) extending between the inner bottom surface (11.2A) and the outer surface (11.1A) of the peripheral sidewall (11.1) of the encapsulation (11), and At least one lead (12) extends from the inner bottom surface (11.2A) into the recess (11.2), and the lead (12) is spaced apart from the side surface (11.2B) of the recess (11.2).

2. The semiconductor package (10) according to claim 1, in, No lead (12) extends beyond the outer surface (11.1A) of the peripheral sidewall (11.1) of the encapsulation (11).

3. The semiconductor package (10) according to claim 1 or 2, in, The outer surface of the lead (12) is coplanar with the outer surface of the outer surface of the outer peripheral sidewall (11.1) of the encapsulation (11), or is retracted from the outer surface of the outer peripheral sidewall (11.1) of the encapsulation (11).

4. The semiconductor package (10) according to any one of the preceding claims further includes: Multiple recesses (11.2, 11.3, 11.4, 11.5), each recess containing at least one lead (12, 13, 14, 15, 16, 17), and each of the recesses and the lead has a shape similar to the at least one recess (11.2) and the lead (12) contained therein.

5. The semiconductor package (10) according to any one of the preceding claims, in, The recesses (11.2, 11.3, 11.4, 11.5) are arranged in the opposite sidewalls of the encapsulation (11).

6. The semiconductor package (10) according to any one of the preceding claims further includes: A semiconductor transistor die (22), the semiconductor transistor die (22) comprising: Drain contact, Source contact (22.1), Gate contact (22.2), and Optionally, source / sensing contact (22.3).

7. The semiconductor package (10) according to claim 5 or 6, in, In the first sidewall of the encapsulation (11), recesses (11.4, 11.5) are arranged, the recesses (11.4, 11.5) including leads (14, 15, 16, 17) connected to the source contact, the gate contact, and optionally the source / sensing contact, and At least one recess (11.2, 11.3) is arranged in the second sidewall of the encapsulation (11) opposite to the first sidewall, the at least one recess (11.2, 11.3) including leads (12, 13) connected to the drain contact; wherein the leads connected to the source contact, the gate contact, and optionally the source / sensing contact are arranged in the same recess (11.5).

8. The semiconductor package (10) according to any one of the preceding claims further comprises: The lead frame (20) includes a die pad (21) and the leads (12-17).

9. The semiconductor package (10) according to claim 7 or 8, in, The semiconductor transistor die (22) is disposed on the first main surface of the die pad (21). The second main surface of the die pad (21) opposite to the first main surface is exposed to the outside.

10. The semiconductor package (10) according to any one of the preceding claims further includes a plurality of via pads (5, 6, 7, 8). in, The drain leads (12, 13) are connected to the first via pad (5). The source leads (14, 15) are connected to the second via pad (6). The gate lead (16) is connected to the third via pad (7), and The source / sensor lead (17) is connected to the fourth via pad (8).

11. The semiconductor package (10) according to claim 10, in, The via pads (5, 6, 7, 8) are embedded in the encapsulation (11) and exposed from the upper surface of the encapsulation (11).

12. The semiconductor package (10) according to any one of claims 6-11, in, The semiconductor transistor die (22) includes one or more of the following: vertical semiconductor transistor die, semiconductor power transistor die, IGBT die, MOSFET die, JFET die, CoolMOS die, wide bandgap semiconductor transistor die, especially SiC transistor die or GaN transistor die.

13. A method for manufacturing a semiconductor package, the method comprising: Provides a lead frame that includes die pads and multiple leads; Attach the semiconductor transistor die to the die pad; An encapsulation is applied to the lead frame and the semiconductor transistor die such that the encapsulation includes a peripheral sidewall having at least one recess therein. The peripheral sidewall includes an outer surface transverse to the recess, an inner surface at the bottom of the recess, and a side surface between the outer surface and the inner surface. Wherein, the encapsulation is applied such that at least one of the plurality of leads extends from the inner surface into the recess, the lead being spaced apart from the side surface of the recess; and Cut the outer end of the lead wire.

14. The method according to claim 13, in, Cut the outer end so that no lead wire extends beyond the outer surface of the peripheral sidewall.

15. The method according to claim 13 or 14, in, Cut the outer end so that the outer surface of the lead retracts from the plane of the outer surface of the encapsulation.

16. The method according to any one of claims 13 to 15, in, The outer end of the lead is cut by one of stamping, sawing or laser cutting.

17. The method according to any one of claims 13-16, in, The encapsulation is applied such that one main surface of the die pad is exposed to the outside.

18. A semiconductor device module (100), comprising: The encapsulation carrier (110) includes an opening (111). Wherein, the semiconductor package (10) according to any one of the preceding claims is disposed in the opening (111).

19. The semiconductor device module (100) according to claim 18, in, The packaging carrier (110) is a printed circuit board.

20. The semiconductor device module (100) according to claim 18 or 19, in, The module is designed to be inserted into another device, particularly a substrate or PCB.

21. A semiconductor package (10), comprising: Encapsulation (11), comprising: A first surface (11.6) and a second surface (11.7) opposite to the first surface (11.6); and An inclined peripheral sidewall (11.1) connecting the first surface and the second surface; The inclined outer sidewall (11.1) includes a corner portion (11.1B), wherein the corner portion (11.1B) is rounded and preferably has a radius of not less than 0.8 mm.

22. The semiconductor package of claim 21, wherein, The semiconductor package is the semiconductor package according to any one of claims 1-12.

23. The semiconductor package (10) according to claim 21 or 22, wherein, The inclined outer sidewall (11.1) includes a first inclined portion (501) with a first inclination and a second inclined portion (502) with a second inclination.

24. The semiconductor package of claim 23, wherein, The first inclined portion (501) and the second inclined portion (502) form a vertex (503) at the outer sidewall (11.1).

25. The semiconductor package according to claim 22 or 23, wherein, The tilt angle of each of the tilted portions is at most 4°.

26. The semiconductor package according to claim 24 or 25, wherein, The second inclined portion (502) is larger than the first inclined portion (501), and wherein the vertex (503) is closer to the first surface (11.6) of the encapsulation (11) than to the second surface (11.7) of the encapsulation (11), and wherein the second inclined portion (502) is connected to the second surface (11.7) of the encapsulation (11).

27. The semiconductor package (10) according to any one of claims 21-26, wherein, The radius of the corner portion (11.1B) is in the range of 0.8 mm to 1.6 mm.

28. The semiconductor package (10) according to any one of claims 21-27, wherein, The encapsulation (11) forms an encapsulation body, wherein the thickness of the encapsulation body corresponds to the distance between the first surface (11.6) and the second surface (11.7) of the encapsulation (11), and wherein the lateral extension of the encapsulation body corresponds to the total distance between the opposing sidewalls of the recesses in which the leads are arranged, and wherein the ratio between the lateral extension and the thickness of the encapsulation body is between 9.0 and 9.5, preferably 9.

19.

29. A method for manufacturing a semiconductor package, the method comprising: Provides a lead frame that includes die pads and multiple leads; Attach the semiconductor transistor die to the die pad; An encapsulation is provided to the lead frame and the semiconductor transistor die, such that the encapsulation includes inclined peripheral sidewalls; The encapsulation is provided such that the inclined outer sidewall includes a corner portion, wherein the corner portion is rounded to have a radius of not less than 0.8 mm.

30. A semiconductor package (10), comprising: Encapsulation material (11); A lead frame (20) includes a die pad (21) and multiple leads (12-17), the die pad having a first main surface and a second main surface (21.1) opposite to the first main surface, wherein the second main surface of the die pad (21) is exposed to the outside of the package on the lower surface (11.7) of the encapsulant (11); Multiple via pads (5, 6, 7, 8), wherein the via pads (5, 6, 7, 8) are exposed from the upper surface (11.6) of the encapsulation (11) and embedded in the encapsulation (11); The ratio of the lateral extension of the second main surface of the die pad in the direction between the via pads exposed on the lower surface of the encapsulation to the distance between the via pads on the upper surface of the encapsulation is at most 0.

55.

31. The semiconductor package of claim 30, wherein, The exposed second main surface of the die pad is configured to fit into a heat sink.

32. The semiconductor package according to any one of claims 30-31, wherein, The exposed via pads are configured to connect to thermal and / or electrical vias.

33. The semiconductor package according to any one of claims 30-32, wherein, The leads, exposed via pads, and exposed die pads are covered with an adhesion promoter, preferably A2.

34. The semiconductor package according to any one of claims 30-33, wherein, The encapsulant (11) has a surface roughness of at least 5 μm, preferably between 5 μm and 10 μm.

35. A system comprising: The semiconductor package according to any one of claims 1-12, 21-28 or 30-34; A core layer (110) having a cavity, wherein the semiconductor package (10) is embedded in the cavity; A first material layer (113) including pre-impregnated fibers covers the lower surface of the core layer and contacts the lower surface (11.7) of the semiconductor package (10); A second material layer (112) including pre-impregnated fibers covers the upper surface of the core layer opposite to the lower surface of the core layer and contacts the upper surface (11.6) of the semiconductor package, wherein the core layer is a printed circuit board (PCB).

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