Semiconductor device
By introducing separate upper and lower electrode structures in the IGBT device and adjusting the resistance connection, the problem of electromagnetic noise suppression during high-speed switching of the IGBT device is solved, thereby reducing the peak value of Ic and increasing the switching speed.
Patent Information
- Application Number
- CN202510084550.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-16
- Filing Date
- 2025-01-20
- Publication Date
- 2025-11-18
AI Technical Summary
Existing IGBT devices have difficulty effectively suppressing electromagnetic noise during high-speed switching, especially due to the increased Ic peak value caused by the large ratio of gate-collector capacitance to gate-emitter capacitance.
In an IGBT device, an upper and lower electrode structure is introduced, which is separated by an intermediate insulating film. Resistors are connected between the upper and lower electrodes to control their respective gate capacitances. The thickness and layout of the electrodes are adjusted to reduce the gate-emitter capacitance of the lower electrode and increase its charging speed.
It effectively reduces electromagnetic noise in IGBT devices, lowers Ic peak value, extends gate oxide life, and improves switching speed.
Smart Images
Figure CN120977995A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor devices. Background Technology
[0002] Increasing the switching speed is effective in reducing switching losses in Insulated Gate Bipolar Transistors (IGBTs). A challenge in achieving higher speeds is the generation of electromagnetic noise. It has been reported that noise is related to the peak value of Ic at low current (e.g., see Non-Patent Literature 1). The peak value of Ic depends on the overshoot of the gate voltage Vge at turn-on; the larger the displacement current (Idis = Cgc × dV / dt), the smaller Cge, and the greater the increase in Vge. Here, Cgc is the gate-collector capacitance, and Cge is the gate-emitter capacitance. Therefore, to suppress electromagnetic noise, it is necessary to reduce the Cgc / Cge ratio.
[0003] Non-patent document 1: K.Nishi, T.Takahashi, and A.Narazaki, 'Analysis the complex tradeoff among Eon-VCEsat-SCSOAand EMI noise through the single chipevaluation method,' in Proc.31st Int.Symp.Power Semiconductor Devices ICs (ISPSD), May 2019, pp.475-478.
[0004] However, no proposals have been made for the construction of IGBTs that can adequately suppress electromagnetic noise. Summary of the Invention
[0005] The present invention was made to solve the aforementioned problems, and its purpose is to obtain a semiconductor device capable of sufficiently suppressing electromagnetic noise.
[0006] The semiconductor device of the present invention is characterized by comprising: a semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a source layer of the first conductivity type formed on the base layer, and a collector layer of the second conductivity type formed below the drift layer; an emitter electrode formed on the upper surface of the semiconductor substrate and connected to the base layer and the source layer; a gate electrode formed on the upper surface of the semiconductor substrate; and a collector electrode formed on the lower surface of the semiconductor substrate and connected to the collector layer. A lower electrode is formed via a lower gate insulating film inside a trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer; an upper electrode is formed via an upper gate insulating film inside the trench, disposed above the lower electrode, and separated from the lower electrode by an intermediate insulating film; a first resistor is connected between the upper electrode and the gate electrode; and a second resistor is connected between the lower electrode and the gate electrode, wherein the gate-emitter capacitance of the lower electrode is smaller than the gate-emitter capacitance of the upper electrode.
[0007] In this invention, the upper and lower electrodes are separated by an intermediate insulating film inside the trench. A first resistor is connected between the upper electrode and the gate electrode. A second resistor is connected between the lower electrode and the gate electrode. The gate-emitter capacitance of the lower electrode is smaller than that of the upper electrode. Therefore, electromagnetic noise can be sufficiently suppressed in the IGBT structure. Attached Figure Description
[0008] Figure 1 This is a cross-sectional view showing the semiconductor device of Embodiment 1.
[0009] Figure 2 This is a graph showing the time changes of Vce, Ic, and Vge when the semiconductor device of Embodiment 1 is turned on.
[0010] Figure 3 This is a graph showing the relationship between Cge2 / Cge1 and the peak value of Ic.
[0011] Figure 4 This is a cross-sectional view showing the relationship between the thickness of the insulating film of the semiconductor device in Embodiment 1.
[0012] Figure 5 This is a graph showing the relationship between the thickness of the lower gate insulating film / the thickness of the upper gate insulating film and the Cge of the lower electrode / the Cge of the upper electrode.
[0013] Figure 6 This is a graph showing the relationship between the thickness of the lower gate insulating film / the thickness of the upper gate insulating film and the peak value of Ic.
[0014] Figure 7 This is a cross-sectional view showing the relationship between the lengths of the carrier accumulation layer and the drift layer of the semiconductor device in Embodiment 1.
[0015] Figure 8 This is a cross-sectional view showing the relationship between the lengths of the lower and upper electrodes of the semiconductor device in Embodiment 1 and the depth of the base layer.
[0016] Figure 9 This is a cross-sectional view showing the semiconductor device of Embodiment 2.
[0017] Figure 10 This is a top view showing the semiconductor device of Embodiment 3.
[0018] Figure 11 It means along Figure 10 Sectional views of sections I-II and III-IV.
[0019] Figure 12 This is a top view showing a modified example of the semiconductor device according to Embodiment 3.
[0020] Figure 13 It means along Figure 12 Sectional views of sections I-II and III-IV.
[0021] Figure 14 This is a diagram showing the semiconductor device of Embodiment 4.
[0022] Figure 15 This is a cross-sectional view showing the semiconductor device of Embodiment 5.
[0023] Figure 16 This is a cross-sectional view showing the semiconductor device of Embodiment 6.
[0024] Figure 17 This is a cross-sectional view showing the semiconductor device of Embodiment 7.
[0025] Explanation of reference numerals in the attached figures: 1…Semiconductor substrate; 2…Drift layer; 3…Base layer; 4…Source layer; 5…Collector layer; 6…Carrier accumulation layer; 8…Trench; 9…Emitter electrode; 10…Gate electrode; 11…Collector; 12…Lower electrode; 13…Lower gate insulating film; 14…Upper electrode; 15…Upper gate insulating film; 16…Intermediate insulating film; 18…First gate wiring; 19…Second gate wiring; 20…First gate contact; 21…Second gate contact; 22…Gate power supply; 23…Dummy trench; 24…Dummy lower electrode; 25…Dummy upper electrode; R1…First resistor; R2…Second resistor; R3…Gate resistor. Detailed Implementation
[0026] The semiconductor device according to the embodiments will be described with reference to the accompanying drawings. Identical or corresponding components are labeled with the same reference numerals, and repeated descriptions are omitted.
[0027] Implementation Method 1
[0028] Figure 1 This is a cross-sectional view showing a semiconductor device according to Embodiment 1. The semiconductor substrate 1 includes at least: a drift layer 2 of a first conductivity type, a base layer 3 of a second conductivity type formed on the drift layer 2, a source layer 4 of the first conductivity type formed on a portion of the base layer 3, and a collector layer 5 of the second conductivity type formed below the drift layer 2. A carrier accumulation layer 6 of the first conductivity type is formed between the drift layer 2 and the base layer 3. A buffer layer 7 of the first conductivity type is formed between the drift layer 2 and the collector layer 5. The carrier accumulation layer 6 and the buffer layer 7 have a higher impurity concentration than the drift layer 2. For example, the first conductivity type is n-type and the second conductivity type is p-type, but the opposite is also possible. A plurality of trenches 8 extending from the upper surface of the semiconductor substrate 1 through the source layer 4 and the base layer 3 are formed side-by-side.
[0029] Emitter electrode 9 is formed on the upper surface of semiconductor substrate 1 and is connected to base layer 3 and source layer 4. Gate electrode 10 is also formed on the upper surface of semiconductor substrate 1. Collector electrode 11 is formed on the lower surface of semiconductor substrate 1 and is connected to collector layer 5. Lower electrode 12 is formed inside trench 8 via lower gate insulating film 13. Upper electrode 14 is formed inside trench 8 via upper gate insulating film 15, disposed above lower electrode 12, and separated from lower electrode 12 by intermediate insulating film 16. Interlayer insulating film 17 is formed on upper electrode 14, separating upper electrode 14 from emitter electrode 9.
[0030] As described above, the upper electrode 14 and the lower electrode 12 are separated inside the trench 8 by the intermediate insulating film 16, thus enabling the gate-emitter capacitance Cge of the two electrodes to be different. The upper electrode 14 is opposite to the base layer 3 connected to the emitter electrode 9, so Cge is larger, but the lower electrode 12 is not opposite to the base layer 3, so Cge is smaller.
[0031] Furthermore, a first resistor R1 is connected between the upper electrode 14 and the gate electrode 10, and a second resistor R2 is connected between the lower electrode 12 and the gate electrode 10. This allows the voltages of the upper electrode 14 and the lower electrode 12 to be controlled independently via their respective gate capacitances. Therefore, by adjusting the thickness of the gate oxide film of each electrode, the Cge of the lower electrode 12 is made smaller than that of the upper electrode 14. This results in a faster charging speed for the capacitor of the lower electrode 12.
[0032] Figure 2This is a graph showing the time changes of Vce, Ic, and Vge when the semiconductor device of Embodiment 1 is turned on. As described above, the capacitor of the lower electrode 12 charges faster, therefore, during the current increase period when the device is turned on, there is a period in which the voltage of the lower electrode 12 is higher than the voltage of the upper electrode 14. During the mirror period following the current increase period, there is a period in which the voltage of the lower electrode 12 is lower than the voltage of the upper electrode 14.
[0033] If the voltage of the lower electrode 12 increases, the potential of the mesa sandwiched laterally by the lower electrode 12 of the adjacent trench 8 also increases. Cgc is the series capacitance of the gate oxide and the depletion layer; if the potential increases and the depletion layer extends, Cgc decreases. Therefore, the displacement current to the upper electrode 14 can be reduced, thus the peak value of Ic decreases. As a result, electromagnetic noise in the IGBT structure can be sufficiently suppressed.
[0034] Furthermore, the main cause of electromagnetic noise is the increase in displacement current due to holes, leading to an increase in the peak value of Ic, a problem that arises in IGBTs with a large number of holes flowing through them. On the other hand, there is no significant increase in the peak value of Ic in MOSFETs, so even if the structure of this embodiment is used in MOSFETs, a sufficient reduction in the peak value of Ic cannot be obtained.
[0035] Figure 3 This is a graph showing the relationship between Cge2 / Cge1 and the Ic peak value. The horizontal axis is the ratio (Cge2 / Cge1) of the gate-emitter capacitance Cge2 of the electrode connected to the second resistor R2 to the gate-emitter capacitance Cge1 of the electrode connected to the first resistor R1. The inventors have discovered that the smaller Cge2 / Cge1 is, the more the Ic peak value can be reduced. By making Cge2 / Cge1 0.5 or less, the Ic peak value can be reduced by more than 30%, and by making Cge2 / Cge1 0.2 or less, the Ic peak value can be reduced by more than 40%. Therefore, in this embodiment, the ratio of Cge of the electrode connected to the lower electrode 12 to Cge of the upper electrode 14 is preferably 0.5 or less, and more preferably 0.2 or less.
[0036] Furthermore, during the mirroring period following the current increase period upon turn-on, there exists a period where the voltage of the lower electrode 12 is lower than the voltage of the upper electrode 14. The mirroring period does not affect the Ic peak value, so even if the voltage of the lower electrode 12 is reduced, the Ic peak value does not increase. By reducing the voltage of the lower electrode 12 during the mirroring period, the voltage applied to the gate oxide film can be reduced. Therefore, compared to the case where the voltage of the lower electrode 12 is always higher, the lifetime of the gate oxide film can be extended. On the other hand, if there is a period during the mirroring period where the voltage of the lower electrode 12 is higher than the voltage of the upper electrode 14, Cgc can be reduced.
[0037] Figure 4 This is a cross-sectional view showing the relationship between the thicknesses of the insulating films in the semiconductor device of Embodiment 1. The thickness T2 of the lower gate insulating film 13 covering the side surface of the lower electrode 12 and the thickness T4 of the lower gate insulating film 13 covering the bottom of the lower electrode 12 are thicker than the thickness T1 of the upper gate insulating film 15 covering the side surface of the upper electrode 14. As a result, the Cge of the lower electrode 12 is smaller than that of the upper electrode 14. Therefore, as described above, the charging speed of the capacitor of the lower electrode 12 is faster, the voltage of the lower electrode 12 can be increased, and Cgc can be reduced to suppress electromagnetic noise.
[0038] Figure 5 This is a graph showing the relationship between the thickness of the lower gate insulating film / the thickness of the upper gate insulating film and the Cge of the lower electrode / the Cge of the upper electrode. Figure 6 This is a graph showing the relationship between the thickness of the lower gate insulating film / the thickness of the upper gate insulating film and the Ic peak value. In order to reduce the ratio of Cge of the lower electrode to Cge of the upper electrode and thus suppress the Ic peak value, the thickness of the lower gate insulating film 13 is preferably 1.5 times or more the thickness of the upper gate insulating film 15, more preferably 2 times or more, and even more preferably 2.5 times or more.
[0039] Furthermore, when the potential of the lower electrode 12 increases, a potential difference is generated between the upper electrode 14 and the lower electrode 12, resulting in capacitance. Therefore, the thickness T3 of the intermediate insulating film 16 is made thicker than the thickness T1 of the upper gate insulating film 15 on the side of the upper electrode 14. As a result, the Cgc of the lower electrode 12 decreases, and thus the charging speed of the capacitance of the lower electrode 12 increases as described above, enabling the voltage of the lower electrode 12 to increase and reducing Cgc, thereby suppressing electromagnetic noise.
[0040] Furthermore, the CR time constant formed by the gate capacitance (Cies2 = Cge + Cgc) of the lower electrode 12 and the second resistor R2 is smaller than the CR time constant formed by the gate capacitance (Cies1 = Cge + Cgc) of the upper electrode 14 and the first resistor R1. As a result, the charging speed of the capacitor of the lower electrode 12 is faster, thus suppressing electromagnetic noise.
[0041] Furthermore, the resistance value of the second resistor R2 is less than that of the first resistor R1. This results in a faster charging speed for the capacitor of the lower electrode 12, thus suppressing electromagnetic noise. On the other hand, if the resistance value of the second resistor R2 is greater than that of the first resistor R1, the rise in gate voltage, determined by displacement current and resistance, increases. Therefore, the voltage of the lower electrode 12 can be made higher than that of the upper electrode 14, and Cgc can be reduced.
[0042] Furthermore, since the impurity concentration in the carrier accumulation layer 6 is higher than that in the drift layer 2, it is easier to increase the voltage of the lower electrode 12. Therefore, by forming the carrier accumulation layer 6, Cgc can be further reduced, thereby suppressing electromagnetic noise.
[0043] Figure 7 This is a cross-sectional view showing the relationship between the lengths of the carrier accumulation layer and the drift layer of the semiconductor device in Embodiment 1. The length I2 of the carrier accumulation layer 6 opposite to the lower electrode 12 is longer than the length I1 of the carrier accumulation layer 6 opposite to the upper electrode 14. By increasing the area where the lower electrode 12 faces the carrier accumulation layer 6, the voltage of the lower electrode 12 can be increased and the Cgc can be reduced. By decreasing the area where the upper electrode 14 faces the carrier accumulation layer 6, the Cgc of the upper electrode can be reduced.
[0044] Furthermore, the length I2 of the carrier accumulation layer 6 opposite to the side of the lower electrode 12 is longer than the length I3 of the drift layer 2 opposite to the side of the lower electrode 12. Since the impurity concentration of the carrier accumulation layer 6 is higher than that of the drift layer 2, it is easier to increase the voltage of the lower electrode 12. Therefore, by increasing the area of the lower electrode 12 opposite to the carrier accumulation layer 6, it is possible to increase the voltage of the lower electrode 12 and reduce Cgc.
[0045] Figure 8 This is a cross-sectional view showing the relationship between the lengths of the lower and upper electrodes of the semiconductor device in Embodiment 1 and the depth of the base layer. Cgc depends on the electrode area opposite to the drift layer 2 and the carrier accumulation layer 6; therefore, the length D1 of the upper electrode 14 extending downwards from the base layer 3 is proportional to the Cgc of the upper electrode 14, and the length L2 of the lower electrode 12 is proportional to the Cgc of the lower electrode 12. In this embodiment, the length L2 is longer than the length D1. The depth P1 of the base layer 3 is longer than the length D1.
[0046] In the region below the base layer 3 where the voltage varies, by shortening the protruding length D1 of the low-voltage upper electrode 14, the depletion layer can be extended, thereby reducing the Cgc of the upper electrode 14 and the peak current Ic. To sufficiently reduce the Cgc of the upper electrode 14, the protruding length D1 of the upper electrode 14 is preferably less than half the length L2 of the lower electrode 12, and more preferably less than one-third.
[0047] Implementation Method 2
[0048] Figure 9This is a cross-sectional view of the semiconductor device according to Embodiment 2. Multiple trenches 8 are formed side-by-side on the semiconductor substrate 1. The width WM of the mesa between adjacent trenches 8 is narrower than the width WTR of the trench 8. This increases the voltage across the mesa and reduces Cgc, thus suppressing electromagnetic noise. Other structures and effects are the same as in Embodiment 1.
[0049] Implementation Method 3
[0050] Figure 10 This is a top view showing the semiconductor device according to Embodiment 3. A first gate wiring 18 and a resistor R1′ connect the upper electrode 14 and the gate electrode 10. A second gate wiring 19 and a resistor R2′ connect the lower electrode 12 and the gate electrode 10. The first resistor R1 is the sum of the resistance of resistor R1′ and the resistance of the first gate wiring 18. The second resistor R2 is the sum of the resistance of resistor R2′ and the resistance of the second gate wiring 19. The length GL2 of the second gate wiring 19 is shorter than the length GL1 of the first gate wiring 18. Therefore, even if the resistance values of resistors R1′ and R2′ are the same, the resistance value of the second resistor R2 is smaller than the resistance value of the first resistor R1. As a result, the charging speed of the capacitor at the lower electrode 12 is faster, thus suppressing electromagnetic noise.
[0051] On the other hand, if the length GL2 of the second gate wiring 19 is longer than the length GL1 of the first gate wiring 18, the resistance value of the second resistor R2 increases. Therefore, the increase in the gate voltage determined by the displacement current and resistance enables the voltage of the lower electrode 12 to be higher than that of the upper electrode 14, and reduces Cgc.
[0052] Figure 11 It means along Figure 10 The cross-sectional views are shown along sections I-II and III-IV. The upper electrode 14 is connected to the first gate wiring 18 via the first gate contact 20. The lower electrode 12 is connected to the second gate wiring 19 via the second gate contact 21. Other structures and effects are the same as in Embodiment 1.
[0053] Figure 12 This is a top view showing a modified example of the semiconductor device according to Embodiment 3. Figure 13 It means along Figure 12 The diagram shows cross-sectional views along sections I-II and III-IV. The upper electrode 14 is connected to the first gate wiring 18 via a plurality of first gate contacts 20. The lower electrode 12 is connected to the second gate wiring 19 via a plurality of second gate contacts 21. Furthermore, by doubly forming the first gate wiring 18 and the second gate wiring 19 on both the outer periphery and the inner side of the substrate, the contact areas with the upper electrode 14 or the lower electrode 12 can be increased. This allows for gate operation without gate delay within the chip plane.
[0054] Implementation Method 4
[0055] Figure 14 This diagram illustrates the semiconductor device according to Embodiment 4. A gate power supply 22 supplies power to the gate electrode 10. To adjust the switching speed, a gate resistor R3 is connected between the gate power supply 22 and the gate electrode 10. The gate resistor R3 has a resistance value larger than that of the first resistor R1 and the second resistor R2. If a large resistance is formed inside the chip, the conduction area shrinks, while conduction losses increase, as do device size and manufacturing costs. Therefore, the gate resistor R3 is formed on the outside of the semiconductor substrate 1. This allows for a smaller resistance area within the substrate, thereby reducing conduction losses, device size, and manufacturing costs. Other structures and effects are the same as in Embodiment 1.
[0056] Implementation Method 5
[0057] Figure 15 This is a cross-sectional view showing the semiconductor device according to Embodiment 5. Multiple trenches 8 and multiple dummy trenches 23 are formed side-by-side on the semiconductor substrate 1. The dummy trenches 23, like the trenches 8, extend from the upper surface of the semiconductor substrate 1 through the source layer 4 and the base layer 3. The depth and width of the dummy trenches 23 are the same as those of the trenches 8.
[0058] A dummy lower electrode 24 is formed inside the dummy trench 23 via a lower gate insulating film 13. The dummy lower electrode 24 is connected to the emitter electrode 9. The material, length, and width of the dummy lower electrode 24 are the same as those of the lower electrode 12. An upper electrode 14 is formed inside the dummy trench 23 via an upper gate insulating film 15, is disposed above the dummy lower electrode 24, and is separated from the dummy lower electrode 24 by an intermediate insulating film 16.
[0059] By forming a dummy lower electrode 24, in the plurality of trenches including trench 8 and dummy trench 23, the proportion of the lower electrode 12 connected to the gate electrode 10 decreases, while the proportion of the dummy lower electrode 24 connected to the emitter electrode 9 increases. Therefore, the parasitic gate capacitance in the lower electrode 12 can be reduced. Consequently, the charging speed of the capacitance of the lower electrode 12 increases, the voltage of the lower electrode 12 can be increased, and Cgc can be reduced. Other structures and effects are the same as in Embodiment 1.
[0060] Implementation Method 6
[0061] Figure 16This is a cross-sectional view of the semiconductor device according to Embodiment 6. A dummy upper electrode 25 is formed inside the dummy trench 23 via an upper gate insulating film 15. The material, length, and width of the dummy upper electrode 25 are the same as those of the upper electrode 14. A lower electrode 12 is formed inside the dummy trench 23 via a lower gate insulating film 13, positioned below the dummy upper electrode 25, and separated from the dummy upper electrode 25 by an intermediate insulating film 16. By forming the dummy upper electrode 25, a coupling capacitance Cge is generated between the upper electrode 14 and the dummy upper electrode 25. This coupling capacitance reduces the increase in the gate voltage of the upper electrode 14, thus suppressing electromagnetic noise. Other structures and effects are the same as in Embodiment 5.
[0062] Implementation Method 7
[0063] Figure 17 This is a cross-sectional view of the semiconductor device according to Embodiment 7. A dummy lower electrode 24 (According to Embodiment 5) and a dummy upper electrode 25 (According to Embodiment 6) are formed in the dummy trench 23. In Embodiment 5, a parasitic gate capacitance (Cge) exists between the upper electrode 14 and the dummy lower electrode 24. However, in this embodiment, by making both the upper and lower electrodes dummy electrodes, Cge can be reduced, thus reducing the parasitic gate capacitance in the lower electrode 12 compared to Embodiment 5. Therefore, the charging speed of the capacitance of the lower electrode 12 is faster, allowing for a higher voltage at the lower electrode 12 and a reduction in Cgc. Other structures and effects are the same as in Embodiment 5.
[0064] Furthermore, the semiconductor substrate 1 is not limited to being formed of silicon; it can also be formed of a wide-bandgap semiconductor with a larger bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. Semiconductor chips formed from such wide-bandgap semiconductors exhibit high voltage withstand capability and allowable current density, thus enabling miniaturization. By using this miniaturized semiconductor chip, semiconductor devices incorporating it can also be miniaturized and highly integrated. Additionally, due to the high heat resistance of the semiconductor chip, the heat sink of the heat sink can be miniaturized, and water-cooling sections can be air-cooled, further enabling miniaturization of the semiconductor device. Furthermore, the low power loss and high efficiency of the semiconductor chip enable high efficiency in semiconductor devices.
[0065] The preferred embodiments have been described in detail above, but the invention is not limited to these embodiments. Various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. Hereinafter, various aspects of the present invention will be described as appendices.
[0066] (Note 1) A semiconductor device, comprising:
[0067] A semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a source layer of the first conductivity type formed on the base layer, and a collector layer of the second conductivity type formed below the drift layer.
[0068] An emitter electrode is formed on the upper surface of the semiconductor substrate and is connected to the base layer and the source layer;
[0069] A gate electrode is formed on the upper surface of the semiconductor substrate;
[0070] A collector electrode is formed on the lower surface of the semiconductor substrate and is connected to the collector electrode layer;
[0071] The lower electrode is formed via a lower gate insulating film inside a trench that extends from the upper surface of the semiconductor substrate through the source layer and the base layer;
[0072] The upper electrode is formed inside the trench via an upper gate insulating film, disposed on top of the lower electrode, and separated from the lower electrode by an intermediate insulating film;
[0073] A first resistor is connected between the upper electrode and the gate electrode; and
[0074] A second resistor is connected between the lower electrode and the gate electrode.
[0075] The gate-emitter capacitance of the lower electrode is smaller than that of the gate-emitter capacitance of the upper electrode.
[0076] (Postscript 2)
[0077] According to the semiconductor device described in Appendix 1, wherein,
[0078] During the period of increased current upon connection, there exists a period in which the voltage of the lower electrode is higher than the voltage of the upper electrode.
[0079] (Note 3)
[0080] The semiconductor device according to Appendix 1 or 2, wherein,
[0081] The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is less than 0.5.
[0082] (Note 4)
[0083] The semiconductor device according to Appendix 1 or 2, wherein,
[0084] The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is 0.2 or less.
[0085] (Note 5)
[0086] The semiconductor device according to any one of Appendices 1 to 4, wherein,
[0087] During the mirroring period when the circuit is turned on, there is a period in which the voltage of the lower electrode is lower than the voltage of the upper electrode.
[0088] (Note 6)
[0089] The semiconductor device according to any one of Appendices 1 to 5, wherein,
[0090] The thickness of the lower gate insulating film covering the sides and bottom of the lower electrode is greater than the thickness of the upper gate insulating film covering the sides of the upper electrode.
[0091] (Note 7)
[0092] According to the semiconductor device described in Appendix 6, wherein...
[0093] The thickness of the lower gate insulating film is more than 1.5 times the thickness of the upper gate insulating film.
[0094] (Postscript 8)
[0095] According to the semiconductor device described in Appendix 6, wherein...
[0096] The thickness of the lower gate insulating film is more than twice the thickness of the upper gate insulating film.
[0097] (Note 9)
[0098] According to the semiconductor device described in Appendix 6, wherein...
[0099] The thickness of the lower gate insulating film is more than 2.5 times the thickness of the upper gate insulating film.
[0100] (Postscript 10)
[0101] The semiconductor device according to any one of Appendices 1 to 9, wherein,
[0102] The thickness of the intermediate insulating film is greater than the thickness of the upper gate insulating film on the side of the upper electrode.
[0103] (Postscript 11)
[0104] The semiconductor device according to any one of Appendices 1 to 10, wherein,
[0105] The CR time constant formed by the gate capacitance of the lower electrode and the second resistor is less than the CR time constant formed by the gate capacitance of the upper electrode and the first resistor.
[0106] (Postscript 12)
[0107] The semiconductor device according to any one of Appendices 1 to 11, wherein,
[0108] The resistance value of the second resistor is less than the resistance value of the first resistor.
[0109] (Postscript 13)
[0110] The semiconductor device according to any one of Appendices 1 to 11, wherein,
[0111] The resistance value of the second resistor is greater than the resistance value of the first resistor.
[0112] (Postscript 14)
[0113] The semiconductor device according to any one of Appendices 1 to 13, wherein,
[0114] It also has a carrier accumulation layer of a first conductivity type, which is formed between the drift layer and the base layer, and the impurity concentration is higher than that of the drift layer.
[0115] (Postscript 15)
[0116] According to the semiconductor device described in Appendix 14, wherein,
[0117] The length of the carrier accumulation layer opposite the side of the lower electrode is longer than the length of the carrier accumulation layer opposite the side of the upper electrode.
[0118] (Postscript 16)
[0119] According to the semiconductor device described in Appendix 14 or 15, wherein,
[0120] The length of the carrier accumulation layer opposite to the side of the lower electrode is longer than the length of the drift layer opposite to the side of the lower electrode.
[0121] (Postscript 17)
[0122] The semiconductor device according to any one of Appendices 11 to 16, wherein,
[0123] The length of the lower electrode is longer than the length of the upper electrode that extends downward from the base layer.
[0124] (Postscript 18)
[0125] The semiconductor device according to any one of Appendices 11 to 17, wherein,
[0126] The depth of the base layer is greater than the length of the upper electrode extending downward from the base layer.
[0127] (Postscript 19)
[0128] The semiconductor device according to any one of Appendices 1 to 18, wherein,
[0129] Multiple trenches are formed side-by-side on the semiconductor substrate.
[0130] The width of the platform between adjacent grooves is narrower than the width of the groove.
[0131] (Postscript 20)
[0132] The semiconductor device according to any one of Appendices 1 to 19 further comprises:
[0133] A first gate wiring connects the upper electrode to the gate electrode; and
[0134] A second gate wiring connects the lower electrode to the gate electrode.
[0135] The length of the second gate wiring is shorter than the length of the first gate wiring.
[0136] (Postscript 21)
[0137] The semiconductor device according to any one of Appendices 1 to 19 further comprises:
[0138] A first gate wiring connects the upper electrode to the gate electrode; and
[0139] A second gate wiring connects the lower electrode to the gate electrode.
[0140] The length of the second gate wiring is longer than the length of the first gate wiring.
[0141] (Postscript 22)
[0142] The semiconductor device according to Appendix 20 or 21, wherein,
[0143] The upper electrode is connected to the first gate wiring via the first gate contact portion.
[0144] The lower electrode is connected to the second gate wiring via the second gate contact portion.
[0145] (Postscript 23)
[0146] The semiconductor device according to any one of Appendices 1 to 22 further comprises:
[0147] A gate power supply that supplies power to the gate electrode; and
[0148] A gate resistor is connected between the gate power supply and the gate electrode.
[0149] The gate resistor has a resistance value larger than that of the first resistor and the second resistor, and is formed on the outer side of the semiconductor substrate.
[0150] (Postscript 24)
[0151] The semiconductor device according to any one of Appendices 1 to 23, wherein,
[0152] It also includes a dummy lower electrode, which is formed via the lower gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode.
[0153] The upper electrode is formed inside the dummy trench via the upper gate insulating film and is disposed on the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.
[0154] (Postscript 25)
[0155] The semiconductor device according to any one of Appendices 1 to 23, wherein,
[0156] It also includes a dummy upper electrode, which is formed via the upper gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode.
[0157] The lower electrode is formed inside the dummy trench via the lower gate insulating film and is disposed below the dummy upper electrode, and is separated from the dummy upper electrode by the intermediate insulating film.
[0158] (Postscript 26)
[0159] The semiconductor device according to any one of Appendices 1 to 23 further comprises:
[0160] A dummy lower electrode is formed via the lower gate insulating film within a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode; and
[0161] A dummy upper electrode is formed inside the dummy trench via the upper gate insulating film and disposed above the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.
[0162] (Postscript 27)
[0163] The semiconductor device according to any one of Appendices 1 to 26, wherein,
[0164] The semiconductor substrate is formed of a wide-bandgap semiconductor.
Claims
1. A semiconductor device, characterized in that, have: A semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a source layer of the first conductivity type formed on the base layer, and a collector layer of the second conductivity type formed below the drift layer. An emitter electrode is formed on the upper surface of the semiconductor substrate and is connected to the base layer and the source layer; A gate electrode is formed on the upper surface of the semiconductor substrate; A collector electrode is formed on the lower surface of the semiconductor substrate and is connected to the collector electrode layer; The lower electrode is formed via a lower gate insulating film inside a trench that extends from the upper surface of the semiconductor substrate through the source layer and the base layer; The upper electrode is formed inside the trench via an upper gate insulating film, disposed on top of the lower electrode, and separated from the lower electrode by an intermediate insulating film; A first resistor is connected between the upper electrode and the gate electrode; as well as A second resistor is connected between the lower electrode and the gate electrode. The gate-emitter capacitance of the lower electrode is smaller than that of the gate-emitter capacitance of the upper electrode.
2. The semiconductor device according to claim 1, characterized in that, During the period of increased current upon connection, there exists a period in which the voltage of the lower electrode is higher than the voltage of the upper electrode.
3. The semiconductor device according to claim 1 or 2, characterized in that, The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is less than 0.
5.
4. The semiconductor device according to claim 1 or 2, characterized in that, The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is 0.2 or less.
5. The semiconductor device according to claim 1 or 2, characterized in that, During the mirroring period when the circuit is turned on, there is a period in which the voltage of the lower electrode is lower than the voltage of the upper electrode.
6. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the lower gate insulating film covering the sides and bottom of the lower electrode is greater than the thickness of the upper gate insulating film covering the sides of the upper electrode.
7. The semiconductor device according to claim 6, characterized in that, The thickness of the lower gate insulating film is more than 1.5 times the thickness of the upper gate insulating film.
8. The semiconductor device according to claim 6, characterized in that, The thickness of the lower gate insulating film is more than twice the thickness of the upper gate insulating film.
9. The semiconductor device according to claim 6, characterized in that, The thickness of the lower gate insulating film is more than 2.5 times the thickness of the upper gate insulating film.
10. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the intermediate insulating film is greater than the thickness of the upper gate insulating film on the side of the upper electrode.
11. The semiconductor device according to claim 1 or 2, characterized in that, The CR time constant formed by the gate capacitance of the lower electrode and the second resistor is less than the CR time constant formed by the gate capacitance of the upper electrode and the first resistor.
12. The semiconductor device according to claim 1 or 2, characterized in that, The resistance value of the second resistor is less than the resistance value of the first resistor.
13. The semiconductor device according to claim 1 or 2, characterized in that, The resistance value of the second resistor is greater than the resistance value of the first resistor.
14. The semiconductor device according to claim 1 or 2, characterized in that, It also has a carrier accumulation layer of a first conductivity type, which is formed between the drift layer and the base layer, and the impurity concentration is higher than that of the drift layer.
15. The semiconductor device according to claim 14, characterized in that, The length of the carrier accumulation layer opposite the side of the lower electrode is longer than the length of the carrier accumulation layer opposite the side of the upper electrode.
16. The semiconductor device according to claim 14, characterized in that, The length of the carrier accumulation layer opposite to the side of the lower electrode is longer than the length of the drift layer opposite to the side of the lower electrode.
17. The semiconductor device according to claim 1 or 2, characterized in that, The length of the lower electrode is longer than the length of the upper electrode that extends downward from the base layer.
18. The semiconductor device according to claim 1 or 2, characterized in that, The depth of the base layer is greater than the length of the upper electrode extending downward from the base layer.
19. The semiconductor device according to claim 1 or 2, characterized in that, Multiple trenches are formed side-by-side on the semiconductor substrate. The width of the platform between adjacent grooves is narrower than the width of the groove.
20. The semiconductor device according to claim 1 or 2, characterized in that, It also has: A first gate wiring connects the upper electrode to the gate electrode; and A second gate wiring connects the lower electrode to the gate electrode. The length of the second gate wiring is shorter than the length of the first gate wiring.
21. The semiconductor device according to claim 1 or 2, characterized in that, It also has: A first gate wiring connects the upper electrode to the gate electrode; and A second gate wiring connects the lower electrode to the gate electrode. The length of the second gate wiring is longer than the length of the first gate wiring.
22. The semiconductor device according to claim 20, characterized in that, The upper electrode is connected to the first gate wiring via the first gate contact portion. The lower electrode is connected to the second gate wiring via the second gate contact portion.
23. The semiconductor device according to claim 1 or 2, characterized in that, It also has: A gate power supply that supplies power to the gate electrode; and A gate resistor is connected between the gate power supply and the gate electrode. The gate resistor has a resistance value larger than that of the first resistor and the second resistor, and is formed on the outer side of the semiconductor substrate.
24. The semiconductor device according to claim 1 or 2, characterized in that, It also includes a dummy lower electrode, which is formed via the lower gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode. The upper electrode is formed inside the dummy trench via the upper gate insulating film and is disposed on the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.
25. The semiconductor device according to claim 1 or 2, characterized in that, It also includes a dummy upper electrode, which is formed via the upper gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode. The lower electrode is formed inside the dummy trench via the lower gate insulating film and is disposed below the dummy upper electrode, and is separated from the dummy upper electrode by the intermediate insulating film.
26. The semiconductor device according to claim 1 or 2, characterized in that, It also has: A dummy lower electrode is formed via the lower gate insulating film within a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode; and A dummy upper electrode is formed inside the dummy trench via the upper gate insulating film and disposed above the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.
27. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor substrate is formed of a wide-bandgap semiconductor.