Fused salt energy storage device and method based on nitrate

Abstract

The invention discloses a molten salt energy storage device and method based on nitrate, and the device comprises a plurality of resistors, a plurality of MOS tubes, a plurality of operational amplifiers, a plurality of diodes, a triode, a capacitor, a solid-state relay, a potentiometer, and a counter. The output end of an operational amplifier U7 in the plurality of operational amplifiers is connected with five pins of the potentiometer U2, and the anti-phase end inputs a temperature parameter signal IN1; the in-phase end is connected with eight pins of the potentiometer U2 and one end of the resistor R5; the six pins of the potentiometer U2 are connected with one end of a resistor R16 and the drain electrode of a PMOS tube Q2; the grid electrode of the PMOS transistor Q2 is connected with the output end of the operational amplifier U8, and the source electrode is connected with a power supply and meets the positive voltage requirement; the inverting end of the operational amplifier U8 is connected with a reference signal, and the in-phase end of the operational amplifier U8 is connected with the grid electrode of the NMOS tube Q1, one end of the resistor R4 and the collector electrode of the NMOS tube Q1; a base electrode of the triode U1 is connected with one end of the resistor R6; the drain electrode of the NMOS tube Q1 is connected with the other end of the resistor R6, one end of a resistor R7 and four pins of the solid-state relay U3; the other end of the resistor R7 is connected with one end of the capacitor C1.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of energy storage, in particular to a molten salt energy storage device and method based on nitrate. BACKGROUND

[0002] With the transformation of global energy structure, the intermittency and instability of renewable energy such as solar energy and wind energy need to be solved. Molten salt energy storage technology has the advantages of high energy storage density, long service life, low cost, etc. Figure One A trough type molten salt energy storage system is provided, and the storage process is to focus sunlight on a heat collector through a heliostat, and the heat medium (molten salt) in the heat collector absorbs heat and warms up. The molten salt after warming is transported to a heat storage tank for storage, and when energy is needed, it exchanges heat with a cold medium to convert into steam, drives a turbine to generate electricity for use. In actual application, due to the fluctuation of solar radiation intensity caused by weather or seasonal changes, when the solar radiation intensity is low, the decrease of the basic temperature on the heat collector will affect the energy storage efficiency, and it is necessary to introduce an intermittent power source to assist heating when the heat medium is lower than the basic temperature. However, due to the real-time change of radiation intensity, if the auxiliary heating is started when the radiation intensity is strong and in the initial warming stage, it may cause the molten salt to warm up too fast, causing the decomposition of the molten salt to produce corrosive substances. And with the operation of the molten salt system, its warming rate will also fluctuate with the change of radiation intensity, which is difficult to accurately control, which will also increase the uncertainty and risk of the molten salt. Therefore, a molten salt energy storage device and method based on nitrate is proposed, which can accurately control the energy storage system under any conditions. SUMMARY

[0003] In order to solve the above technical problems, the application aims to provide a nitrate-based molten salt energy storage device, which comprises a plurality of resistors, a plurality of MOS tubes, a plurality of operational amplifiers, a plurality of diodes, a plurality of triodes, a plurality of capacitors, a plurality of solid-state relays, a plurality of potentiometers and a plurality of counters, wherein the output end of the operational amplifier U7 is connected to the five-pin end of the potentiometer U2, the inverting input end inputs a temperature parameter signal IN1, and the non-inverting input end is connected to the eight-pin end of the potentiometer U2 and the one end of the resistor R5; the six-pin end of the potentiometer U2 is connected to the one end of the resistor R16 and the drain electrode of the PMOS tube Q2; the gate electrode of the PMOS tube Q2 is connected to the output end of the operational amplifier U8, and the source electrode is connected to a power supply and meets the positive voltage requirement; the inverting input end of the operational amplifier U8 is connected to a reference signal, the non-inverting input end is connected to the gate electrode of the NMOS tube Q1, the one end of the resistor R4 and the collector electrode of the NMOS tube Q1; the emitter electrode of the triode U1 is connected to a power supply, and the base electrode is connected to the one end of the resistor R6; the drain electrode of the NMOS tube Q1 is connected to the other end of the resistor R6, the one end of the resistor R7 and the four-pin end of the solid-state relay U3; the other end of the resistor R7 is connected to the one end of the capacitor C1; the one end of the resistor R11, the cathodes of the diodes D1 and D2 are connected to the one pin end of the solid-state relay U3; the two-pin end of the counter U4 is connected to the anode of the diode D1, the seven-pin end is connected to the anode of the diode D2, the tenth-pin end is connected to the fifteen-pin end and a fault reset signal IN3, the fourteen-pin end inputs a time sequence signal IN2, and the fourth-pin end outputs a feedback signal VO1; the other ends of the capacitor C1, the resistor R4, the resistor R7, the resistor R11, the resistor R16 and the three-pin end of the solid-state relay U3 are connected to the ground.

[0004] Further, the application further comprises a plurality of resistors and a plurality of operational amplifiers, wherein the inverting input end of the operational amplifier U5 is connected to the one end of the resistor R1 and the resistor R2, the non-inverting input end is connected to the one end of the resistor R8, and the output end is connected to the other end of the resistor R2 and outputs a prediction signal VO2; the other end of the resistor R1 is connected to the one end of the resistor R3 and the output end of the operational amplifier U6; the non-inverting input end of the operational amplifier U6 is connected to the other end of the resistor R3, and the inverting input end is connected to the one end of the resistor R5; the other end of the resistor R8 is connected to the one end of the resistor R9 and the inverting input end of the operational amplifier U7; the other end of the resistor R9 is connected to the ground.

[0005] Further, the application further comprises a plurality of resistors, wherein the one end of the resistor R12 is connected to the one end of the resistor R13 and the inverting input end of the operational amplifier U8; the one end of the resistor R14 is connected to the source electrode of the PMOS tube Q2 and the one end of the resistor R17; the other ends of the resistors R12 and R14 are connected to a power supply; the other ends of the resistors R13 and R17 are connected to the ground.

[0006] Further, the application further comprises a plurality of resistors, wherein the one end of the resistor R16 is connected to the fourteen-pin end of the counter U4; the one end of the resistor R19 is connected to the tenth-pin end of the counter U4; the other ends of the resistors R18 and R19 are connected to the ground.

[0007] Further, the application further comprises a resistor, wherein the one end of the resistor R15 is connected to the gate electrode of the PMOS tube Q2, and the other end is connected to the ground.

[0008] Furthermore, it also includes a processor, which sets preset progressive temperature parameters and samples the VO2 signal for comparison when VO1 is input, and controls the heating device to be adjusted up or down based on the result.

[0009] Furthermore, a molten salt energy storage method based on nitrates is also provided, characterized by comprising the following steps; S1. Detect the current temperature of the heat medium, preset the temperature rise rate corresponding to the progressive temperature parameter, and set four timing signals: S2. The circuit is activated when the first timing signal is received; S3. When the second time sequence signal arrives, the current thermal medium temperature parameter is set as the prediction reference parameter, and the predicted temperature change parameter is fed back to VO2 when the third time sequence arrives. S4. After the third time sequence arrives, the sampled VO2 signal is compared with the progressive temperature parameter corresponding to the preset rise rate. If it is greater than but not a multiple of the progressive temperature parameter, the heating power is reduced according to the currently set progressive temperature parameter and the system enters the fourth time sequence standby state. S5. If it is greater than and in a multiple state, then enter the second time sequence again and cycle until the fourth time sequence state is entered.

[0010] The advantages of this invention compared to the prior art are: By using a four-time sequence control method, the heat medium can maintain a specific heating rate under different solar radiation intensity fluctuations and arbitrary start-up time conditions, thus avoiding risks caused by uncontrollable factors. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 The diagram shows the structure of the molten salt energy storage device provided by this invention.

[0013] Figure 2 The circuit structure diagram of the energy storage device provided by the present invention. Detailed Implementation

[0014] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0015] This invention discloses a molten salt energy storage device based on nitrate, comprising several resistors, several MOSFETs, several operational amplifiers, several diodes, transistors, capacitors, a solid-state relay, a potentiometer, and a counter. Among the several operational amplifiers, the output terminal of operational amplifier U7 is connected to pin 5 of potentiometer U2, the inverting input of the temperature parameter signal IN1 is input, and the non-inverting input is connected to pin 8 of potentiometer U2 and one end of resistor R5. Pin 6 of potentiometer U2 is connected to one end of resistor R16 and the drain of PMOS transistor Q2. The gate of PMOS transistor Q2 is connected to the output terminal of operational amplifier U8, and the source is connected to the power supply, satisfying the positive voltage requirement. The inverting input of operational amplifier U8 is connected to a reference signal, and the non-inverting input is connected to the gate of NMOS transistor Q1, one end of resistor R4, and the NMOS transistor... The collector of transistor Q1 is connected to the power supply; the emitter of transistor U1 is connected to the power supply, and the base is connected to one end of resistor R6; the drain of NMOS transistor Q1 is connected to the other end of resistor R6, one end of resistor R7, and the four pins of solid-state relay U3; the other end of resistor R7 is connected to one end of capacitor C1; one pin of solid-state relay U3 is connected to one end of resistor R11, and the cathodes of D1 and D2; the second pin of counter U4 is connected to the anode of D1, the seventh pin is connected to the anode of D2, the tenth pin is connected to the fifteenth pin and the fault reset signal IN3, the fourteenth pin inputs the timing signal IN2, and the fourth pin outputs the feedback signal VO1; the other ends of capacitor C1, resistor R4, resistor R7, resistor R11, and resistor R16, as well as the three pins of solid-state relay U3, are grounded; Specifically, it also includes several resistors and several operational amplifiers. Among the several operational amplifiers, the inverting input of operational amplifier U5 is connected to one end of resistors R1 and R2, the non-inverting input is connected to one end of resistor R8, and the output input is connected to the other end of resistor R2 and outputs a prediction signal VO2; the other end of resistor R1 is connected to one end of resistor R3 and the output terminal of operational amplifier U6; the non-inverting input of operational amplifier U6 is connected to the other end of resistor R3, and the inverting input is connected to one end of resistor R5; the other end of resistor R8 is connected to one end of resistor R9 and the inverting input of operational amplifier U7; the other end of resistor R9 is grounded.

[0016] Specifically, it also includes several resistors, wherein one end of resistor R12 is connected to one end of resistor R13 and the inverting input of operational amplifier U8; one end of resistor R14 is connected to the source of PMOS transistor Q2 and one end of resistor R17; the other ends of resistors R12 and R14 are connected to the power supply; and the other ends of resistors R13 and R17 are grounded.

[0017] Specifically, it also includes several resistors, of which one end of resistor R16 is connected to pin 14 of counter U4; one end of resistor R19 is connected to pin 10 of counter U4; and the other ends of resistors R18 and R19 are grounded.

[0018] Specifically, it also includes a resistor, wherein one end of resistor R15 is connected to the gate of PMOS transistor Q2, and the other end is grounded.

[0019] Specifically, it also includes a processor, which sets preset progressive temperature parameters and samples the VO2 signal for comparison when VO1 is input, and controls the heating device to be adjusted up or down based on the result.

[0020] Specifically, a molten salt energy storage method based on nitrates is also provided, characterized by comprising the following steps; S1. Detect the current temperature of the heat medium, preset the temperature rise rate corresponding to the progressive temperature parameter, and set four timing signals: S2. The circuit is activated when the first timing signal is received; S3. When the second time sequence signal arrives, the current thermal medium temperature parameter is set as the prediction reference parameter, and the predicted temperature change parameter is fed back to VO2 when the third time sequence arrives. S4. After the third time sequence arrives, the sampled VO2 signal is compared with the progressive temperature parameter corresponding to the preset rise rate. If it is greater than but not a multiple of the progressive temperature parameter, the heating power is reduced according to the currently set progressive temperature parameter and the system enters the fourth time sequence standby state. S5. If it is greater than and in a multiple state, then enter the second time sequence again and cycle until the fourth time sequence state is entered.

[0021] In one embodiment, VO2 is a prediction signal. When VO1 is output, the processor samples and compares this signal, and controls the heating power of the heating medium based on the comparison result. IN1 is the current temperature parameter signal of the heating medium. IN2 is a timing signal. Upon initial power-up, a single pulse signal is first input to IN2 to activate the circuit. Subsequently, IN2 enters a four-timing control mode. IN2 enters the first timing sequence when the first pulse signal is input to activate the circuit. When the radiation intensity is high and the heating device is started, the second pulse signal enters the second timing sequence, and the circuit sets the current temperature parameter as the prediction reference parameter. When the third timing sequence arrives, the predicted temperature change parameter is fed back to VO2. The third timing sequence is entered when the third pulse signal is input. The feedback signal is input to the processor via VO1. The processor samples the VO2 signal and compares it with the preset progressive temperature parameter corresponding to the required rise rate. If the VO2 signal is greater than but not a multiple of the progressive temperature parameter, the heating power is reduced according to the currently set progressive temperature parameter, and the fourth pulse signal is fed back to IN2 to enter the fourth timing standby state (the first timing is switched from active to standby). Then, the cycle is repeated according to the change in radiation intensity. If the VO2 signal is greater than and is a multiple of the parameter, the fifth pulse signal is fed back to enter the second timing cycle until the VO2 parameter is less than the progressive temperature parameter and is not zero. Regardless of the change in radiation intensity, the temperature rise of the heat medium is within the progressive temperature parameter range to avoid uncontrollable situations. IN3 is the fault reset signal.

[0022] In one embodiment, counter U4 in the circuit is used to receive pulse signals fed back by the processor. Upon initial power-up, when the first pulse signal is fed back from IN2, the third pin of counter U4 is in output state, activating the power reset function of the fifteenth pin of counter U4 and putting it into standby mode. At this time, the circuit state is such that the inverting input of operational amplifier U7 samples the current temperature parameter signal of the thermal medium at IN1, while the non-inverting input of operational amplifier U7 samples the voltage at the eighth pin of potentiometer U2. After comparison, the voltage is pulled up through resistor R10 and ground, and then input to the fifth pin of potentiometer U2. Potentiometer U2 adjusts the vernier input to increment or decrement the voltage at the eighth pin. Decrease; When the processor feeds back the second pulse signal, the output of the third pin of counter U4 switches to the output of the second pin. The signal is then current-limited by D1 and resistor R11 and input to the anode of solid-state relay U3. After coupling, the internal MOS transistor of solid-state relay U3 is turned on. During initial power-up, the emitter power supply of transistor U1 is turned on after being disconnected through the base, resistor R6, resistor R7, and capacitor C1. The emitter of transistor U1 is pulled up through the collector and resistor R4 and input to the gate of NMOS transistor Q1. NMOS transistor Q1 is turned on, and capacitor C1 changes from being disconnected to storing energy. At this time, transistor U1 returns to the gate through resistor R6 and capacitor C1. The circuit transitions to a loop through the drain, source, and ground of NMOS transistor Q1. The gate potential of NMOS transistor Q1 is pulled up and exceeds the reference voltage set by resistors R12 and R13 for operational amplifier U8. Operational amplifier U8 outputs a signal to the gate of PMOS transistor Q2, causing PMOS transistor Q2 to be cut off. Resistor R16 pulls down, and potentiometer U2 maintains increment or decrement control. When the third pin of counter U4 switches to the output of the second pin, the signal is current-limited by D1 and resistor R11 and input to the anode of solid-state relay U3. After coupling, the internal MOS transistor of solid-state relay U3 conducts. Transistor U1, resistor R6, and NMOS... The circuit of OS transistor Q1 is shunted to solid-state relay U3 and ground. Capacitor C1 is decoupled through solid-state relay U3. The voltage at the connection point of capacitor C1 and resistor R7 is equal to the gate voltage of NMOS transistor Q1. The gate-to-drain voltage of NMOS transistor Q1 is lower than the positive turn-on voltage and it is cut off. At the same time, the gate voltage drop of NMOS transistor Q1 is lower than the reference voltage set at the inverting input of op-amp U8, so op-amp U8 is cut off. The gate-to-source voltage difference of PMOS transistor Q2 reaches the negative turn-on voltage difference. After PMOS transistor Q2 is turned on, it is pulled up through resistor R16 and fed back to the sixth pin of potentiometer U2. Potentiometer U2 is cut off and stops the voltage increase / decrease control of the eighth pin.When the third pulse signal is input, the second pin of counter U4 switches to the fourth pin. During this process, the solid-state relay U3 stops coupling while in a low-potential state, capacitor C1 is open-circuited, and the original circuit of transistor U1, resistor R6, and solid-state relay U3 is cut off, causing transistor U1 to turn off. The gate potential of NMOS transistor Q1 is pulled down again, and the output of operational amplifier U8 remains unchanged. At the same time, during the transition from the second pin to the fourth pin of counter U4, the IN1 signal is also input to the non-inverting input of operational amplifier U5 via resistor R8, and the eighth pin of potentiometer U2 is input to the non-inverting input via operational amplifier U6 and resistor R8. After being proportionally isolated by resistor R3, the output is fed back to operational amplifier U5 via resistor R1. Operational amplifier U5 differentially divides the non-inverting and inverting inputs and feeds the result back to VO2. After the second pin of counter U4 switches to the fourth pin, the fourth pin of counter U4 feeds back to the processor. The processor samples the VO2 signal and compares it with preset progressive temperature parameters. Based on the comparison result, it controls the heating device to adjust the temperature up or down. The processor can obtain the required parameters through internal integration or a combination of a proportional circuit and a comparator circuit (the attached diagram does not show the processor and external circuitry). The proportional circuit... The circuit detects whether the value is a multiple of the incremental temperature parameter, while the comparator circuit detects whether the value is greater than the incremental temperature parameter's amplitude. When the value is a multiple, the processor feeds back two pulse signals, namely the fourth and fifth pulse signals; when the value is greater than the parameter, it feeds back only one pulse signal, namely the fourth pulse signal. When the fourth pulse signal is received, the fourth pin of counter U4 switches to the seventh pin for output. The signal from the seventh pin is fed back to the solid-state relay U3 via D2. The solid-state relay U3 is recoupled, and transistor U1 is turned on again through resistor R6 and the solid-state relay U3 circuit. The gate potential of NMOS transistor Q1 is increased. The signal is pulled back to the non-inverting input of op-amp U8, and op-amp U8 outputs a signal to the gate of PMOS transistor Q2. PMOS transistor Q2 is turned off. The sixth pin of potentiometer U2 is pulled down by resistor R16, and the voltage of the eighth pin of potentiometer U2 is increased or decreased based on the output of op-amp U7. On the fifth pulse signal, the seventh pin of counter U4 jumps to the tenth pin for output. When the tenth pin outputs, the signal is pulled up by resistor R19 and fed back to the fifteenth pin for power reset, allowing the circuit to enter the activated standby state of the first pulse signal, waiting to cycle again when the IN2 input signal is received.

[0023] In one embodiment, the reference signal at the inverting input of operational amplifier U8 and the power supply to the source of PMOS transistor Q2 can be provided by a power supply or a processor, in addition to the voltage divider method shown in the attached figure. The power supply to the source of PMOS transistor Q2 satisfies the positive voltage conduction characteristic. When operational amplifier U8 uses rail-to-rail devices, the on-state voltage drop of the internal transistor needs to be increased.

[0024] In one embodiment, the resistors connected to the fourteenth and tenth pins of counter U4 and the sixth pin of potentiometer U2 are pull-down resistors, used to establish a loop when there is no input, and the pull-down resistors can also be enabled by the processor.

[0025] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. A molten salt energy storage device based on nitrates, characterized in that, The system includes several resistors, several MOSFETs, several operational amplifiers, several diodes, transistors, capacitors, solid-state relays, potentiometers, and counters. Among the operational amplifiers, the output of operational amplifier U7 is connected to pin 5 of potentiometer U2, the inverting input is the temperature parameter signal IN1, and the non-inverting input is connected to pin 8 of potentiometer U2 and one end of resistor R5. Pin 6 of potentiometer U2 is connected to one end of resistor R16 and the drain of PMOS transistor Q2. The gate of PMOS transistor Q2 is connected to the output of operational amplifier U8, and the source is connected to the power supply, meeting the positive voltage requirement. The inverting input of operational amplifier U8 is connected to the reference signal, and the non-inverting input is connected to the gate of NMOS transistor Q1, one end of resistor R4, and the collector of NMOS transistor Q1. The transistors... The emitter of U1 is connected to the power supply, and the base is connected to one end of resistor R6; the drain of NMOS transistor Q1 is connected to the other end of resistor R6, one end of resistor R7, and the four pins of solid-state relay U3; the other end of resistor R7 is connected to one end of capacitor C1; one pin of solid-state relay U3 is connected to one end of resistor R11, and the cathodes of D1 and D2; the second pin of counter U4 is connected to the anode of D1, the seventh pin is connected to the anode of D2, the tenth pin is connected to the fifteenth pin and the fault reset signal IN3, the fourteenth pin inputs the timing signal IN2, and the fourth pin outputs the feedback signal VO1; the other ends of capacitor C1, resistor R4, resistor R7, resistor R11, and resistor R16, as well as the three pins of solid-state relay U3, are grounded.

2. The nitrate-based molten salt energy storage device according to claim 1, characterized in that, It also includes several resistors and several operational amplifiers. Among the several operational amplifiers, the inverting input of operational amplifier U5 is connected to one end of resistors R1 and R2, the non-inverting input is connected to one end of resistor R8, and the output input is connected to the other end of resistor R2 and outputs a prediction signal VO2; the other end of resistor R1 is connected to one end of resistor R3 and the output terminal of operational amplifier U6; the non-inverting input of operational amplifier U6 is connected to the other end of resistor R3, and the inverting input is connected to one end of resistor R5; the other end of resistor R8 is connected to one end of resistor R9 and the inverting input of operational amplifier U7; the other end of resistor R9 is grounded.

3. The nitrate-based molten salt energy storage device according to claim 1, characterized in that, It also includes several resistors, wherein one end of resistor R12 is connected to one end of resistor R13 and the inverting input of operational amplifier U8; one end of resistor R14 is connected to the source of PMOS transistor Q2 and one end of resistor R17; the other ends of resistors R12 and R14 are connected to the power supply; and the other ends of resistors R13 and R17 are grounded.

4. The nitrate-based molten salt energy storage device according to claim 1, characterized in that, It also includes several resistors, of which one end of resistor R16 is connected to pin 14 of counter U4; one end of resistor R19 is connected to pin 10 of counter U4; and the other ends of resistors R18 and R19 are grounded.

5. The nitrate-based molten salt energy storage device according to claim 1, characterized in that, It also includes a resistor, wherein one end of resistor R15 is connected to the gate of PMOS transistor Q2, and the other end is grounded.

6. The nitrate-based molten salt energy storage device according to claim 1, characterized in that, It also includes a processor, which sets preset progressive temperature parameters and samples the VO2 signal for comparison when VO1 is input, and controls the heating device to be adjusted up or down based on the result.

7. A molten salt energy storage method based on nitrates, characterized in that, Includes the following steps: S1. Detect the current temperature of the heat medium, preset the temperature rise rate corresponding to the progressive temperature parameter, and set four timing signals; S2. The circuit is activated when the first timing signal is received; S3. When the second time sequence signal arrives, the current thermal medium temperature parameter is set as the prediction reference parameter, and the predicted temperature change parameter is fed back to VO2 when the third time sequence arrives. S4. After the third time sequence arrives, the sampled VO2 signal is compared with the progressive temperature parameter corresponding to the preset rise rate. If it is greater than but not a multiple of the progressive temperature parameter, the heating power is reduced according to the currently set progressive temperature parameter and the system enters the fourth time sequence standby state. S5. If it is greater than and in a multiple state, then enter the second time sequence again and cycle until the fourth time sequence state is entered.

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