Switched capacitor power supply circuit

Abstract

A switched capacitor power supply circuit capable of reducing BOX capacitance even when an integrated circuit is formed using a general process. In a switched capacitor power supply circuit (1) comprising an integrated circuit, an N-well layer (15) located below each capacitor element (C1-C5) is connected to a potential point that is the same as the potential of a semiconductor substrate (11) via a resistance element (R).

Description

Technical Field

[0001] This invention relates to a switched capacitor power supply circuit, which is composed of integrated circuits. By using multiple clock signals with different phases to charge and discharge multiple capacitor elements through multiple switching elements, the input voltage is converted into a specified output voltage. Background Technology

[0002] In recent years, there has been a demand for high-step-down ratio DC / DC converters capable of converting power from high-voltage systems (above 400V, such as automotive batteries) to low-voltage systems (around 12V). In such DC / DC converters, switching power supplies utilizing transformers are often used to achieve high conversion efficiency. However, when performing power conversion with a high step-down ratio, the duty cycle of the PWM signal needs to be reduced. That is, with the control signal becoming narrower pulses, the difficulty of timing design increases, or it may lead to a deterioration in conversion efficiency. Furthermore, transformers are generally large and heavy. Such switching power supplies are not suitable for high step-down ratios and miniaturization; therefore, switched-capacitor type power supplies, consisting only of capacitors and switches, have attracted attention.

[0003] For example, Non-Patent Document 1 proposes a fully integrated switched capacitor power supply circuit using a Dickson star topology. When the switched capacitor power supply circuit is configured as an integrated circuit, a so-called BOX capacitor is generated as a capacitor component in the BOX (Buried-Oxide) layer located below the capacitor element. Since this BOX capacitor is connected in series with the capacitor element, the power conversion efficiency of the switched capacitor power supply circuit is reduced. Regarding this, see [reference needed]. Figures 7 to 12 This will be explained. Additionally, S1 and S2 in these diagrams represent clock signals with different phases and switches driven by those clock signals.

[0004] Figure 7 It is a Dickson star-type switched capacitor power supply circuit. For example... Figure 8 As shown, in stage 1 when switch S2 is high, the BOX capacitor CBOX is charged via capacitors C1, C3, and C5 using the output voltage Vout. At this time, the lower plates of capacitors C2 and C4 are grounded, thus the charge on these BOX capacitors CBOX is discharged and lost. Additionally, as... Figure 9 As shown, in stage 2 when switch S1 is at a high level, the BOX capacitor CBOX is charged by the output voltage Vout via capacitor elements C2 and C4, while the charge of the BOX capacitor CBOX in capacitor elements C1, C3, and C5 is discharged and lost.

[0005] Figure 10 It is a LADDER-type switched capacitor power supply circuit. For example... Figure 11As shown, in stage 1 when switch S2 is high, each BOX capacitor CBOX is charged via capacitors C5, C6, and C7 using the output voltage Vout, the voltage VT0 at the common connection point of capacitors C2 and C3, and the voltage VT1 at the common connection point of capacitors C3 and C4, respectively. Additionally, as... Figure 12 As shown, in stage 2 when switch S1 is at a high level, the charged charge of BOX capacitor CBOX5 is discharged, BOX capacitor CBOX6 is charged with output voltage Vout, and BOX capacitor CBOX7 is charged with voltage VT0.

[0006] Thus, the charge difference ΔQ between the BOX capacitors in stage 1 and stage 2 becomes the loss. Specifically, VT1≈3VOUT, VT0≈2VOUT, therefore,

[0007] C5:ΔQ5=CBOX(VOUT-GND)≈CBOX×Vout

[0008] C6:ΔQ6=CBOX(VT0-Vout)≈CBOX×Vout

[0009] C7:ΔQ7=CBOX(VT1-VT0)≈CBOX×Vout,

[0010] ΔQ = ΔQ5 + ΔQ6 + ΔQ7.

[0011] In non-patent literature 1 Figure 12 In this study, as a solution for BOX capacitors, a structure using a special process is disclosed, in which an n-type buried layer is formed on a p-type substrate layer and a high voltage is imparted.

[0012] Existing technical documents

[0013] Non-patent literature

[0014] Non-Patent Document 1: IEEE JOURNAL OF SOLID-STATE CIRCUITS, Fully Integrating a400V-to-12V DC-DC Converter in High-Voltage CMOSTuur Van Daele, and FilipTavernier. Summary of the Invention

[0015] However, in solutions like those in Non-Patent Document 1, the circuit area increases by adding an n-buried layer, thus increasing manufacturing costs.

[0016] The present invention was made in view of the above circumstances, and its object is to provide a switched capacitor power supply circuit that can reduce BOX capacitance even when the integrated circuit is formed by a common process.

[0017] According to the switched capacitor power supply circuit of the first embodiment, the well layer (15) located below the capacitor elements (C1 to C5) in the integrated circuit is connected to a potential point below the potential of the semiconductor substrate (11) via a load circuit (R). Furthermore, the "load circuit" is a circuit that has at least a resistive component and may also include a single element. Here, let the capacitance of the well layer in the capacitor element be C. W The BOX capacitor is C BOX s=jω, the resistance of the load circuit is R. The impedance Z1 of a single BOX capacitor is Z1=1 / (sC) BOX If, assuming that one end of the BOX capacitor is also connected to the aforementioned potential point, and the well layer is connected to the aforementioned potential point via a load circuit, then the impedance Z2 of the well layer becomes the impedance of the capacitor C. BOX and the parallel circuit of the load circuit R and the capacitor C W The value obtained by connecting in series.

[0018] Therefore, if set to s C BOX Since >> 1 / R, the value of 1 / R can be ignored in the calculation of impedance Z2. Therefore, it essentially becomes the capacitance C. W A capacitor C is connected in series above. BOX The obtained value is Z2 = 1 / (s C) BOX )+1 / (sC W Z2 < Z1. In this way, by simply adding a load circuit, the influence of BOX capacitor 12 can be reduced and the reduction in power conversion efficiency can be prevented.

[0019] According to the second method of the switched capacitor power supply circuit, the load circuit is connected to all the corresponding well layers of the multiple capacitor elements. Therefore, the influence of the BOX capacitor can be reduced for all capacitor elements.

[0020] According to a third-party switched capacitor power supply circuit, the well layers corresponding to groups of capacitor elements with equal charging and discharging timings are wired to the same potential, and the load circuit is connected to each group of capacitor elements. This reduces the number of load circuits, suppresses the increase in circuit area, and minimizes the increase in manufacturing costs. Attached Figure Description

[0021] Figure 1 This is a diagram showing the structure of the switched capacitor power supply circuit according to the first embodiment.

[0022] Figure 2 It is a schematic cross-sectional view showing the semiconductor structure of a capacitor element.

[0023] Figure 3 It is a schematic cross-sectional view of the semiconductor structure of a conventional capacitor element.

[0024] Figure 4 This is a graph representing the simulation results.

[0025] Figure 5 This is a diagram showing the structure of the switched capacitor power supply circuit according to the second embodiment.

[0026] Figure 6 This is a diagram showing the structure of the switched capacitor power supply circuit according to the third embodiment.

[0027] Figure 7 This is a diagram showing the structure of a conventional Dickson star-type switched capacitor power supply circuit.

[0028] Figure 8 This is a diagram showing the connection state of stage 1 when switch S2 is at a high level.

[0029] Figure 9 This is a diagram showing the connection state in stage 2 when switch S1 is at a high level.

[0030] Figure 10 This is a diagram showing the structure of a conventional LADDER-type switched capacitor power supply circuit.

[0031] Figure 11 This is a diagram showing the connection state of stage 1 when switch S2 is at a high level.

[0032] Figure 12 This diagram shows the connection state of S2 when switch S1 is at a high level. Detailed Implementation

[0033] (First Implementation)

[0034] like Figure 1 As shown, the switched capacitor power supply circuit 1 of this embodiment is a Dickson type and is constructed from integrated circuits. Between the input terminal Vin and the output terminal Vout, five groups of P-channel MOSFETs 2 and N-channel MOSFETs 3 are connected in series. S1, S2, and S3 are applied to the gates of each FET 2 and FET 3. Figure 7 The same clock signal is shown.

[0035] The upper plates of capacitors C1 to C5 are connected to the drains of FETs 2 (1-5) and FET 3 (1-5), which serve as the common connection point. The lower plates of capacitors C2 and C4 are connected to the drains of P-channel MOSFET 4 and N-channel MOSFET 5, and the lower plates of capacitors C1, C3, and C5 are connected to the drains of P-channel MOSFET 6 and N-channel MOSFET 7. The sources of FETs 4 and FET 7 are connected to the output terminal Vout, and the sources of FETs 5 and FET 6 are grounded. Furthermore, the N-well layers (NW) formed on the lower layers of capacitors C1 to C5 are connected to ground, which also serves as the substrate potential, via resistors R1 to R5. The resistors R, which are passive components, are an example of a load circuit.

[0036] like Figure 2 As shown, a BOX layer 12 is formed on top of an N-type semiconductor substrate 11. Above the BOX layer 12, a deep N-well layer 14 and an N-well layer 15 are formed in a region defined by trenches 13 containing buried insulators. A capacitor element C is formed, for example, through comb-shaped electrodes on a wiring layer that serves as the surface of the N-well layer 15. In this figure, Vin on the upper electrode side and Vout on the lower electrode side represent the input and output sides of a capacitor element C. Furthermore, the N-well layer 15 is grounded via a resistor element R formed in the wiring layer, thereby achieving the same potential as the semiconductor substrate 11.

[0037] With a semiconductor structure as described above, and as shown in the equivalent circuit in the figure, the lower plate of each capacitor element C is connected to the ground via the parasitic capacitance C of the N-well layer 15. NW And grounded through a series circuit of the resistive element R. Additionally, capacitor C... NW The common connection point of the resistor R and the BOX capacitor C BOX And grounding.

[0038] like Figure 3 As shown, for conventional capacitor elements, since the N-well layer is directly connected to the lower plate of the capacitor element, the parasitic capacitance to ground C is... NW It is short-circuited. Therefore, when s = jω, the impedance Z1 of the N-well layer is Z1 = 1 / (s C). BOX ).

[0039] In contrast, the impedance Z2 of the N-well layer 15 in the capacitor element C of this embodiment is Z2 = 1 / (s C) BOX )+1 / (sC W +1 / R). Therefore, if set to s C BOX Since >> 1 / R, the value of 1 / R can be ignored in the calculation of impedance Z2. Therefore, impedance Z2 is essentially capacitance C. W With capacitor C BOX The value obtained by connecting in series.

[0040] Since Z2≈1 / (s C) BOX )+1 / (sC W Therefore, Z2 < Z1. This reduces the impact of the BOX capacitor and prevents a decrease in power conversion efficiency.

[0041] Figure 4 The simulation results are shown in the figure. The horizontal axis represents the ratio of the BOX capacitor to the capacitance of the capacitor element C itself, i.e., the main capacitor. As this ratio increases, the power conversion efficiency of the switched capacitor power supply circuit tends to decrease. In the conventional structure, the efficiency at the maximum ratio is 34.51%, while in the structure of this embodiment, the efficiency increases to 44.22%, confirming an improvement in power conversion efficiency.

[0042] As described above, according to this embodiment, in the switched capacitor power supply circuit 1 composed of integrated circuits, the N-well layer 15 located on the lower layer of each capacitor element C1 to C5 is connected to a potential point at the same potential as the semiconductor substrate 11 via a resistor element R. In this way, by simply adding a resistor element R, the influence of the BOX capacitor can be reduced and the reduction in power conversion efficiency can be prevented.

[0043] (Second Implementation)

[0044] Hereinafter, the same reference numerals will be used for parts that are the same as in the first embodiment, and their descriptions will be omitted; the different parts will be described. Figure 5 In the switched capacitor power supply circuit 21 of the second embodiment shown, resistors R1 to R3 are omitted. Furthermore, the upper end of resistor R4 is connected to the N-well layer 15 corresponding to capacitors C2 and C4, and the upper end of resistor R5 is connected to the N-well layer 15 corresponding to capacitors C1, C3, and C5.

[0045] That is, capacitor elements C1, C3, and C5, and capacitor elements C2 and C4 are charged and discharged by clock signals of the same phase. Therefore, the potentials of their respective N-well layers 15 can be common, thus reducing the number of resistors to only R4 and R5.

[0046] (Third Implementation)

[0047] Figure 6The switched capacitor power supply circuit 22 of the third embodiment shown is applied to a LADDER-type 4:1 buck converter, and for example, four groups of FETs 2 and FET 3 are connected in series. A capacitor element C7 is connected between the drain of FET 2 (4) and FET 3 (4) and the drain of FET 2 (3) and FET 3 (3). A capacitor element C6 is connected between the drain of FET 2 (3) and FET 3 (3) and the drain of FET 2 (2) and FET 3 (2). A capacitor element C5 is connected between the drain of FET 2 (2) and FET 3 (2) and the drain of FET 2 (1) and FET 3 (1). The N-well layers corresponding to capacitor elements C5 to C7 are grounded via resistor elements R5 to R7, respectively.

[0048] According to the third embodiment configured as described above, it can also be applied to a LADDER-type switched capacitor power supply circuit 22.

[0049] In addition to the inventions described in the claims, this application also includes the following inventions.

[0050] (1) A switched capacitor power supply circuit, which is composed of an integrated circuit, uses multiple clock signals with different phases to charge and discharge multiple capacitor elements (C1 to C5) via multiple switching elements (2 to 7) to convert the input voltage into a specified output voltage. The well layer (15) located on the lower layer of the capacitor element is connected to a potential point below the potential of the semiconductor substrate (11) constituting the integrated circuit via a load circuit (R).

[0051] (2) According to the switched capacitor power supply circuit of (1), the load circuit is connected to the well layer corresponding to all of the plurality of capacitor elements.

[0052] (3) According to the switched capacitor power supply circuit of (1) or (2), the well layer corresponding to the capacitor element group whose charging and discharging timing is equal to that of the plurality of capacitor elements is wired to the same potential, and the load circuit is connected to each of the capacitor element groups.

[0053] (4) The switched capacitor power supply circuit according to any one of (1) to (3), wherein the load circuit is a passive element formed on the wiring layer.

[0054] (Other implementation methods)

[0055] In various embodiments, the number of FET2 and FET3 connected in series can be appropriately varied according to the individual design. Furthermore, it can also be applied to a series-parallel configuration. The well layer can be a P-well layer, in which case the semiconductor substrate can also be P-type. The electrode shape of the capacitor element is not limited to a comb-shaped design. The load circuit can also be a multi-resistor element, a metal resistor element, other reverse-connected diodes, etc., as long as it is a passive element with at least a resistive component. The potential of the connection point of the load circuit can also be lower than the potential of the semiconductor substrate. The switching element is not limited to MOSFETs.

[0056] This disclosure has been described with reference to embodiments. However, this disclosure is not limited to these embodiments and constructions. This disclosure also includes various modifications and equivalent variations. Furthermore, various combinations and forms, and thus other combinations and forms that include only one element, more than one element, or less than one element, also fall within the scope and spirit of this disclosure.

Claims

1. A switched capacitor power supply circuit, composed of integrated circuits, which converts an input voltage into a specified output voltage by using multiple clock signals with different phases to charge and discharge multiple capacitor elements via multiple switching elements. The well layer located below the capacitor element is connected to a potential point below the potential of the semiconductor substrate constituting the integrated circuit via a load circuit.

2. The switched capacitor power supply circuit as described in claim 1, The load circuit is connected to the well layer corresponding to all of the plurality of capacitor elements.

3. The switched capacitor power supply circuit as described in claim 1, The well layers corresponding to the capacitor groups with the same charging and discharging timing as the plurality of capacitor elements are wired to the same potential. The load circuit is connected to each of the capacitor element groups.

4. The switched capacitor power supply circuit as described in any one of claims 1 to 3, The load circuit is a passive component formed on the wiring layer.

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