Low-temperature-drift high-precision on-chip oscillator circuit capable of being trimmed

Abstract

The invention relates to the technical field of oscillators, in particular to a low-temperature-drift high-precision on-chip oscillator circuit capable of being trimmed, which comprises a reference bias circuit, a temperature compensation resistor module, a current trimming module and an RC oscillating circuit, wherein the reference bias circuit is used for generating a reference current and a comparator reference current, and converting the reference current into a reference voltage through the temperature compensation resistor module; the current trimming module is used for converting the comparator reference current into a charging current; the RC oscillating circuit is used for outputting a clock signal according to the reference voltage and the charging current. The circuit disclosed by the invention is simple in structure and easy to integrate, improves the temperature, process and power supply stability of the oscillator circuit, and can be widely applied to an SOC system.

Description

Technical Field

[0001] This disclosure relates to the field of oscillator technology, and more particularly to an adjustable, low-temperature drift, high-precision on-chip oscillator circuit. Background Technology

[0002] With the rapid development of the semiconductor electronics industry, the integration level of integrated circuits is becoming increasingly higher, and the requirements for chip miniaturization and refinement are also gradually increasing. Currently, clock frequency reference sources are an important component of digital and mixed-signal circuits and SOC systems. In systems requiring high precision and high stability, the role of the clock becomes even more critical. Quartz crystal oscillators are commonly used to provide a high-precision reference clock for the system, but they are not easily integrated monolithically with other circuit components. Therefore, on-chip reference clock circuits have been widely used in various integrated circuit applications, such as implantable medical devices, sensor networks, and portable mobile devices.

[0003] RC oscillators are harmonic oscillators that utilize the periodic charging and discharging of a capacitor. Compared to crystal oscillators, they offer significant advantages such as low cost, low power consumption, and ease of integration, making them the primary choice for on-chip clock sources. However, the output frequency of a typical RC oscillator is susceptible to drift due to variations in process technology, power supply voltage, and external temperature, failing to meet the high precision and stability requirements of SOC chips for clock signals. Therefore, the impact of temperature and power supply voltage on the output frequency of RC oscillators has become a key focus. Among related technologies, RC oscillators suffer from issues of low accuracy and large temperature drift. Summary of the Invention

[0004] To address the aforementioned technical issues, this disclosure provides an adjustable, low-temperature drift, high-precision on-chip oscillator circuit. The circuit has a simple structure, is easy to integrate, and improves the temperature, process, and power supply stability of the oscillator circuit. It can be widely used in SOC systems.

[0005] This disclosure provides an adjustable, low-temperature drift, high-precision on-chip oscillator circuit, comprising: a reference bias circuit, a temperature compensation resistor module, a current adjustment module, and an RC oscillation circuit; wherein, the reference bias circuit is used to generate a reference current and a comparator reference current, and converts the reference current into a reference voltage through the temperature compensation resistor module; the current adjustment module is used to convert the comparator reference current into a charging current; and the RC oscillation circuit is used to output a clock signal based on the reference voltage and the charging current.

[0006] In some embodiments, the reference bias circuit includes a startup circuit, a reference circuit, and a bias circuit; wherein the startup circuit is used to control the reference circuit to generate a negative temperature coefficient current and a positive temperature coefficient current; the bias circuit is used to weight and sum the negative temperature coefficient current and the positive temperature coefficient current according to a ratio to generate a reference current and a comparator reference current.

[0007] In some embodiments, the startup circuit includes a first to a fourth transistor and a first capacitor; one plate of the first capacitor is electrically connected to the first node, and the other plate of the first capacitor is grounded; the first to fourth transistors are used to adjust the signals of the second node and the third node based on the enable signal and the signal of the first node.

[0008] In some embodiments, the gate of the first transistor is electrically connected to the second node, the source of the first transistor is electrically connected to the first power supply signal terminal, and the drain of the first transistor is electrically connected to the first node; the second transistor and the third transistor are connected in series between the first power supply signal terminal and the third node, the gate of the second transistor is electrically connected to the first node, and the gate of the third transistor is connected to an enable signal; the gate of the fourth transistor is connected to an enable signal, the source of the fourth transistor is grounded, and the drain of the fourth transistor is electrically connected to the first node.

[0009] In some embodiments, the reference circuit includes a first current branch and a second current branch. The first current branch includes a fifth to an eighth transistor and a negative temperature coefficient resistor, and the first current branch is used to generate a negative temperature coefficient current. The second current branch includes a ninth to a twelfth transistor and a positive temperature coefficient resistor, and the second current branch is used to generate a positive temperature coefficient current.

[0010] In some embodiments, a negative temperature coefficient resistor, a fifth transistor, and a seventh transistor are connected in series between a first power supply signal terminal and ground; a sixth transistor and an eighth transistor are connected in series between a first power supply signal terminal and ground; and the seventh and eighth transistors form a current mirror structure. A ninth to eleventh transistor are connected in series between a first power supply signal terminal and ground; a twelfth transistor and a positive temperature coefficient resistor are connected in series between a first power supply signal terminal and ground; and the eleventh and twelfth transistors form a current mirror structure. A second node is electrically connected to the gates of the seventh and eighth transistors and to the drain of the fifth transistor. A third node is electrically connected to the gates of the ninth and tenth transistors and to the drains of the sixth and eighth transistors.

[0011] In some embodiments, the bias circuit includes a set of reference current output circuits and at least one set of comparator reference current output circuits; the reference current output circuit includes a thirteenth transistor and a fourteenth transistor connected in parallel, the gate of the thirteenth transistor being electrically connected to a first current branch, and the gate of the fourteenth transistor being electrically connected to a second current branch; the comparator reference current output circuit includes a fifteenth transistor and a sixteenth transistor connected in parallel, the gate of the fifteenth transistor being electrically connected to the first current branch, and the gate of the sixteenth transistor being electrically connected to the second current branch.

[0012] In some embodiments, the first to third transistors, the seventh transistor, the eighth transistor, and the eleventh to sixteenth transistors are P-type transistors; the fourth to sixth transistors, the ninth transistor, and the tenth transistor are N-type transistors.

[0013] In some embodiments, the temperature compensation resistor module includes a positive temperature coefficient resistor and / or a negative temperature coefficient resistor; the temperature compensation resistor module is connected in series between the reference current output circuit and ground.

[0014] In some embodiments, the current adjustment module includes a comparator reference current branch and at least one adjustment current branch; the comparator reference current branch includes a seventeenth to a twentieth transistor, the seventeenth and eighteenth transistors forming a current mirror structure, the nineteenth and twentieth transistors forming a current mirror structure, the drain of the seventeenth transistor receiving the comparator reference current, and the drain of the eighteenth transistor being electrically connected to the drain of the nineteenth transistor; the adjustment current branch includes a twenty-first and a twenty-second transistor connected in series, the gate of the twenty-first transistor being electrically connected to the drain of the twenty-second transistor, the gate of the twenty-second transistor being connected to a digital control signal; and the drain of the twentieth transistor being electrically connected to the drain of the twenty-second transistor.

[0015] In some embodiments, the seventeenth and eighteenth transistors are N-type transistors, and the nineteenth to twenty-second transistors are P-type transistors.

[0016] In some embodiments, the RC oscillation circuit includes a comparator, a flip-flop, a second capacitor, a twenty-third transistor, and an inverter; the first plate of the second capacitor receives the charging current, and the second plate of the second capacitor is grounded; the twenty-third transistor is connected in parallel with the second capacitor, and the gate of the twenty-third transistor is electrically connected to the clock input terminal of the flip-flop; the positive input terminal of the comparator is electrically connected to the first plate of the second capacitor, the negative input terminal of the comparator receives a reference voltage, and the output terminal of the comparator is electrically connected to the clock input terminal of the flip-flop; the output terminal of the flip-flop outputs a clock signal; an inverter is connected between the output terminal of the comparator and the clock input terminal of the flip-flop, between the gate of the twenty-third transistor and the clock input terminal of the flip-flop, and at the output terminal of the flip-flop.

[0017] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0018] The adjustable, low-temperature-drift, high-precision on-chip oscillator circuit disclosed herein includes a reference bias circuit, a temperature compensation resistor module, a current adjustment module, and an RC oscillation circuit. The circuit structure is simple and easy to integrate. The reference bias circuit generates a zero-temperature-coefficient reference current and a comparator reference current. It also converts the reference current into a reference voltage via the temperature compensation resistor module to compensate for temperature drift caused by comparator delay in the RC oscillation circuit. The current adjustment module converts the comparator reference current into a charging current. The RC oscillation circuit outputs a clock signal based on the reference voltage and charging current. Since the charging current is generated based on the comparator reference current and the reference voltage is generated based on the reference current, the charging current and reference voltage are unaffected by temperature and voltage. Furthermore, the reference voltage is generated by the temperature compensation resistor module after compensating for temperature drift caused by comparator delay in the RC oscillation circuit. This improves the temperature, process, and power supply stability of the oscillator circuit, making it widely applicable in SOC systems. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a modifiable, low-temperature drift, high-precision on-chip oscillator circuit provided in this disclosure;

[0022] Figure 2 This is a temperature compensation resistor module and a circuit diagram of the temperature compensation resistor module provided in this disclosure;

[0023] Figure 3 This is a circuit diagram of a current adjustment module provided in this disclosure;

[0024] Figure 4 This is a circuit diagram of an RC oscillation circuit provided in this disclosure. Detailed Implementation

[0025] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0026] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0027] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0028] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0029] Unless otherwise stated, the term "multiple" means two or more.

[0030] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0031] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0032] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0033] Figure 1 This is a schematic diagram of a modifiable, low-temperature drift, high-precision on-chip oscillator circuit disclosed herein, for reference. Figure 1 This disclosure provides an adjustable, low-temperature drift, high-precision on-chip oscillator circuit, comprising: a reference bias circuit 10, a temperature compensation resistor module 20, a current adjustment module 30, and an RC oscillation circuit 40; wherein,

[0034] The reference bias circuit 10 is used to generate a reference current Iref1 and a comparator reference current Iref2, and converts the reference current Iref1 into a reference voltage Vref through the temperature compensation resistor module 20;

[0035] The current trimming module 30 is used to convert the comparator reference current Iref2 into the charging current Icharge;

[0036] The RC oscillation circuit 40 is used to output a clock signal based on the reference voltage Vref and the charging current Icharge.

[0037] Specifically, this disclosure provides an adjustable, low-temperature-drift, high-precision on-chip oscillator circuit. The circuit includes a reference bias circuit 10, a temperature compensation resistor module 20, a current adjustment module 30, and an RC oscillation circuit 40. The circuit structure is simple and easy to integrate. The reference bias circuit 10 generates a zero-temperature-coefficient reference current Iref1 and a comparator reference current Iref2. The reference bias circuit 10 also converts the reference current Iref1 into a reference voltage Vref through the temperature compensation resistor module 20 to compensate for the temperature drift caused by the comparator delay in the RC oscillation circuit 40. The current adjustment module 30 converts the comparator reference current Iref2 into a charging current Icharge. The RC oscillation circuit 40 is used to output a clock signal based on the reference voltage Vref and the charging current Icharge. Since the charging current Icharge is generated based on the comparator reference current Iref2 and the reference voltage Vref is generated based on the reference current Iref1, the charging current Icharge and the reference voltage Vref are not affected by temperature and voltage. Moreover, the reference voltage Vref is generated by the temperature compensation resistor module 20 after compensating for the temperature drift caused by the comparator delay in the RC oscillation circuit 40, thereby improving the temperature, process, and power supply stability of the oscillator circuit, and can be widely used in SOC systems.

[0038] Figure 2 This disclosure provides a temperature compensation resistor module and a circuit diagram of the temperature compensation resistor module. (Refer to...) Figure 1 and Figure 2 In some optional embodiments, the reference bias circuit 10 includes a startup circuit 11, a reference circuit 12, and a bias circuit 13; wherein,

[0039] The starting circuit 11 is used to control the reference circuit 12 to generate a negative temperature coefficient current I. PTAT and positive temperature coefficient current I CTAT ;

[0040] Bias circuit 13 is used to convert the negative temperature coefficient current I PTAT and positive temperature coefficient current I CTAT The reference current Iref1 and the comparator reference current Iref2 are generated by weighting them proportionally.

[0041] Specifically, the reference bias circuit 10 includes a startup circuit 11, a reference circuit 12, and a bias circuit 13. The startup circuit 11 controls the state of the reference circuit 12, causing the reference circuit 12 to generate a negative temperature coefficient current I. PTAT and positive temperature coefficient current I CTAT The bias circuit 13 is used to convert the negative temperature coefficient current I... PTAT and positive temperature coefficient current I CTAT The reference current Iref1 and the comparator reference current Iref2 are generated by weighting them proportionally. As a result, both the reference current Iref1 and the comparator reference current Iref2 are zero-temperature coefficient currents. The reference current Iref1 and the comparator reference current Iref2 are not affected by temperature and voltage. Therefore, the reference voltage Vref and the charging current Icharge generated based on the reference current Iref1 and the comparator reference current Iref2 are not affected by temperature and voltage, which can compensate for the temperature drift caused by the comparator delay in the RC oscillation circuit 40.

[0042] Continue to refer to Figure 1 and Figure 2 In some alternative embodiments, the startup circuit 11 includes first to fourth transistors MP0-MP2, MN0 and a first capacitor C0;

[0043] One plate of the first capacitor C0 is electrically connected to the first node A, and the other plate of the first capacitor C0 is grounded.

[0044] The first to fourth transistors MP0-MP2 are used to regulate the signals of the second node B and the third node C based on the enable signal ENN and the signal of the first node A.

[0045] Specifically, the startup circuit 11 includes first to fourth transistors MP0-MP2, MN0, and a first capacitor C0. The first capacitor C0 is used to maintain the potential of the first node A. The first to fourth transistors MP0-MP2 are used to adjust the signals of the second node B and the third node C based on the enable signal ENN and the signal of the first node A, thereby controlling the state of the reference circuit 12 through the signals of the second node B and the third node C. That is, the startup circuit 11 is used to ensure that the circuit can start up quickly before the reference circuit outputs the negative temperature coefficient current IPTAT and the positive temperature coefficient current ICTAT, and to control the state of the reference circuit 12 so that the reference circuit 12 generates the negative temperature coefficient current IPTAT and the positive temperature coefficient current ICTAT. After the reference circuit 12 generates the negative temperature coefficient current IPTAT and the positive temperature coefficient current ICTAT, the startup circuit 11 is turned off.

[0046] Continue to refer to Figure 1 and Figure 2In some alternative embodiments, the gate of the first transistor MP0 is electrically connected to the second node B, the source of the first transistor MP0 is electrically connected to the first power supply signal terminal VDD, and the drain of the first transistor MP0 is electrically connected to the first node A.

[0047] The second transistor MP1 and the third transistor MP2 are connected in series between the first power supply signal terminal VDD and the third node C. The gate of the second transistor MP1 is electrically connected to the first node A, and the gate of the third transistor MP2 is connected to the enable signal ENN.

[0048] The gate of the fourth transistor MN0 is connected to the enable signal ENN, the source of the fourth transistor MN0 is grounded, and the drain of the fourth transistor MN0 is electrically connected to the first node A.

[0049] It should be noted that, Figure 2 The example shown is one circuit of the startup circuit 11. In other embodiments of this disclosure, the startup circuit 11 may also employ other circuit structures to control the state of the reference circuit 12, causing the reference circuit 12 to generate a negative temperature coefficient current I. PTAT and positive temperature coefficient current I CTAT This will not be elaborated upon further here.

[0050] Continue to refer to Figure 1 and Figure 2 In some alternative embodiments, the reference circuit 12 includes a first current branch and a second current branch. The first current branch includes fifth to eighth transistors MN1, MN2, MP3, MP4 and a negative temperature coefficient resistor R0. The first current branch is used to generate a negative temperature coefficient current I. PTAT The second current branch includes transistors MN3, MN4, MP5, and MP6 (ninth to twelfth) and a positive temperature coefficient resistor R1. This second current branch is used to generate a positive temperature coefficient current I. CTAT .

[0051] Specifically, the reference circuit 12 includes a first current branch, which is used to generate a negative temperature coefficient current I. PTAT The first current branch includes transistors MN1, MN2, MP3, and MP4 (fifth to eighth) and a negative temperature coefficient resistor R0. The reference circuit 12 also includes a second current branch, which generates a positive temperature coefficient current I. CTAT The second current branch includes the ninth to twelfth transistors MN3, MN4, MP5, MP6 and the positive temperature coefficient resistor R1.

[0052] Continue to refer to Figure 1 and Figure 2In some alternative embodiments, the negative temperature coefficient resistor R0, the fifth transistor MN1 and the seventh transistor MP3 are connected in series between the first power supply signal terminal VDD and ground, the sixth transistor MN2 and the eighth transistor MP4 are connected in series between the first power supply signal terminal VDD and ground, and the seventh transistor MP3 and the eighth transistor MP4 form a current mirror structure.

[0053] The ninth to eleventh transistors MN3, MN4, and MP5 are connected in series between the first power signal terminal VDD and ground. The twelfth transistor MP6 and the positive temperature coefficient resistor R1 are connected in series between the first power signal terminal VDD and ground. The eleventh transistor MP5 and the twelfth transistor MP6 form a current mirror structure.

[0054] The second node B is electrically connected to the gates of the seventh transistor MP3 and the eighth transistor MP4, and is also electrically connected to the drain of the fifth transistor MN1.

[0055] The third node C is electrically connected to the gates of the ninth transistor MN3 and the tenth transistor MN4, and is electrically connected to the drains of the sixth transistor MN2 and the eighth transistor MP4.

[0056] Specifically, the reference circuit 12 includes a first current branch, which is used to generate a negative temperature coefficient current I. PTAT The first current branch includes transistors MN1, MN2, MP3, and MP4 (from the fifth to the eighth) and a negative temperature coefficient resistor R0. The negative temperature coefficient resistor R0, transistor MN1, and transistor MP3 are connected in series between the first power supply signal terminal VDD and ground. One end of the negative temperature coefficient resistor R0 is grounded, and the other end is electrically connected to the source of transistor MN1. The drain of transistor MN1 is electrically connected to the drain of transistor MP3, and the source of transistor MP3 is electrically connected to the first power supply signal terminal VDD. Transistors MN2 and MP4 are connected in series between the first power supply signal terminal VDD and ground. The source of transistor MN2 is grounded, and the drain of transistor MN2 is electrically connected to the drain of transistor MP4. The source of transistor MP4 is electrically connected to the first power supply signal terminal VDD. Transistors MP3 and MP4 form a current mirror structure, and the gates of both transistors MP3 and MP4 are electrically connected to the second node B.

[0057] The reference circuit 12 also includes a second current branch, which is used to generate a positive temperature coefficient current I. CTATThe second current branch includes transistors MN3, MN4, MP5, and MP6 (9th to 12th) and a positive temperature coefficient resistor R1. Transistors MN3, MN4, and MP5 (9th to 11th) are connected in series between the first power supply signal terminal VDD and ground. The source of transistor MN4 is grounded, and its drain is electrically connected to the source of transistor MN3. The drain of transistor MN3 is electrically connected to the drain of transistor MN5 (11th), and its source is electrically connected to the first power supply signal terminal VDD. Transistor MP6 (12th) and the positive temperature coefficient resistor R1 are connected in series between the first power supply signal terminal VDD and ground. The source of transistor MP6 is electrically connected to the first power supply signal terminal VDD, and its drain is electrically connected to one end of the positive temperature coefficient resistor R1, with the other end of R1 grounded. Transistors MP5 (11th) and MP6 (12th) form a current mirror structure, and their gates are both electrically connected to the drain of transistor MN3 (9th).

[0058] The gates of the fifth transistor MN1 and the sixth transistor MN2 are both electrically connected to the drain of the twelfth transistor MP6.

[0059] Continue to refer to Figure 1 and Figure 2 In some alternative embodiments, the bias circuit 13 includes a set of reference current output circuits and at least one set of comparator reference current output circuits;

[0060] The reference current output circuit includes a thirteenth transistor MP7 and a fourteenth transistor MP8 connected in parallel. The gate of the thirteenth transistor MP7 is electrically connected to the first current branch, and the gate of the fourteenth transistor MP8 is electrically connected to the second current branch.

[0061] The comparator reference current output circuit includes a fifteenth transistor MP9 and a sixteenth transistor MP10 connected in parallel. The gate of the fifteenth transistor MP9 is electrically connected to the first current branch, and the gate of the sixteenth transistor MP10 is electrically connected to the second current branch.

[0062] Specifically, the bias circuit 13 includes a set of reference current output circuits, which include a thirteenth transistor MP7 and a fourteenth transistor MP8 connected in parallel. The gate of the thirteenth transistor MP7 is electrically connected to the gates of the seventh transistor MP3 and the eighth transistor MP4. The gate of the fourteenth transistor MP8 is electrically connected to the gates of the eleventh transistor MP5 and the twelfth transistor MP6. The sources of the thirteenth transistor MP7 and the fourteenth transistor MP8 are electrically connected to the first power supply signal terminal VDD. The drains of the thirteenth transistor MP7 and the fourteenth transistor MP8 are electrically connected. The drains of the thirteenth transistor MP7 and the fourteenth transistor MP8 output a reference current Iref1, where Iref1 = α1IPTAT +β1I CTAT α1 is equal to the ratio of the channel width-to-length ratio of the thirteenth transistor MP7 to the channel width-to-length ratio of the seventh transistor MP3, and β1 is equal to the ratio of the channel width-to-length ratio of the fourteenth transistor MP8 to the channel width-to-length ratio of the eleventh transistor MP5.

[0063] Similarly, the bias circuit 13 includes at least one comparator reference current output circuit, which includes a fifteenth transistor MP9 and a sixteenth transistor MP10 connected in parallel. The gate of the fifteenth transistor MP9 is electrically connected to the gates of the seventh transistor MP3 and the eighth transistor MP4. The gate of the sixteenth transistor MP10 is electrically connected to the gates of the eleventh transistor MP5 and the twelfth transistor MP6. The sources of the fifteenth transistor MP9 and the sixteenth transistor MP10 are electrically connected to the first power supply signal terminal VDD. The drains of the fifteenth transistor MP9 and the sixteenth transistor MP10 are electrically connected. The drains of the fifteenth transistor MP9 and the sixteenth transistor MP10 output the comparator reference current Iref2, where Iref2 = α2I. PTAT +β2I CTAT α2 is equal to the ratio of the channel width-to-length ratio of the fifteenth transistor MP9 to the channel width-to-length ratio of the seventh transistor MP3, and β2 is equal to the ratio of the channel width-to-length ratio of the sixteenth transistor MP10 to the channel width-to-length ratio of the eleventh transistor MP5.

[0064] The output reference current Iref1 and comparator reference current Iref2 can be adjusted by adjusting the channel width-to-length ratio of the seventh transistor MP3, the eighth transistor MP4, and the eleventh to sixteenth transistors MP5-MP10.

[0065] Continue to refer to Figure 1 and Figure 2 In some embodiments, the first to third transistors MP0-MP2, the seventh transistor MP3, the eighth transistor MP4, and the eleventh to sixteenth transistors MP5-MP10 are P-type transistors;

[0066] The fourth to sixth transistors MN0-MN2, the ninth transistor MN3, and the tenth transistor are N-type transistors.

[0067] It should be noted that, in this embodiment, the first to third transistors MP0-MP2, the seventh transistor MP3, the eighth transistor MP4, and the eleventh to sixteenth transistors MP5-MP10 are P-type transistors, and the fourth to sixth transistors MN0-MN2, the ninth transistor MN3, and the tenth transistor are N-type transistors. In other embodiments of this disclosure, the first to sixteenth transistors may also be configured in other ways, which will not be described in detail here.

[0068] Combined with appendix Figure 1 and Figure 2 The working principle of the reference bias circuit 10 is described in detail. Since the voltage difference across the first capacitor C0 cannot change abruptly, the first node A initially remains at a low level, causing the second transistor MP1 to conduct. When enabled, the enable signal ENN is at a low level, the fourth transistor MN0 is turned off, and the third transistor MP2 is turned on. At this time, the potential of the third node C gradually increases, causing all transistors in the reference circuit 12 to conduct, and the first current branch can generate a negative temperature coefficient current I. PTAT The second current branch can generate a positive temperature coefficient current I. CTAT When the circuit is working normally, the potential of the second node B drops, the first transistor MP0 turns on, the first node A is pulled to a high level, the second transistor MP1 turns off, and the startup circuit 11 turns off.

[0069] Continue to refer to Figure 1 and Figure 2 In some alternative embodiments, the temperature compensation resistor module 20 includes a positive temperature coefficient resistor and / or a negative temperature coefficient resistor;

[0070] The temperature compensation resistor module 20 is connected in series between the reference current output circuit and ground.

[0071] Specifically, the comparator in the RC oscillation circuit 40 has a delay, which affects the final output frequency of the entire circuit, causing it to shift with changes in ambient temperature. The circuit provided in this embodiment includes a temperature compensation resistor module 20, which is connected in series between the drains of the thirteenth transistor MP7 and the fourteenth transistor MP8 in the reference current output circuit and ground. The temperature coefficient of the comparator delay in the RC oscillation circuit 40 can be obtained through preliminary simulation. By using resistors with positive and / or negative temperature coefficients in the temperature compensation resistor module 20 that have the opposite temperature coefficient to the comparator delay, the effect of the comparator delay is compensated. Thus, the reference voltage Vref converted from the reference current Iref1 by the reference bias circuit 10 through the temperature compensation resistor module 20 can compensate for the temperature drift caused by the comparator delay in the RC oscillation circuit 40, resulting in the RC oscillation circuit 40 ultimately outputting a zero-temperature-coefficient frequency. For example, when the comparator delay has a negative temperature coefficient, a set of resistor arrays with positive temperature coefficients is designed as temperature compensation resistor module 20 by linearly combining the resistors of positive temperature coefficient resistors and negative temperature coefficient resistors to compensate for the negative temperature coefficient effect caused by the comparator delay.

[0072] Figure 3 This is a circuit diagram of a current adjustment module provided in this disclosure, for reference. Figure 1 and Figure 3In some alternative embodiments, the current trimming module 30 includes a comparator reference current branch and at least one adjustment current branch;

[0073] The comparator reference current branch includes transistors MN5, MN6, MP11, and MP12 from the seventeenth to the twentieth. Transistor MN5 and transistor MN6 form a current mirror structure, and transistors MP11 and MP12 form a current mirror structure. The drain of transistor MN5 receives the comparator reference current Iref2, and the drain of transistor MN6 is electrically connected to the drain of transistor MP11.

[0074] The regulating current branch includes a 21st transistor MP13 and a 22nd transistor MP14 connected in series. The gate of the 21st transistor MP13 is electrically connected to the drain of the 22nd transistor MP14, and the gate of the 22nd transistor MP14 is connected to a digital control signal.

[0075] The drain of the twentieth transistor MP12 is electrically connected to the drain of the twenty-second transistor MP14.

[0076] Specifically, the current adjustment module 30 includes a comparator reference current branch, which includes transistors MN5, MN6, MP11, and MP12 from the seventeenth to the twentieth. Transistor MN5 and transistor MN6 form a current mirror structure, as do transistors MP11 and MP12. The drain of transistor MN5 receives the comparator reference current Iref2, and the drain of transistor MN6 is electrically connected to the drain of transistor MP11. Thus, the drain of transistor MP12 outputs the comparator reference current Iref2.

[0077] The current adjustment module 30 includes at least one current adjustment branch, which includes a 21st transistor MP13 and a 22nd transistor MP14 connected in series. The gate of the 21st transistor MP13 is electrically connected to the drain of the 22nd transistor MP14. The gate of the 22nd transistor MP14 is connected to a digital control signal. The 22nd transistor MP14 is turned on and off by the digital control signal, thereby controlling whether the current adjustment branch outputs the comparator reference current Iref2.

[0078] The drain of the twentieth transistor MP12 is electrically connected to the drain of the twenty-second transistor MP14. The charging current Icharge is output through the comparator reference current branch and the adjustment current branch, which are controlled by the digital control signal Itrim. <n:0>The on and off of the twenty-second transistor MP14 in each regulating current branch is determined, so as to control the size of the charging current Icharge, and ensure high-precision output of the oscillator circuit under different process angles.

[0079] It should be noted that the number of regulating current branches can be set according to the required current adjustment range, and the present disclosure does not make specific limitations thereon.

[0080] Reference Figure 1 and Figure 3 In some embodiments, the seventeenth transistor MN5 and the eighteenth transistor MN6 are N-type transistors, and the nineteenth to twenty-second transistors MP11-MP14 are P-type transistors.

[0081] It should be noted that the seventeenth transistor MN5 and the eighteenth transistor MN6 are N-type transistors, and the nineteenth to twenty-second transistors MP11-MP14 are P-type transistors in the exemplary embodiment, and the seventeenth to twenty-second transistors can also adopt other setting modes in other embodiments of the present disclosure, which will not be described one by one herein.

[0082] Figure 4 is a circuit diagram of an RC oscillation circuit provided by the present disclosure, reference Figure 1 and Figure 4 In some embodiments, the RC oscillation circuit 40 includes a comparator comp, a flip-flop D, a second capacitor C1, a twenty-third transistor MN7, and an inverter;

[0083] The first plate of the second capacitor C1 receives the charging current Icharge, and the second plate of the second capacitor C1 is grounded.

[0084] The twenty-third transistor MN7 is connected in parallel with the second capacitor C1, and the gate of the twenty-third transistor MN7 is electrically connected with the clock input end of the flip-flop D.

[0085] The positive input end of the comparator comp is electrically connected with the first plate of the second capacitor C1, the negative input end of the comparator comp receives a reference voltage Vref, and the output end of the comparator comp is electrically connected with the clock input end of the flip-flop D.

[0086] The output end of the flip-flop D outputs a clock signal CLK.

[0087] The output end of the comparator comp and the clock input end of the flip-flop D, the gate of the twenty-third transistor MN7 and the clock input end of the flip-flop D, and the output end of the flip-flop D are all connected with an inverter.

[0088] Specifically, the RC oscillation circuit 40 includes a comparator comp, a flip-flop D, a second capacitor C1, a twenty-third transistor MN7, and an inverter. The second capacitor C1 is charged by a charging current Icharge. The comparator comp compares the voltage on the second capacitor C1 with the reference voltage Vref. The output of the comparator comp is shaped by the inverter and fed back to the gate of the twenty-third transistor MN7, thereby controlling the conduction and turn-off of the twenty-third transistor MN7. This enables the second capacitor C1 to perform periodic charging and discharging, thus obtaining a periodic oscillating clock signal. Finally, the output is converted into a 50% duty cycle square wave clock signal CLK by the flip-flop D.

[0089] Wherein, the reference voltage Vref is equal to the reference current Iref1 multiplied by the resistance. The reference current Iref1 is not affected by temperature and voltage, and the charging current Icharge is also not affected by temperature and voltage. When the resistance and the second capacitor C1 are fixed, the oscillation frequency of the clock signal CLK is only related to the ratio of the charging current Icharge to the reference current Iref1. Therefore, the magnitude of the charging current can be precisely adjusted through the current adjustment network to control the output frequency at the target frequency.

[0090] For example, inverters INV1-INV3 are provided between the output of comparator comp and the clock input of flip-flop D, inverter INV4 is provided between the gate of the twenty-third transistor MN7 and the clock input of flip-flop D, and inverters INV5 and INV6 are connected to the output of flip-flop D. In other embodiments of this disclosure, the inverters in the RC oscillation circuit 40 may also adopt other configuration methods, which will not be described in detail here.

[0091] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0092] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0093] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0094] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A adjustable, low-temperature drift, high-precision on-chip oscillator circuit, characterized in that, include: The circuit includes a reference bias circuit, a temperature compensation resistor module, a current adjustment module, and an RC oscillation circuit; among which, The reference bias circuit is used to generate a reference current and a comparator reference current, and converts the reference current into a reference voltage through the temperature compensation resistor module. The current adjustment module is used to convert the comparator reference current into a charging current. The RC oscillation circuit is used to output a clock signal based on the reference voltage and the charging current.

2. The circuit according to claim 1, characterized in that, The reference bias circuit includes a startup circuit, a reference circuit, and a bias circuit; wherein, The startup circuit is used to control the reference circuit to generate negative temperature coefficient current and positive temperature coefficient current; The bias circuit is used to weight and sum the negative temperature coefficient current and the positive temperature coefficient current according to a ratio to generate the reference current and the comparator reference current.

3. The circuit according to claim 2, characterized in that, The startup circuit includes first to fourth transistors and a first capacitor; One plate of the first capacitor is electrically connected to the first node, and the other plate of the first capacitor is grounded. The first to fourth transistors are used to adjust the signals of the second and third nodes based on the enable signal and the signal of the first node.

4. The circuit according to claim 3, characterized in that, The gate of the first transistor is electrically connected to the second node, the source of the first transistor is electrically connected to the first power signal terminal, and the drain of the first transistor is electrically connected to the first node. The second transistor and the third transistor are connected in series between the first power signal terminal and the third node. The gate of the second transistor is electrically connected to the first node, and the gate of the third transistor is connected to the enable signal. The gate of the fourth transistor is connected to the enable signal, the source of the fourth transistor is grounded, and the drain of the fourth transistor is electrically connected to the first node.

5. The circuit according to claim 4, characterized in that, The reference circuit includes a first current branch and a second current branch. The first current branch includes a fifth to an eighth transistor and a negative temperature coefficient resistor. The first current branch is used to generate the negative temperature coefficient current. The second current branch includes a ninth to a twelfth transistor and a positive temperature coefficient resistor. The second current branch is used to generate the positive temperature coefficient current.

6. The circuit according to claim 5, characterized in that, The negative temperature coefficient resistor, the fifth transistor, and the seventh transistor are connected in series between the first power signal terminal and ground; the sixth transistor and the eighth transistor are connected in series between the first power signal terminal and ground; and the seventh transistor and the eighth transistor form a current mirror structure. The ninth to eleventh transistors are connected in series between the first power signal terminal and ground, the twelfth transistor and the positive temperature coefficient resistor are connected in series between the first power signal terminal and ground, and the eleventh transistor and the twelfth transistor form a current mirror structure. The second node is electrically connected to the gates of the seventh and eighth transistors and to the drain of the fifth transistor; The third node is electrically connected to the gates of the ninth and tenth transistors and to the drains of the sixth and eighth transistors.

7. The circuit according to claim 6, characterized in that, The bias circuit includes a set of reference current output circuits and at least one set of comparator reference current output circuits. The reference current output circuit includes a thirteenth transistor and a fourteenth transistor connected in parallel. The gate of the thirteenth transistor is electrically connected to the first current branch, and the gate of the fourteenth transistor is electrically connected to the second current branch. The comparator reference current output circuit includes a fifteenth transistor and a sixteenth transistor connected in parallel. The gate of the fifteenth transistor is electrically connected to the first current branch, and the gate of the sixteenth transistor is electrically connected to the second current branch.

8. The circuit according to claim 7, characterized in that, The first to third transistors, the seventh transistor, the eighth transistor, and the eleventh to sixteenth transistors are P-type transistors; The fourth to sixth transistors, the ninth transistor, and the tenth transistor are N-type transistors.

9. The circuit according to claim 7, characterized in that, The temperature compensation resistor module includes positive temperature coefficient resistors and / or negative temperature coefficient resistors; The temperature compensation resistor module is connected in series between the reference current output circuit and ground.

10. The circuit according to claim 1, characterized in that, The current adjustment module includes a comparator reference current branch and at least one adjustment current branch. The comparator reference current branch includes the seventeenth to the twentieth transistors. The seventeenth and eighteenth transistors form a current mirror structure, and the nineteenth and twentieth transistors form a current mirror structure. The drain of the seventeenth transistor receives the comparator reference current, and the drain of the eighteenth transistor is electrically connected to the drain of the nineteenth transistor. The regulating current branch includes a 21st transistor and a 22nd transistor connected in series. The gate of the 21st transistor is electrically connected to the drain of the 22nd transistor, and the gate of the 22nd transistor is connected to a digital control signal. The drain of the twentieth transistor is electrically connected to the drain of the twentieth transistor.

11. The circuit according to claim 10, characterized in that, The seventeenth and eighteenth transistors are N-type transistors, and the nineteenth to twenty-second transistors are P-type transistors.

12. The circuit according to claim 1, characterized in that, The RC oscillation circuit includes a comparator, a flip-flop, a second capacitor, a twenty-third transistor, and an inverter; The first plate of the second capacitor receives the charging current, and the second plate of the second capacitor is grounded. The 23rd transistor is connected in parallel with the 2nd capacitor, and the gate of the 23rd transistor is electrically connected to the clock input terminal of the flip-flop; The positive input terminal of the comparator is electrically connected to the first plate of the second capacitor, the negative input terminal of the comparator receives the reference voltage, and the output terminal of the comparator is electrically connected to the clock input terminal of the flip-flop. The clock signal is output from the output terminal of the trigger. The inverter is connected between the output of the comparator and the clock input of the flip-flop, between the gate of the 23rd transistor and the clock input of the flip-flop, and between the output of the flip-flop.

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