Doherty power amplifier with reconfigurable output circuit

Abstract

The invention relates to a Doherty power amplifier with a reconfigurable output circuit. A Doherty power amplifier includes a first amplifier having a first output capacitance, a second amplifier having a second output capacitance, a reconfigurable impedance inverter, and a variable output impedance converter. A reconfigurable impedance inverter includes a combining node and first, second, and third variable networks. The first variable network and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first output capacitance. A second variable network provides a series inductance between the first amplifier output and the combining node. A third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second output capacitance. The output impedance transformer includes a fourth variable network that establishes a combined node impedance. The first, second and third variable networks and the output impedance transformer may be reconfigured based on traffic loading conditions.

Description

TECHNICAL FIELD

[0001] Embodiments of the subject matter described herein relate generally to Doherty power amplifiers. BACKGROUND

[0002] For many years, Doherty power amplifiers have been one of the most popular amplifiers for cellular infrastructure applications, provided that the Doherty power amplifier is capable of providing high efficiency and linear amplification of high peak-to-average power ratio (PAPR) signals. A well-designed conventional Doherty power amplifier exhibits linear signal amplification over a range of average output power levels, where high efficiency amplification can be achieved in the high power operating region.

[0003] A conventional bidirectional Doherty power amplifier is configured such that the operating efficiency is higher in the high power operating region (i.e., above a first average output power level, P SAT , and a back-off efficiency peak occurs in the low power operating region (i.e., below a second average output power level, P BO , where P SAT and P BO are substantially fixed power levels. Linear and high efficiency amplification can be achieved at average output power levels ranging from just below P BO up to P SAT . However, in the low power operating region (i.e., below P BO ), only the carrier amplifier is active, and the average output power level decreases further below P BO , the amplifier efficiency decreases more rapidly. This low power region is characterized as low power inefficient because the load modulation associated with amplifier operation in the high power region is not maintained in the low power region. Thus, the operating efficiency of a conventional Doherty power amplifier is relatively low when operating at reduced average output power levels significantly below P BO .

[0004] High efficiency operation over a wide range of average output power levels is a desirable quality of a Doherty power amplifier. Therefore, what is needed is a Doherty power amplifier that exhibits high efficiency performance in the high power operating region, while also exhibiting high efficiency performance at significantly reduced average output power levels. SUMMARY

[0005] According to a first aspect of the present invention, there is provided a Doherty power amplifier, comprising:

[0006] a first amplifier having a first amplifier output, wherein the first amplifier is configured to produce an amplified first output signal, and the first amplifier output is characterized as a first amplifier output capacitance;

[0007] a second amplifier having a second amplifier output, wherein the second amplifier is configured to produce an amplified second output signal, and the second amplifier output is characterized as a second amplifier output capacitance;

[0008] a reconfigurable impedance inverter circuit comprising

[0009] a combining node configured to combine the amplified first output signal and the amplified second output signal, wherein the combining node is characterized as a combining node impedance,

[0010] a first variable network coupled to the first amplifier output, wherein the first variable network and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance,

[0011] a second variable network coupled between the first amplifier output and the combining node, wherein the second variable network is configured to provide a series inductance between the first amplifier output and the combining node, and

[0012] a third variable network coupled to the second amplifier output and the combining node, wherein the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance; and

[0013] an output impedance transformer coupled between the combining node and an output of the Doherty power amplifier, wherein the output impedance transformer comprises a fourth variable network configured to establish the combining node impedance.

[0014] In one or more embodiments, the first amplifier comprises a first power transistor having a first drain terminal and a first source terminal, wherein the first drain terminal corresponds to the first amplifier output;

[0015] the first amplifier output capacitance is a first drain-source capacitance between the first drain terminal and the first source terminal;

[0016] the second amplifier comprises a second power transistor having a second drain terminal and a second source terminal, wherein the second drain terminal corresponds to the second amplifier output; and

[0017] the second amplifier output capacitance is a second drain-source capacitance between the second drain terminal and the second source terminal.

[0018] In one or more embodiments, the first variable network comprises a first reconfigurable shunt inductance network coupled between the first amplifier output and a ground reference node; and

[0019] The third variable network includes a second reconfigurable shunt inductive network coupled between the second amplifier output and the ground reference node.

[0020] In one or more embodiments, the first variable network includes a number M of first reconfigurable shunt inductive branches, where M is an integer equal to or greater than 1, and a first one of the first reconfigurable shunt inductive branches includes a first inductor coupled in series with a first switching element; and

[0021] The third variable network includes the number M of second reconfigurable shunt inductive branches, and a first one of the second reconfigurable shunt inductive branches includes a second inductor coupled in series with a second switching element.

[0022] In one or more embodiments, the first variable network further includes a second shunt inductive branch having a third inductor coupled in series with a third switching element; and

[0023] The third variable network further includes a second shunt inductive branch having a fourth inductor coupled in series with a fourth switching element.

[0024] In one or more embodiments, the second variable network includes:

[0025] a first inductor coupled between the first amplifier output and the combination node; and

[0026] a first reconfigurable shunt inductive branch coupled in parallel with the first inductor, where the first reconfigurable shunt inductive branch includes a second inductor and a first switching element coupled in series between the first amplifier output and the combination node.

[0027] In one or more embodiments, the second variable network additionally includes:

[0028] a second reconfigurable shunt inductive branch coupled in parallel with the first inductor, where the second reconfigurable shunt inductive branch includes a third inductor and a second switching element coupled in series between the first amplifier output and the combination node.

[0029] In one or more embodiments, the second variable network includes:

[0030] a first transmission line segment coupled between the intermediate node and the combination node; and

[0031] a first reconfigurable shunt transmission line branch coupled in shunt with the first transmission line segment, wherein the first reconfigurable shunt transmission line branch includes a second transmission line segment and a first switching element coupled in series between the first amplifier output and the combining node.

[0032] In one or more embodiments, the second variable network additionally includes:

[0033] a second reconfigurable shunt transmission line branch coupled in shunt with the first transmission line segment, wherein the second reconfigurable shunt transmission line branch includes a third transmission line segment and a second switching element coupled in series between the first amplifier output and the combining node.

[0034] In one or more embodiments, the first transmission line segment is characterized by a first electrical length and a first characteristic impedance;

[0035] the second transmission line segment is characterized by the first electrical length; and

[0036] the third transmission line segment is characterized by the first electrical length.

[0037] In one or more embodiments, the second variable network includes:

[0038] a first inductor coupled between the first amplifier output and the combining node;

[0039] a second inductor coupled in series with the first inductor between the first amplifier output and the combining node; and

[0040] a first bypass switch coupled across the second inductor.

[0041] In one or more embodiments, the second variable network additionally includes:

[0042] a third inductor coupled in series with the first inductor and the second inductor; and

[0043] a second bypass switch coupled across the third inductor.

[0044] In one or more embodiments, the fourth variable network includes:

[0045] a phase shift element having a first end coupled to the combining node and a second end coupled to the output of the Doherty power amplifier;

[0046] a first variable capacitance circuit coupled between the first end of the phase shift element and a ground reference node; and

[0047] a second variable capacitance circuit coupled between the second end of the phase shift element and the ground reference node.

[0048] In one or more embodiments, the Doherty power amplifier additionally includes:

[0049] an amplifier controller coupled to the first, second, third, and fourth variable networks, wherein,

[0050] the amplifier controller is configured to receive a signal indicative of a full power state and, in response, provide first control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier in a first amplifier state in which the first amplifier effective output capacitance has a first capacitance value, the second amplifier effective output capacitance has a second capacitance value, the series inductance has a first inductance value, and the combined node impedance has a first impedance value, and

[0051] the amplifier controller is configured to receive a signal indicative of a first back-off power state and, in response, provide second control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier in a second amplifier state in which the first amplifier effective output capacitance has a third capacitance value less than the first capacitance value, the second amplifier effective output capacitance has a fourth capacitance value less than the second capacitance value, the series inductance has a second inductance value greater than the first inductance value, and the combined node impedance has a second impedance value greater than the first impedance value.

[0052] In one or more embodiments, the first amplifier is a carrier amplifier; and

[0053] the second amplifier is a peaking amplifier.

[0054] According to a second aspect of the application, there is provided a method of operating a Doherty power amplifier, comprising:

[0055] generating an amplified first output signal at a first amplifier output by a first amplifier, the first amplifier output characterized by a first amplifier output capacitance;

[0056] generating an amplified second output signal at a second amplifier output by a second amplifier, the second amplifier output characterized by a second amplifier output capacitance;

[0057] communicating the amplified first output signal through a first variable network and through a second variable network to a combined node, wherein

[0058] the first variable network is coupled to the first amplifier output,

[0059] the first variable network and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance, and

[0060] the second variable network is configured to provide a series inductance between the first amplifier output and the combining node;

[0061] the amplified second output signal is delivered to the combining node through a third variable network, wherein

[0062] the third variable network is coupled to the second amplifier output, and

[0063] the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance;

[0064] the first and second amplified output signals are combined at the combining node to produce an amplified combining output signal, wherein the combining node is characterized as a combining node impedance; and

[0065] the amplified combining output signal is delivered through an output impedance transformer coupled between the combining node and an output of the Doherty power amplifier, wherein the output impedance transformer includes a fourth variable network configured to establish the combining node impedance.

[0066] In one or more embodiments, the method further includes reconfiguring the Doherty power amplifier by:

[0067] reconfiguring the first variable network to modify the first amplifier effective output capacitance;

[0068] reconfiguring the second variable network to modify the series inductance between the first amplifier output and the combining node while the first variable network is being reconfigured;

[0069] reconfiguring the third variable network to modify the second amplifier effective output capacitance while the first variable network is being reconfigured; and

[0070] reconfiguring the fourth variable network to modify the combining node impedance while the first variable network is being reconfigured.

[0071] In one or more embodiments, reconfiguring the first variable network to modify the first amplifier effective output capacitance includes providing, by an amplifier controller, a first switch control signal to the first variable network, the first switch control signal causing at least one first switching element in the first variable network to change state;

[0072] reconfiguring the second variable network to modify the series inductance between the first amplifier output and the combining node includes providing, by the amplifier controller, a second switch control signal to the second variable network, the second switch control signal causing at least one second switch element in the second variable network to change state; and

[0073] reconfiguring the third variable network to modify the second amplifier effective output capacitance includes providing, by the amplifier controller, a third switch control signal to the third variable network, the third switch control signal causing at least one third switch element in the third variable network to change state.

[0074] In one or more embodiments, the method further includes:

[0075] receiving an amplifier state control signal indicative of at least one of a traffic loading condition, a power level, or an amplifier state; and

[0076] determining, by the amplifier controller, the first, second, and third control signals from a lookup table that associates values of the amplifier state control signal with states of the at least one first switch element, the at least one second switch element, and the at least one third switch element.

[0077] In one or more embodiments, the method further includes:

[0078] determining, by a base station controller, a current traffic loading condition of a system that includes the Doherty power amplifier;

[0079] generating, by the base station controller, the amplifier state control signal based on the current traffic loading condition; and

[0080] sending, by the base station controller, the amplifier state control signal to the amplifier controller.

[0081] These and other aspects of the application will become apparent from the embodiments described below, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0082] A more complete understanding of the subject matter can be obtained by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein like reference numerals indicate like elements in the figures, and by

[0083] Figure 1 is a simplified block diagram of an example communications device in which embodiments of a reconfigurable Doherty power amplifier can be incorporated;

[0084] Figure 2is a plot illustrating theoretical efficiency performance as a function of various output power levels for embodiments as reconfigurable Doherty power amplifiers;

[0085] Figure 3 is a schematic diagram of a reconfigurable Doherty power amplifier according to an example embodiment;

[0086] Figure 4 is a schematic diagram of a reconfigurable Doherty power amplifier according to another example embodiment;

[0087] Figure 5 is a schematic diagram of a reconfigurable Doherty power amplifier according to yet another example embodiment; and

[0088] Figure 6 is a flowchart of a method of operating a reconfigurable Doherty power amplifier according to an example embodiment. DETAILED DESCRIPTION

[0089] Doherty power amplifiers include, among other things, an amplifier input, a power divider, a carrier amplifier, a peaking amplifier, an output circuit having a combining node and an output impedance transformer, and an amplifier output. Embodiments of the present subject matter specifically include a "reconfigurable" Doherty power amplifier having a "reconfigurable" output circuit coupled between the output terminals (e.g., intrinsic drain terminals) of the carrier and peaking amplifiers and the amplifier output. The reconfigurability of the output circuit enables the establishment of the correct and proper impedances at the carrier and peaking output terminals over a wide range of average output power levels, thus enabling optimal signal amplification and combining over full average output power levels and reduced average output power levels.

[0090] As used herein, the term "reconfigurable" in the context of an output circuit means that the state (e.g., electrical characteristics and / or values) of components, nodes, and / or sub-circuits within the output circuit can be selectively changed during operation. According to one or more embodiments, the output circuit reconfigurability can be implemented for N discrete states (N > 2), resulting in enhanced Doherty efficiency operation at N power back-off levels. Thus, the reconfigurable Doherty power amplifier embodiments described herein can exhibit high efficiency operation at full average output power levels (e.g., at full saturated output power P SAT-F and high power regions between corresponding full back-off output power P BO-F and significantly reduced average output power levels (e.g., at output power levels below full back-off output power P BO-F .

[0091] As will be described in detail later, embodiments of the Doherty power amplifiers described herein are capable of being dynamically reconfigured into different amplifier states. In various embodiments, the Doherty amplifiers are electronically controlled into different amplifier states based on actual or expected traffic loading (e.g., based on how many users are communicating on the system or expected to communicate). For example, when a communication device including a reconfigurable Doherty power amplifier is handling (or expected to handle) a high amount of traffic (e.g., between 75% and 100% traffic loading), the system can determine that the reconfigurable Doherty power amplifier should be configured (or reconfigured) into a "full power state," in which the amplifier should be operating efficiently at a full average output power level. Conversely, when the amplifier system is handling (or expected to handle) a lower amount of traffic (e.g., less than 75% traffic loading), the system can determine that the reconfigurable Doherty power amplifier should be configured (or reconfigured) into a "fallback power state" (or one of a plurality of different fallback power states), in which the amplifier should be operating efficiently at a reduced average output power level. Either way, the system can generate a control signal that causes the reconfigurable Doherty power amplifier to be reconfigured into either the full power state or the fallback power state. In other words, according to some embodiments, traffic tracking can be performed on the traffic being handled by the amplifier system, and a selected amplifier state can be determined based on the instantaneous measured traffic loading. In other embodiments, relative traffic loading during various time ranges can be anticipated (rather than measured instantaneously), and an amplifier state can be selected based on the time information (e.g., the current time of day, the current day of the week, or based on some other time information). In yet other embodiments, an amplifier state can be selected based on other factors.

[0092] It is noted here that the various embodiments described herein provide reconfigurability of the Doherty amplifier based on actual or expected system traffic or traffic loading. These "traffic tracking" techniques are different from "envelope tracking" techniques, in which operation of the amplifier can be modified based on the instantaneous amplitude of a signal to be amplified by the system (e.g., a signal having a high PAPR). Envelope tracking techniques can include, for example, high-speed (e.g., on the order of a few nanoseconds) adjustment of transistor bias voltages based on the instantaneous signal amplitude. In contrast, the traffic tracking techniques discussed herein involve reconfiguring the amplifier output circuitry into different amplifier states based on actual or expected traffic loading, where each amplifier state corresponds to a different set of components and impedance values. With these traffic tracking techniques, transitions between amplifier states can be performed less frequently than with envelope tracking bias adjustments. For example, as will be described in greater detail later, some embodiments of traffic tracking-based circuit reconfiguration can be performed in response to dynamic traffic loading measurements taken every few milliseconds or longer. Other embodiments of traffic tracking-based circuit reconfiguration can be performed in response to expected traffic loading during predetermined time ranges (e.g., from midnight to 5 AM, from 5 AM to 9 AM, from 9 AM to 6 PM, and from 6 PM to midnight) and / or based on expected traffic loading on particular days (e.g., Monday through Friday or on weekends). Although envelope tracking techniques can be used in addition to the traffic tracking techniques described herein, inventive subject matter of embodiments of the present disclosure includes the use of traffic tracking techniques.

[0093] To provide context, Figure 1 is a simplified block diagram of an example communication device 100 in which embodiments of a reconfigurable Doherty power amplifier (e.g., amplifier 112) can be incorporated. For example, the communication device 100 can be implemented in a base station (not shown) of a cellular communication system (or in another device associated with a cellular or other type of communication system). The communication device 100 includes a baseband and intermediate frequency (IF) processing subsystem 101, a base station controller 103, a radio frequency (RF) transceiver 106, and an antenna 190.

[0094] The base station controller 103 includes hardware and associated software that is generally responsible for controlling operation of the communication device 100, including managing radio channels (e.g., allocating channels and optimizing utilization of available resources), performing mobile device handovers, and performing call setup, among other operations.

[0095] According to one or more embodiments, the base station controller 103 can periodically or continuously perform traffic loading measurements (traffic tracking) and can provide control signals 104 to the RF transceiver 106 based on the traffic loading measurements. Based on the control signals 104 from the base station controller 103, the RF transceiver 106 (and more specifically, the amplifier controller 114) can reconfigure the output circuit of the amplifier 112 into one of N amplifier states (N > 2), as will be discussed in greater detail later. The examples provided below assume that the number of amplifier states N is equal to 4. Based on the description herein, those skilled in the art will understand that the number of amplifier states N can be different (e.g., N = 2, N = 3, or N > 4).

[0096] According to one or more embodiments, the base station controller 103 can maintain a lookup table (see Table 1 below) that relates traffic loading ranges to power levels (and / or amplifier states). The number of discrete power levels and the number of traffic loading ranges can be equal to the number of amplifier states N.

[0097] Referring to Table 1 below, the base station controller 103 can periodically or continuously measure or determine the instantaneous traffic loading condition of the system and can compare the instantaneous traffic loading condition to one or more thresholds to determine which of the N traffic loading ranges (first column of Table 1) the instantaneous traffic loading condition belongs to. Each of the traffic loading ranges can correspond to one of the N power levels and / or amplifier states (second column of Table 1). The base station controller 103 can then provide a control signal (e.g., control signal 104) to the transmitter 107 that indicates the power level and / or amplifier state corresponding to the current traffic loading. As will be described in detail below, the transmitter 107 then configures (or reconfigures) the amplifier (e.g., amplifier 112) in response to the control signal.

[0098] Business load range Power level (amplifier state) 75％-100％ Full power (state 1) 50％-75％ First back-off power (state 2) 25％-50％ Second back-off power (state 3) 0％-25％ Third back-off power (state 4)

[0099] Table 1 - Traffic Loading to Amplifier State Table

[0100] According to one or more other example embodiments, the base station controller 103 can maintain a lookup table (see Table 2 below) that relates time-of-day ranges to power levels (and / or amplifier states). The number of discrete power levels and the number of time-of-day ranges can be equal to the number of amplifier states N.

[0101] Referring to Table 2 below, the base station controller 103 can determine which of the N time-of-day ranges (first column of Table 2) the current time-of-day falls within. Each time-of-day range can correspond to one of N power levels and / or amplifier states (second column of Table 2). The base station controller 103 can then provide a control signal (e.g., control signal 104) to the transmitter 107 indicating the power level and / or amplifier state corresponding to the current time-of-day. As will be described in detail below, the transmitter 107 then configures (or reconfigures) the amplifier (e.g., amplifier 112) in response to the control signal.

[0102] Time of day range Power level (amplifier state) 9 AM to 6 PM Full power (state 1) 6 PM to midnight First back-off power (state 2) 5 AM to 9 AM Second back-off power (state 3) Midnight to 5 AM Third back-off power (state 4)

[0103] Table 2 - Time-of-Day and Amplifier State Table

[0104] Referring again to Figure 1 , the baseband and IF processing subsystem 101 includes a transmit signal processor 102 and a receive signal processor 188. According to one or more embodiments, the transceiver 106 includes a transmitter 107, a circulator 180, an RF switch 184, and a receiver 186.

[0105] In a transmit mode of operation of the system 100, the transmit signal processor 102 of the baseband and IF processing subsystem 101 performs baseband and IF processing to produce an RF transmit signal 105. The transmitter 107 receives and amplifies the RF transmit signal 105 and produces an amplified RF transmit signal 113 that will ultimately be transmitted over the air by the antenna 190.

[0106] According to one or more embodiments, the transmitter 107 includes an RF signal input 108, a control signal input 109, a power amplifier 112, an amplifier controller 114, and an RF signal output 110. Through the RF signal input 108, the power amplifier 112 receives the RF transmit signal 105 from the transmit signal processor 102. According to one or more embodiments, the power amplifier 112 is a relatively high gain amplifier that amplifies the RF transmit signal 105 and produces the amplified RF transmit signal 113 at the RF signal output 110.

[0107] According to various embodiments, the power amplifier 112 can be a reconfigurable Doherty power amplifier (e.g., Doherty power amplifier 350, 450, 550) having a reconfigurable output circuit (e.g., output circuit 360, 460, 560) of the type described in U.S. Patent Application No. 13 / 097,871, entitled "Reconfigurable Doherty Power Amplifier," filed April 26, 2011, which is incorporated by reference herein in its entirety. Figures 3-5 Figures 3-5 ​amplifiers 300, 400, 500). As will be described in detail later, the configuration of the reconfigurable output circuit is established based on control signals 104 received from base station controller 103. As indicated above, control signals 104 can indicate a power level (e.g., full power, first back-off power, etc.) and / or an amplifier state (e.g., state 1, state 2, etc.). In accordance with one or more embodiments, amplifier controller 114 receives control signals 104 from base station controller 103 through control signal input 109 (e.g., a serial peripheral input (SPI) port or another suitable control signal interface). Based on control signals 104, amplifier controller 114 can determine additional control signals (e.g., through Figure 1 , 3 -5 of switches 115 of power amplifier 112) and provide them to power amplifier 112, which can cause power amplifier 112 to reconfigure its output circuit (e.g., output circuit 360, 460, 560 of power amplifiers 300, 400, 500). As will be described in greater detail later, the reconfigurable output circuit of power amplifier 112 enables power amplifier 112 to amplify RF transmit signals 105 in a linear and efficient manner over a wide range of average power levels and traffic loading conditions. Figures 3-5

[0108] Amplified RF transmit signals 113 generated at RF output 110 of transmitter 107 are communicated to circulator 180. Circulator 180 includes a transmitter port 181, an antenna port 182, and a receiver port 183. Amplified RF transmit signals 113 are received at transmitter port 181 of circulator 180. Circulator 180 can then communicate amplified RF transmit signals 113 to antenna port 182, which is coupled to antenna 190. Antenna 180 is configured to radiate amplified RF transmit signals 113 over an air interface.

[0109] Circulator 180 is characterized by a signal conduction directionality indicated by the arrows within the drawing of circulator 180. Essentially, RF signals are communicated between circulator ports 181-183 in the indicated direction (counterclockwise) and not the opposite direction (clockwise). Thus, during normal operation, signals can be communicated through circulator 180 from transmitter port 181 to antenna port 182 and from antenna port 182 to receiver port 183, but not directly from transmitter port 181 to receiver port 183 or from receiver port 183 to antenna port 182.

[0110] ​In the receive mode of operation, the antenna 190 can receive RF signals over the air interface and can provide the RF receive signal to the antenna port 182 of the circulator 180. The circulator 180 can then transmit the RF receive signal to the receiver port 183 of the circulator 180. The receiver port 183 of the circulator 180 can be coupled through the RF switch 184 to the receiver 186. The receiver 186 includes a receive amplifier 187 (e.g., a low noise amplifier) that amplifies the RF receive signal and provides the amplified RF receive signal to a receive signal processor 188 of the baseband and IF processing subsystem 101.

[0111] The RF switch 184 is optional, but desirably included to ensure good isolation for the receiver 186. In particular, in some cases, the circulator 180 can not be able to transmit signal energy received through the transmitter port 181 through the antenna port 182 to the antenna 190 when the transceiver 106 is in the transmit mode of operation. For example, the antenna 190 can be disconnected from the antenna port 182, or can otherwise be in a very high impedance state. In such cases, the circulator 180 can transmit energy from the transmitter 107 signal (i.e., signal energy received through the transmitter port 181) through the antenna port 182 to the receiver port 183. To avoid transmitting transmitter signal energy into the receiver 186 when the transceiver 106 is in the transmit mode, the RF switch 184 can operate as a fail-safe switch that couples any transmitter signal energy to a ground reference node (not shown) when the transceiver 106 is in the transmit mode.

[0112] Figure 1 The configuration of the communication device 100 shown in FIG. 1 is provided for purposes of context and example. In other embodiments, the circulator 180 can not be included, and an RF switch can instead be used to establish a signal path between the antenna 190 and the transmitter 107 or receiver 186 in a half-duplex fashion. Other modifications to the communication device 100 can also be made.

[0113] To better explain how the power amplifier 112 can be reconfigured to provide linear and high efficiency amplification over a wide range of average output power levels, reference is now made to Figure 2FIG. 2 is a graph 200 showing a plurality of power efficiency curves 210, 220, 230, 240, where each curve is associated with one of a plurality of amplifier states for an embodiment of a reconfigurable Doherty power amplifier. More specifically, the power efficiency curve 210 is associated with a first amplifier state (State 1) corresponding to a full average output power, the power efficiency curve 220 is associated with a second amplifier state (State 2) corresponding to a first back-off power, the power efficiency curve 230 is associated with a third amplifier state (State 3) corresponding to a second back-off power, and the power efficiency curve 240 is associated with a fourth amplifier state (State 4) corresponding to a third back-off power.

[0114] The horizontal axis of the graph 200 corresponds to output power (in dBm), and the vertical axis of the graph 200 corresponds to drain efficiency (in percent). Again, the example assumes that the number of amplifier states N is equal to 4, and thus, the graph 200 includes 4 power efficiency curves 210, 220, 230, 240. Based on the description herein, one of skill in the art will understand that the number of amplifier states N can be different (e.g., N = 2, N = 3, or N > 4), and correspondingly, the system can support a different number of power efficiency curves.

[0115] In the terminology used herein for Doherty power amplifiers, the "saturated output power" P SAT refers to the output power level at which the Doherty amplifier enters saturation, and the "back-off output power" P BO refers to a lower output power level along the same power efficiency curve at which the peaking amplifier of the Doherty power amplifier begins to conduct (e.g., typically between about 6 dBm to about 10 dBm below P SAT Each amplifier state causes the reconfigurable Doherty power amplifier to be characterized by a different saturated output power P SAT and a different back-off output power level P BO . Thus, each power efficiency curve 210, 220, 230, 240 is characterized by a different saturated output power P SAT and a different back-off output power level P BO .

[0116] As used herein, the "full" saturated output power P SAT-F means the theoretically highest saturated output power associated with an embodiment of a reconfigurable Doherty power amplifier configured in a "full output power" state. Similarly, as used herein, the "full" back-off output power P BO-F means the output power at which the amplifier is in a "full power" state (e.g., below the full saturated output power P SAT-Fa first efficiency peak occurs at P SAT-F The following power levels.

[0117] Conversely, "reduced" saturated output power P SAT-R means the saturated power associated with embodiments of the Doherty power amplifier in the "reduced output power" state. Thus, "reduced" back-off output power P BO-R means the power level at which a first efficiency peak occurs at a lower P SAT-R when the amplifier is in the "reduced output power" state.

[0118] Embodiments of the reconfigurable Doherty power amplifier discussed herein are configured to support a full output power state (corresponding to P SAT-F and P BO-F ) and one or more reduced output power states. In such embodiments, a particular reduced output power state can be indicated with a number in the suffix of P SAT-R and P BO-R . For example, the saturated output power and back-off output power for a first reduced output power state can be designated as P SAT-R1 and P BO-R1 , the saturated output power and back-off output power for a second (lower) reduced output power state can be designated as P SAT-R2 and P BO-R2 , the saturated output power and back-off output power for a third (lower) reduced output power state can be designated as P SAT-R3 and P BO-R3 , and so on. Other embodiments of the reconfigurable Doherty power amplifier can be configured to support only two amplifier states (i.e., N = 2), including a full output power state (corresponding to P SAT-F and P BO-F ), and only one reduced output power state (corresponding to P SAT-R and P BO-R ).

[0119] Referring to Figure 2 , power efficiency curve 210 corresponds to a full output power state (e.g., state 1). As indicated by curve 210, when an embodiment of the reconfigurable Doherty amplifier is in the full output power state, the full saturated output power P SAT-F is about 47 dBm, as indicated by circle 211, and the full back-off output power P BO-F is about 37 dBm, as indicated by point 212 (e.g., lower than the full saturated output power 211 P SAT-F(Approximately 10 dBm). Depending on various characteristics of the reconfigurable Dougherty amplifier (e.g., operating frequency, circuit topology, and other characteristics), the full-saturation output power and full-back output power may have values ​​higher or lower than those given above.

[0120] Power efficiency curve 220 corresponds to a first reduced output power state (e.g., state 2). As indicated by curve 220, when the embodiment of the reconfigurable Dougherty amplifier is in the first reduced output power state, the reduced saturated output power P SAT-R1 It is approximately 45 dBm, as indicated by circle 221 (e.g., below P). SAT-F Point 211 (approximately 3.0 dBm), and reduced backoff output power P BO-R1 It is approximately 35 dBm, as indicated by point 222 (e.g., below the reduced saturation output power 221P). SAT-R1 (Approximately 10 dBm). Similarly, depending on the various characteristics of the reconfigurable Dougherty amplifier, the first reduced saturation output power and the first reduced backoff output power may have values ​​higher or lower than those given above.

[0121] Power efficiency curve 230 corresponds to a second and further reduced output power state (e.g., state 3). As indicated by curve 230, when the embodiment of the reconfigurable Dougherty amplifier is in the second reduced output power state, the reduced saturated output power P SAT-R2 It is approximately 42 dBm, as indicated by circle 231 (e.g., below P). SAT-F Point 211 (approximately 6.0 dBm), and the second reduced backoff output power P BO-R2 It is approximately 32 dBm, as indicated by point 232 (e.g., below the second reduced saturation output power 231P). SAT-R2 (Approximately 10 dBm). Similarly, depending on the various characteristics of the reconfigurable Dougherty amplifier, the second reduced saturation output power and the second reduced back-off output power may have values ​​higher or lower than those given above.

[0122] Finally, power efficiency curve 240 corresponds to a third and further reduced output power state (e.g., state 4). As indicated by curve 240, when the embodiment of the reconfigurable Dougherty amplifier is in the third reduced output power state, the reduced saturated output power P SAT-R3 It is approximately 38 dBm, as indicated by circle 241 (e.g., below P). SAT-F Point 211 (approximately 10.0 dBm), and the third reduced backoff output power P BO-R3 It is approximately 28 dBm, as indicated by point 242 (e.g., below the third reduced saturation output power 241P). SAT-R3approximately 10 dBm). Again, depending on the various characteristics of the reconfigurable Doherty amplifier, the third reduced saturated output power and the third reduced backoff output power can have higher or lower values than those given above. Moreover, the reconfigurable Doherty amplifier can have more or less than three reduced output power states.

[0123] During operation of embodiments of the reconfigurable Doherty power amplifier, an amplifier state (e.g., the full output power state) having a power efficiency curve (e.g., curve 210) characterized by a relatively high P SAT and a relatively high corresponding P BO may be selected for higher traffic loading conditions in order to support amplification at high average output power levels. Conversely, an amplifier state (e.g., a reduced output power state) having a power efficiency curve (e.g., one of curves 220, 230, 240) characterized by a relatively low P SAT and a relatively low corresponding P BO may be selected for lower traffic loading conditions in order to support amplification at lower average output power levels. The ability to reconfigure the Doherty power amplifier to operate at reduced P SAT and reduced corresponding P BO has the potential advantage (e.g., while traffic loading is relatively low) of enabling efficient processing of signals at lower average output power levels, thus enabling overall power savings.

[0124] Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., the output circuit 360, 460, 560 of Figures 3-5 ). Each reconfigurable output circuit includes a combination node (e.g., the combination node 370 of Figures 3-5 ), a reconfigurable carrier output circuit (e.g., the circuit 334, 340, 440, 540 of Figures 3-5 ) coupled between a carrier amplifier intrinsic drain terminal and the combination node, and a reconfigurable peaking output circuit (e.g., the circuit 354 of Figures 3-5 ) coupled between a peaking amplifier intrinsic drain terminal and the combination node. In addition, each reconfigurable Doherty power amplifier includes a reconfigurable output impedance transformer (e.g., the transformer 380 of Figures 3-5 ) coupled between the combination node and an amplifier output terminal (e.g., the RF output 110 of Figures 3-5 ).

[0125] As used herein, “reconfigurable” means the ability to control (e.g., enable or disable) various elements in the output circuitry embodiment to configure the Dougherty power amplifier into any of N amplifier states, where N ≥ 2 (N is greater than or equal to 2). Each amplifier state can be structured such that the amplifier operates at multiple backoff output power levels P BO-F P BO-R1 P BO-R2 One of these achieves peak efficiency (e.g., 70% or higher efficiency).

[0126] For example, some embodiments of the reconfigurable Dougherty power amplifier include a reconfigurable output circuit that can be selectively configured to either of two amplifier states (i.e., N=2), wherein a first amplifier state is selected as needed for full average output power (e.g., 39.5 dBm or some other value), and a second amplifier state is selected as needed for a single reduced average output power level (e.g., 38.0 dBm or some other value). As another example, some embodiments of the reconfigurable Dougherty power amplifier include a reconfigurable output circuit that can be selectively configured to any of four amplifier states (i.e., N=4), wherein a first amplifier state is selected as needed for full average output power (e.g., 39.5 dBm or some other value), a second amplifier state is selected as needed for a first reduced average output power level (e.g., 38.0 dBm or some other value), a third amplifier state is selected as needed for a second and further reduced average output power level (e.g., 36.5 dBm or some other value), and a fourth amplifier state is selected as needed for a third and further reduced average output power level (e.g., 29.5 dBm or some other value). In other example embodiments, the number of amplifier states N that the reconfigurable output circuit can be selectively configured to may be greater than 4 (e.g., up to or more than 16 amplifier states), thus enabling the reconfigurable Dougherty power amplifier to be configured for high-efficiency operation at even more than three different reduced average output power levels.

[0127] In various embodiments, the Dougherty power amplifier (e.g., Figures 3-5 The reconfigurable output circuitry of amplifiers 300, 400, and 500 (e.g., Figures 3-5 The output circuits (360, 460, 560) can be selectively configured to modify the drain-source capacitance C used for the carrier and peaking amplifiers accordingly. EFF_C and C EFF_Pthe effective value of the peak amplifier. Embodiments of the reconfigurable output circuit of the Doherty power amplifier can also be selectively configured to reconfigure the variable circuit coupling the carrier amplifier intrinsic drain terminal to the combining node. Further, embodiments of the reconfigurable output circuit of the Doherty power amplifier can also be configured to modify the impedance at the combining node by reconfiguring the output impedance transformer circuit coupling the combining node to the amplifier output.

[0128] For purposes of illustration and not limitation, the example Doherty power amplifier embodiments discussed in detail below have a 2: 1 asymmetric ratio and include a reconfigurable 0 degree / 90 degree (0 / 90) output combiner structure (i.e., an electrical length of approximately 0 degrees couples the peak amplifier intrinsic drain terminal and the combining node, and an electrical length of approximately 90 degrees couples the carrier amplifier intrinsic drain terminal and the combining node). With a 2: 1 asymmetric ratio, the size and power handling capability P peaking of the peak amplifier is approximately twice the size and power handling capability P carrier of the carrier amplifier. Other embodiments can include reconfigurable output combiner structures implemented in symmetric Doherty power amplifiers or implemented in asymmetric Doherty power amplifiers having different asymmetric ratios. In addition, other embodiments can include reconfigurable output combiner structures having different electrical lengths (e.g., 90 / 180, 180 / 270, etc.) between the carrier and peak intrinsic drain terminals and the combining node. In addition, the Doherty amplifier embodiments discussed herein correspond to a "non-inverted" configuration in which the peak input RF signal (at the input of the peak amplifier 351) is delayed by approximately 90 degrees from the carrier input RF signal (at the input of the carrier amplifier 331) in order to compensate for the approximately 90 degree phase delay imposed on the amplified carrier output RF signal between the carrier amplifier output 332 and the combining node 370. Alternative embodiments can include an "inverted" Doherty amplifier configuration in which the carrier input RF signal (at the input of the carrier amplifier 331) is delayed by approximately 90 degrees from the peak input RF signal (at the input of the peak amplifier 351) in order to compensate for the approximately 90 degree phase delay imposed on the amplified peak output RF signal between the peak amplifier output 352 and the combining node 370. In the inverted Doherty amplifier configuration, the second variable network (e.g., network 340, 440, 540) would exist between the peak amplifier output 352 and the combining node 370, rather than between the carrier amplifier output 332 and the combining node 370. Figures 3-5

[0129] The example component values provided below correspond to a Doherty power amplifier having a full saturated output power P SAT-F of approximately 48 dBm, a full average output power level of approximately 39.5 dBm, and a full backoff output power P BO-F ​a first efficiency peak (i.e., lower than P SAT-F about 9.5 dB). It should be understood that embodiments of the Doherty power amplifier can be designed with different asymmetry ratios (including symmetric Doherty power amplifiers), different full saturated output powers, different full average output power levels, and / or efficiency peaks at different full back-off output powers, and such Doherty amplifier embodiments can have different component values than those provided herein.

[0130] Additionally, although embodiments of asymmetric Doherty power amplifiers are described in detail herein, it should be understood that other embodiments of reconfigurable Doherty power amplifiers can have symmetric configurations (e.g., relative sizes and power handling capabilities of the carrier and peaking amplifiers are equal). As used herein, the term "size" when referring to physical characteristics of a power amplifier or power transistor refers to the periphery or power handling capability of the transistor associated with the amplifier or transistor. When referring to relative sizes and power handling capabilities of the carrier and peaking amplifiers, the term "symmetric" means that the cumulative size of the power transistors forming the carrier amplifier is substantially equal to (i.e., within 5%) the cumulative size of the power transistors forming the peaking amplifier. Conversely, the term "asymmetric" means that the cumulative size of the power transistors forming the peaking amplifier is 25% to 200% (e.g., 100%) greater than the cumulative size of the power transistors forming the carrier amplifier. Thus, for example, when the ratio of peaking amplifier size to carrier amplifier size (or "peaking-to-carrier ratio") is expressed as x:y (where x corresponds to the relevant peaking amplifier size and y corresponds to the relevant carrier amplifier size), according to the above definitions, a ratio of 1 : 1 corresponds to a symmetric amplifier, while a ratio of 2: 1 corresponds to an asymmetric amplifier. Furthermore, as used herein, the term "shunt" means electrically coupled between a circuit node and a ground reference (or other DC voltage reference).

[0131] Additional details will now be provided for embodiments of a reconfigurable Doherty power amplifier (e.g., amplifier 112) that is capable of being dynamically configured into different states to achieve multiple power efficiency curves (e.g., power efficiency curves 210, 220, 230, 240). Figure 1 Figure 2

[0132] Figure 3 ​​is a schematic diagram of a reconfigurable Doherty power amplifier 300 having a reconfigurable output circuit 360 that can be selectively configured into any of N impedance states, according to example embodiments. As will be discussed in greater detail below, each state is associated with a different average output power level. For context, the reconfigurable Doherty power amplifier 300 can be used in a power amplifier (e.g., amplifier 112) in RF circuitry of a communication system (e.g., communication system 100 of FIG. 1). Figure 1

[0133] The Doherty amplifier 300 includes an RF input 108, an RF output 110, a power divider 320, a carrier amplification path 330 having a carrier amplifier 331, a peaking amplification path 350 having a peaking amplifier 351, a reconfigurable output circuit 360 (or "reconfigurable impedance inverter") having a combining node 370, and a reconfigurable output impedance transformer 380. In embodiments, an antenna 388 (or other type of load) is coupled to the RF output 110 (e.g., through a circulator (e.g., circulator 180), RF switch, or other circuitry). Although not shown, a dc-blocking capacitor can also be coupled between the combining node 370 and the RF output 110. Figure 1

[0134] The Doherty power amplifier 300 is considered a "bidirectional" Doherty power amplifier, which includes one carrier amplification path 330 and one peaking amplification path 350. Essentially, the carrier amplifier 331 provides RF signal amplification along the carrier amplification path 330, and the peaking amplifier 351 provides RF signal amplification along the peaking amplification path 350. The amplified carrier and peaking RF signals are then conveyed through the reconfigurable output circuit 360 and combined at the combining node 370, before being provided through the reconfigurable output impedance transformer 380 to the RF output 110.

[0135] The power divider 320 is configured to receive an input RF signal at a power divider input 322 from the RF input 108. The power divider 320 is additionally configured to divide the power of the input RF signal into a carrier input RF signal and a peaking input RF signal that are respectively produced at power divider outputs 324, 326. In this way, the power divider 320 is configured to provide the carrier input RF signal to the carrier amplification path 330, and provide the peaking input RF signal to the peaking amplification path 350. According to embodiments, the power divider 320 is configured to produce the carrier and peaking input RF signals with a desired phase difference (typically about 90 degrees) between them.

[0136] ​​The power divider 320 can have any of a variety of configurations, including a Wilkinson-type divider, a hybrid-quadrature divider, and the like. The power divider 320 divides the power of the input RF signal according to the carrier-to- peaking size ratio. For example, when the Doherty amplifier 300 has a symmetric Doherty amplifier configuration in which the sizes of the carrier amplifier 331 and the peaking amplifier 351 are substantially equal, the power divider 320 can divide the power such that about half of the input signal power is provided to the carrier amplification path 330 and about half of the input signal power is provided to the peaking amplification path 350. Conversely, when the Doherty amplifier 300 has an asymmetric Doherty amplifier configuration, the power divider 320 can divide the power unequally. For example, when the Doherty amplifier 300 has such a 2: 1 peaking-to-carrier size ratio, the power divider 320 can divide the input signal power such that approximately one-third of the input signal power is provided to the carrier amplification path 330 and approximately two-thirds of the input signal power is provided to the peaking amplification path 350. In the Doherty amplifier 300, the power divider 320 is configured such that, at the center operating frequency fo of the amplifier 300, the input signal supplied to the peaking amplification path 350 is delayed relative to the input signal supplied to the carrier amplification path 330 by some input phase offset (e.g., about 90 degrees).

[0137] According to one or more embodiments, the carrier amplification path 330 includes a carrier input matching network (IMN) 327, a carrier amplifier 331, and a first variable network 334 and a second variable network 340. Similarly, the peaking amplification path 350 includes a peaking IMN 328, a peaking amplifier 351, and a third variable network 354. It can be noted here that the term "network" as used herein is analogous to "circuit," "electronic circuit," and "circuitry."

[0138] The carrier IMN 327 and the peaking IMN 328 are coupled between the power divider outputs 324 and 326 and the carrier amplifier 331 and the peaking amplifier 351, respectively. The carrier IMN 327 and the peaking IMN 328 can each include, for example, a low-pass or band-pass circuit configured as a T- or pi-type impedance matching network, although other matching network topologies are contemplated. Regardless of configuration, the IMNs 327, 328 incrementally increase circuit impedance toward a source impedance.

[0139] The carrier amplifier 331 and the peaking amplifier 351 can each be implemented as a power transistor (or a series of power transistors). Thus, each of the carrier amplifier 331 and the peaking amplifier 351 has a control input (e.g., a gate terminal) and two current-carrying terminals (e.g., a drain terminal and a source terminal). A first one of the current-carrying terminals (e.g., the drain terminal) of the amplifiers 331, 351 acts as an output 332, 352 of the carrier amplifier 332 and the peaking amplifier 351, with the amplified RF signal being produced by the amplifiers 331, 351. A second one of the current-carrying terminals (e.g., the source terminal) of the amplifiers 331, 351 can be coupled to a ground reference node.

[0140] According to embodiments, the first current-carrying terminals (e.g., the drain terminals) each correspond to an intrinsic current generator (e.g., an intrinsic drain) of each amplifier 331, 351. The capacitors 333, 353 represent parasitic output capacitances (e.g., drain-source capacitances) that exist at the outputs of the carrier amplifier 331 and the peaking amplifier 351 (e.g., at the drain terminals of the carrier and peaking power transistors). In other words, the carrier amplifier output 332 is characterized by a drain-source capacitance 333 (or carrier amplifier output capacitance) between the drain terminal and the source terminal of the carrier amplifier 331. Similarly, the peaking amplifier output 352 is characterized by a drain-source capacitance 353 (or peaking amplifier output capacitance) between the drain terminal and the source terminal of the peaking amplifier 351. Although the capacitances 333, 353 are not discrete physical components (e.g., discrete capacitors), the Figure 3 The capacitances 333, 353 are depicted in FIG. 3 to help later discuss how the variable output networks 334, 354 can contribute to effective output capacitances C EFF_C and C EFF_P According to embodiments, the parasitic capacitances 333, 353 each have a capacitance value in a range of about 0.25 picofarads (pF) to about 20 pF, although the capacitance value can also be lower or higher.

[0141] The carrier amplifier 331 and the peaking amplifier 351 each include one or more power transistors (e.g., field effect transistors) embodied in a semiconductor die. In some embodiments, the semiconductor die that includes the carrier amplifier 331 and the peaking amplifier 351 can be packaged in a power amplifier device or a power amplifier module along with all or portions of the carrier IMN 327 and the peaking IMN 328, and the first, second, and third variable networks 334, 354, 340.

[0142] According to embodiments, the carrier amplifier 331 and the peaking amplifier 351 each comprise a single-stage amplifier (i.e., an amplifier having a single amplification stage or power transistor). In other embodiments, the carrier amplifier 331 is a two-stage amplifier that includes a relatively low-power driver amplifier (not shown) and a relatively high-power final amplifier (not shown) connected in a cascaded (or series) arrangement between the carrier amplifier input and the carrier amplifier output. Similarly, the peaking amplifier 351 can comprise a two-stage amplifier that includes a relatively low-power driver amplifier (not shown) and a relatively high-power final amplifier (not shown) connected in a cascaded arrangement between the peaking amplifier input and the peaking amplifier output.

[0143] Although Figure 3 Although not shown in FIG. 3, various DC bias circuits are coupled to the inputs and outputs of the carrier amplifier 331 and the peaking amplifier 351 in order to deliver DC bias voltages that will ensure proper operation of the Doherty amplifier 300. More specifically, during operation of the Doherty amplifier 300, the carrier amplifier 331 is biased to operate in an AB class mode or a deep AB class mode, and the peaking amplifier 351 is biased to operate in a C class mode or a deep C class mode. In some configurations, the peaking amplifier 351 can be biased to operate in a B class mode.

[0144] For example, output DC bias circuits 390, 392 can be coupled to the outputs (e.g., drain terminals) of the carrier amplifier 331 and the peaking amplifier 351, respectively, and the output DC bias circuits 390, 392 are configured to deliver drain bias voltages V DDC and V DDP to the outputs (e.g., drain terminals) of the carrier amplifier 331 and the peaking amplifier 351, respectively. According to one or more embodiments, each output DC bias circuit 390, 392 can include a bias inductor 391, 393. The bias inductors 391, 393 can affect the effective output capacitances C EFF_C and C EFF_P of each of the carrier amplifier 331 and the peaking amplifier 351, respectively. When the amplifier 300 is a symmetric Doherty power amplifier having substantially equal parasitic output capacitances 333, 353, the bias inductors 391, 393 can have substantially equal inductance values. Conversely, when the amplifier 300 is an asymmetric Doherty power amplifier having unequal parasitic output capacitances 333, 353 (e.g., for a 2: 1 Doherty power amplifier, the parasitic output capacitance 353 of the peaking amplifier 351 can be about twice the parasitic output capacitance 353 of the carrier amplifier 331), the bias inductors 391, 393 can have unequal inductance values that result in effective output capacitances C EFF_C and C EFF_PEqual (assuming none of the shunt inductors 335, 336, 355, 356 are coupled to ground). To avoid complicating the following description of various embodiments, it will be assumed that the value of the parasitic output capacitance 333, 353 includes the effect of biasing inductors 391, 393.

[0145] The carrier amplifier 331 is configured to amplify the carrier input RF signal produced at the distributor output 324 and produce an amplified carrier output RF signal at a carrier amplifier output 332 (e.g., a carrier amplifier intrinsic drain terminal). Similarly, the peaking amplifier 351 is configured to amplify the peaking input RF signal produced at the distributor output 326 and produce an amplified peaking output RF signal at a peaking amplifier output 352 (e.g., a peaking amplifier intrinsic drain terminal).

[0146] The carrier amplifier output 332 and the peaking amplifier output 352 are coupled to the RF output 110 through a reconfigurable output circuit 360 and a reconfigurable output impedance transformer 380. According to one or more embodiments, the reconfigurable output circuit 360 includes a combination node 370, a first variable network 334 coupled to the carrier amplifier output 332, a second variable network 340 coupled between the carrier amplifier output 332 and the combination node 370, and a third variable network 354 coupled to the peaking amplifier output 352 and to the combination node 370.

[0147] The first variable network 334, the second variable network 340, and the third variable network 354 are configured to act as an impedance inverter. In general, and as will be described in greater detail below, an impedance inverter includes a first shunt capacitance (the carrier drain-source capacitance 333 modified by the first variable network 334), a series inductance (the second variable network 340), and a second shunt capacitance (the peaking drain-source capacitance 353 modified by the third variable network 354). In other words, the circuit formed by the variable networks 334, 340, and 354 is a pi network consisting of a shunt C (variable network 334), a series L (network 340), and a shunt C (network 354). In theory, when the capacitance values of the first C and the last C are substantially equal (i.e., C EFF_C = C EFF_P) can be achieved. As will be described in greater detail below, during operation of the amplifier 300, the first variable network 334, the second variable network 340, and the third variable network 354 are controlled in synchronization to establish an impedance inverter configuration that will achieve the desired peak efficiency power level. The reconfigurability of the first variable network 334, the second variable network 340, and the third variable network 354 (impedance inverter) establishes the correct / proper impedance at the carrier amplifier output 332 and the peaking amplifier output 352 (i.e., the drain terminals of the amplifiers 331, 351), which can ensure optimal signal amplification and later combining at full average output power levels and reduced average output power levels.

[0148] As mentioned above, each of the carrier amplifier 331 and the peaking amplifier 351 is characterized by a parasitic drain-source capacitance 333, 353. According to one or more embodiments, the first variable network 334 is used to modify the parasitic drain-source capacitance 333 of the carrier amplifier 331, thereby producing an effective output capacitance C EFF_C at the carrier amplifier output 332 that is different from (e.g., lower than) the parasitic drain-source capacitance 333. Similarly, the third variable network 354 is used to modify the parasitic drain-source capacitance 353 of the peaking amplifier 351, thereby producing an effective output capacitance C EFF_P at the peaking amplifier output 352 that is different from (e.g., lower than) the parasitic drain-source capacitance 353. During operation, the shunt inductance provided by the first variable network 334 and the third variable network 354 is used to resonate out some of the parasitic drain-source capacitance 333, 353. In other words, the carrier amplifier effective output capacitance C EFF_C (or first shunt capacitance of the impedance inverter) is defined by the carrier amplifier parasitic drain-source capacitance 333 modified by the first variable network 334, and the peaking amplifier effective output capacitance C EFF_P (or second shunt capacitance of the impedance inverter) is defined by the peaking amplifier parasitic drain-source capacitance 353 modified by the third variable network 354. It can be noted here that the peaking amplifier effective output capacitance C EFF_P may also be affected by the capacitance value of the first variable capacitance circuit 383 of the later described reconfigurable output impedance transformer 380.

[0149] According to one or more embodiments, to achieve optimal performance, the effective output capacitances C EFF_C and C EFF_P associated with the carrier amplifier 331 and the peaking amplifier 351 can be controlled to be equal or approximately equal to each other, regardless of whether the Doherty power amplifier 300 is a symmetric or asymmetric Doherty power amplifier. In other embodiments, the effective output capacitances C EFF_C and CEFF_P The controls are different from each other, yet at least some of the benefits described herein are still achieved.

[0150] exist Figure 3 In the illustrated embodiment, the first variable network 334 includes a reconfigurable shunt inductor network coupled between the carrier amplifier output 332 and the ground reference node. Similarly, the third variable network 354 includes a reconfigurable shunt inductor network coupled between the peaking amplifier output 352 and the ground reference node. More specifically, each of the first variable network 334 and the third variable network 354 includes a number M reconfigurable shunt inductor branches, where M ≥ 1. For example, the number M of reconfigurable shunt inductor branches can be in the range of 1 to 5 or greater. Although Figure 3 Two reconfigurable shunt inductor branches are depicted in each of the first variable network 334 and the third variable network 354, but the ellipsis between those branches indicates that each of the first variable network 334 and the third variable network 354 may also have more than two reconfigurable shunt inductor branches.

[0151] Each branch inductor includes inductors 335, 336, 355, and 356 coupled in series with switching elements 337, 338, 357, and 358. Each branch inductor in the first variable network 334 is coupled between the carrier amplifier output 332 and a ground reference node. Similarly, each branch inductor in the third variable network 354 is coupled between the peaking amplifier output 352 and a ground reference node. More specifically, a first terminal of each inductor 335, 336, 355, and 356 is coupled to either the carrier amplifier output 332 or the peaking amplifier output 352, and a second terminal of each inductor 335, 336, 355, and 356 is coupled to a first terminal of the switching elements 337, 338, 357, and 358. The second terminals of the switching elements 337, 338, 357, and 358 are coupled to a ground reference node. In an alternative embodiment, the order of inductors 335, 336, 355, 356 and switches 337, 338, 357, 358 in each branch can be reversed (i.e., the switching elements 337, 338, 357, 358 can be connected between amplifier outputs 332, 352 and the first terminals of inductors 335, 336, 355, 356, and the second terminals of the inductors can be coupled to a ground reference node).

[0152] According to various embodiments, the inductance values ​​of inductors 335 and 355 (hereinafter referred to as L) 335 L 355 The inductance values ​​of inductors 356 and 356 (hereinafter referred to as L) are equal to each other. 336 and L 356equal to one another. However, the inductance values of inductors 335 and 336 can be equal or unequal, and the inductance values of inductors 355 and 356 can be equal or unequal. For example, in some embodiments, L 335 = L 355 and L 336 = L 356 = x x L 335 where x > 1. As a particular example, x can equal 2, meaning that the inductance values of inductors 336 and 356 are twice the inductance values of inductors 335 and 355. Alternatively, other relative values of L 335 , L 336 , L 355 , and L 356 may be implemented. Regardless, at any given time, the effective output capacitances C EFF_C and C EFF_P of carrier amplifier 331 and peaking amplifier 351, respectively, can have one of the following values:

[0153] • C EFF_C = C 333 and C EFF_P = C 353 when switch elements 337, 338, 357, and 358 are open;

[0154] • C EFF_C = C 333 -(1 / ω*ω*L 335 ) and C EFF_P = C 353 -(1 / ω*ω*L 355 ) when switch elements 337, 357 are closed and switch elements 338, 358 are open, where ω is the operating frequency (e.g., the operating fundamental frequency f0);

[0155] • C EFF_C = C 333 -(1 / ω*ω*L 336 ) and C EFF_P = C 353 -(1 / ω*ω*L 356 ) when switch elements 338, 358 are closed and switch elements 337, 357 are open; and

[0156] • C EFF_C = C 333 -(1 / ω*ω*L 335 )-(1 / ω*ω*L 336 ) and

[0157] C EFF_P = c 353 -(1 / ω*ω*L 355) - (1 / ω*ω*L 356 ) when the switch elements 337, 338, 357, 358 are closed.

[0158] The inductance values selected for the inductors 335, 336, 355, 356 can be based on an operating fundamental frequency fo of the amplifier 300. For example, fo can be in a range of about 800 megahertz (MHz) to about 7 gigahertz (GHz), although fo can be lower or higher. According to one or more embodiments, each of the inductors 335, 336, 355, 356 has an inductance value in a range of about 0.25 nanohenry (nH) to about 10 nH, although the inductance values can be lower or higher.

[0159] According to one or more embodiments, the first variable network 334 and the third variable network 354 can have similar or identical circuit topologies. For example, the first variable network 334 and the third variable network 354 can have the same number M of shunt inductance branches. Moreover, in embodiments where the Doherty power amplifier 300 is a symmetric amplifier, corresponding inductors in the first variable network 334 and the third variable network 354 can have equal inductance values (e.g., the inductors 335, 355 can have equal inductance values, the inductors 336, 356 can have equal inductance values, and so on). Conversely, in embodiments where the Doherty power amplifier 300 is an asymmetric amplifier, corresponding inductors in the first variable network 334 and the third variable network 354 can have unequal but scaled inductance values (e.g., for a 2: 1 peaking-to-carrier ratio, the inductor 355 can have twice the inductance value of the inductor 335, and so on).

[0160] As shown in FIG. 3, the series inductance of the impedance inverter is provided by the second variable network 340. In the embodiment shown in FIG. 3, the second variable network 340 includes a variable inductance network coupled between the carrier amplifier output 332 and a combining node 370. More specifically, the second variable network 340 includes a first inductor 341 and a number P of reconfigurable shunt inductance branches (P > 1) coupled in parallel with the first inductor 341. The first inductor 341 has a first end coupled to the carrier amplifier output 332, and a second end coupled to the combining node 370. Figure 3 Figure 3 For example, the number P of reconfigurable shunt inductance branches can be in a range of 1 to 5 or more. The number P of reconfigurable shunt inductance branches in the network 340 can or can not be equal to the number M of shunt inductance branches in the networks 334 and 354. Although the number P of reconfigurable shunt inductance branches in the network 340 is shown as being equal to the number M of shunt inductance branches in the networks 334 and 354, the number P of reconfigurable shunt inductance branches in the network 340 can be different than the number M of shunt inductance branches in the networks 334 and 354.

[0161] For example, the number P of reconfigurable shunt inductance branches can be in a range of 1 to 5 or more. The number P of reconfigurable shunt inductance branches in the network 340 can or can not be equal to the number M of shunt inductance branches in the networks 334 and 354. Although the number P of reconfigurable shunt inductance branches in the network 340 is shown as being equal to the number M of shunt inductance branches in the networks 334 and 354, the number P of reconfigurable shunt inductance branches in the network 340 can be different than the number M of shunt inductance branches in the networks 334 and 354. Figure 3 ​Two reconfigurable parallel inductance branches are depicted in the second variable network 340, but the ellipsis between those branches indicates that the second variable network 340 can also have more than two reconfigurable parallel inductance branches.

[0162] Each reconfigurable parallel inductance branch includes an inductor 342, 343 coupled in series with one or more switching elements 345, 346, 347, 348. Each parallel inductance branch in the second variable network 340 is coupled between the carrier amplifier output 332 and the combination node 370. More specifically, a first end of each inductor 342, 343 can be coupled to the carrier amplifier output 332 through a switching element 345, 347, and a second end of each inductor 342, 343 can be coupled to the combination node 370 through another switching element 346, 348. In alternative embodiments, the switching elements 345, 347 can not be included, or alternatively, the switching elements 346, 348 can not be included.

[0163] According to various embodiments, the inductance values of the inductors 341, 342, 343 (hereinafter referred to as L 341 , L 342 , and L 343 ) can be equal or unequal. For example, in some embodiments, L 341 = L 342 = L 343 . In other embodiments, L 342 = 0.5 x L 341 and L 343 = 0.5 x L 341 . Other relative values of L 341 , L 342 , and L 343 may be alternatively implemented. Regardless, at any given time, the total inductance value L TOT of the second variable network 340 between the carrier amplifier output 332 and the combination node 370 can have one of the following values:

[0164] • L TOT = L 341 when the switching elements 345, 346, 347, 348 are open;

[0165] • L TOT = 1 / (1 / L 341 + 1 / L 342 ) when the switching elements 345, 346 are closed and the switching elements 347, 348 are open;

[0166] • L TOT = 1 / (1 / L 341 + 1 / L 343) when the switch elements 345, 346 are open and the switch elements 347, 348 are closed; and

[0167] · L TOT = 1 / (1 / L 341 + 1 / L 342 + 1 / L 343 ) when the switch elements 345, 346, 347, 348 are closed.

[0168] The inductance values selected for the inductors 341-343 can be based on an operating fundamental frequency fo (e.g., about 800 MHz to about 7 GHz) of the amplifier 300. According to one or more embodiments, each of the inductors 341-343 has an inductance value in a range of about 1.0 nanohenry (nH) to about 10 nH, although the inductance values can also be lower or higher.

[0169] As discussed above, in the embodiment of the Doherty power amplifier 300 shown in Figure 3 , the series inductance provided by the second variable network 340 includes a first inductor 341 and a number P (P > 1) of reconfigurable parallel inductance branches coupled in parallel with the first inductor 341. According to one or more alternative embodiments, some or all of the inductors 341-343 can be replaced with transmission line (TL) segments.

[0170] For example, Figure 4 is a schematic diagram of a reconfigurable Doherty power amplifier 400 according to another example embodiment, in which a transmission line-based second variable network 440 is utilized. Except for differences between the second variable networks 340 Figure 3 ) and 440 Figure 4 ), all other features of the Doherty power amplifier 400 are the same (or substantially the same) as the corresponding features of the Doherty power amplifier 300. For brevity, substantially the same features are not described again in detail. It is to be understood that the description of features of Figure 4 with the same reference numerals as the corresponding features in Figure 3 also apply to the Doherty power amplifier 400 of Figure 4 .

[0171] As shown in Figure 4 , the effective series impedance of the impedance inverter is provided by the second variable network 440. In Figure 4In the embodiment shown in FIG. 3, the second variable network 440 includes a variable transmission line (TL) network coupled between the carrier amplifier output 332 and the combining node 370. More specifically, the second variable network 440 includes a first transmission line (TL) section 441 and P number of reconfigurable shunt TL branches (P > 1) coupled in parallel with the first TL section 441. The first shunt TL section 441 has a first end coupled to the carrier amplifier output 332, and a second end coupled to the combining node 370.

[0172] For example, the number P of reconfigurable shunt TL branches can range from 1 to 5 or more. Likewise, the number P of reconfigurable shunt inductive branches in the network 440 can or can not be equal to the number M of shunt inductive branches in the networks 334 and 354. Although Figure 4 Two reconfigurable shunt TL branches are depicted in the second variable network 440, but the ellipses between those branches indicates that the second variable network 440 can also have more than two reconfigurable shunt TL branches.

[0173] Each reconfigurable shunt TL branch includes a TL section 442, 443 coupled in series with one or more switching elements 345, 346, 347, 348. Each TL branch in the second variable network 440 is coupled between the carrier amplifier output 332 and the combining node 370. More specifically, a first end of each shunt TL section 442, 443 can be coupled to the carrier amplifier output 332 through a switching element 345, 347, and a second end of each shunt TL section 442, 443 can be coupled to the combining node 370 through another switching element 346, 348. In alternative embodiments, the switching elements 345, 347 can not be included, or alternatively, the switching elements 346, 348 can not be included.

[0174] According to various embodiments, each of the shunt TL sections 441, 442, 443 is defined by a characteristic impedance Z and an electrical length β. The characteristic impedance values (hereinafter referred to as Z 441 , Z 442 , and Z 443 ) of the shunt TL sections 441, 442, 443 can or can not be equal. For example, in some embodiments, Z 441 = Z 442 = Z 443 . In other embodiments, Z 442 = Z 341 and Z 443 = 0.5 x Z 441 . Alternatively, Z 441 , Z 442 , and Z 443other relative values. Similarly, the electrical lengths (hereinafter referred to as β 441 , β 442 , β 443 ) of the parallel TL segments 441, 442, 443 can be equal or unequal. For space and layout purposes, it can be desirable for the parallel TL segments 441-443 to have the same electrical (and physical) length. As will be described below, this can make it possible to achieve coordinated selection of characteristic impedance values Z 441 , Z 442 , Z 443 and coordinated control of the effective output capacitances C EFF_C , C EFF_P of the carrier amplifier 331 and the peaking amplifier 351.

[0175] Regardless, at any given time, the total impedance value Z TOT of the second variable network 440 between the carrier amplifier output 332 and the combined node 370 can have one of the following values:

[0176] • Z TOT = Z 441 (when the switch elements 345, 346, 347, 348 are open);

[0177] • Z 442 = 1 / (1 / Z TOT + 1 / Z 441 )(when the switch elements 345, 346 are closed and the switch elements 347, 348 are open);

[0178] • Z 443 = 1 / (1 / Z TOT + 1 / Z 441 )(when the switch elements 345, 346 are open and the switch elements 347, 348 are closed); and

[0179] • Z 442 = 1 / (1 / Z 443 + 1 / Z 541 + 1 / Z 542 )(when the switch elements 345, 346, 347, 348 are closed).

[0180] The impedance values and electrical lengths selected for the shunt TL segments 441-443 can be based on an operating fundamental frequency fo (e.g., about 800 MHz to about 7 GHz) of the amplifier 400. According to one or more embodiments, each of the shunt TL segments 441-443 has an impedance value in a range of about 30 ohms to about 100 ohms, although the impedance value can also be lower or higher. Further, according to one or more embodiments, each of the shunt TL segments 441-443 has an electrical length in a range of about 45 degrees to about 90 degrees, although the electrical length can also be lower or higher.

[0181] As discussed above, Figure 3 and 4 The embodiments of the Doherty power amplifiers 300, 400 shown in FIGS. 1-4, 6, and 8-10, respectively, each include a second variable network 340, 440, 640, 840, 940 that includes a first inductor 341 or TL segment 441 and a number P of reconfigurable shunt inductors or TL branches (P > 1) coupled in shunt with the first inductor 341 or TL segment 441. According to one or more alternative embodiments, a different topology can be implemented for the second variable network in order to provide a series inductance of the impedance inverter.

[0182] For example, Figure 5 is a schematic diagram of a reconfigurable Doherty power amplifier 500 according to another example embodiment, in which the second variable network 540 includes a first inductor 341 and a number Q of bypassable inductors 542, 543 coupled in series with the first inductor 341. As used herein, the term "bypassable inductor" refers to an inductor having a switching element coupled across the inductor terminals, such that when the switching element is open, substantially all of the current flows through the inductor, and when the switching element is closed, substantially all of the current flows through the switching element, thus bypassing the inductor. Except for the difference between the second variable networks 340 Figure 3 ) and 540 Figure 5 ), all other features of the Doherty power amplifier 500 are the same as (or substantially the same as) the corresponding features of the Doherty power amplifier 300. For brevity, the substantially same features are not described again in detail. It is to be understood that the description of features of Figure 5 ) having the same reference numerals as the corresponding features of Figure 3 also apply to the Doherty power amplifier 500 of Figure 5 .

[0183] As shown in FIG. 10, Figure 5 the series inductance of the impedance inverter is provided by the second variable network 540. In Figure 5In the embodiment shown in FIG. 5, the second variable network 540 includes a plurality of inductors 541, 542, 543 coupled in series between the carrier amplifier output 332 and the combining node 370, with bypass switches 545, 546 coupled across the terminals of some of the inductors 542, 543. More specifically, the second variable network 540 includes a first inductor 541 and Q reconfigurable (bypassable) inductors 542, 543 coupled in series with the first inductor 541 (Q > 1). The first inductor 541 has a first terminal coupled to the carrier amplifier output 332, and a second terminal coupled to a first terminal of a first bypassable inductor 542. A second terminal of the first bypassable inductor 542 can be coupled to the combining node 370 (when Q = 1), or alternatively (when Q > 1) to a series of one or more additional bypassable inductors, with a qth bypassable inductor 543 being the last inductor in the series. A second terminal of the qth bypassable inductor 543 is coupled to the combining node 370.

[0184] For example, the number Q of bypassable inductors 542, 543 can be in the range of 1 to 5 or more. Although Figure 5 Two bypassable inductors 542, 543 are depicted in the second variable network 540, but the ellipses between those inductors 542, 543 also indicate that the second variable network 540 can also have more than two bypassable inductors 542, 543.

[0185] A bypass switch 545, 546 is coupled across the first and second terminals of each bypassable inductor 542, 543. When the bypass switch 545, 546 is in the "open" or "off state, the inductance of the corresponding inductor 542, 543 will be added to the inductance of the first inductor 541 between the carrier amplifier output 332 and the combining node 370. Conversely, when the bypass switch 545, 546 is in the "closed" or "on" state, the corresponding inductor 542, 543 will be bypassed by the switch 545, 546, and the inductance of the corresponding inductor 542, 543 will not be added to the inductance of the first inductor 541 between the carrier amplifier output 332 and the combining node 370.

[0186] According to various embodiments, the inductance values (hereinafter referred to as L 541 , L 542 , and L 543 ) of the inductors 541, 542, 543 can be equal or unequal. For example, in some embodiments, L 541 = L 542 = L 543 In other embodiments, L 542 = x x L 541 and L 543 = y x L 541where x and y can have any non-zero value. Either way, the total inductance value L of the second variable network 540 between the carrier amplifier output 332 and the combining node 370 at any given time is TOT may have one of the following values:

[0187] • L TOT = L 541 when bypass switches 545, 546 are closed);

[0188] • L TOT = L 541 + L 542 when bypass switch 545 is open and bypass switch 546 is closed);

[0189] • L TOT = L 541 + L 543 when bypass switch 545 is closed and bypass switch 546 is open); and

[0190] • L TOT = L 541 + L 542 + L 543 when bypass switches 545 and 546 are open.

[0191] The inductance values selected for inductors 541-543 can be based on an operating fundamental frequency fo (e.g., about 800 MHz to about 7 GHz) of the amplifier 500. According to one or more embodiments, each of inductors 541-543 has an inductance value in a range of about 1.0 nanohenry (nH) to about 10 nH, although the inductance values can also be lower or higher.

[0192] For each of the embodiments of the Doherty power amplifiers 300, 400, 500 Figures 3-5 ) discussed above, and according to one or more embodiments, each of the switch elements 337, 338, 345-348, 545-547, 357, 358 can be implemented as an active switching device (e.g., a field effect transistor (FET)) having a control terminal (e.g., a gate terminal) and current conduction terminals (e.g., drain and source terminals). For example, the switch elements 337, 338, 345-348, 545-547, 357, 358 can include a metal-oxide-semiconductor FET (MOSFET), a high electron mobility transistor (HEMT), a metal- semiconductor field effect transistor (MESFET), a laterally diffused metal-oxide-semiconductor (LDMOS) FET, an enhancement-mode MOSFET (EMOSFET), and / or a junction gate FET (JFET), to name a few.

[0193] During operation of the Doherty power amplifiers 300, 400, 500, the states of the first, second, and third variable networks 334, 340, or 440 or 540, 354 can be reconfigured synchronously (e.g., by switch control signals provided via the switch control lines 116). In other words, to establish any of the N configurations of the amplifiers 300, 400, 500, the states of all of the switch elements 337, 338, 345-348, 545-547, 357, 358 are controlled by the amplifier controller 114 in a synchronous manner. Based on the switch control signals provided to the control terminals of the switch elements, each of the switch elements 337, 338, 345-348, 545-547, 357, 358 can be“turned off’ or“open” (e.g., placed in a high impedance state between the drain terminal and the source terminal), or“turned on” or“closed” (e.g., placed in a low impedance state between the drain terminal and the source terminal). To provide the switch control signals, according to one or more embodiments, the amplifier controller 114 can include a plurality of drivers (not shown), where each driver is coupled to one or more of the control terminals of the switch elements 337, 338, 345-348, 545-547, 357, 358 by a switch control line 116.

[0194] According to one or more embodiments, during operation of the amplifiers 300, 400, 500, the first variable network 334 and the third variable network 354 can be controlled synchronously to have the same configuration at any given time. For example, when a switch control signal is provided to the first variable network 334 that causes all of the switch elements 337, 338 to be“closed,” a simultaneous switch control signal is provided to the third variable network 354 that causes both of the switch elements 357, 358 to be“closed.” In such a configuration, the inductors 335 and 336 are used to resonate out some of the drain-source capacitance 333, and the inductors 355, 356 are used to resonate out some of the drain-source capacitance 353. Similarly, when a switch control signal is provided to the first variable network 334 that causes the switch element 337 to be“closed” and the switch element 338 to be“open,” a simultaneous switch control signal is provided to the third variable network 354 that causes the switch element 357 to be“closed” and the switch element 358 to be“open.” In such a configuration, only the inductor 335 is used to resonate out some of the drain-source capacitance 333, and only the inductor 355 is used to resonate out some of the drain-source capacitance 353. According to one or more embodiments, the second variable network 340 is also reconfigured synchronously with the reconfiguration of the first variable network 334 and the third variable network 354.

[0195] As indicated above, at any given time, the Doherty power amplifier 300 can be configured or reconfigured into any of N amplifier states, where each amplifier state corresponds to a full power state or a back-off power state (e.g., selected from one or more back-off power states). As previously discussed in connection with Figure 1 and 2 The instantaneous configuration of the Doherty power amplifier 300, 400, 500 can be controlled by the amplifier controller 114 based on control signals 104 from the base station controller 103 Figure 1 ) in accordance with an embodiment.

[0196] In accordance with an embodiment, the amplifier controller 114 includes a memory (not shown) configured to store a look-up table that relates the control signals 104 from the base station controller 103 to the switching states of the plurality of switching elements 337, 338, 345-348, 357, 358 in the embodiments of the Doherty power amplifier 300, 400 shown in Figure 3 , 4

[0197] For illustration, the following is a first example of a look-up table (Table 3) that can be utilized in connection with a reconfigurable Doherty power amplifier 300, 400 that includes only one reconfigurable shunt inductor branch (i.e., M = 1, corresponding to inductor 335, 355 and switching elements 337, 357) in each of the first and third variable networks 334, 354, and only one reconfigurable series inductor (or series TL) branch (i.e., P = 1, corresponding to inductor 342 or TL 442 and switching elements 345, 346) in the second variable network. Although such a reconfigurable Doherty power amplifier 300, 400 can theoretically be selectively configured into any of four possible amplifier states at any given time, some of the theoretically possible amplifier states do not yield acceptable performance. Thus, the system can be configured such that only some of the theoretically possible amplifier states are selectable (e.g., those that yield acceptable performance). The following look-up table includes entries for two amplifier states (i.e., N = 2, corresponding to a full power state and a single back-off power state).

[0198] Amplifier state Switch state of switches 337, 357 Switch state of switches 345, 346 Full power (state 1) Open Closed Back-off power (state 2) Closed Open

[0199] Table 3 - Switching states for N = 2 state amplifier 300, 400

[0200] ​As indicated in Table 3, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into a full power state (state 1, with 0 dB backoff), the amplifier controller 114 will provide the following switch control signals over the switch control lines 116:

[0201] • the switch elements 337, 357 are placed in an open state (i.e. the inductors 335, 355 do not affect the effective output capacitance of the amplifiers 331, 351 ); and

[0202] • the switch elements 345, 346 are placed in a closed state (i.e. the inductance of the network 340 comprises the parallel inductors 341, 342, or the impedance of the network 440 comprises the parallel TLs 441, 442).

[0203] Alternatively, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into a backoff power state (state 2, with 3 dB backoff), the amplifier controller 114 will provide the following switch control signals over the switch control lines 116:

[0204] • the switch elements 337, 357 are placed in a closed state (i.e. the inductors 335, 355 affect (reduce) the effective output capacitance of the amplifiers 331, 351 ); and

[0205] • the switch elements 345, 346 are placed in an open state (i.e. the inductance of the network 340 comprises only the inductor 341, or the impedance of the network 440 comprises only the TL 441 ).

[0206] As another example, the following is a second example of a lookup table (Table 4) that can be utilized in connection with reconfigurable Doherty power amplifiers 300, 400 that include two reconfigurable shunt inductive branches in each of the first variable network 334 and the third variable network 354 (i.e., M = 2, corresponding to inductors 335, 336, 355, 356 and switch elements 337, 338, 357, 358) and two reconfigurable series inductances (or series TL) branches in the second variable network 340 or 440 (i.e., P = 2, corresponding to inductors 342, 343 or TLs 442, 443 and switch elements 345-348). Although such reconfigurable Doherty power amplifiers 300, 400 can theoretically be selectively configured into any of eight (or more) possible amplifier states at any given time, some of the theoretically possible amplifier states do not yield acceptable performance. Accordingly, the system can be configured such that a subset of the theoretically possible amplifier states are selectable (e.g., those states that yield acceptable performance). The following lookup table includes entries for three amplifier states (i.e., N = 3, corresponding to a full power state and two backoff power states). Based on the description herein, those skilled in the art will understand that the Doherty power amplifiers 300, 400 can theoretically support more than three amplifier states.

[0207]

[0208] Table 4 - Switching states for N = 3 state amplifiers 300, 400

[0209] As indicated by Table 4, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into a full power state (state 1, with 0 dB backoff), the amplifier controller 114 will provide the following switching control signals over the switching control lines 116:

[0210] • Switch elements 337, 357, 338, and 358 are placed in an open state (i.e., the inductors 335, 336, 355, 356 do not affect the effective output capacitance of the amplifiers 331, 351); and

[0211] • Switch elements 345-348 are placed in a closed state (i.e., the inductance of the network 340 includes parallel inductances 341, 342, and 343, or the impedance of the network 440 includes parallel TLs 441, 442, and 443).

[0212] Alternatively, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into the first back-off power state (state 2, with 3dB back-off), the amplifier controller 114 will provide the following switch control signals via the switch control lines 116:

[0213] • the switch elements 337, 357 are placed in a closed state (i.e. the inductors 335, 355 affect (reduce) the effective output capacitance of the amplifier 331, 351);

[0214] • the switch elements 338, 358 are placed in an open state (i.e. the inductors 336, 356 do not affect the effective output capacitance of the amplifier 331, 351); and

[0215] • the switch elements 345, 346 are placed in a closed state and the switch elements 347, 348 are placed in an open state (i.e. the inductance of the network 340 comprises the inductors 341, 342, or the impedance of the network 440 comprises the TLs 441, 442).

[0216] Alternatively, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into the second back-off power state (state 3, with 6dB back-off), the amplifier controller 114 will provide the following switch control signals via the switch control lines 116:

[0217] • the switch elements 337, 338, 357, 358 are placed in a closed state (i.e. the inductors 335, 336, 355, 356 affect (reduce) the effective output capacitance of the amplifier 331, 351); and

[0218] • the switch elements 345-348 are placed in an open state (i.e. the inductance of the network 340 comprises only the inductor 341, or the impedance of the network 440 comprises only the TL 441).

[0219] As another example, the following is an alternative example of a lookup table (Table 5) that includes two reconfigurable shunt inductance branches in each of the first variable network 334 and the third variable network 354 (i.e., M = 2), and two reconfigurable series inductance (or series TL) branches in the second variable network 340 or 440 (i.e., P = 2). Again, while such a reconfigurable Doherty power amplifier 300, 400 can theoretically be selectively configured into any of eight (or more) possible amplifier states at any given time, some of the theoretically possible amplifier states do not yield acceptable performance. Thus, the system can be configured such that a subset of the theoretically possible amplifier states are selectable (e.g., those that yield acceptable performance). The following lookup table includes entries for three amplifier states (i.e., N = 3, corresponding to a full power state and two backoff power states). Based on the description herein, one of skill in the art will understand that the Doherty power amplifier 300, 400 can theoretically support more than three amplifier states.

[0220]

[0221] Table 5 - Alternative switch states for N = 3 state amplifier 300, 400

[0222] As Table 5 indicates, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into the full power state (state 1, with 0 dB backoff), the amplifier controller 114 will provide the following switch control signals over the switch control lines 116:

[0223] • switch elements 337, 357, 338, and 358 into an open state (i.e., the inductors 335, 336, 355, 356 do not affect the effective output capacitance of the amplifiers 331, 351); and

[0224] • switch elements 345-348 into a closed state (i.e., the inductance of the network 340 includes the parallel inductors 341, 342, and 343, or the impedance of the network 440 includes the parallel TLs 441, 442, and 443).

[0225] Alternatively, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into the first backoff power state (state 2, with 3 dB backoff), the amplifier controller 114 will provide the following switch control signals over the switch control lines 116:

[0226] • switch elements 337, 357 into an open state (i.e., the inductors 335, 355 do not affect the effective output capacitance of the amplifiers 331, 351);

[0227] • switch elements 338, 358 are in a closed state (i.e. the inductors 336, 356 affect (reduce) the effective output capacitance of the amplifiers 331, 351); and

[0228] • switch elements 345, 346 are in an open state and switch elements 347, 348 are in a closed state (i.e. the inductance of the network 340 comprises inductors 341, 343, or the impedance of the network 440 comprises TLs 441, 443).

[0229] Alternatively, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300, 400 should be reconfigured into a second back-off power state (state 3, with a 6dB back-off), the amplifier controller 114 will provide the following switch control signals over the switch control lines 116:

[0230] • switch elements 337, 338, 357, 358 are in a closed state (i.e. the inductors 335, 336, 355, 356 affect (reduce) the effective output capacitance of the amplifiers 331, 351); and

[0231] • switch elements 345-348 are in an open state (i.e. the inductance of the network 340 comprises only inductor 341, or the impedance of the network 440 comprises only TL 441).

[0232] As discussed above, the reconfigurable Doherty power amplifiers 300, 400 each comprise a second variable network 340, 440 having parallel coupled reconfigurable inductor or TL branches. In contrast, the reconfigurable Doherty power amplifier 500 comprises a second variable network 540 having series coupled bypassable inductors. The series coupling nature of the switch elements 545, 546 in the reconfigurable Doherty power amplifier 500 guarantees different switch control procedures for the amplifier 500.

[0233] Thus, as another example, the following is a look-up table (Table 6) that can be utilized in connection with a reconfigurable Doherty power amplifier 500 that includes two reconfigurable shunt inductor branches in each of the first and third variable networks 334, 354 (i.e., M = 2, corresponding to inductors 335, 336, 355, 356 and switch elements 337, 338, 357, 358), and two reconfigurable (bypassable) inductors in the second variable network 540 (i.e., P = 2, corresponding to inductors 542, 543 and switch elements 545, 546). Although such a reconfigurable Doherty power amplifier 500 can theoretically be selectively configured into any of eight (or more) possible amplifier states at any given time, some of the theoretically possible amplifier states do not yield acceptable performance. Thus, the system can be configured such that a subset of the theoretically possible amplifier states are selectable (e.g., those states that yield acceptable performance). The following look-up table includes entries for three amplifier states (i.e., N = 3, corresponding to a full power state and two back-off power states). Based on the description herein, those skilled in the art will understand that the Doherty power amplifier 500 can theoretically support more than three amplifier states.

[0234]

[0235] Table 6 - Switching states for N = 3 state amplifier 500

[0236] As indicated by Table 6, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 500 should be reconfigured into the full power state (state 1, with 0 dB back-off), the amplifier controller 114 will provide the following switching control signals over the switching control lines 116:

[0237] • switching elements 337, 357, 338, and 358 into an open state (i.e., inductors 335, 336, 355, 356 do not affect the effective output capacitance of the amplifiers 331, 351); and

[0238] • switching elements 545, 546 into a closed state (i.e., the inductance of the network 540 does not include the series inductors 542, 543).

[0239] Alternatively, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 500 should be reconfigured into the first back-off power state (state 2, with 3 dB back-off), the amplifier controller 114 will provide the following switching control signals over the switching control lines 116:

[0240] • the switching elements 337, 357 are in a closed state (i.e. the inductors 335, 355 affect (reduce) the effective output capacitance of the amplifiers 331, 351);

[0241] • the switching elements 338, 358 are in an open state (i.e. the inductors 336, 356 do not affect the effective output capacitance of the amplifiers 331, 351); and

[0242] • the switching element 545 is in a closed state and the switching element 546 is in an open state (i.e. the inductance of the network 540 comprises the inductors 541 and 543 but not the inductor 542).

[0243] Alternatively, when the amplifier controller 114 receives the control signal 104 from the base station controller 103 indicating that the amplifier 500 should be reconfigured into a second back-off power state (state 3, with a 6dB back-off), the amplifier controller 114 will provide the following switching control signals over the switching control lines 116:

[0244] • the switching elements 337, 338, 357, 358 are in a closed state (i.e. the inductors 335, 336, 355, 356 affect (reduce) the effective output capacitance of the amplifiers 331, 351); and

[0245] • the switching elements 545, 546 are in an open state (i.e. the inductance of the network 540 comprises the inductors 541, 542 and 543).

[0246] For each of the Doherty power amplifiers 300, 400, 500, Figures 3-5 ) the above configurations provide the correct phase relationship for optimal load modulation and ensure that the amplified signals from the carrier path 330 and the peaking path 350 arrive in phase (or coherently) at the combining node 370. The combining node 370 comprises an electrically conductive structure adapted to combine the amplified RF signals produced by the carrier amplification path 330 and the peaking amplification path 350 in order to produce an amplified combined output RF signal. In some embodiments, the combining node 370 can be in the same location or correspond to the output 352 (e.g. drain terminal) of the peaking amplifier 351.

[0247] According to embodiments, a variable output impedance transformer 380 is coupled between the combining node 370 and the RF output 110. During operation of the amplifier 300, 400, 500, the variable output impedance transformer 380 is configured to transform the impedance at the RF output 110 to the impedance at the combining node 370. Thus, the impedance at the combining node 370 is established by the reconfigurable output impedance transformer 380. In particular, the impedance at the combining node 370 depends on the desired first efficiency peak (e.g. Figure 2The power levels at points 212, 222, 232, and 242 are determined. During operation, the variable output impedance converter 380 is controlled to establish the correct combination of node impedances for the desired power levels under backoff conditions.

[0248] According to one or more embodiments, the variable output impedance transformer 380 includes a phase shifting element 382 (e.g., a transmission line segment or inductor) having a first end (or first terminal) coupled to a combination node 370 and a second end (or second terminal) coupled to an RF output 110. Additionally, the variable output impedance transformer 380 includes a first variable capacitor circuit 383 coupled between the first end of the phase shifting element 382 and a ground reference node, and a second variable capacitor circuit 384 coupled between the second end of the phase shifting element 382 and the ground reference node.

[0249] The phase shift element 382 is characterized by its characteristic impedance Z1 and electrical length (or phase shift) at the center operating frequency f0 of amplifiers 300, 400, and 500. For example, the impedance Z1 may be in the range of about 20 to about 100, and the electrical length may be in the range of about 15 to about 90 degrees, but the electrical length may also be shorter or longer.

[0250] In various embodiments, each of the first variable capacitor circuit 383 and the second variable capacitor circuit 384 may be implemented using a tunable capacitor, such as, but not limited to, a voltage-controlled variable capacitor (VVAC), a digitally controlled variable capacitor (DVC) (also referred to as a digitally programmable capacitor or a digitally tunable capacitor), or another suitable tunable / variable capacitor. The instantaneous capacitance values ​​of the first variable capacitor circuit 383 and the second variable capacitor circuit 384 may be modified based on control signals from the amplifier controller 114. For example, VVAC is a component having a capacitance value between a first terminal and a second terminal that varies according to a control voltage applied to a tuning input (not shown). DVC is a component having a capacitance value between a first terminal and a second terminal that varies based on a digital value programmed (e.g., via a serial interface not shown) into a digital register of the DVC. For example, DVC may be implemented using an array of switched capacitors. The RF switch in the DVC can be a semiconductor switch, such as a gallium arsenide (GaAs), gallium nitride (GaN), or silicon-on-insulator (SOI) switch. Alternatively, the RF switch can be a switching device using a phase change material (PCM), such as germanium telluride (GeTe) or germanium-antimony-tellurium (GeSbTe). Any other suitable RF switching technology can also be used.

[0251] It can span the minimum capacitance value C MIN With the maximum capacitance value C MAX The capacitance value range between the two circuits is tuned to each of the first variable capacitor circuit 383 and the second variable capacitor circuit 384. For example, the minimum capacitance value CMIN It can be between approximately 0.2pF and approximately 0.6pF, and the maximum capacitance value C MAX The capacitance can be between approximately 0.9 pF and approximately 2.0 pF. The minimum and / or maximum capacitance values ​​of the first variable capacitor circuit 383 and the second variable capacitor circuit 384 can also be lower or higher. During operation, the capacitance values ​​of the first variable capacitor circuit 383 and the second variable capacitor circuit 384 can be controlled to be approximately equal, or the capacitance values ​​can be controlled to be unequal.

[0252] According to one or more embodiments, the capacitance values ​​of the first variable capacitor circuit 383 and the second variable capacitor circuit 384 are controlled to establish a desired impedance Z0 at the combined node 370 corresponding to an amplifier state (e.g., full power state or back-off power state). For example, the variable capacitor circuits 383, 384 can be controlled to have capacitance values ​​that establish a relatively low combined node impedance Z0 (e.g., from 10 to 15 ohms) when the reconfigurable Dougherty power amplifiers 300, 400, 500 are in a full power state (e.g., 0 dB back-off), and can be controlled to have capacitance values ​​that establish a relatively high combined node impedance Z0 (e.g., from 20 to 30 ohms) when the reconfigurable Dougherty power amplifiers 300, 400, 500 are in a first back-off state (e.g., 3 dB back-off). According to embodiments, the variable capacitor circuits 383, 384 are controlled to have capacitance values ​​that double the combined node impedance Z0 for every 3 dB of desired back-off.

[0253] To provide additional clarity, the discussion will now cover asymmetric (2:1 peaking-carrier ratio) reconfigurable Dougherty power amplifiers (e.g., Figure 3 An example embodiment of amplifier 300 is provided, which can be selectively configured to either of two amplifier states (i.e., N=2). In the example embodiment, all inductors 335, 341, 342, 355 ( Figure 3 These can have substantially equal inductance values ​​(e.g., approximately 3.9 nH for illustrative purposes only). In this example embodiment, the reconfigurable Dougherty power amplifier can be characterized by the following parameters in full-power state (state 1) and in a single back-off power state (state 2) 3 dB lower than full-power state:

[0254] Parameter - unit Full power (state 1) Back-off power (state 2) P carrier -W]] 21.03 10.54 P peaking -W]] 42.06 21.08 [RC o – ohms 14.65 29.23 C EFF_c -pF]] 1.00 0.50 C EFF_p -pF]] 1.00 0.50 L TOT -nH]]> 1.94 3.88

[0255] Table 7 - Implementation Scheme of Asymmetric Dougherty Power Amplifier with N=2 Amplifier States

[0256] In the table above (and also in Tables 8 and 9 below), P carrier P is the maximum output power of the carrier amplifier 331. peakingto maximize the output power of the peak amplifier 351, and R o is the impedance looking to the right at the combining node 370. The different values of R o are produced by different configurations of the variable capacitance circuits 383, 384 in the reconfigurable output impedance transformer 380. As example parameter values indicate, when the amplifier is configured in the full power state, the impedance R o has a first value (i.e., 14.65 ohms), while when the amplifier is configured in the first back-off power state, the combining node impedance has a second value (i.e., 29.23 ohms) that is about twice the first value. Further, when the amplifier is configured in the full power state, the effective capacitance C EFF at the power amplifier outputs 332, 352 has a first value (i.e., 1.00 pF), while when the amplifier is configured in the first back-off power state, the effective capacitance at the power amplifier outputs 332, 352 has a second value (i.e., 0.50 pF) that is about half the first value. Additionally, when the amplifier is configured in the full power state, the total inductance L TOT of the second variable network 340 has a first value (i.e., 1.94 nH), while when the amplifier is configured in the first back-off power state, the total inductance of the second variable network 340 has a second value (i.e., 3.88 nH).

[0257] The above example shows that effective control of the reconfigurable Doherty power amplifier 300 to transition to a back-off power state that is about 3 dB below the full power state includes simultaneously:

[0258] • reconfiguring the variable output impedance transformer 380 to increase (e.g., double) the combining node impedance;

[0259] • reconfiguring the first and third variable networks 334, 354 to decrease (e.g., halve) the effective capacitance C EFF at the outputs 332, 352 of the power amplifiers 331, 351; and

[0260] • reconfiguring the second variable network 340 to increase (e.g., double) the total inductance L TOT of the second variable network 340.

[0261] Interestingly, for the Doherty power amplifier 300 Figure 3 ), the values of C EFF and L TOT are controlled in opposite ways (i.e., when C EFF is decreased, L TOT is increased, and vice versa). Note here that for Figure 4 and 5Alternative embodiments of the Dougherty power amplifiers 400 and 500 shown in the figure, C EFF and Z TOT ( Figure 4 ) or C EFF and L TOT ( Figure 5 Similar relative controls for the value of ) will apply.

[0262] The following discussion will focus on asymmetric (2:1 peaking-carrier ratio) reconfigurable Dougherty power amplifiers (e.g., Figure 3 An additional example embodiment of amplifier 300 is provided, which can be selectively configured to any of three amplifier states (i.e., N=3). In the example embodiment, inductors 335, 343, and 356 ( Figure 3 They may have substantially equal first inductance values ​​(e.g., about 3.9 nH for example purposes only), and inductors 336, 356, 341 and 342 ( Figure 3 The second inductance value may be substantially equal (e.g., about 7.7 nH). In such example embodiments, the reconfigurable Dougherty power amplifier can be characterized by the following parameters in full power state (state 1), a first back-off power state (state 2) 3 dB below full power state, and a second back-off power state (state 3) 6 dB below full power state:

[0263]

[0264] Table 8 - Implementation Scheme of Asymmetric Dougherty Power Amplifier with N=3 Amplifier States

[0265] The above examples demonstrate that effectively controlling the reconfigurable Dougherty power amplifier 300 to transition to a backoff power state approximately 6 dB below full power involves simultaneously performing the following operations:

[0266] • Reconfigure the variable output impedance converter 380 to increase (e.g., quadruple) the combined node impedance;

[0267] • Reconfigure the first variable network 334 and the third variable network 354 to reduce (e.g., reduce to a quarter) the effective capacitance C at the outputs 332 and 352 of the power amplifiers 331 and 351. EFF ;as well as

[0268] • Reconfigure the second variable network 340 to increase (e.g., quadruple) the total inductance L of the second variable network 340. TOT .

[0269] It should be noted here that, for Figure 4 and 5Alternative embodiments of the Dougherty power amplifiers 400 and 500 shown in the figure, C EFF and Z TOT ( Figure 4 ) or C EFF and L TOT ( Figure 5 Similar relative controls for the value of ) will apply.

[0270] The following discussion will focus on the Dougherty power amplifier 400 ( Figure 4 This is a specific case of an embodiment. As previously mentioned, it may be necessary to implement a second variable network 440 of amplifier 400 having TL segments 441-443 characterized as having the same electrical length as each other. Additionally, it may be necessary to reconfigure the output circuitry 460 of amplifier 400 in a way that allows TL segments 441-443 to be characterized as having the same electrical length, regardless of the amplifier state.

[0271] The following discussion will focus on asymmetric (2:1 peaking-carrier ratio) reconfigurable Dougherty power amplifiers (e.g., Figure 4 An additional example embodiment of the amplifier 400 is provided, which can be selectively configured to any of three amplifier states (i.e., N=3) and includes a second variable network 440, wherein TL segments 441-443 may have a fixed electrical length regardless of the amplifier state. In the example embodiment, TL segment 441 is characterized as a first impedance Z. 441 and the first electrical length β 441 / 442 / 443 TL segment 442 is characterized by different second impedances Z 442 and the same first electrical length β 441 / 442 / 443 Furthermore, TL segment 443 is characterized as a different third impedance Z. 443 and the same first electrical length β 441 / 442 / 443 .

[0272] In such example embodiments, the reconfigurable Dougherty power amplifier 400 can be characterized by the following parameters in a full-power state (state 1), a first back-off power state (state 2) 3 dB below full power, and a second back-off power state (state 3) 6 dB below full power:

[0273]

[0274] Table 9 - Implementation scheme of the asymmetric Dougherty power amplifier 400 with N=3 amplifier states

[0275] Similarly, the above examples demonstrate that effectively controlling the reconfigurable Dougherty power amplifier 400 to transition to a backoff power state approximately 6 dB below full power involves simultaneously performing the following operations:

[0276] • Reconfigure the variable output impedance converter 380 to increase (e.g., quadruple) the combined node impedance;

[0277] • Reconfigure the first variable network 334 and the third variable network 354 to reduce (e.g., reduce to a quarter) the effective capacitance C at the outputs 332 and 352 of the power amplifiers 331 and 351. EFF ;as well as

[0278] • Reconfigure the second variable network 440 to increase (e.g., quadruple) the total impedance Z of the second variable network 440. TOT .

[0279] Figure 6 The Dougherty power amplifier can be reconfigured according to the operation of the example embodiment (e.g., Figures 3-5 A flowchart of a method for amplifiers 300, 400, 500. According to one or more embodiments, the method includes two parallel processes, including the use of a Dougherty power amplifier (e.g., Figure 1 , 3 The process performed by amplifiers 112, 300, 400, and 500 (-5) and the process controlled by the base station controller and amplifier controller (e.g., Figure 1 , 3 The process is executed by controllers 103 and 114 (-5). These parallel processes can be executed simultaneously (e.g., continuously amplifying the RF signal while performing reconfiguration of the variable network). Alternatively, the reconfiguration of the variable network can be performed when RF signal amplification does not occur (e.g., before amplification or during amplification pause).

[0280] The overview will begin with the Dougherty power amplifier (e.g., Figure 1 , 3 The process is performed by amplifiers 112, 300, 400, and 500 (-5). According to one or more embodiments, the method begins at block 602, which includes receiving an input RF signal (e.g., at RF input 108 and power divider input 322). For example, the input RF signal may be characterized as an operating base frequency f0. In block 604, the input RF signal (e.g., via power divider 320) is divided into a carrier input RF signal and a peaked input RF signal. The carrier input RF signal (e.g., via divider output 324) is provided to the input of a carrier amplifier (e.g., amplifier 331), and the peaked RF signal (e.g., via divider output 326) is provided to the input of a peaked amplifier 351. One or more phase delays may be applied such that the carrier and peaked input RF signals are out of phase with each other by approximately 90 degrees at the carrier and peaked amplifier inputs. In block 606, the carrier input RF signal is amplified by the carrier amplifier (e.g., amplifier 331), and the peaked input RF signal is amplified by the peaked amplifier (e.g., amplifier 351).

[0281] According to one or more embodiments, in block 608, the amplified carrier RF signal is delivered through the reconfigurable impedance inverter (e.g., through variable network 334 and variable network 340, 440, 540) to a combining node (e.g., combining node 370). At the same time, the amplified peaking RF signal is delivered (e.g., through variable network 354) to the combining node (e.g., combining node 370), and the amplified carrier and peaking RF signals are combined at the combining node 370. Finally, in block 610, and according to one or more embodiments, the amplified combined RF output signal is delivered from the combining node through the variable output impedance transformer (e.g., variable output impedance transformer 380) to the RF output (e.g., RF output 110).

[0282] At the same time as the above-described amplification process performed by the Doherty amplifier, various traffic loading measurements and amplifier control processes are performed in order to reconfigure the Doherty power amplifier into any of a plurality of amplifier states. According to one or more embodiments, prior to reconfiguring the Doherty power amplifier, an initial amplifier configuration is established in block 618. In some embodiments, the initial amplifier configuration can be predetermined to correspond to any amplifier state (e.g., to correspond to the full power state or to another state). Establishing the initial amplifier configuration can involve the base station controller sending an amplifier state control signal to the Doherty power amplifier (or more specifically, to the amplifier controller, e.g., controller 114), and in response, the Doherty power amplifier determining and providing control signals consistent with the initial amplifier state for the reconfigurable output circuit (e.g., circuit 360, 460, 560) of the Doherty power amplifier. Figures 3-5

[0283] ​After establishing the initial amplifier state, the measurement and control process includes block 620 in which the base station controller (or another subsystem) determines the current traffic loading conditions of the communication system. As previously discussed, the traffic loading can be determined based on a measurement or determination of the instantaneous traffic loading of the system compared to one or more thresholds (see, e.g., Table 1 above). Alternatively, the traffic loading can be estimated based on temporal factors (e.g., time of day, day of week, etc.) (see, e.g., Table 2 above). Either way, the base station controller can determine the desired amplifier state to be one of N possible amplifier states (e.g., full power, first back-off power, second back-off power, and so on) based on the measured or expected current traffic loading. After determining the desired amplifier state, the base station controller generates an amplifier state control signal and sends the amplifier state control signal to the Doherty power amplifier (or more specifically, to the amplifier controller, e.g., controller 114). The amplifier state control signal can indicate at least one of the traffic loading conditions, the power level (e.g., full power, first back-off power, etc.), or the amplifier state (e.g., state 1, state 2, etc.).

[0284] According to one or more embodiments, in block 622, the amplifier controller (e.g., amplifier controller 114) receives the amplifier state control signal from the base station controller. In block 624, the amplifier controller then determines a control signal for the reconfigurable output circuit (e.g., circuit 360, 460, 560) corresponding to the desired amplifier state. As previously discussed, each reconfigurable output circuit includes a combining node (e.g., combining node 370), a reconfigurable carrier output circuit (e.g., circuit 334, 340, 440, 540) coupled between a carrier amplifier intrinsic drain terminal and the combining node, a reconfigurable peaking output circuit (e.g., circuit 354) coupled between a peaking amplifier intrinsic drain terminal and the combining node, and a reconfigurable output impedance transformer (e.g., circuit 350) coupled between the combining node and an amplifier output terminal (e.g., RF output 110). Figures 3-5 Figures 3-5 Figures 3-5 Figures 3-5 Figures 3-5 Figures 3-5 Figures 3-5 ​​​​​The amplifier controller can determine the particular control signals, e.g., using one or more look-up tables that relate values of the control signals to switch states (for switch elements 335, 336, 345-348, 355, 356, 545, 546) or variable component states (for variable capacitors 383, 384) (see, e.g., Tables 3-6 above). Alternatively, other suitable control circuitry can be utilized. After determining the control signals, the amplifier controller then provides the control signals to the first, second, third, and fourth variable networks in block 626. According to one or more embodiments, the first, second, third, and fourth variable networks are reconfigured in a synchronized manner with each other to establish each amplifier state. The amplification and network control processes are continuously repeated throughout operation of the Doherty power amplifier.

[0285] An embodiment of a Doherty power amplifier includes first and second amplifiers (e.g., a carrier amplifier and a peaking amplifier, or a peaking amplifier and a carrier amplifier, respectively), a reconfigurable impedance inverter, and an output impedance transformer. The first amplifier has a first amplifier output, and the first amplifier is configured to produce an amplified first output signal. The first amplifier output is characterized as a first amplifier output capacitance. The second amplifier has a second amplifier output, and the second amplifier is configured to produce an amplified second output signal. The second amplifier output is characterized as a second amplifier output capacitance. The reconfigurable impedance inverter circuit includes a combining node and first, second, and third variable networks. The combining node is configured to combine the amplified first output signal with the amplified second output signal, and the combining node is characterized as a combining node impedance. The first variable network is coupled to the first amplifier output, and the first variable network and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance. The second variable network is coupled between the first amplifier output and the combining node, and the second variable network is configured to provide a series inductance between the first amplifier output and the combining node. The third variable network is coupled to the second amplifier output and the combining node, and the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance. The output impedance transformer is coupled between the combining node and an output of the Doherty power amplifier, and the output impedance transformer includes a fourth variable network configured to establish the combining node impedance.

[0286] According to one or more further embodiments, the first variable network includes a first reconfigurable shunt inductance network coupled between the first amplifier output and a ground reference node, and the third variable network includes a second reconfigurable shunt inductance network coupled between the second amplifier output and the ground reference node. According to one or more further embodiments, the second variable network includes a first inductor coupled between the first amplifier output and the combining node, and a first reconfigurable parallel inductance branch coupled in parallel with the first inductor, wherein the first reconfigurable parallel inductance branch includes a second inductor and a first switching element coupled in series between the first amplifier output and the combining node. According to one or more other further embodiments, the fourth variable network includes a phase shift element having a first end coupled to the combining node and a second end coupled to the output of the Doherty power amplifier, a first variable capacitance circuit coupled between the first end of the phase shift element and a ground reference node, and a second variable capacitance circuit coupled between the second end of the phase shift element and the ground reference node.

[0287] According to one or more additional embodiments, the Doherty power amplifier further includes an amplifier controller coupled to the first, second, third, and fourth variable networks. The amplifier controller is configured to receive a signal indicative of a full power state and, in response, provide first control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier in a first amplifier state in which the first amplifier effective output capacitance has a first capacitance value, the second amplifier effective output capacitance has a second capacitance value, the series inductance has a first inductance value, and the combined node impedance has a first impedance value. Additionally, the amplifier controller is configured to receive a signal indicative of a first back-off power state and, in response, provide second control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier in a second amplifier state in which the first amplifier effective output capacitance has a third capacitance value less than the first capacitance value, the second amplifier effective output capacitance has a fourth capacitance value less than the second capacitance value, the series inductance has a second inductance value greater than the first inductance value, and the combined node impedance has a second impedance value greater than the first impedance value.

[0288] An embodiment of a method of operating a Doherty power amplifier includes producing, by a first amplifier, an amplified first output signal at a first amplifier output characterized as a first amplifier output capacitance, and producing, by a second amplifier, an amplified second output signal at a second amplifier output characterized as a second amplifier output capacitance. The method additionally includes passing the amplified first output signal through a first variable network and through a second variable network to a combined node, where the first variable network is coupled to the first amplifier output, the first variable network and the first amplifier output capacitance establish a first amplifier effective output capacitance less than the first amplifier output capacitance, and the second variable network is configured to provide a series inductance between the first amplifier output and the combined node. The method additionally includes passing the amplified second output signal through a third variable network to the combined node, where the third variable network is coupled to the second amplifier output, and the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance less than the second amplifier output capacitance. The method additionally includes combining the first and second amplified output signals at the combined node to produce an amplified combined output signal, where the combined node is characterized as a combined node impedance. The method additionally includes passing the amplified combined output signal through an output impedance transformer coupled between the combined node and an output of the Doherty power amplifier, where the output impedance transformer includes a fourth variable network configured to establish the combined node impedance.

[0289] According to one or more additional embodiments, the method of reconfiguring a Doherty power amplifier includes reconfiguring a first variable network to modify a first amplifier effective output capacitance; reconfiguring a second variable network to modify a series inductance between a first amplifier output and a combining node while reconfiguring the first variable network; reconfiguring a third variable network to modify a second amplifier effective output capacitance while reconfiguring the first variable network; and reconfiguring a fourth variable network to modify a combining node impedance while reconfiguring the first variable network.

[0290] According to one or more additional embodiments, the method includes reconfiguring the first variable network to modify the first amplifier effective output capacitance includes providing, by the amplifier controller, a first switch control signal to the first variable network, the first switch control signal causing at least one first switching element in the first variable network to change state; reconfiguring the second variable network to modify the series inductance between the first amplifier output and the combining node includes providing, by the amplifier controller, a second switch control signal to the second variable network, the second switch control signal causing at least one second switching element in the second variable network to change state; and reconfiguring the third variable network to modify the second amplifier effective output capacitance includes providing, by the amplifier controller, a third switch control signal to the third variable network, the third switch control signal causing at least one third switching element in the third variable network to change state.

[0291] According to one or more additional embodiments, the method includes receiving an amplifier state control signal indicative of at least one of a traffic loading condition, a power level, or an amplifier state; and determining, by the amplifier controller, the first, second, and third control signals from a lookup table, the lookup table associating values of the amplifier state control signal with states of the at least one first switching element, the at least one second switching element, and the at least one third switching element.

[0292] The connecting lines shown in the various figures contained herein are intended to represent example functional relationships and / or physical couplings between the various elements. It should be noted that many alternatives or additional functional relationships or physical connections can be present in a

[0293] As used herein, a "node" means any internal or external reference point, connection point, junction point, signal line, conductive element, etc., at which a given signal, logic level, voltage, data pattern, current, or quantity exists. Moreover, two or more nodes can be implemented by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even if received or output at a common node).

[0294] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated to the contrary, "connected" means that one element is directly connected to another element (or directly communicates with another element) and not necessarily mechanically. Likewise, unless expressly stated to the contrary, "coupled" means that one element is either directly or indirectly connected to (or directly or indirectly communicates with) another element, either electrically or otherwise, and not necessarily mechanically. Therefore, although the schematic diagrams illustrated in the drawings depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components can be present in embodiments of the depicted subject matter.

[0295] As used herein the words "exemplary" or "example" mean "serving as an example, instance, or illustration." Any implementation described herein as exemplary or as an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the foregoing description of various aspects of the subject matter discloses the best mode contemplated at present but does not necessarily comprehensively describe many modifications and variations to which aspects of the subject matter can be prone. Implementations subsumed under the wing of a disclosure as set forth herein are not all that can be resorted to.

[0296] While at least one exemplary embodiment has been presented in the foregoing detailed description of the specific embodiments, it should be appreciated that a vast number of modifications can be made to the embodiments without departing from the scope disclosed herein. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the claimed subject matter, which is defined by the appended claims and their equivalents.

Claims

1. A Doherty power amplifier characterized by, comprises: a first amplifier having a first amplifier output, wherein the first amplifier is configured to produce an amplified first output signal, and the first amplifier output is characterized as a first amplifier output capacitance; a second amplifier having a second amplifier output, wherein the second amplifier is configured to produce an amplified second output signal, and the second amplifier output is characterized as a second amplifier output capacitance; a reconfigurable impedance inverter circuit comprising a combining node configured to combine the amplified first output signal and the amplified second output signal, wherein the combining node is characterized as a combining node impedance, a first variable network coupled to the first amplifier output, wherein the first variable network and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance, a second variable network coupled between the first amplifier output and the combining node, wherein the second variable network is configured to provide a series inductance between the first amplifier output and the combining node, and a third variable network coupled to the second amplifier output and the combining node, wherein the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance; and an output impedance transformer coupled between the combining node and an output of the Doherty power amplifier, wherein the output impedance transformer comprises a fourth variable network configured to establish the combining node impedance.

2. The Doherty power amplifier of claim 1, wherein: the first amplifier comprises a first power transistor having a first drain terminal and a first source terminal, wherein the first drain terminal corresponds to the first amplifier output; the first amplifier output capacitance is a first drain-source capacitance between the first drain terminal and the first source terminal; the second amplifier comprises a second power transistor having a second drain terminal and a second source terminal, wherein the second drain terminal corresponds to the second amplifier output; and the second amplifier output capacitance is a second drain-source capacitance between the second drain terminal and the second source terminal.

3. The Doherty power amplifier of claim 1, wherein: the first variable network comprises a first reconfigurable shunt inductance network coupled between the first amplifier output and a ground reference node; and the third variable network comprises a second reconfigurable shunt inductance network coupled between the second amplifier output and the ground reference node.

4. The Doherty power amplifier of claim 1, wherein: the first variable network comprises a number M of first reconfigurable shunt inductance branches, wherein M is an integer equal to or greater than 1, and a first shunt inductance branch of the first reconfigurable shunt inductance branches comprises a first inductor coupled in series with a first switching element; and the fourth variable network comprises a number N of fourth reconfigurable shunt inductance branches, wherein N is an integer equal to or greater than 1, and a first shunt inductance branch of the fourth reconfigurable shunt inductance branches comprises a fourth inductor coupled in series with a fourth switching element. The third variable network includes the number M of second reconfigurable shunt inductive branches, and a first shunt inductive branch of the second reconfigurable shunt inductive branches includes a second inductor coupled in series with a second switching element.

5. The Doherty power amplifier of claim 1, wherein, The second variable network includes: a first inductor coupled between the first amplifier output and the combination node; and a first reconfigurable shunt inductive branch coupled in shunt with the first inductor, where the first reconfigurable shunt inductive branch includes a second inductor and a first switching element coupled in series between the first amplifier output and the combination node.

6. The Doherty power amplifier of claim 1, wherein, The second variable network includes: a first transmission line segment coupled between the intermediate node and the combination node; and a first reconfigurable shunt transmission line branch coupled in shunt with the first transmission line segment, where the first reconfigurable shunt transmission line branch includes a second transmission line segment and a first switching element coupled in series between the first amplifier output and the combination node.

7. The Doherty power amplifier of claim 1, wherein, The second variable network includes: a first inductor coupled between the first amplifier output and the combination node; a second inductor coupled in series with the first inductor between the first amplifier output and the combination node; and a first bypass switch coupled across the second inductor.

8. The Doherty power amplifier of claim 1, wherein, The fourth variable network includes: a phase shift element having a first end coupled to the combination node and a second end coupled to the output of the Doherty power amplifier; a first variable capacitance circuit coupled between the first end of the phase shift element and a ground reference node; and a second variable capacitance circuit coupled between the second end of the phase shift element and the ground reference node.

9. The Doherty power amplifier of claim 1, wherein, Additionally included are: an amplifier controller coupled to the first, second, third, and fourth variable networks, where the amplifier controller is configured to receive a signal indicative of a full power state and, in response, provide first control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier in a first amplifier state in which the first amplifier effective output capacitance has a first capacitance value, the second amplifier effective output capacitance has a second capacitance value, the series inductance has a first inductance value, and the combination node impedance has a first impedance value, and the amplifier controller is configured to receive a signal indicative of a first back-off power state and, in response, provide second control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier in a second amplifier state in which the first amplifier effective output capacitance has a third capacitance value less than the first capacitance value, the second amplifier effective output capacitance has a fourth capacitance value less than the second capacitance value, the series inductance has a second inductance value greater than the first inductance value, and the combination node impedance has a second impedance value greater than the first impedance value.

10. A method of operating a Doherty power amplifier, characterized by, included are: generating an amplified first output signal at a first amplifier output by a first amplifier, the first amplifier output characterized as a first amplifier output capacitance; generating an amplified second output signal at a second amplifier output by a second amplifier, the second amplifier output characterized as a second amplifier output capacitance; transmitting the amplified first output signal through a first variable network and through a second variable network to a combining node, wherein the first variable network is coupled to the first amplifier output, the first variable network and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance, and the second variable network is configured to provide a series inductance between the first amplifier output and the combining node; transmitting the amplified second output signal through a third variable network to the combining node, wherein the third variable network is coupled to the second amplifier output, and the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance; combining the first and second amplified output signals at the combining node to generate an amplified combining output signal, wherein the combining node is characterized as a combining node impedance; and transmitting the amplified combining output signal through an output impedance transformer coupled between the combining node and an output of the Doherty power amplifier, wherein the output impedance transformer includes a fourth variable network configured to establish the combining node impedance.

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