Low-pass filter chip

Abstract

The invention provides a low-pass filter chip, which is characterized in that an error amplification module outputs error current according to a reference signal and a feedback signal to charge an integrating capacitor module, and a first comparison module compares voltage on a first node with first reference voltage and outputs a first comparison signal; the first comparison module is used for comparing the voltage on the first node with a first reference voltage and outputting a first comparison signal, the second comparison module is used for comparing the voltage on the first node with a second reference voltage and outputting a second comparison signal, and the counting module is used for counting according to the first comparison signal and the second comparison signal; and when the second comparison signal indicates that the voltage on the first node is greater than the second reference voltage, the digital-to-analog conversion module charges the integrating capacitor module, and discharges the integrating capacitor module when the second comparison signal indicates that the voltage on the first node is greater than the second reference voltage, and outputs an integrating signal according to a count value of the counting module. According to the invention, the integrating capacitor module with a small capacitance value can be used for simulating a large capacitor, so that the integrating capacitor module can be integrated in a chip, the integration level is improved, the area of a circuit board and the device cost are reduced, and peripheral elements and failure risks are reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a low-pass filter chip. Background Technology

[0002] In circuits such as PWM dimming circuits, active power factor correction (APFC) circuits, or LED frequency reduction circuits, a low-bandwidth low-pass filter (frequency, for example, 1 / 4 to 1 / 10 of the power frequency) is typically required. This type of low-pass filter often requires a large-value filter capacitor, such as a separate electrolytic capacitor (μF level). Because the capacitance of this filter capacitor is too large, it cannot be integrated into the chip and must be placed externally, thus increasing the board area and component cost, and raising the risk of circuit failure. Summary of the Invention

[0003] The purpose of this invention is to provide a low-pass filter chip to solve the problems of existing low-pass filters where the filter capacitor can only be placed outside the chip, resulting in low integration, high cost, and high failure risk.

[0004] To achieve the above objectives, the present invention provides a low-pass filter chip, comprising:

[0005] The error amplifier module is used to receive the reference signal and the feedback signal, and output the error current.

[0006] An integrating capacitor module is connected between the error amplification module and ground to be charged by the error current, and a first node is provided between the error amplification module and the integrating capacitor module.

[0007] The first comparison module is used to compare the voltage at the first node with the first reference voltage and output a first comparison signal;

[0008] The second comparison module is used to compare the voltage at the first node with the second reference voltage and output a second comparison signal, wherein the second reference voltage is greater than the first reference voltage.

[0009] The counting module is used to determine the relationship between the voltage at the first node and the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, and to perform counting.

[0010] A charge / discharge module is configured to charge the integrating capacitor module when the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, and to discharge the integrating capacitor module when the second comparison signal indicates that the voltage at the first node is greater than the second reference voltage; and,

[0011] A digital-to-analog converter module, connected to the counting module, is used to output an integral signal based on the counting value of the counting module.

[0012] Optionally, the low-pass filter chip further includes:

[0013] The third comparison module is used to compare the voltage at the first node with the magnitude of the third reference voltage and output a third comparison signal, wherein the third reference voltage is the average value of the first reference voltage and the second reference voltage;

[0014] An OR gate is used to perform an OR operation on the first comparison signal and the second comparison signal; and,

[0015] The counting module is connected to the OR gate and the third comparison module to obtain the output signal of the OR gate and the third comparison signal, and to determine the relationship between the voltage on the first node and the first reference voltage and the second reference voltage based on the output signal of the OR gate and the third comparison signal, and to perform counting.

[0016] Optionally, when the voltage at the first node is less than the first reference voltage, the count value of the counting module is reduced by a set value; when the voltage at the first node is greater than the second reference voltage, the count value of the counting module is increased by the set value.

[0017] Optionally, the charging and discharging module includes a first switch and a second switch, the first switch and the second switch being sequentially connected between the power supply terminal and the ground terminal, a second node between the first switch and the second switch being connected to the first node, the output terminal of the first comparison module being connected to the control terminal of the first switch to control the on / off state of the first switch via the first comparison signal, and the output terminal of the second comparison module being connected to the control terminal of the second switch to control the on / off state of the second switch via the second comparison signal.

[0018] Optionally, when the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, the charging and discharging module charges the integrating capacitor module; when the second comparison signal indicates that the voltage at the first node is greater than the second reference voltage, the charging and discharging module discharges the integrating capacitor module.

[0019] Optionally, the charging / discharging module further includes a logic processing module connected between the output of the first comparison module and the control terminal of the first switching transistor. The logic processing module performs logic processing on the first comparison signal to generate a first logic signal to control the on / off state of the first switching transistor; and / or,

[0020] The logic processing module is connected between the output of the second comparison module and the control terminal of the second switch. The logic processing module performs logic processing on the second comparison signal to generate a second logic signal to control the on / off state of the second switch.

[0021] Optionally, the low-pass filter chip may further include:

[0022] A controlled current source, connected to the first node and the digital-to-analog converter module, is used to generate a current signal proportional to the voltage of the first node and inject it into the digital-to-analog converter module.

[0023] Optionally, the digital-to-analog converter module includes an adjustable resistor and a fixed resistor, which are connected in series between the controlled current source and the ground terminal. A current source is connected to a third node between the adjustable resistor and the fixed resistor. The resistance value of the adjustable resistor is adjusted according to the count value of the counter. The fourth node between the adjustable resistor and the controlled current source serves as the output terminal of the digital-to-analog converter module.

[0024] Optionally, the low-pass filter chip further includes:

[0025] A proportional circuit module, connected to the first node, is used to generate a voltage signal proportional to the voltage at the first node; and,

[0026] The adder circuit module is connected to the proportional circuit module and the digital-to-analog converter module, and outputs the superimposed signal of the integral signal and the voltage signal.

[0027] Optionally, the change in the current signal or voltage signal that is proportional to the voltage of the first node during a single charging or discharging process is equal to the minimum change in the output signal of the digital-to-analog converter module.

[0028] In the low-pass filter chip provided by this invention, the error amplification module outputs an error current based on the error between the reference signal and the feedback signal to charge the integrating capacitor module. The voltage at the first node between the error amplification module and the integrating capacitor module is the integral of the error between the reference signal and the feedback signal. The first comparison module compares the voltage at the first node with the first reference voltage and outputs a first comparison signal. The second comparison module compares the voltage at the first node with the second reference voltage and outputs a second comparison signal. When the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, the counting module determines the relationship between the voltage at the first node and the first and second reference voltages based on the first and second comparison signals and performs counting. The charging and discharging module charges the integrating capacitor module when the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, and discharges the integrating capacitor module when the second comparison signal indicates that the voltage at the first node is greater than the second reference voltage. The digital-to-analog conversion module outputs an integral signal based on the count value of the counting module. This invention can use a small-capacity integrating capacitor module to simulate a large capacitor, allowing the integrating capacitor module to be integrated into the chip, improving integration density, reducing circuit board area and device cost, and reducing external components and failure risks. Attached Figure Description

[0029] Figure 1 The circuit diagram of the low-pass filter chip provided in Embodiment 1 of the present invention;

[0030] Figure 2 The circuit diagram is shown for the low-pass filter chip provided in Embodiment 2 of the present invention;

[0031] Figure 3 This is a partial circuit diagram of the digital-to-analog converter module provided in Embodiment 2 of the present invention;

[0032] Figure 4 This is a schematic diagram of the output signal of the digital-to-analog converter module provided in Embodiment 2 of the present invention;

[0033] Figure 5 The circuit diagram of the low-pass filter chip provided in Embodiment 3 of the present invention;

[0034] Figure 6 The circuit diagram of the low-pass filter chip provided in Embodiment 4 of the present invention;

[0035] The attached figures are labeled as follows:

[0036] EA - Transconductance amplifier; LF - Reference signal; VCS - Feedback signal; C - Integrating capacitor; K1 - First node; K2 - Second node; K3 - Third node; K4 - Fourth node; VCOMP_PRE - Voltage at the first node; COMP1 - First comparator; COMP2 - Second comparator; COMP3 - Third comparator; Co1 - First comparison signal; Co2 - Second comparison signal; Co3 - Third comparison signal; VREFL - First reference voltage; VREFH - Second reference voltage; VREFM - Third reference voltage; Counter - Counter; Q1 - First switch; Q2 - Second switch; R1 - First protection resistor; R2 - Second protection resistor; R3 - Adjustable resistor; R4 - Fixed resistor; NO - Inverter gate; DAC - Digital-to-analog converter; Is1 - Current source; I1 - Output current of the current source; Is2 - Controlled current source; I2 - Output current of the controlled current source; VCOMP - Integrating signal; ΔV - Change in voltage at the first node during a single charge / discharge cycle. Detailed Implementation

[0037] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0038] Figure 1 This is a circuit diagram of the low-pass filter chip provided in this embodiment. Figure 1 As shown, the low-pass filter chip can be applied to PWM dimming circuits, active power factor correction circuits, or LED flash reduction circuits, but it should not be limited thereto. The low-pass filter chip in this invention can also be applied to other applications as a highly integrated low-pass filter. The low-pass filter chip includes an error amplification module, an integrating capacitor module, a first comparison module, a second comparison module, a counting module, a charging / discharging module, and a digital-to-analog conversion module.

[0039] Specifically, the error amplification module includes a transconductance amplifier EA. The first input terminal of the transconductance amplifier EA (positive input terminal in this embodiment) is used to receive the reference signal LF, and the second input terminal of the transconductance amplifier EA (negative input terminal in this embodiment) is used to receive the feedback signal VCS. The transconductance amplifier EA amplifies the difference between the reference signal LF and the feedback signal VCS and outputs an error current.

[0040] The feedback signal VCS is typically obtained by sampling parameters in the circuit, while the reference signal LF is a reference signal that needs to be compared with the feedback signal VCS. For example, in an active power factor correction circuit, the feedback signal VCS is a sampled signal of the voltage (or current) signal with power frequency ripple at the circuit output, and the reference signal LF is a constant voltage (or current) signal; in a PWM dimming circuit, the feedback signal VCS is a sampled signal of the LED current, and the reference signal LF is a PWM signal ranging from several hundred Hz to several kHz; in an LED frequency reduction circuit, the feedback signal VCS is a sampled signal of the voltage signal with power frequency ripple at a certain node in the circuit, and the reference signal LF is a constant voltage signal.

[0041] The integrating capacitor module includes an integrating capacitor C. The first terminal of the integrating capacitor C is connected to the output terminal of the transconductance amplifier EA, and the second terminal of the integrating capacitor C is connected to ground. Thus, the integrating capacitor C can be charged by the error current output by the transconductance amplifier EA. There is a first node K1 between the first terminal of the integrating capacitor C and the output terminal of the transconductance amplifier EA. The voltage VCOMP_PRE at the first node K1 is also the voltage across the integrating capacitor C, reflecting the integral of the error between the reference signal LF and the feedback signal VCS.

[0042] It should be understood that the integrating capacitor module is not limited to containing only one integrating capacitor, but may also contain at least two integrating capacitors.

[0043] In this embodiment, the capacitance value of the integrating capacitor C is less than 100pF, so it can be easily integrated into the low-pass filter chip without needing to be placed outside the chip. The reason why the capacitance value of the integrating capacitor C can be in the pF level will be explained below.

[0044] Further, the first comparison module includes a first comparator COMP1. The first input terminal of the first comparator COMP1 (positive input terminal in this embodiment) receives a first reference voltage VREFL. The second input terminal of the first comparator COMP1 (negative input terminal in this embodiment) is connected to the first node K1 to receive the voltage VCOMP_PRE on the first node K1. The first comparator COMP1 compares the voltage VCOMP_PRE on the first node K1 with the first reference voltage VREFL and outputs a first comparison signal Co1. The first comparison signal Co1 indicates the magnitude relationship between the voltage VCOMP_PRE on the first node K1 and the first reference voltage VREFL. Specifically, when the voltage VCOMP_PRE on the first node K1 is less than the first reference voltage VREFL, the first comparison signal Co1 is high; when the voltage VCOMP_PRE on the first node K1 is greater than the first reference voltage VREFL, the first comparison signal Co1 is low.

[0045] Similarly, the second comparison module includes a second comparator COMP2. The first input terminal of the second comparator COMP2 (the positive input terminal in this embodiment) is connected to the first node K1 to receive the voltage VCOMP_PRE on the first node K1. The second input terminal of the first comparator COMP1 (the negative input terminal in this embodiment) receives the second reference voltage VREFH. The second comparator COMP2 compares the voltage VCOMP_PRE on the first node K1 with the second reference voltage VREFH and outputs a second comparison signal Co2. The second comparison signal Co2 can indicate the magnitude relationship between the voltage VCOMP_PRE on the first node K1 and the second reference voltage VREFH. Specifically, when the voltage VCOMP_PRE on the first node K1 is greater than the second reference voltage VREFH, the second comparison signal Co2 is high; when the voltage VCOMP_PRE on the first node K1 is less than the second reference voltage VREFH, the second comparison signal Co2 is low.

[0046] In this embodiment, the second reference voltage VREFH is greater than the first reference voltage VREFL.

[0047] The counting module can determine the relationship between the voltage VCOMP_PRE at the first node K1 and the first reference voltage VREFL and the second reference voltage VREFH based on the first comparison signal Co1 and the second comparison signal Co2, and then perform counting. Specifically, the counting module includes a counter, which in this embodiment is an up-and-down counter. The two input terminals of the counter are respectively connected to the output terminals of the first comparator COMP1 and the second comparator COMP2, and are used to receive the first comparison signal Co1 and the second comparison signal Co2. The counter can determine the relationship between the voltage at the first node K1 and the first reference voltage VREFL and the second reference voltage VREFH based on the first comparison signal Co1 and the second comparison signal Co2, and then perform counting. Specifically, when the first comparison signal Co1 indicates that the voltage VCOMP_PRE on the first node K1 is less than the first reference voltage VREFL (i.e., when the first comparison signal Co1 is high), the counter count value is reduced by the set value, and when the second comparison signal Co2 indicates that the voltage VCOMP_PRE on the first node K1 is greater than the second reference voltage VREFH (i.e., when the second comparison signal Co2 is high), the counter count value is increased by the set value.

[0048] In this embodiment, the setting value is 1, that is, the counter value is increased by 1 or decreased by 1 each time, but it should not be limited to this, and the setting value can also be other values.

[0049] The charging / discharging module includes a first switch Q1, a second switch Q2, a first protection resistor R1, and a second protection resistor R2. The first switch Q1, the first protection resistor R1, the second switch Q2, and the second protection resistor R2 are sequentially connected between a power supply terminal and a ground terminal. Specifically, the source of the first switch Q1 is connected to the power supply terminal, the drain of the first switch Q1 is connected to the first terminal of the first protection resistor R1, the second terminal of the first protection resistor R1 is connected to the drain of the second switch Q2, the source of the second switch Q2 is connected to the first terminal of the second protection resistor R2, the second terminal of the second protection resistor R2 is connected to the ground terminal, and a second node K2 is located between the second terminal of the first protection resistor R1 and the drain of the second switch Q2, and the second node K2 is connected to the first node K1. Furthermore, in this embodiment, the first switch Q1 is a PMOS transistor, and the second switch Q2 is an NMOS transistor.

[0050] Furthermore, the charging / discharging module also includes a NOT gate NO. The input of NOT gate NO is connected to the output of the first comparator COMP1 to receive the first comparison signal Co1. The output of NOT gate NO is connected to the gate of the first switch Q1 to perform a NOT operation on the first comparison signal Co1 and input the result to the gate of the first switch Q1 to control the on / off state of the first switch Q1. The gate of the second switch Q2 is directly connected to the second comparator COMP2 to receive the second comparison signal Co2. The second comparison signal Co2 directly controls the on / off state of the second switch Q2. Specifically, when the first comparison signal Co1 indicates that the voltage VCOMP_PRE on the first node K1 is less than the first reference voltage VREFL, the second comparison signal Co2 indicates that the voltage VCOMP_PRE on the first node K1 is less than the second reference voltage VREFH. The first switch Q1 is turned on, the second switch Q2 is turned off, and the power supply charges the integrating capacitor C through the first switch Q1. At this time, the voltage VCOMP_PRE on the first node K1 increases, specifically, it can increase to be greater than the first reference voltage VREFL and less than the second reference voltage VREFH. When the second comparison signal Co2 indicates that the voltage VCOMP_PRE on the first node K1 is greater than the second reference voltage VREFH, the first comparison signal Co1 indicates that the voltage VCOMP_PRE on the first node K1 is greater than the first reference voltage VREFL. The second switch Q2 is turned on, the first switch Q1 is turned off, and the voltage on the integrating capacitor C is released to ground through the second switch Q2. At this time, the voltage VCOMP_PRE on the first node K1 decreases, specifically, it can decrease to be greater than the first reference voltage VREFL and less than the second reference voltage VREFH.

[0051] It should be noted that the first protection resistor R1 and the second protection resistor R2 can be designed to be relatively small, thereby enabling rapid charging and discharging of the integrating capacitor C. In some embodiments, the first protection resistor R1 and the second protection resistor R2 can be omitted.

[0052] In some embodiments, when the positive and negative input terminals of the first comparator COMP1 are swapped, or the positive and negative input terminals of the second comparator COMP2 are swapped, or the device types of the first switch Q1 and the second switch Q2 are changed, the NOT gate NO can be omitted. Of course, the NOT gate NO may be replaced by other logic processing modules. The logic processing module can perform logic processing on the first comparison signal Co1 to generate a first logic signal to control the on / off state of the first switch Q1; and / or, the logic processing module can also be located between the output terminal of the second comparator COMP2 and the control terminal of the second switch Q2. The logic processing module performs logic processing on the second comparison signal Co2 to generate a second logic signal to control the on / off state of the second switch Q2. The specific structure of the logic processing module can be designed according to the situation, as long as it can achieve the same control logic as this embodiment. Examples will not be given here.

[0053] The digital-to-analog conversion module includes a digital-to-analog converter (DAC). The input of the DAC is connected to the output of a counter (Counter) to acquire the count value of the counter. As the count value of the counter changes, the DAC can output an integral signal VCOMP of corresponding magnitude based on the count value.

[0054] In this embodiment, the low-pass filter chip further includes a current source Is1, which is connected to the digital-to-analog converter (DAC) and is used to provide a constant current to the DAC. In some embodiments, the current source Is1 may be omitted.

[0055] Please continue reading. Figure 1For example, when the reference signal LF is greater than the feedback signal VCS, the voltage VCOMP_PRE on the first node K1 increases. When the voltage VCOMP_PRE on the first node K1 increases to be greater than the second reference voltage VREFH, the second comparison signal Co2 flips to a high level (the first comparison signal Co1 is at a low level at this time), indicating that the voltage VCOMP_PRE on the first node K1 is greater than the second reference voltage VREFH. At this time, the counter value is incremented by 1, and the value of the integral signal VCOMP output by the digital-to-analog converter DAC increases. At the same time, the second switch Q2 is turned on at a high level (at this time, the first switch Q1 is turned off at a high level), and the integrating capacitor C discharges rapidly through the second switch Q2 until the voltage VCOMP_PRE on the first node K1 is less than the second reference voltage VREFH (but still greater than the first reference voltage VREFL), at which point the discharge stops. At this time, the second comparison signal Co2 flips to a low level, the second switch Q2 is turned off at a low level, while the first comparison signal Co1 is still at a low level, and the first switch Q1 is also turned off at a high level, and the charging and discharging module does not work.

[0056] After this, if the reference signal LF is still greater than the feedback signal VCS, the above operation is repeated. The count value of the counter Counter increases continuously, and the value of the integral signal VCOMP output by the digital-to-analog converter DAC also gradually increases. Each increment is related to the resolution of the digital-to-analog converter DAC (LSB, the minimum change in the output signal of the digital-to-analog converter DAC).

[0057] Similarly, when the reference signal LF is less than the feedback signal VCS, the voltage VCOMP_PRE on the first node K1 decreases. When the voltage VCOMP_PRE on the first node K1 decreases to less than the first reference voltage VREFL, the first comparison signal Co1 flips to a high level (the second comparison signal Co2 is low at this time), indicating that the voltage VCOMP_PRE on the first node K1 is less than the first reference voltage VREFL. At this time, the counter value is decremented by 1, and the value of the integral signal VCOMP output by the digital-to-analog converter DAC decreases. At the same time, the first switch Q1 is turned on at a low level (the second switch Q2 is turned off at a low level at this time), and the power supply quickly charges the integrating capacitor C through the first switch Q1 until the voltage VCOMP_PRE on the first node K1 is greater than the first reference voltage VREFL (but still less than the second reference voltage VREFH), then the discharge stops. At this time, the first comparison signal Co1 flips to a low level, the first switch Q1 is turned off at a high level, while the second comparison signal Co2 is still low, and the second switch Q2 is also turned off at a low level. The charging and discharging module does not work.

[0058] After this, if the reference signal LF is still less than the feedback signal VCS, the above operation is repeated. The count value of the counter Counter continues to decrease, and the value of the integral signal VCOMP output by the digital-to-analog converter DAC also gradually decreases. Each decrease is related to the resolution of the digital-to-analog converter DAC.

[0059] As can be seen, the integral signal VCOMP output by the digital-to-analog converter (DAC) changes with the feedback signal VCS. VCOMP reflects the integral of the error between the reference signal LF and the feedback signal VCS. When the change (increment or decrease) of the voltage VCOMP_PRE at the first node K1 is large (i.e., when the voltage change across the integrating capacitor C is large), the change in the integral signal VCOMP is small each time. Therefore, low-pass filtering of the voltage VCOMP_PRE at the first node K1 is achieved, which is equivalent to amplifying the integrating capacitor C. This means a smaller integrating capacitor C can simulate a large capacitor, allowing the integrating capacitor C to be integrated into the chip, improving integration density, reducing board area and device cost, and reducing external components and failure risks. In practical applications, the integral signal VCOMP can control the frequency / peak current of the applied circuit system, increasing or decreasing the circuit system's output, thereby achieving system stability.

[0060] Example 2

[0061] Figure 2 This is a circuit diagram of the low-pass filter chip provided in this embodiment. Figure 2 As shown, the difference from Embodiment 1 is that in this embodiment, the low-pass filter chip further includes a controlled current source Is2, used to generate a current signal proportional to the voltage VCOMP_PRE of the first node K1, and inject it into the digital-to-analog converter (DAC). Specifically, the controlled current source Is2 is connected to the first node K1 and the DAC. Is2 is a voltage-controlled current source that can inject the current signal corresponding to a k-fold reduction of the voltage VCOMP_PRE on the first node K1 into the DAC. At this time, the DAC can output the superposition signal of the integral signal VCOMP and the voltage VCOMP_PRE reduced by a k-fold on the first node K1. That is, the output of the DAC can represent VCOMP + VCOMP_PRE / k, where k is between 100 and 1000.

[0062] Figure 3 This is a partial circuit diagram of the digital-to-analog converter (DAC) module provided in this embodiment. Figure 3As shown, the digital-to-analog converter (DAC) module includes an adjustable resistor R3 and a fixed resistor R4. The adjustable resistor R3 and the fixed resistor R4 are connected sequentially between the controlled current source Is2 and ground. Specifically, the first end of the adjustable resistor R3 is connected to the output terminal of the controlled current source Is2, the second end of the adjustable resistor R3 is connected to the first end of the fixed resistor R4, the second end of the fixed resistor R4 is connected to ground, the third node K3 between the second end of the adjustable resistor R3 and the first end of the fixed resistor R4 is connected to the output terminal of the current source Is1, and the fourth node K4 between the first end of the adjustable resistor R3 and the output terminal of the controlled current source Is2 serves as the output terminal of the DAC module.

[0063] It is understandable that the voltage at the fourth node K4 is I1*(R3+R4)+I2*R4, where I1 is the output current of current source Is1 and I2 is the output current of controlled current source Is2. The digital-to-analog converter (DAC) can adjust the resistance of the adjustable resistor R3 according to the count value of the counter, thereby changing the value of I1*(R3+R4). Therefore, I1*(R3+R4) can represent the integral signal VCOMP, and I2 is the current corresponding to VCOMP_PRE / k. Therefore, I2*R4 can represent VCOMP_PRE / k. It can be seen that the output signal of the DAC can represent VCOMP+VCOMP_PRE / k.

[0064] Understandably, in Embodiment 1, the integral signal VCOMP output by the digital-to-analog converter (DAC) is a discontinuous digital voltage signal. The amount of change in the integral signal VCOMP is affected by the resolution of the DAC. In some applications, such as PWM dimming circuits, it is desirable for the change in the output of the DAC to be very small between two consecutive outputs. This places very high demands on the DAC and is difficult to achieve. In this embodiment, the output of the DAC is VCOMP + VCOMP_PRE / k, which is equivalent to adding an analog quantity proportional to the voltage VCOMP_PRE at the first node K1 to the digital integral signal VCOMP, making the output signal of the DAC continuously changing. In particular, if the change in current or voltage signal proportional to the voltage VCOMP_PRE at the first node K1 during a single charging or discharging process is equal to the minimum change in the output signal of the digital-to-analog converter (DAC), that is, the change in voltage VCOMP_PRE at the first node K1 during a single charging / discharging process ΔV multiplied by k is equal to the minimum change in the output signal of the DAC, then the output signal of the DAC will not have low-frequency abrupt changes during the change process, thus avoiding the quantization abrupt change problem caused by digital output.

[0065] Figure 4This is a schematic diagram of the output signal of the digital-to-analog converter (DAC) module provided in this embodiment. Figure 4 As shown, when the voltage VCOMP_PRE at the first node K1 integrates to a value greater than the second reference voltage VREFH, the output signal of the digital-to-analog converter (DAC) increases by a change. Simultaneously, the voltage VCOMP_PRE at the first node K1 is rapidly discharged by a ΔV. If the voltage corresponding to ΔV multiplied by k equals the minimum change in the output signal of the DAC, then the value of the DAC's output signal is rapidly reduced to its value before the minimum change, which manifests as a short pulse with a change in amplitude on the voltage waveform. Figure 4 The vertical line in the DAC output (this short pulse has a relatively small impact and is easily filtered out (it can be filtered out using a low-value capacitor or the parasitic capacitance inside the chip). A similar operation occurs when the voltage VCOMP_PRE on the first node K1 drops below the first reference voltage VREFL, ultimately achieving continuously adjustable output voltage for the DAC module. The final bandwidth of the low-pass filter chip is approximately Gm / (Cm / k), where Gm is the transconductance of the transconductance amplifier EA, Cm is the capacitance of the integrating capacitor C, which is amplified by a factor of k, and retains the advantages of analog filtering methods: high speed, no digital quantization error, and lower requirements on the DAC module.

[0066] Example 3

[0067] Figure 5 This is a circuit diagram of the low-pass filter chip provided in this embodiment. Figure 5 As shown, the difference from Embodiment 2 is that in this embodiment, the low-pass filter chip further includes a proportional circuit module and an adder circuit module. The proportional circuit module is connected to the first node K1 and is used to generate a voltage signal proportional to the voltage VCOMP_PRE on the first node K1, specifically by reducing the voltage VCOMP_PRE on the first node K1 by a factor of k. The adder circuit module is connected to the proportional circuit module and the digital-to-analog converter (DAC) module, and is used to output the superposition signal of the voltage signal VCOMP_PRE / k output by the proportional circuit module and the integral signal VCOMP output by the DAC module. That is, the output signal of the adder circuit module can also represent VCOMP + VCOMP_PRE / k.

[0068] Example 4

[0069] Figure 6 This is a circuit diagram of the low-pass filter chip provided in this embodiment. Figure 6 As shown, the difference from Embodiment 1 is that in this embodiment, the low-pass filter chip further includes a third comparison module and an OR gate.

[0070] The third comparison module includes a third comparator COMP3. The first input terminal of COMP3 (positive input in this embodiment) is connected to the first node K1 to receive the voltage VCOMP_PRE on the first node K1. The second input terminal of COMP3 (negative input in this embodiment) receives the third reference voltage VREFM. COMP3 compares the voltage VCOMP_PRE on the first node K1 with the third reference voltage VREFM and outputs a third comparison signal Co3. Co3 indicates the magnitude relationship between VCOMP_PRE and VREFM. Specifically, Co3 is high when VCOMP_PRE is greater than VREFM and low when VCOMP_PRE is less than VREFM.

[0071] In this embodiment, the third reference voltage VREFM is equal to the average of the first reference voltage VREFL and the second reference voltage VREFH, that is: VREFM=(VREFL+VREFH) / 2.

[0072] The two inputs of the OR gate are connected to the outputs of the first comparator COMP1 and the second comparator COMP2, respectively, to receive the first comparison signal Co1 and the second comparison signal Co2, and to perform an OR operation on the first comparison signal Co1 and the second comparison signal Co2. The outputs of the OR gate and the third comparator COMP3 are both connected to a counter. The counter can determine the relationship between the voltage at the first node K1 and the first reference voltage VREFL and the second reference voltage VREFH based on the output signal of the OR gate, and then count the values.

[0073] For example, when the voltage VCOMP_PRE on the first node K1 is greater than the second reference voltage VREFH, the voltage VCOMP_PRE on the first node K1 will also necessarily be greater than the third reference voltage VREFM. In this case, the second comparison signal Co2 is high, the first comparison signal Co1 is low, the OR gate outputs a high level, the third comparison signal Co3 is also high, and the counter value is incremented by 1. When the voltage VCOMP_PRE on the first node K1 is less than the first reference voltage VREFL, the voltage VCOMP_PRE on the first node K1 will also necessarily be less than the third reference voltage VREFM. In this case, the first comparison signal Co1 is high, the second comparison signal Co2 is low, the OR gate outputs a high level, the third comparison signal Co3 is also low, and the counter value is decremented by 1.

[0074] In summary, in the low-pass filter chip provided in this embodiment of the invention, the error amplification module outputs an error current based on the error between the reference signal and the feedback signal to charge the integrating capacitor module. The voltage at the first node between the error amplification module and the integrating capacitor module is the integral of the error between the reference signal and the feedback signal. The first comparison module compares the voltage at the first node with the first reference voltage and outputs a first comparison signal. The second comparison module compares the voltage at the first node with the second reference voltage and outputs a second comparison signal. When the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, the counting module determines the relationship between the voltage at the first node and the first and second reference voltages based on the first and second comparison signals and performs counting. The charging and discharging module charges the integrating capacitor module when the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, and discharges the integrating capacitor module when the second comparison signal indicates that the voltage at the first node is greater than the second reference voltage. The digital-to-analog conversion module outputs an integral signal based on the count value of the counting module. This invention can use a small-capacity integrating capacitor module to simulate a large capacitor, allowing the integrating capacitor module to be integrated into the chip, improving integration density, reducing circuit board area and device cost, and reducing external components and failure risks.

[0075] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0076] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0077] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0078] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A low-pass filter chip, characterized in that, include: The error amplifier module is used to receive the reference signal and the feedback signal, and output the error current. An integrating capacitor module is connected between the error amplification module and ground to be charged by the error current, and a first node is provided between the error amplification module and the integrating capacitor module. The first comparison module is used to compare the voltage at the first node with the first reference voltage and output a first comparison signal; The second comparison module is used to compare the voltage at the first node with the second reference voltage and output a second comparison signal, wherein the second reference voltage is greater than the first reference voltage. The counting module is used to determine the relationship between the voltage at the first node and the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, and to perform counting. A charge / discharge module is configured to charge the integrating capacitor module when the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, and to discharge the integrating capacitor module when the second comparison signal indicates that the voltage at the first node is greater than the second reference voltage; and, A digital-to-analog converter module, connected to the counting module, is used to output an integral signal based on the counting value of the counting module.

2. The low-pass filter chip as described in claim 1, characterized in that, The low-pass filter chip also includes: The third comparison module is used to compare the voltage at the first node with the magnitude of the third reference voltage and output a third comparison signal, wherein the third reference voltage is the average value of the first reference voltage and the second reference voltage; An OR gate is used to perform an OR operation on the first comparison signal and the second comparison signal; and, The counting module is connected to the OR gate and the third comparison module to obtain the output signal of the OR gate and the third comparison signal, and to determine the relationship between the voltage on the first node and the first reference voltage and the second reference voltage based on the output signal of the OR gate and the third comparison signal, and to perform counting.

3. The low-pass filter chip as described in claim 1 or 2, characterized in that, When the voltage at the first node is less than the first reference voltage, the count value of the counting module is reduced by a set value; when the voltage at the first node is greater than the second reference voltage, the count value of the counting module is increased by the set value.

4. The low-pass filter chip as described in claim 1, characterized in that, The charging and discharging module includes a first switch and a second switch, which are sequentially connected between a power supply terminal and a ground terminal. A second node between the first and second switches is connected to the first node. The output terminal of the first comparison module is connected to the control terminal of the first switch to control the switching on and off of the first switch via the first comparison signal. The output terminal of the second comparison module is connected to the control terminal of the second switch to control the switching on and off of the second switch via the second comparison signal.

5. The low-pass filter chip as described in claim 4, characterized in that, When the first comparison signal indicates that the voltage at the first node is less than the first reference voltage, the charge-discharge module charges the integrating capacitor module; when the second comparison signal indicates that the voltage at the first node is greater than the second reference voltage, the charge-discharge module discharges the integrating capacitor module.

6. The low-pass filter chip as described in claim 4, characterized in that, The charging and discharging module further includes a logic processing module, which is connected between the output terminal of the first comparison module and the control terminal of the first switching transistor. The logic processing module performs logic processing on the first comparison signal to generate a first logic signal to control the on / off state of the first switching transistor. And / or, The logic processing module is connected between the output of the second comparison module and the control terminal of the second switch. The logic processing module performs logic processing on the second comparison signal to generate a second logic signal to control the on / off state of the second switch.

7. The low-pass filter chip as described in claim 1, characterized in that, The low-pass filter chip also includes: A controlled current source, connected to the first node and the digital-to-analog converter module, is used to generate a current signal proportional to the voltage of the first node and inject it into the digital-to-analog converter module.

8. The low-pass filter chip as described in claim 7, characterized in that, The digital-to-analog converter module includes an adjustable resistor and a fixed resistor. The adjustable resistor and the fixed resistor are connected in series between the controlled current source and the ground terminal. A current source is connected to the third node between the adjustable resistor and the fixed resistor. The resistance value of the adjustable resistor is adjusted according to the count value of the counter. The fourth node between the adjustable resistor and the controlled current source serves as the output terminal of the digital-to-analog converter module.

9. The low-pass filter chip as described in claim 1, characterized in that, The low-pass filter chip also includes: A proportional circuit module, connected to the first node, is used to generate a voltage signal proportional to the voltage at the first node; and, The adder circuit module is connected to the proportional circuit module and the digital-to-analog converter module, and outputs the superimposed signal of the integral signal and the voltage signal.

10. The low-pass filter chip according to any one of claims 7 to 9, characterized in that, The change in the current signal or voltage signal that is proportional to the voltage of the first node during a single charging or discharging process is equal to the minimum change in the output signal of the digital-to-analog converter module.

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