Gain error compensation circuit and method for pipelined analog-to-digital converter and pipelined analog-to-digital converter

Abstract

The invention discloses a gain error compensation circuit and method of a pipelined analog-to-digital converter and the pipelined analog-to-digital converter, and belongs to the technical field of electronic circuits, and the circuit comprises a first-stage quantization circuit which is used for carrying out quantization on a sampling signal to obtain a first-stage quantization code and a residual error; the residual error amplifying circuit is used for amplifying the first-stage quantized residual error to obtain a quantized and amplified residual error; the second-stage quantization circuit is used for quantizing the quantization amplification residual error to obtain a second-stage quantization code; wherein the residual amplification circuit is provided with a time domain analog-to-digital converter which is used for detecting the voltage of a virtual ground point and converting the voltage into compensation gain through a capacitive digital-to-analog converter, so that the compensation gain is compensated to the output end of the closed-loop residual amplifier. According to the application, the virtual point is detected through the time domain analog-to-digital converter, the parasitic capacitance can be effectively reduced, the noise performance of the amplifier and the whole system can be improved, and the whole precision can be effectively improved by performing gain compensation on the closed-loop residual amplifier.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to a gain error compensation circuit, method and pipelined analog-to-digital converter. BACKGROUND

[0002] Currently, among various analog-to-digital converter architectures, a pipelined ADC (Pipelined ADC) is widely used in high-speed communication systems due to its ability to achieve high-speed, high-precision data conversion and relatively low power consumption.

[0003] In related technologies, as integrated circuit technology upgrades, transistor feature sizes under advanced process nodes are becoming smaller and smaller, resulting in reduced operating voltages and intrinsic gains, which in turn causes gain error problems in traditional closed-loop negative feedback residual amplifiers. Therefore, to overcome the above problems, it is common to reduce the closed-loop gain of the residual amplifier or use an open-loop sub-amplifier with the same gain as the ideal gain of the closed-loop amplifier to compensate for the amplifier. However, in actual applications, it is found that reducing the closed-loop gain of the residual amplifier will cause the output swing of the next stage analog-to-digital converter to decrease, thereby affecting its resolution. In addition, using an open-loop sub-amplifier for compensation often means that a larger input transistor size is needed, thereby introducing larger parasitic capacitances, which affects the performance of the amplifier and the entire ADC, and a complex calibration circuit is needed to calibrate its gain, increasing the design difficulty of the circuit.

[0004] To sum up, the technical problems in related technologies need to be improved. SUMMARY

[0005] The embodiments of the present application provide a gain error compensation circuit, method and pipelined analog-to-digital converter, which can automatically evaluate software workload, reduce the influence of human subjective factors, improve the accuracy of software workload evaluation, and provide a scientific basis for software project management.

[0006] In one aspect, the embodiments of the present application provide a gain error compensation circuit for a pipelined analog-to-digital converter, which comprises a first quantization circuit, a second quantization circuit and a residual amplification circuit. The first quantization circuit is configured to quantize a sampling signal to obtain a first quantization code and a first quantization residual, and output the first quantization residual to the residual amplification circuit. The residual amplification circuit is configured to amplify the first quantization residual to obtain a quantization amplified residual, and output the quantization amplified residual to the second quantization circuit. The second quantization circuit is configured to quantize the quantization amplified residual to obtain a second quantization code. The residual amplification circuit is provided with a time domain analog-to-digital converter, which is used for detecting the virtual ground voltage of a closed-loop residual amplifier in the residual amplification circuit, and converting the detection result into a compensation gain through a capacitive digital-to-analog converter, so as to compensate the compensation gain to the output end of the closed-loop residual amplifier.

[0007] Optionally, the residual amplification circuit comprises a first capacitor, a second capacitor, a closed-loop residual amplifier, a first time domain analog-to-digital converter, and a first capacitive digital-to-analog converter. One end of the first capacitor is connected to the output end of the first-stage quantization circuit. The other end of the first capacitor and one end of the second capacitor are connected to the residual input end of the closed-loop residual amplifier. The other end of the second capacitor is connected to the output end of the closed-loop residual amplifier. The input end of the first time domain analog-to-digital converter is connected to the residual input end of the closed-loop residual amplifier. The output end of the first time domain analog-to-digital converter is connected to the input end of the first capacitive digital-to-analog converter. The output end of the first capacitive digital-to-analog converter is connected to the output end of the closed-loop residual amplifier. The output end of the closed-loop residual amplifier is connected to the second-stage quantization circuit.

[0008] Optionally, the residual amplification circuit further comprises a first voltage-to-time converter. One end of the first voltage-to-time converter is connected to the input end of the first time domain analog-to-digital converter. The other end of the first voltage-to-time converter is connected to the residual input end of the closed-loop residual amplifier.

[0009] Optionally, the first-stage quantization circuit comprises a first sample-and-hold device, a second capacitive digital-to-analog converter, a second sample-and-hold device, a third capacitive digital-to-analog converter, a first successive approximation type quantizer, and a second time domain analog-to-digital converter. One end of the first sample-and-hold device and one end of the second sample-and-hold device are connected to the input end of a sampling signal. The other end of the first sample-and-hold device is connected to the input end of the second capacitive digital-to-analog converter. The other end of the second sample-and-hold device is respectively connected to the input end of the third capacitive digital-to-analog converter and the input end of the first successive approximation type quantizer. The output end of the first successive approximation type quantizer is connected to the input end of the second capacitive digital-to-analog converter and the input end of the third capacitive digital-to-analog converter. an output terminal of the third capacitive digital-to-analog converter is connected to an input terminal of the second time-domain analog-to-digital converter; an output terminal of the second time-domain analog-to-digital converter is connected to an input terminal of the second capacitive digital-to-analog converter; an output terminal of the second capacitive digital-to-analog converter is connected to an output terminal of the first-stage quantization circuit.

[0010] Optionally, the first-stage quantization circuit further comprises a second voltage-to-time converter. one end of the second voltage-to-time converter is connected to an input terminal of the second time-domain analog-to-digital converter; the other end of the second voltage-to-time converter is connected to an output terminal of the third capacitive digital-to-analog converter.

[0011] Optionally, the second-stage quantization circuit comprises a fourth capacitive digital-to-analog converter, a comparator, and a second successive approximation quantizer. an input terminal of the fourth capacitive digital-to-analog converter is connected to the residual amplification circuit; an output terminal of the fourth capacitive digital-to-analog converter is connected to the comparator; an input terminal of the second successive approximation quantizer is connected to the comparator; an output terminal of the second successive approximation quantizer is connected to an output terminal of the second-stage quantization circuit.

[0012] Optionally, the gain error compensation circuit of the pipeline analog-to-digital converter further comprises a quantization and coding splicing module. the quantization and coding splicing module is configured to receive the first-stage quantization coding and the second-stage quantization coding; the quantization and coding splicing module is further configured to splice and align the first-stage quantization coding and the second-stage quantization coding to obtain and output a quantization coding result of the sampling signal.

[0013] In another aspect, an embodiment of the present application provides a gain error compensation method of a pipeline analog-to-digital converter, and the method comprises the following steps: obtaining a sampling signal; quantizing the sampling signal by a first-stage quantization circuit to obtain first-stage quantization coding and a first-stage quantization residual; amplifying the first-stage quantization residual by a residual amplification circuit to obtain a quantization amplified residual; quantizing the quantization amplified residual by a second-stage quantization circuit to obtain second-stage quantization coding; The residual amplifier circuit is equipped with a time-domain analog-to-digital converter. The time-domain analog-to-digital converter is used to detect the virtual ground voltage of the closed-loop residual amplifier in the residual amplifier circuit, and convert the detection result into a compensation gain through a capacitive digital-to-analog converter, thereby compensating the output terminal of the closed-loop residual amplifier.

[0014] Optionally, after quantizing the quantization amplification residual through a two-stage quantization circuit to obtain a two-stage quantization code, the method further includes: Based on the first-level quantization code and the second-level quantization code, the data is spliced ​​and aligned to obtain and output the quantization code result of the sampled signal.

[0015] On the other hand, embodiments of this application provide a pipelined analog-to-digital converter, including: a gain error compensation circuit for the pipelined analog-to-digital converter as described in any of the above embodiments.

[0016] This application embodiment detects virtual locations using a time-domain analog-to-digital converter, which can effectively reduce parasitic capacitance, improve the noise performance of the amplifier and the overall system, and effectively improve overall accuracy by compensating the gain of the closed-loop residual amplifier. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the gain error compensation circuit of a pipelined analog-to-digital converter provided in an embodiment of this application; Figure 2 This is a schematic diagram of a residual amplifier circuit provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a gain error compensation method for a pipelined analog-to-digital converter provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0020] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Currently, among various analog-to-digital converter architectures, pipelined ADCs are widely used in high-speed communication systems due to their ability to achieve high-speed, high-precision data conversion and relatively low power consumption.

[0023] In related technologies, with the upgrading of integrated circuit processes, the feature size of transistors at advanced process nodes is becoming smaller and smaller, leading to a decrease in operating voltage and intrinsic gain. This, in turn, causes gain error problems in traditional closed-loop negative feedback residual amplifiers. Therefore, the above problems are usually overcome by reducing the closed-loop gain of the residual amplifier or by using an open-loop sub-amplifier with the same gain as the ideal gain of the closed-loop amplifier. However, in practical applications, it has been found that reducing the closed-loop gain of the residual amplifier leads to a decrease in the output swing of the next stage analog-to-digital converter, thus affecting its resolution. In addition, using an open-loop sub-amplifier for compensation often means requiring a larger input transistor size, which introduces a larger parasitic capacitance, thus affecting the performance of the amplifier and the entire ADC. At the same time, it requires a complex calibration circuit to calibrate its gain, increasing the design difficulty of the circuit.

[0024] In view of this, the present application provides a gain error compensation circuit, method and pipelined analog-to-digital converter for a pipelined analog-to-digital converter. By detecting virtual points through a time-domain analog-to-digital converter, parasitic capacitance can be effectively reduced, the noise performance of the amplifier and the overall system can be improved, and the overall accuracy can be effectively improved by compensating the gain of the closed-loop residual amplifier.

[0025] The specific implementation methods of the embodiments of this application will be described in detail below with reference to the accompanying drawings. First, a gain error compensation circuit for a pipelined analog-to-digital converter provided in an embodiment of this application will be described with reference to the accompanying drawings.

[0026] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the gain error compensation circuit of a pipelined analog-to-digital converter provided in an embodiment of this application. The gain error compensation circuit of the pipelined analog-to-digital converter includes: a first-stage quantization circuit, a second-stage quantization circuit, and a residual amplifier circuit. The first-level quantization circuit is used to quantize the sampled signal to obtain a first-level quantization code and a first-level quantization residual, and output the first-level quantization residual to the residual amplifier circuit. The residual amplifier circuit is used to amplify the first-stage quantization residual to obtain the quantization amplified residual, and output the quantization amplified residual to the second-stage quantization circuit. The secondary quantization circuit is used to quantize the quantization amplification residual to obtain a secondary quantization code; The residual amplifier circuit is equipped with a time-domain analog-to-digital converter. The time-domain analog-to-digital converter is used to detect the virtual ground voltage of the closed-loop residual amplifier in the residual amplifier circuit, and convert the detection result into a compensation gain through a capacitive digital-to-analog converter, thereby compensating the output terminal of the closed-loop residual amplifier.

[0027] In the embodiments of this application, such as Figure 1 As shown, the gain error compensation circuit of the pipelined analog-to-digital converter mainly consists of three parts: a first-stage quantization circuit, a residual amplifier circuit, and a second-stage quantization circuit.

[0028] The first-level quantization circuit is mainly used to sample the input signal to obtain the sampled signal and quantize the sampled signal. During the quantization process, the sampled analog level is compared with a set of discrete reference levels to map it into the closest digital code, which is the first-level quantization code. At the same time, after the first-level quantization, a difference between the real value and the mapped digital level is introduced, which is the first-level quantization residual.

[0029] Furthermore, the first-stage quantization residual can be output to the subsequent residual amplifier circuit. The first-stage residual is amplified by the closed-loop residual amplifier in the residual amplifier circuit, and then the amplified quantization residual is output to the subsequent second-stage quantization circuit. The second-stage quantization circuit is used to quantize the quantization residual to obtain the second-stage quantization code, thereby completing the quantization encoding process of the sampled signal.

[0030] In practical applications, the residual amplifier circuit of this application is equipped with a time-domain analog-to-digital converter (ADC), which is used to detect the virtual ground voltage of the closed-loop residual amplifier in the residual amplifier circuit. For an ideal closed-loop amplifier, due to the effect of charge redistribution, the voltage across the amplifier input becomes 0. However, for a non-ideal amplifier, there will still be a voltage difference across the amplifier input, which will lead to gain error. Existing technologies choose to reduce the closed-loop gain of the closed-loop amplifier, which leads to a decrease in the input swing and resolution requirements of the second-stage ADC, or to compensate the amplifier by using an open-loop sub-amplifier with the same gain as the ideal gain of the closed-loop amplifier. However, the sub-amplifier used for compensation often requires a large input transistor size, which introduces a large parasitic capacitance at the virtual ground of the main amplifier, thereby affecting the performance of the amplifier and the entire ADC.

[0031] like Figure 1 As shown, the residual amplifier circuit includes a closed-loop residual amplifier, a first time-domain analog-to-digital converter (ADC), and a first capacitive digital-to-analog converter (DAC). The first capacitive DAC can be configured as a single-sided 10.5fF (composed of 15 0.7fF capacitors) CDAC. By converting the digital code output by the first time-domain ADC into an equivalent amount of analog charge and injecting it back into the output node of the closed-loop residual amplifier, closed-loop gain error compensation is achieved.

[0032] Therefore, this application utilizes a time-domain analog-to-digital converter to detect the virtual ground voltage of the closed-loop residual amplifier, converts the detection result into a compensation gain via a capacitive digital-to-analog converter, and then applies this compensation gain to the output of the closed-loop residual amplifier. This effectively reduces the size of the input transistor and thus lowers the parasitic virtual ground. Furthermore, the compensation gain can be quickly changed by adjusting the reference voltage of the capacitive digital-to-analog converter without the need for complex calibration circuits, effectively improving the noise performance of the pipelined analog-to-digital converter. Through gain error compensation, the stability of the closed-loop residual amplifier is effectively guaranteed without reducing the input swing of the subsequent analog-to-digital converter, ensuring resolution accuracy.

[0033] It is understood that the pipelined analog-to-digital converter (ADC) in this application is configured as a single-channel, two-stage pipelined ADC only as an optional application environment provided in the embodiments of this application, and the actual application is not fixed. Figure 1 The circuit structure shown is not specifically limited in this application.

[0034] Specifically, as an optional implementation, the residual amplifier circuit includes: a first capacitor, a second capacitor, a closed-loop residual amplifier, a first time-domain analog-to-digital converter, and a first capacitive digital-to-analog converter; One end of the first capacitor is connected to the output terminal of the first-stage quantization circuit; The other end of the first capacitor and one end of the second capacitor are connected to the residual input terminal of the closed-loop residual amplifier; The other end of the second capacitor is connected to the output terminal of the closed-loop residual amplifier; The input terminal of the first time-domain analog-to-digital converter is connected to the residual input terminal of the closed-loop residual amplifier; The output terminal of the first time-domain analog-to-digital converter is connected to the input terminal of the first capacitive digital-to-analog converter; The output terminal of the first capacitive digital-to-analog converter is connected to the output terminal of the closed-loop residual amplifier; The output of the closed-loop residual amplifier is connected to the second-level quantization circuit.

[0035] In the embodiments of this application, please refer to Figure 2 , Figure 2 This is a schematic diagram of a residual amplifier circuit provided in an embodiment of this application. The residual amplifier circuit includes a first capacitor and a second capacitor. One end of the first capacitor is connected to the output terminal of the first-stage quantization circuit, and the other end is connected to the residual input terminal of the closed-loop residual amplifier, so that the first capacitor can act as a coupling capacitor to couple the first-stage quantization residual output from the first-stage quantization circuit to the residual input terminal of the closed-loop residual amplifier. One end of the second capacitor is connected to the residual input terminal of the closed-loop residual amplifier, and the other end is connected to the output terminal of the closed-loop residual amplifier, serving as a feedback capacitor. Through a switch, a closed-loop feedback is formed to determine the amplification factor of the closed-loop residual amplifier.

[0036] Furthermore, the input terminal of the first time-domain analog-to-digital converter is connected to the residual input terminal of the closed-loop residual amplifier, and the output terminal is connected to the input terminal of the first capacitive digital-to-analog converter. This is used to detect the virtual ground voltage of the closed-loop residual amplifier and output a digital code result, representing the offset caused by the actual gain error of the amplifier.

[0037] Furthermore, the output of the first capacitor-type digital-to-analog converter is connected to the output of the closed-loop residual amplifier. By receiving the digital code result output by the first time-domain analog-to-digital converter, the capacitor array is controlled to inject the corresponding charge into the amplifier output node. The injected charge is equivalent to generating an equivalent voltage, which can be used to compensate for the output error caused by the gain deviation of the closed-loop residual amplifier, so that the synthesized closed-loop gain matches the ideal value.

[0038] Finally, the output of the closed-loop residual amplifier is connected to the second-level quantization circuit, which outputs the amplified quantization residual to the second-level quantization circuit for subsequent quantization.

[0039] In practical applications, such as Figure 3 As shown, the residual amplifier circuit further includes: a first voltage-time converter; One end of the first voltage-time converter is connected to the input end of the first time-domain analog-to-digital converter; The other end of the first voltage-time converter is connected to the residual input terminal of the closed-loop residual amplifier.

[0040] In this embodiment, the residual amplifier circuit may further include a first voltage-to-time converter, which connects the input terminal of the first time-domain analog-to-digital converter to the residual input terminal of the closed-loop residual amplifier, and can convert the virtual ground voltage difference into a time signal so that the subsequent first time-domain analog-to-digital converter can perform quantization.

[0041] Therefore, by working in conjunction with the first voltage-time converter and the first time-domain analog-to-digital converter, not only can the parasitic capacitance introduced by the virtual point be effectively reduced and the overall noise performance improved, but the gain error of the closed-loop residual amplifier can also be quickly compensated, thereby improving the stability of the closed-loop residual amplifier.

[0042] Specifically, as an optional implementation method, please refer to Figure 1 The first-level quantization circuit includes: a first sample-and-hold circuit, a second capacitive digital-to-analog converter, a third capacitive digital-to-analog converter, a first successive approximation quantizer, and a second time-domain analog-to-digital converter. One end of the first sample-and-hold circuit and one end of the second sample-and-hold circuit are connected to the input terminal of the sampling signal; The other end of the first sample-and-hold circuit is connected to the input of the second capacitive digital-to-analog converter; The other end of the second sample-and-hold circuit is connected to the input of the third capacitive digital-to-analog converter and the input of the first successive approximation quantizer, respectively. The output of the first successive approximation quantizer is connected to the input of the second capacitive digital-to-analog converter and the input of the third capacitive digital-to-analog converter. The output terminal of the third capacitive digital-to-analog converter is connected to the input terminal of the second time-domain analog-to-digital converter; The output terminal of the second time-domain analog-to-digital converter is connected to the input terminal of the second capacitive digital-to-analog converter; The output terminal of the second capacitive digital-to-analog converter is connected to the output terminal of the first-stage quantization circuit.

[0043] In this embodiment, the first-level quantization circuit includes a first sample-and-hold circuit, a second capacitive digital-to-analog converter, a third capacitive digital-to-analog converter, a first successive approximation quantizer, and a second time-domain analog-to-digital converter.

[0044] In this design, one end of both the first and second sample-and-hold circuits is connected to the sampling signal input terminal, recording the analog input signal onto a capacitor to ensure that the signal does not change during subsequent quantization and residual processing. Furthermore, the other end of the first sample-and-hold circuit is connected to the input terminal of the second capacitive digital-to-analog converter (DAC), and the other end of the second sample-and-hold circuit is connected to the input terminal of the third capacitive DAC. This enables simultaneous parallel sampling, ensuring the consistency of the sampled signals. The second capacitive DAC can be used as the primary CDAC, and the third capacitive DAC as an auxiliary CDAC.

[0045] Furthermore, the input of the first successive approximation quantizer is connected to the second sample-and-hold circuit to receive the sampled signal and perform successive approximation quantization. The output of the first successive approximation quantizer is connected to the input of the second capacitive digital-to-analog converter and the input of the third capacitive digital-to-analog converter to send the output quantization result digital code back to the second capacitive digital-to-analog converter for equal-capacitance complementation, thereby removing the quantized part. At the same time, the residual voltage is obtained through the third capacitive digital-to-analog converter for subsequent further quantization.

[0046] For example, the output of the third capacitive digital-to-analog converter is connected to the input of the second time-domain analog-to-digital converter, and the output of the second time-domain analog-to-digital converter is connected to the input of the second capacitive digital-to-analog converter. After quantization by the first successive approximation quantizer, the second time-domain analog-to-digital converter can further quantize based on the residual voltage on the third capacitive digital-to-analog converter, thereby obtaining the quantization result of the second time-domain analog-to-digital converter, and outputting the quantization result to the second capacitive digital-to-analog converter. Thus, the quantization results of the first successive approximation quantizer and the second time-domain analog-to-digital converter are combined to obtain a first-level quantization code, and the first-level quantization residual is formed by the charge subtracted from the second capacitive digital-to-analog converter.

[0047] Finally, the output of the second capacitor-type digital-to-analog converter, as well as the output of the quantization circuit, outputs the first-stage quantization residual to the subsequent residual amplifier circuit.

[0048] In practical applications, the first-level quantization circuit further includes: a second voltage-time converter; One end of the second voltage-time converter is connected to the input end of the second time-domain analog-to-digital converter; The other end of the second voltage-time converter is connected to the output of the third capacitive digital-to-analog converter.

[0049] In this embodiment, the first-stage quantization circuit may further include a second voltage-to-time converter, which connects the input of the second time-domain analog-to-digital converter to the output of the third capacitive digital-to-analog converter. This converter can convert the residual voltage on the third capacitive digital-to-analog converter after quantization by the first successive approximation quantizer into a time signal, so that the subsequent second time-domain analog-to-digital converter can perform quantization.

[0050] Therefore, by adopting a hybrid quantization structure that combines successive approximation analog-to-digital converters (ADCs) and time-domain ADCs, we can not only take advantage of the low power consumption of successive approximation ADCs and the high speed of time-domain ADCs, but also avoid the disadvantages of successive approximation ADCs being slow when converting small voltage swings and time-domain ADCs having poor linearity when converting large voltage swings.

[0051] Specifically, as an optional implementation method, please refer to Figure 1 The secondary quantization circuit includes: a fourth capacitive digital-to-analog converter, a comparator, and a second successive approximation quantizer; The input terminal of the fourth capacitor-type digital-to-analog converter is connected to the residual amplifier circuit. The output terminal of the fourth capacitive digital-to-analog converter is connected to the comparator; The input of the second successive approximation quantizer is connected to the comparator; The output of the second successive approximation quantizer is connected to the output of the second-level quantization circuit.

[0052] In this embodiment, the quantized amplified residual, amplified by the residual amplifier circuit, is output to the secondary quantization circuit. The input of the fourth capacitive digital-to-analog converter is connected to the residual amplifier circuit, and the output is connected to the comparator. The input of the second successive approximation quantizer is also connected to the comparator, thereby refining the quantized amplified residual within a larger dynamic range and serving as the output of the secondary quantization circuit to output the secondary quantization code. Thus, a pipelined analog-to-digital converter architecture is realized through multi-stage quantization. By superimposing multiple stages, a higher resolution can be achieved to meet the needs of subsequent data processing.

[0053] Specifically, as an optional implementation method, please refer to Figure 1 The gain error compensation circuit of the pipeline analog-to-digital converter further includes: a quantization encoding and splicing module; The quantization encoding and splicing module is used to receive the first-level quantization encoding and the second-level quantization encoding; The quantization encoding splicing module is also used to splice and align the first-level quantization encoding and the second-level quantization encoding to obtain and output the quantization encoding result of the sampled signal.

[0054] In this embodiment, the quantization encoding and splicing module can receive first-level quantization encoding and second-level quantization encoding, and splice and align them according to digital end alignment, thereby obtaining and outputting the quantization encoding result of the sampled signal for subsequent data processing.

[0055] In practical applications, such as Figure 1 As shown, the outputs of the first successive approximation quantizer, the second time-domain analog-to-digital converter, and the second successive approximation quantizer can be connected to the quantization encoding splicing module to splice and align the quantization results output by each quantizer, thereby obtaining the final quantization result.

[0056] Please see Figure 3 , Figure 3 This is a flowchart illustrating a gain error compensation method for a pipelined analog-to-digital converter (ADC) according to an embodiment of this application. This application also provides a gain error compensation method for a pipelined ADC, which can be applied to the gain error compensation circuit of the aforementioned pipelined ADC. The method includes the following steps: Acquire the sampled signal; The sampled signal is quantized using a first-level quantization circuit to obtain a first-level quantization code and a first-level quantization residual. The first-stage quantization residual is amplified by a residual amplifier circuit to obtain the quantization amplified residual. The quantization amplification residual is quantized using a two-stage quantization circuit to obtain a two-stage quantization code; The residual amplifier circuit is equipped with a time-domain analog-to-digital converter. The time-domain analog-to-digital converter is used to detect the virtual ground voltage of the closed-loop residual amplifier in the residual amplifier circuit, and convert the detection result into a compensation gain through a capacitive digital-to-analog converter, thereby compensating the output terminal of the closed-loop residual amplifier.

[0057] In the embodiments of this application, the first-level quantization circuit is mainly used to sample the input signal to obtain the sampled signal and quantize the sampled signal. During the quantization process, the sampled analog level is compared with a set of discrete reference levels to map it into the closest digital code, i.e., the first-level quantization code. At the same time, after the first-level quantization, a difference between the real value and the mapped digital level is introduced, i.e., the first-level quantization residual.

[0058] Furthermore, the first-stage quantization residual can be output to the subsequent residual amplifier circuit. The first-stage residual is amplified by the closed-loop residual amplifier in the residual amplifier circuit, and then the amplified quantization residual is output to the subsequent second-stage quantization circuit. The second-stage quantization circuit is used to quantize the quantization residual to obtain the second-stage quantization code, thereby completing the quantization encoding process of the sampled signal.

[0059] In practical applications, this application uses a time-domain analog-to-digital converter to detect the virtual ground voltage of the closed-loop residual amplifier, and converts the detection result into a compensation gain through a capacitive digital-to-analog converter. This compensation gain is then applied to the output of the closed-loop residual amplifier, effectively reducing the size of the input transistor and thus reducing the parasitic virtual ground. Furthermore, the compensation gain can be quickly changed by adjusting the reference voltage of the capacitive digital-to-analog converter without the need for complex calibration circuits, effectively improving the noise performance of the pipelined analog-to-digital converter. Through gain error compensation, the stability of the closed-loop residual amplifier is effectively guaranteed without reducing the input swing of the subsequent analog-to-digital converter, ensuring resolution accuracy.

[0060] It is understood that the contents of the above circuit embodiments are all applicable to the present method embodiments. The specific functions implemented in the present method embodiments are the same as those in the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved in the above circuit embodiments.

[0061] In practical applications, after quantizing the quantization amplification residual through a two-stage quantization circuit to obtain the two-stage quantization code, the process further includes: Based on the first-level quantization code and the second-level quantization code, the data is spliced ​​and aligned to obtain and output the quantization code result of the sampled signal.

[0062] In this embodiment, the quantization encoding and splicing module can also receive the first-level quantization encoding and the second-level quantization encoding, and splice and align them according to the digital end alignment, thereby obtaining and outputting the quantization encoding result of the sampled signal for subsequent data processing.

[0063] This application also provides a pipelined analog-to-digital converter, which includes a gain error compensation circuit for any of the above-described pipelined analog-to-digital converters.

[0064] It is understood that the contents of the above circuit embodiments are all applicable to this pipelined analog-to-digital converter embodiment. The specific functions implemented by this pipelined analog-to-digital converter embodiment are the same as those of the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved by the above circuit embodiments.

[0065] This application provides a gain error compensation circuit, method, and pipelined analog-to-digital converter (ADC) according to its embodiments. By detecting virtual points through a time-domain ADC, it can effectively reduce parasitic capacitance, improve the noise performance of the amplifier and the overall system, and effectively improve the overall accuracy by compensating the gain of the closed-loop residual amplifier.

[0066] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0067] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0068] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0069] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0070] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0071] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0073] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0074] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0075] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0076] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A gain error compensation circuit for a pipelined analog-to-digital converter, characterized in that, The gain error compensation circuit of the pipelined analog-to-digital converter includes: a first-stage quantization circuit, a second-stage quantization circuit, and a residual amplifier circuit; The first-level quantization circuit is used to quantize the sampled signal to obtain a first-level quantization code and a first-level quantization residual, and output the first-level quantization residual to the residual amplifier circuit. The residual amplifier circuit is used to amplify the first-stage quantization residual to obtain the quantization amplified residual, and output the quantization amplified residual to the second-stage quantization circuit. The secondary quantization circuit is used to quantize the quantization amplification residual to obtain a secondary quantization code; The residual amplifier circuit is equipped with a time-domain analog-to-digital converter. The time-domain analog-to-digital converter is used to detect the virtual ground voltage of the closed-loop residual amplifier in the residual amplifier circuit, and convert the detection result into a compensation gain through a capacitive digital-to-analog converter, thereby compensating the output terminal of the closed-loop residual amplifier.

2. The gain error compensation circuit for the pipelined analog-to-digital converter according to claim 1, characterized in that, The residual amplifier circuit includes: a first capacitor, a second capacitor, a closed-loop residual amplifier, a first time-domain analog-to-digital converter, and a first capacitive digital-to-analog converter; One end of the first capacitor is connected to the output terminal of the first-stage quantization circuit; The other end of the first capacitor and one end of the second capacitor are connected to the residual input terminal of the closed-loop residual amplifier; The other end of the second capacitor is connected to the output terminal of the closed-loop residual amplifier; The input terminal of the first time-domain analog-to-digital converter is connected to the residual input terminal of the closed-loop residual amplifier; The output terminal of the first time-domain analog-to-digital converter is connected to the input terminal of the first capacitive digital-to-analog converter; The output terminal of the first capacitive digital-to-analog converter is connected to the output terminal of the closed-loop residual amplifier; The output of the closed-loop residual amplifier is connected to the second-level quantization circuit.

3. The gain error compensation circuit for the pipelined analog-to-digital converter according to claim 2, characterized in that, The residual amplifier circuit further includes: a first voltage-time converter; One end of the first voltage-time converter is connected to the input end of the first time-domain analog-to-digital converter; The other end of the first voltage-time converter is connected to the residual input terminal of the closed-loop residual amplifier.

4. The gain error compensation circuit for the pipelined analog-to-digital converter according to claim 1, characterized in that, The first-level quantization circuit includes: a first sample-and-hold circuit, a second capacitive digital-to-analog converter, a third capacitive digital-to-analog converter, a first successive approximation quantizer, and a second time-domain analog-to-digital converter. One end of the first sample-and-hold circuit and one end of the second sample-and-hold circuit are connected to the input terminal of the sampling signal; The other end of the first sample-and-hold circuit is connected to the input of the second capacitive digital-to-analog converter; The other end of the second sample-and-hold circuit is connected to the input of the third capacitive digital-to-analog converter and the input of the first successive approximation quantizer, respectively. The output of the first successive approximation quantizer is connected to the input of the second capacitive digital-to-analog converter and the input of the third capacitive digital-to-analog converter. The output terminal of the third capacitive digital-to-analog converter is connected to the input terminal of the second time-domain analog-to-digital converter; The output terminal of the second time-domain analog-to-digital converter is connected to the input terminal of the second capacitive digital-to-analog converter; The output terminal of the second capacitive digital-to-analog converter is connected to the output terminal of the first-stage quantization circuit.

5. The gain error compensation circuit for the pipelined analog-to-digital converter according to claim 4, characterized in that, The primary quantization circuit further includes: a second voltage-time converter; One end of the second voltage-time converter is connected to the input end of the second time-domain analog-to-digital converter; The other end of the second voltage-time converter is connected to the output of the third capacitive digital-to-analog converter.

6. The gain error compensation circuit for the pipelined analog-to-digital converter according to claim 1, characterized in that, The secondary quantization circuit includes: a fourth capacitive digital-to-analog converter, a comparator, and a second successive approximation quantizer; The input terminal of the fourth capacitor-type digital-to-analog converter is connected to the residual amplifier circuit. The output terminal of the fourth capacitive digital-to-analog converter is connected to the comparator; The input of the second successive approximation quantizer is connected to the comparator; The output of the second successive approximation quantizer is connected to the output of the second-level quantization circuit.

7. The gain error compensation circuit for the pipelined analog-to-digital converter according to claim 1, characterized in that, The gain error compensation circuit of the pipeline analog-to-digital converter also includes: a quantization encoding and splicing module; The quantization encoding and splicing module is used to receive the first-level quantization encoding and the second-level quantization encoding; The quantization encoding splicing module is also used to splice and align the first-level quantization encoding and the second-level quantization encoding to obtain and output the quantization encoding result of the sampled signal.

8. A gain error compensation method for a pipelined analog-to-digital converter, characterized in that, The method includes the following steps: Acquire the sampled signal; The sampled signal is quantized using a first-level quantization circuit to obtain a first-level quantization code and a first-level quantization residual. The first-stage quantization residual is amplified by a residual amplifier circuit to obtain the quantization amplified residual. The quantization amplification residual is quantized using a two-stage quantization circuit to obtain a two-stage quantization code; The residual amplifier circuit is equipped with a time-domain analog-to-digital converter. The time-domain analog-to-digital converter is used to detect the virtual ground voltage of the closed-loop residual amplifier in the residual amplifier circuit, and convert the detection result into a compensation gain through a capacitive digital-to-analog converter, thereby compensating the output terminal of the closed-loop residual amplifier.

9. The gain error compensation method for a pipelined analog-to-digital converter according to claim 8, characterized in that, After quantizing the quantization amplification residual through a two-stage quantization circuit to obtain a two-stage quantization code, the method further includes: Based on the first-level quantization code and the second-level quantization code, the data is spliced ​​and aligned to obtain and output the quantization code result of the sampled signal.

10. A pipelined analog-to-digital converter, characterized in that, include: The gain error compensation circuit for a pipelined analog-to-digital converter as described in any one of claims 1-7.

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