Time sequence calibration method, device and equipment for analog-to-digital converter

Abstract

The invention relates to the technical field of analog-to-digital converters, and provides a time sequence calibration method, device and equipment for an analog-to-digital converter, and the method comprises the steps: obtaining original sampling data of a target analog-to-digital converter based on a target FPGA, and transmitting the original sampling data to upper computer analysis software; determining a time deviation corresponding to each sub-analog-to-digital converter of the target analog-to-digital converter by using upper computer analysis software, and calculating a filter coefficient array of each sub-analog-to-digital converter according to the time deviation and a preset filter order; transmitting the filter coefficient array to a target software development kit, and transmitting the filter coefficient array to a target FPGA by using the target software development kit; and driving the target FPGA, and performing filtering processing on the original sampling data according to the filtering coefficient array to generate calibration data. According to the technical scheme provided by one or more embodiments of the invention, time sequence calibration can be conveniently and accurately carried out on the analog-to-digital converter for the field programmable gate array.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of analog-to-digital converters, in particular to a timing calibration method, device and equipment of an analog-to-digital converter. BACKGROUND

[0002] In today's highly digitized society, analog-to-digital converters (ADCs) have become the core bridge connecting the physical world and the digital world. From smartphones to industrial Internet of Things, from medical diagnosis to aerospace, analog-to-digital converters support the underlying architecture of modern technology by converting analog signals into digital signals. With the continuous development of technology, the sampling requirements of various modern engineering fields for analog-to-digital converters are also constantly improving.

[0003] Currently, many engineering fields mostly use time-interleaved technology to design analog-to-digital converters to meet the application requirements of high speed and high precision. Since the sampling time mismatch problem seriously restricts the performance of time-interleaved analog-to-digital converters, some timing calibration schemes are needed to calibrate the timing of the sampling data of time-interleaved analog-to-digital converters.

[0004] In some actual engineering systems, time-interleaved analog-to-digital converters are prone to form a tightly coupled "sampling-processing-feedback" closed loop structure with field programmable gate arrays (FPGAs). In this scenario, the sampling time mismatch problem of time-interleaved analog-to-digital converters will be further amplified, and more accurate timing calibration is needed. SUMMARY

[0005] Therefore, one or more embodiments of the present disclosure provide a timing calibration method, device and equipment of an analog-to-digital converter, which can conveniently and accurately calibrate the timing of an analog-to-digital converter for a field programmable gate array by using a unique design structure.

[0006] This disclosure provides a timing calibration method for an analog-to-digital converter (ADC). The method includes: acquiring raw sampling data of the target ADC based on a target FPGA, and sending the raw sampling data to a host computer analysis software. The target ADC is a time-interleaved ADC, which includes multiple sub-ADCs. Using the host computer analysis software, the raw sampling data is analyzed to determine the time deviation corresponding to each sub-ADC. Using the host computer analysis software, a filter coefficient array corresponding to each sub-ADC is calculated based on the time deviation and a preset filter order. The filter coefficient array calculated by the host computer analysis software is transmitted to a target software development kit (SDK), and the filter coefficient array is transmitted to the target FPGA using the SSD. The target FPGA is then driven to filter the raw sampling data according to the filter coefficient array to generate calibration data.

[0007] This disclosure also provides a timing calibration device for an analog-to-digital converter (ADC). The device includes: a data acquisition unit, configured to acquire raw sampling data of a target ADC based on a target FPGA, and send the raw sampling data to a host computer analysis software; the target ADC is a time-interleaved ADC, and the target ADC includes multiple sub-ADCs; a time deviation calculation unit, configured to analyze the raw sampling data using the host computer analysis software to determine the time deviation corresponding to each sub-ADC; a filter coefficient calculation unit, configured to calculate a filter coefficient array corresponding to each sub-ADC based on the time deviation and a preset filter order using the host computer analysis software; a filter coefficient transmission unit, configured to transmit the filter coefficient array calculated by the host computer analysis software to a target software development kit (SDK), and use the target SSD to transmit the filter coefficient array to the target FPGA; and a timing calibration unit, configured to drive the target FPGA to filter the raw sampling data according to the filter coefficient array to generate calibration data.

[0008] This disclosure also provides an electronic device including a memory and a processor, the memory storing a computer program that, when executed by the processor, implements the above-described timing calibration method for an analog-to-digital converter.

[0009] This disclosure also provides a computer-readable storage medium for storing a computer program that, when executed by a processor, implements the above-described timing calibration method for an analog-to-digital converter.

[0010] This disclosure provides a technical solution through one or more embodiments, utilizing the target FPGA to acquire raw sampling data from a time-interleaved target ADC, ensuring strict synchronization between the raw sampling data and the clock domain of the target FPGA. Subsequently, the host computer analysis software calculates the time deviation of each sub-ADC in the target ADC based on the raw sampling data acquired by the target FPGA. Based on the calculated time deviation, the host computer analysis software can also obtain the filter coefficient array for each sub-ADC. By fully utilizing the computing resources of the host computer, the numerical accuracy of the time deviation and the numerical reliability of the filter coefficient array can be guaranteed.

[0011] This disclosure provides a technical solution through one or more embodiments, which exposes a filter parameter interface in the target FPGA, allowing the target software development kit (SDK) to control the filter parameters via this interface. By relaying the filter coefficient array calculated by the host computer analysis software to the target FPGA through the SSD, the filter parameters in the target FPGA can be updated quickly and efficiently without recompiling the FPGA firmware, thus increasing the convenience of practical applications.

[0012] This disclosure provides a technical solution through one or more embodiments, offering a mechanism for the joint use of a target FPGA, host computer analysis software, and a target software development kit. This mechanism enables flexible updating of the filter parameters of the target FPGA and convenient and accurate timing calibration of analog-to-digital converters used in field-programmable gate arrays. Attached Figure Description

[0013] The features and advantages of the embodiments of this disclosure will be more clearly understood by referring to the accompanying drawings, which are illustrative and should not be construed as limiting the present disclosure in any way. In the drawings:

[0014] Figure 1 A schematic diagram illustrating the steps of a timing calibration method for an analog-to-digital converter in one embodiment of this disclosure is shown.

[0015] Figure 2 A schematic diagram of the filter coefficient calculation process in one embodiment of this disclosure is shown;

[0016] Figure 3 A schematic diagram of the filtering process in one embodiment of this disclosure is shown;

[0017] Figure 4 This diagram illustrates the data flow of a timing calibration method for an analog-to-digital converter according to one embodiment of the present disclosure.

[0018] Figure 5 A schematic diagram of the functional modules of a timing calibration device for an analog-to-digital converter in one embodiment of the present disclosure is shown;

[0019] Figure 6 A schematic diagram of the structure of an electronic device according to one embodiment of the present disclosure is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] In related technologies, timing calibration algorithms for time-interleaved analog-to-digital converters require generating a fixed bitstream file from the program code containing the timing calibration algorithm if it needs to be applied in FPGA projects. After generating the bitstream file, the filter parameters are difficult to change. If the filter parameters need to be changed, the bitstream file needs to be regenerated, which is complex in practical applications.

[0022] Therefore, the timing calibration method for analog-to-digital converters provided in one embodiment of this disclosure can conveniently and accurately perform timing calibration on analog-to-digital converters used in field-programmable gate arrays. The timing calibration method for analog-to-digital converters provided in one embodiment of this disclosure can be applied to measurement and control equipment that can drive FPGAs. The measurement and control equipment can be an electronic device with data processing capabilities. For example, the measurement and control equipment can be a personal computer, workstation, etc. Furthermore, this method can also be applied to software running within the aforementioned measurement and control equipment.

[0023] Please see Figure 1 The timing calibration method for an analog-to-digital converter provided in one embodiment of this disclosure may include the following steps.

[0024] S1: Based on the target FPGA, acquire the raw sampling data of the target analog-to-digital converter and send the raw sampling data to the host computer analysis software. The target analog-to-digital converter is a time-interleaved analog-to-digital converter, which contains multiple sub-analog-to-digital converters.

[0025] In this embodiment, the target ADC can acquire externally input analog signals, convert the analog signals into digital signals, and then transmit them to the target FPGA via a data interface. Utilizing the target FPGA to acquire the raw sampling data of the target ADC ensures strict synchronization between the raw sampling data and the clock domain of the target FPGA, making it suitable for scenarios where the time-interleaved ADC and the FPGA are tightly coupled. The time-interleaved ADC may include one or more sampling channels, each sampling channel comprising multiple sub-ADCs. The number of sampling channels and the number of sub-ADCs within each sampling channel are not limited here.

[0026] In a practical application example, consider a four-channel high-speed, high-precision time-interleaved ADC chip with a 10GHz sampling rate and 10-bit resolution. This ADC chip contains four sampling channels, each containing 32 sub-ADCs, for a total of 128 sub-ADCs. Each sub-ADC operates independently at a frequency of 312.5MHz. By time-interleaving the sampling results of each sub-ADC, the entire chip can achieve an equivalent sampling rate of 10GHz.

[0027] S2: Using the host computer analysis software, analyze the original sampled data and determine the time deviation corresponding to each of the sub-analog-to-digital converters.

[0028] In this embodiment, the computational resources of the host computer are utilized to ensure the numerical accuracy of the time deviation. The host computer analysis software can be MATLAB.

[0029] In some implementations, the original sampled data can be split according to the total number of sub-analog-to-digital converters (ADCs), and sub-sampled data corresponding to each ADC can be determined. Based on the candidate sampled data corresponding to the candidate ADCs and the reference sampled data corresponding to the reference ADC, the phase deviation of the candidate ADC relative to the reference ADC can be determined. The phase deviation can then be converted into the time deviation using a preset conversion formula.

[0030] Specifically, the raw sampled data received by the host computer analysis software is a collection of data acquired by all sub-ADCs in the target ADC. Timing calibration of the raw sampled data requires timing calibration of the sub-sampled data corresponding to each sub-ADC. Therefore, based on the total number of sub-ADCs and their sampling order, the raw sampled data can be broken down into the sub-sampled data corresponding to each sub-ADC.

[0031] The prerequisite for timing calibration is determining the time deviation of each sub-ADC. First, any sub-ADC can be randomly selected as a reference ADC, typically the one ranked first. Then, any sub-ADC of the target ADC can be used as a candidate ADC, compared with the reference ADC, and its time deviation is calculated. Specifically, if the candidate sampling data of a candidate ADC is the same as the reference sampling data of the reference ADC, then their time deviation is zero.

[0032] Directly calculating the time deviation from two sets of sampled data is typically difficult. However, by first calculating the phase deviation between the two sets of sampled data based on the conversion relationship between phase deviation and time deviation, and then indirectly calculating the time deviation, the computational complexity can be simplified.

[0033] In some implementations, the original sampled data can be split according to the number of channels of the target analog-to-digital converter (ADC) to determine the channel sampled data for each target channel. Furthermore, the channel sampled data can be split according to the number of ADCs corresponding to each target channel to determine the sub-sampled data corresponding to each sub-ADC.

[0034] In a practical application example, the raw sampled data transmitted from the target FPGA to MATLAB contains channel sampled data from four channels. Therefore, it is necessary to split the overall raw sampled data into channel sampled data for each channel according to the data transmission rules. At this point, the sampled data for each channel is still the result of time interleaving of multiple sub-sampled data. If each channel sampled data is obtained by interleaving sub-sampled data from 32 sub-ADCs, it can be further split into 32 sub-sampled data after obtaining the sampled data for each channel.

[0035] In some implementations, determining the phase deviation of the candidate analog-to-digital converter relative to the reference analog-to-digital converter based on the candidate sampling data corresponding to the candidate analog-to-digital converter in the sub-analog-to-digital converter and the reference sampling data corresponding to the reference analog-to-digital converter in the sub-analog-to-digital converter includes: performing a Fourier transform on the candidate sampling data to determine the candidate fundamental frequency position of the candidate sampling data; performing a Fourier transform on the reference sampling data to determine the reference fundamental frequency position of the reference sampling data; determining the candidate phase angle value of the candidate analog-to-digital converter based on the candidate fundamental frequency position; determining the reference phase angle value of the reference analog-to-digital converter based on the reference fundamental frequency position; and calculating the phase deviation based on the candidate phase angle value and the reference phase angle value.

[0036] In a practical application example, after acquiring the sub-sampled data of each sub-ADC, each sub-ADC functions as an independent ADC. Performing a Fast Fourier Transform (FFT) on the sub-sampled data acquired by the sub-ADC yields the frequency domain data, thus determining the dominant frequency position. Based on the dominant frequency position, the phase angle value of each sub-ADC can be calculated. Subsequently, using the calculated phase angle value as a reference, subtracting the phase angle value of the reference ADC from the phase angle value of the candidate ADC gives the phase deviation of the candidate ADC relative to the reference ADC.

[0037] S3: Using the host computer analysis software, calculate the filter coefficient array corresponding to each of the sub-analog-to-digital converters based on the time deviation and the preset filter order.

[0038] In this embodiment, the preset filter is a time-delay filter, which can be a finite-length impulse response (FIR) filter, a fractional-delay filter, an all-pass filter, a linear-phase FIR filter, or other filter structures. The preset filter order can represent the number of coefficients in the filter coefficient array. Generally, the higher the filter order, the better the filtering effect, but the higher the computational cost. Therefore, the preset filter order can be determined according to the actual filtering requirements.

[0039] In this embodiment, by inputting the time deviation and the preset filter order into a preset delay function, the filter coefficient array corresponding to each sub-analog-to-digital converter can be calculated. The preset delay function may include, but is not limited to, the Sinc function, the Lagrange function, and a polynomial function.

[0040] In some implementations, calculating the filter coefficient array corresponding to each of the sub-analog-to-digital converters based on the time deviation and the preset filter order includes: for the current analog-to-digital converter among the sub-analog-to-digital converters, performing a difference operation between each order value of the preset filter order and the time deviation of the current analog-to-digital converter to determine the current difference array; and using each current difference value of the current difference array as the input variable of the Singer function to generate the filter coefficient array corresponding to the current analog-to-digital converter.

[0041] In a practical application example, please refer to Figure 2 Assuming the preset filter order is X and the current time deviation of the analog-to-digital converter is u, the current differences in the current difference array are: 1-u, 2-u, 3-u, ..., Xu. Using these X current differences sequentially as input variables to the Singer function generates X function output values, forming a filter coefficient array.

[0042] S4: The filter coefficient array calculated by the host computer analysis software is transmitted to the target software development kit, and the filter coefficient array is transmitted to the target FPGA using the target software development kit.

[0043] In this embodiment, the filter coefficient array can be transferred to the reserved array storage area of ​​the target software development kit (SDK). Using the SSD, and based on the reserved communication channel between the SSD and the target FPGA, the filter coefficient array can be transferred to the target register of the target FPGA.

[0044] Specifically, a software development kit (SDK) is a set of software development tools and libraries provided by FPGA chip manufacturers or development board suppliers. Its core purpose is to simplify the process of developing, debugging, and deploying applications (including hardware-software co-operation) on specific FPGA target hardware. The main components of the target SSD can run on a host computer and can reside on the same device as the host computer analysis software.

[0045] Because the target development kit encapsulates the underlying hardware interface and communication protocol, users only need to call the application programming interface to transfer the filter coefficient array to the target register of the target FPGA, avoiding the tedious and error-prone work of manually handling data packaging, transmission, and verification.

[0046] During the programming of the target SDK, a space can be reserved for an array to store filter parameters. The filter coefficient array can be transferred to the reserved array storage area of ​​the target SDK manually or via a script. When the host computer analysis software calculates new filter parameters based on the actual data acquired by the target FPGA, the filter parameters in the target SDK can be updated.

[0047] A pre-configured communication channel is reserved between the target SDK and the target FPGA. The target FPGA also has reserved registers for storing filter parameters. After the target SDK obtains the filter parameters, it transmits the filter parameters through the reserved communication channel, enabling the target FPGA to acquire the filter parameters.

[0048] S5: Drive the target FPGA to filter the original sampled data according to the filter coefficient array to generate calibration data.

[0049] In this embodiment, the process of filtering the data is essentially a process of multiplying and accumulating the data. By multiplying the sub-sampled data of each sub-ADC with the filter coefficients and accumulating the final data, the filtered data for each sub-ADC can be obtained. Re-interleaving the filtered data from each sub-ADC yields the timing calibration result of the original sampled data, which is the calibration data.

[0050] In some implementations, the step of filtering the original sampled data according to the filter coefficient array to generate calibration data includes: determining the data to be filtered corresponding to each of the sub-analog-to-digital converters based on the original sampled data; performing matched multiplication of the data to be filtered with each filter coefficient of the filter coefficient array to determine the product array corresponding to each of the sub-analog-to-digital converters; accumulating the data within the product array to generate the filtered data corresponding to each of the sub-analog-to-digital converters; and performing time interleaving on the filtered data to generate the calibration data.

[0051] In a practical application example, please refer to Figure 3 Assuming the preset filter order is X, each filter coefficient array includes X filter coefficients. A segment of data to be filtered from a certain sub-ADC can be ADC data 1, ADC data 2, ..., ADC data X-1, ADC data X. Multiplying ADC data 1 with filter coefficient 1, multiplying ADC data 2 with filter coefficient 2, and so on, yields X products. Summing these X products provides the filtered data for that sub-ADC. Finally, time-interleaving the filtered data from each sub-ADC of the target ADC generates calibration data.

[0052] Please see Figure 4 This disclosure provides a timing calibration method for an analog-to-digital converter (ADC) based on one embodiment, employing a MATLAB+FPGA+SDK design scheme. In the overall design process, the FPGA first acquires the raw data of the time-interleaved ADC. Then, MATLAB calculates the time deviation of each sub-ADC in the time-interleaved ADC based on the raw data acquired by the FPGA, obtains the required filter coefficient set for each sub-ADC based on the calculated time deviation, and transmits all calculated filter coefficient sets to the SDK. Next, the SDK transmits these filter parameters to the FPGA and controls the filter parameters in the FPGA. Finally, the FPGA uses the filter parameters to perform filtering operations on each sub-ADC, completing the timing calibration of the time-interleaved ADC.

[0053] This disclosure provides a technical solution through one or more embodiments, utilizing the target FPGA to acquire raw sampling data from a time-interleaved target ADC, ensuring strict synchronization between the raw sampling data and the clock domain of the target FPGA. Subsequently, the host computer analysis software calculates the time deviation of each sub-ADC in the target ADC based on the raw sampling data acquired by the target FPGA. Based on the calculated time deviation, the host computer analysis software can also obtain the filter coefficient array for each sub-ADC. By fully utilizing the computing resources of the host computer, the numerical accuracy of the time deviation and the numerical reliability of the filter coefficient array can be guaranteed.

[0054] This disclosure provides a technical solution through one or more embodiments, which exposes a filter parameter interface in the target FPGA, allowing the target software development kit (SDK) to control the filter parameters via this interface. By relaying the filter coefficient array calculated by the host computer analysis software to the target FPGA through the SSD, the filter parameters in the target FPGA can be updated quickly and efficiently without recompiling the FPGA firmware, thus increasing the convenience of practical applications.

[0055] This disclosure provides a technical solution through one or more embodiments, offering a mechanism for the joint use of a target FPGA, host computer analysis software, and a target software development kit. This mechanism enables flexible updating of the filter parameters of the target FPGA and convenient and accurate timing calibration of analog-to-digital converters used in field-programmable gate arrays.

[0056] Please see Figure 5 This disclosure also provides a timing calibration apparatus for an analog-to-digital converter, the apparatus comprising:

[0057] The data acquisition unit 100 is used to acquire the raw sampling data of the target analog-to-digital converter based on the target FPGA, and send the raw sampling data to the host computer analysis software. The target analog-to-digital converter is a time-interleaved analog-to-digital converter, and the target analog-to-digital converter includes multiple sub-analog-to-digital converters.

[0058] The time deviation calculation unit 200 is used to analyze the original sampling data using the host computer analysis software to determine the time deviation corresponding to each of the sub-analog-to-digital converters;

[0059] The filter coefficient calculation unit 300 is used to calculate the filter coefficient array corresponding to each of the sub-analog-to-digital converters based on the time deviation and the preset filter order using the host computer analysis software.

[0060] The filter coefficient transmission unit 400 is used to transmit the filter coefficient array calculated by the host computer analysis software to the target software development kit, and use the target software development kit to transmit the filter coefficient array to the target FPGA.

[0061] The timing calibration unit 500 is used to drive the target FPGA to filter the original sampled data according to the filter coefficient array to generate calibration data.

[0062] In one embodiment, the time deviation calculation unit 200 is specifically used to: split the original sampled data according to the total number of the sub-analog-to-digital converters, and determine the sub-sampled data corresponding to each of the sub-analog-to-digital converters; determine the phase deviation of the candidate analog-to-digital converter relative to the reference analog-to-digital converter according to the candidate sampled data corresponding to the candidate analog-to-digital converter in the sub-analog-to-digital converters and the reference sampled data corresponding to the reference analog-to-digital converter in the sub-analog-to-digital converters; and convert the phase deviation into the time deviation according to a preset conversion formula.

[0063] In one embodiment, the time deviation calculation unit 200 further includes a data splitting subunit. This data splitting subunit is specifically used for: splitting the original sampled data according to the number of channels of the target analog-to-digital converter to determine the channel sampled data for each target channel; and splitting the channel sampled data according to the number of channel analog-to-digital converters corresponding to each target channel to determine the sub-sampled data corresponding to each sub-analog-to-digital converter.

[0064] In one embodiment, the time deviation calculation unit 200 further includes a phase deviation calculation subunit. This phase deviation calculation subunit is specifically used for: performing a Fourier transform on the candidate sampled data to determine the candidate dominant frequency position of the candidate sampled data; performing a Fourier transform on the reference sampled data to determine the reference dominant frequency position of the reference sampled data; determining the candidate phase angle value of the candidate analog-to-digital converter based on the candidate dominant frequency position; determining the reference phase angle value of the reference analog-to-digital converter based on the reference dominant frequency position; and calculating the phase deviation based on the candidate phase angle value and the reference phase angle value.

[0065] In one embodiment, the filter coefficient calculation unit 300 is specifically used to: for the current analog-to-digital converter in the sub-analog-to-digital converter, perform difference calculation on each order value of the preset filter order and the time deviation of the current analog-to-digital converter to determine the current difference array; and use each current difference value of the current difference array as the input variable of the Singer function to generate the filter coefficient array corresponding to the current analog-to-digital converter.

[0066] In one embodiment, the filter coefficient transmission unit 400 is specifically used to: transmit the filter coefficient array to the reserved array storage area of ​​the target software development kit; and, using the target software development kit, transmit the filter coefficient array to the target register of the target FPGA based on the reserved communication channel between the target software development kit and the target FPGA.

[0067] In one embodiment, the timing calibration unit 500 is specifically configured to: determine the data to be filtered corresponding to each of the sub-analog-to-digital converters based on the original sampling data; perform matched multiplication of the data to be filtered with each filter coefficient of the filter coefficient array to determine the product array corresponding to each of the sub-analog-to-digital converters; accumulate the data within the product array to generate the filtered data corresponding to each of the sub-analog-to-digital converters; and perform time interleaving on the filtered data to generate the calibration data.

[0068] The various units described in the above embodiments can be implemented by a computer chip or by a product with a certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0069] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0070] Please see Figure 6 This disclosure also provides an electronic device, which includes a memory and a processor. The memory is used to store a computer program, and when the computer program is executed by the processor, it implements the timing calibration method for the analog-to-digital converter described above.

[0071] This disclosure also provides a computer-readable storage medium for storing a computer program that, when executed by a processor, implements the timing calibration method for the analog-to-digital converter described above.

[0072] The processor can be a central processing unit (CPU). It can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.

[0073] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the methods in the above-described embodiments.

[0074] The memory may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0075] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0076] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, embodiments of apparatus, devices, and storage media are basically similar to method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0077] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0078] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A timing calibration method for an analog-to-digital converter, characterized in that, The method includes: Based on the target FPGA, the raw sampling data of the target analog-to-digital converter is acquired and sent to the host computer analysis software. The target analog-to-digital converter is a time-interleaved analog-to-digital converter and contains multiple sub-analog-to-digital converters. Using the host computer analysis software, the raw sampling data is analyzed to determine the time deviation corresponding to each of the sub-analog-to-digital converters; Using the host computer analysis software, the filter coefficient array corresponding to each of the sub-analog-to-digital converters is calculated based on the time deviation and the preset filter order; The filter coefficient array calculated by the host computer analysis software is transmitted to the target software development kit, and the filter coefficient array is transmitted to the target FPGA using the target software development kit; The target FPGA is driven to filter the original sampled data according to the filter coefficient array to generate calibration data.

2. The method according to claim 1, characterized in that, The analysis of the original sampled data to determine the time deviation corresponding to each of the sub-analog-to-digital converters includes: Based on the total number of sub-analog-to-digital converters, the original sampled data is split, and the sub-sampled data corresponding to each sub-analog-to-digital converter is determined. Based on the candidate sampling data corresponding to the candidate analog-to-digital converter in the sub-analog-to-digital converter, and the reference sampling data corresponding to the reference analog-to-digital converter in the sub-analog-to-digital converter, the phase deviation of the candidate analog-to-digital converter relative to the reference analog-to-digital converter is determined; The phase deviation is converted into the time deviation according to a preset conversion formula.

3. The method according to claim 2, characterized in that, The step of splitting the original sampled data according to the total number of sub-analog-to-digital converters and determining the sub-sampled data corresponding to each sub-analog-to-digital converter includes: Based on the number of channels of the target analog-to-digital converter, the original sampled data is split to determine the channel sampled data of each target channel; Based on the number of channel analog-to-digital converters corresponding to each target channel, the channel sampling data is split to determine the sub-sampling data corresponding to each sub-analog-to-digital converter.

4. The method according to claim 3, characterized in that, The step of determining the phase deviation of the candidate analog-to-digital converter relative to the reference analog-to-digital converter based on the candidate sampling data corresponding to the candidate analog-to-digital converter in the sub-analog-to-digital converters and the reference sampling data corresponding to the reference analog-to-digital converter in the sub-analog-to-digital converters includes: Perform a Fourier transform on the candidate sampled data to determine the candidate dominant frequency position of the candidate sampled data; Perform a Fourier transform on the reference sampled data to determine the reference main frequency position of the reference sampled data; Based on the candidate main frequency position, determine the candidate phase angle value of the candidate analog-to-digital converter; The reference phase angle value of the reference analog-to-digital converter is determined based on the reference main frequency position. The phase deviation is calculated based on the candidate phase angle value and the reference phase angle value.

5. The method according to claim 1, characterized in that, The step of calculating the filter coefficient array corresponding to each of the sub-analog-to-digital converters based on the time deviation and the preset filter order includes: For the current analog-to-digital converter in the sub-analog-to-digital converter, the difference operation is performed between each order value of the preset filter order and the time deviation of the current analog-to-digital converter to determine the current difference array; Each current difference in the current difference array is used as the input variable of the Singer function to generate the filter coefficient array corresponding to the current analog-to-digital converter.

6. The method according to claim 1, characterized in that, The step of transmitting the filter coefficient array calculated by the host computer analysis software to the target software development kit (SDK), and then using the SSD to transmit the filter coefficient array to the target FPGA, includes: The filter coefficient array is transferred to the reserved array storage area of ​​the target software development kit; Using the target software development kit, and based on the reserved communication channel between the target software development kit and the target FPGA, the filter coefficient array is transmitted to the target register of the target FPGA.

7. The method according to claim 1, characterized in that, The step of filtering the original sampled data according to the filter coefficient array to generate calibration data includes: Based on the original sampled data, determine the data to be filtered corresponding to each of the sub-analog-to-digital converters; The data to be filtered is matched and multiplied with each filter coefficient in the filter coefficient array to determine the product array corresponding to each sub-analog-to-digital converter; The data within the product array are accumulated to generate the filter data corresponding to each of the sub-analog-to-digital converters; The filtered data is interleaved over time to generate the calibration data.

8. A timing calibration device for an analog-to-digital converter, characterized in that, The device includes: The data acquisition unit is used to acquire the raw sampling data of the target analog-to-digital converter based on the target FPGA, and send the raw sampling data to the host computer analysis software. The target analog-to-digital converter is a time-interleaved analog-to-digital converter, and the target analog-to-digital converter includes multiple sub-analog-to-digital converters. The time deviation calculation unit is used to analyze the original sampling data using the host computer analysis software to determine the time deviation corresponding to each of the sub-analog-to-digital converters; The filter coefficient calculation unit is used to calculate the filter coefficient array corresponding to each of the sub-analog-to-digital converters based on the time deviation and the preset filter order using the host computer analysis software. The filter coefficient transmission unit is used to transmit the filter coefficient array calculated by the host computer analysis software to the target software development kit, and use the target software development kit to transmit the filter coefficient array to the target FPGA; The timing calibration unit is used to drive the target FPGA to filter the original sampled data according to the filter coefficient array to generate calibration data.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory being used to store a computer program that, when executed by the processor, implements the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 7.

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