Data calibration method, device and equipment of analog-to-digital converter, medium and product

Abstract

The invention relates to the technical field of analog-to-digital conversion, and discloses a data calibration method, device and equipment of an analog-to-digital converter, a medium and a product, the method comprises the following steps: a field programmable logic gate array obtains an original digital interleaved signal output by the analog-to-digital converter, and sends the original digital interleaved signal to a simulation system; the simulation system simulates the original digital interleaved signal to obtain a filter coefficient, and sends the filter coefficient to the field programmable logic gate array through the software development kit; and the field programmable logic gate array reads the original digital interleaved signal from a special random access memory of the field programmable logic gate array, and performs filtering calculation on the original digital interleaved signal to obtain a filtering result. Therefore, through the simulation system, the field programmable logic gate array, the software development kit and the special random access memory, joint debugging is carried out on the digital interleaved signals obtained through analog-to-digital conversion, and a good calibration effect under the condition of low resource consumption is achieved.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital conversion technology, specifically to data calibration methods, apparatus, equipment, media, and products for analog-to-digital converters. Background Technology

[0002] In high-speed digitization systems, the ADC (Analog-to-Digital Converter) plays an increasingly important role as the core bridge connecting the analog world and digital processing. It is widely used in high-speed oscilloscopes, autonomous driving sensors, and MRI (Magnetic Resonance Imaging) medical imaging systems. The sampling rate, accuracy, and linearity of the ADC directly determine the overall performance of the system using it. With the surge in signal bandwidth demands, traditional single-channel ADCs face physical limitations, while Time-Interleaved ADCs achieve GHz-level ultra-high-speed conversion through multi-channel parallel sampling.

[0003] However, the time interleaving of interleaved ADCs introduces sampling time skew, which easily leads to sampling time mismatch, severely limiting the overall performance of the ADC. Common solutions to sampling time mismatch in related technologies include analog domain calibration and digital domain calibration. However, the accuracy of these calibration schemes urgently needs improvement. Summary of the Invention

[0004] In view of the above, the present invention provides a data calibration method, apparatus, device, medium and product for an analog-to-digital converter to solve or at least partially solve the above-mentioned technical problems.

[0005] In a first aspect, the present invention provides a data calibration method for an analog-to-digital converter, the method comprising:

[0006] The field-programmable gate array (FPGA) acquires the raw digitally interleaved signal output from the analog-to-digital converter (ADC) and sends the raw digitally interleaved signal to the simulation system.

[0007] The simulation system simulates the original digitally interleaved signal, obtains the filter coefficients, and sends the filter coefficients to the field-programmable gate array via a software development kit;

[0008] The field-programmable gate array (FPGA) reads the original digital interleaved signal from its dedicated random access memory (RAM) and performs filtering calculations on the original digital interleaved signal to obtain the filtering result.

[0009] The present invention provides a data calibration method for analog-to-digital converters. By using a simulation system, a field-programmable gate array (FPGA), a software development kit (SDK), and a dedicated random access memory (RAM), the digital interleaved signal obtained from the analog-to-digital conversion is jointly debugged, achieving good calibration results under conditions of low resource consumption.

[0010] In some alternative implementations, the simulation system simulates the original digitally interleaved signal to obtain filter coefficients, including:

[0011] The simulation system analyzes the sub-ADC data of multiple channels in the original digitally interleaved signal;

[0012] The clock signal deviation of the sub-ADC is obtained by calculating the data from the sub-ADC.

[0013] Obtain the phase angle of the sub-ADC;

[0014] Based on the phase angle, determine the phase deviation of the sub-ADC;

[0015] Convert phase deviation into time deviation;

[0016] The filter coefficients of the sub-ADC are obtained based on the time deviation and the preset filter order.

[0017] In some alternative implementations, obtaining the phase angle of the sub-ADC includes:

[0018] Based on the data collected by the sub-ADC, obtain the main frequency position of the sub-ADC;

[0019] Based on the main frequency position, the phase angle of the sub-ADC is calculated.

[0020] In some alternative implementations, the filter coefficients are sent to the field-programmable gate array via a software development kit, including:

[0021] Based on the array reserved in the software development kit for storing filter coefficients, the filter coefficients are written into the software package file of the software development kit;

[0022] The software development kit transmits the filter coefficients to the field-programmable gate array;

[0023] Field-programmable gate arrays (FPGAs) save filter coefficients to pre-configured registers for storing filter coefficients.

[0024] In some alternative implementations, sending filter coefficients to a field-programmable gate array via a software development kit further includes:

[0025] The filter coefficients are updated in real time based on the computation request of the field-programmable gate array (FPGA) and written into the software development kit (SDK).

[0026] The data calibration method for analog-to-digital converters of the present invention enables the continuous updating of filter coefficients through software package files of a software development kit and registers of a field-programmable gate array, effectively improving the overall calibration effect of data calibration for analog-to-digital converters.

[0027] In some optional implementations, filtering calculations are performed on the original digitally interleaved signal to obtain the filtering result, including:

[0028] For the raw digitally interleaved signal of a sub-ADC, the data of each channel of the raw digitally interleaved signal is multiplied and accumulated with the corresponding filter coefficients;

[0029] Based on the calculation results of each channel, the sub-filtering results of the sub-ADC are obtained.

[0030] In a second aspect, the present invention provides a data calibration device for an analog-to-digital converter, the device comprising:

[0031] The acquisition module is used to acquire the raw digital interleaved signal output by the analog-to-digital converter from the field-programmable gate array and send the raw digital interleaved signal to the simulation system.

[0032] The simulation module is used to simulate the original digitally interleaved signal, obtain the filter coefficients, and send the filter coefficients to the field-programmable gate array via the software development kit.

[0033] The filtering module is used to read the original digital interleaved signal from the dedicated random access memory of the field-programmable gate array (FPGA), perform filtering calculations on the original digital interleaved signal, and obtain the filtering result.

[0034] Thirdly, the present invention provides a computer device, comprising:

[0035] The memory and processor are interconnected and communicate with each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the data calibration method of the analog-to-digital converter described in the first aspect or any of its corresponding embodiments.

[0036] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the data calibration method for an analog-to-digital converter according to the first aspect or any corresponding embodiment described above.

[0037] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the data calibration method for an analog-to-digital converter according to the first aspect or any corresponding embodiment described above. Attached Figure Description

[0038] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0039] Figure 1 This is a flowchart of a data calibration method for an analog-to-digital converter according to an embodiment of the present invention;

[0040] Figure 2 A schematic diagram illustrating the algorithm principle of the data calibration method for the analog-to-digital converter of the invention is shown;

[0041] Figure 3 This is a flowchart of another analog-to-digital converter data calibration method according to an embodiment of the present invention;

[0042] Figure 4 This diagram illustrates the data change process of the filter coefficients obtained by simulating the original digitally interleaved signal using a simulation system.

[0043] Figure 5 The diagram illustrates the process of how the simulation system analyzes the changes in sub-ADC data from multiple channels in the original digitally interleaved signal.

[0044] Figure 6 This diagram illustrates the data transformation process of the filtering result obtained by the FPGA performing filtering calculations on the original digital interleaved signal.

[0045] Figure 7 This is a structural block diagram of a data calibration device for an analog-to-digital converter according to an embodiment of the present invention;

[0046] Figure 8 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] In related technologies, common solutions to sampling time mismatch include analog domain calibration and digital domain calibration, but their calibration accuracy is not high enough. This invention proposes a digital domain calibration method to address this problem. This method employs a combined design scheme of MATLAB (simulation system), FPGA (Field Programmable Gate Array), SDK (Software Development Kit), and BRAM (Block Random Access Memory), achieving good calibration results with low resource consumption and enabling real-time updates of filter parameters to improve overall calibration performance. The BRAM is a dedicated random access memory used in the FPGA.

[0049] Specifically, embodiments of the present invention provide a data calibration method, apparatus, device, medium, and product for an analog-to-digital converter.

[0050] According to an embodiment of the present invention, a data calibration method for an analog-to-digital converter is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0051] This embodiment provides a data calibration method for an analog-to-digital converter, which can be used for signal calibration of the aforementioned ADC. Figure 1 This is a flowchart of a data calibration method for an analog-to-digital converter according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0052] In step S101, the field programmable gate array acquires the raw digital interleaved signal output by the analog-to-digital converter and sends the raw digital interleaved signal to the simulation system.

[0053] In some alternative implementations, the analog-to-digital converter may be a time-interleaved analog-to-digital converter.

[0054] For example, consider the raw digitally interleaved signal output from a four-channel high-speed, high-precision ADC chip with a sampling rate of 10 GHz and a resolution of 10 bits. The analog-to-digital converter chip can be designated as a 10G10 chip. This ADC has 128 sub-ADCs, each operating at a frequency of 312.5 MHz. The entire ADC has four channels, and each channel uses 32 sub-ADCs interleaved to achieve a sampling rate of 10 GHz.

[0055] Figure 2A schematic diagram illustrating the algorithm principle of the data calibration method for the invented analog-to-digital converter is shown. (Reference) Figure 2 As shown, an external analog signal is input to the ADC chip. After analog-to-digital conversion, the ADC chip transmits the data to the FPGA via a data interface. The FPGA acquires the collected signal data and saves it locally on the computer, for example, through BRAM. This enables the field-programmable gate array (FPGA) to acquire the raw digital interleaved signal output from the analog-to-digital converter. Furthermore, the FPGA can send the acquired raw digital interleaved signal from the analog-to-digital converter to the simulation system.

[0056] In step S102, the simulation system simulates the original digitally interleaved signal to obtain filter coefficients, and sends the filter coefficients to the field-programmable gate array via a software development kit.

[0057] refer to Figure 2 As shown, in some optional implementations, MATLAB (the simulation system) can perform MATLAB simulation on the original digitally interleaved signal to obtain filter coefficients. These filter coefficients are then sent to the SDK (Software Development Kit). After obtaining the filter coefficients, the SDK can send them to the FPGA via communication. Sending the filtering system to the FPGA through the SDK is primarily to utilize the array reserved for storing filter coefficients in the C language code written in the SDK. The calculated filter coefficients can be saved to the SDK file via script or manual writing. Furthermore, during actual testing, the filter coefficients in the SDK can be changed at any time, thereby changing the filter coefficients on the FPGA side.

[0058] In step S103, the field-programmable gate array (FPGA) reads the original digital interleaved signal from its dedicated random access memory (RAM) and performs filtering calculations on the original digital interleaved signal to obtain the filtering result.

[0059] In some optional implementations, after the SDK obtains the filter coefficients, a register for storing the filter coefficients is still reserved on the FPGA side during the communication between the SDK and the FPGA. Through the communication protocol between the SDK and the FPGA, the SDK transmits the stored filter coefficients to the FPGA and stores the filter coefficients in the FPGA's register. Then, the FPGA performs filtering operations on the FPGA side based on the obtained filter coefficients.

[0060] During the filtering operation, the raw data acquired by the ADC and the filter coefficients are used for filtering. In order to reduce the overall resource consumption during the filtering operation, the data acquired by the FPGA is stored in BRAM. During the filtering process, one cycle of data is read from the BRAM for operation. Although using BRAM to store data for data filtering will increase the filtering time, it will save a lot of resources.

[0061] Furthermore, the FPGA outputs the filtered data, allowing the user to obtain the necessary filtered data for subsequent operations.

[0062] The present invention provides a data calibration method for analog-to-digital converters. By using a simulation system, a field-programmable gate array (FPGA), a software development kit (SDK), and a dedicated random access memory (RAM), the digital interleaved signal obtained from the analog-to-digital conversion is jointly debugged, achieving good calibration results under conditions of low resource consumption.

[0063] This embodiment provides a data calibration method for an analog-to-digital converter, which can be used for signal calibration of the aforementioned ADC. Figure 3 This is a flowchart of another analog-to-digital converter data calibration method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps:

[0064] In step S301, the field programmable gate array acquires the raw digital interleaved signal output by the analog-to-digital converter and sends the raw digital interleaved signal to the simulation system.

[0065] Please see details Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0066] In step S302, the simulation system simulates the original digitally interleaved signal to obtain filter coefficients, and sends the filter coefficients to the field-programmable gate array via a software development kit.

[0067] Figure 4 This diagram illustrates the data change process of the filter coefficients obtained by simulating the original digitally interleaved signal using a simulation system. (Refer to...) Figure 4 In some optional implementations, the step S302 "simulation system simulates the original digitally interleaved signal to obtain filter coefficients" can be achieved by the following operations: thereby, sub-ADC data is acquired sequentially, phase angle is acquired, converted into time deviation, and the time deviation and filter order are input into the filter function to obtain filter coefficients.

[0068] Step a1: The simulation system analyzes the sub-ADC data of multiple channels in the original digitally interleaved signal.

[0069] Figure 5 This diagram illustrates the process of a simulation system parsing the changes in sub-ADC data across multiple channels of a raw digitally interleaved signal. In some alternative implementations, refer to... Figure 5 The raw data acquired by the FPGA is the raw digitally interleaved signal output by the analog-to-digital converter (ADC). This raw digitally interleaved signal is obtained by interleaving the data through the ADC. In the process of analyzing the data, MATLAB first acquires the interleaved data for each channel, and then obtains the data for each sub-ADC within each channel. This data is then used in subsequent operations to calculate the phase difference of each sub-ADC within each channel, etc.

[0070] Step a2: Calculate the sub-ADC data to obtain the clock signal deviation of the sub-ADC.

[0071] In some alternative implementations, the phase difference of each sub-ADC in each channel, i.e., the SKEW deviation (clock signal deviation) of the sub-ADC, can be calculated based on the data of each sub-ADC obtained.

[0072] Step a3: Obtain the phase angle of the sub-ADC.

[0073] In some alternative implementations, the main frequency position of the sub-ADC can be obtained based on the data collected by the sub-ADC, and the phase angle of the sub-ADC can be calculated based on the main frequency position. This achieves step a3 above.

[0074] Step a4: Determine the phase deviation of the sub-ADC based on the phase angle.

[0075] Step a5: Convert the phase deviation into a time deviation;

[0076] Step a6: Based on the time deviation and the preset filter order, obtain the filter coefficients of the sub-ADC.

[0077] In some alternative implementations, step S302, "sending filter coefficients to the field-programmable gate array via a software development kit," can be achieved through the following operations:

[0078] Step b1: Based on the array reserved in the software development kit for storing filter coefficients, write the filter coefficients into the software package file of the software development kit.

[0079] Specifically, after analyzing the data in MATLAB, the filter coefficients required for each sub-ADC are obtained. The obtained filter coefficients can then be used for subsequent filtering operations. The C language code written in the SDK software reserves an array to store the filter coefficients. The calculated filter coefficients can be saved to the SDK file through scripts or manual writing.

[0080] In step b2, the software development kit transmits the filter coefficients to the field-programmable gate array.

[0081] Specifically, after the SDK obtains the filter coefficients, in the communication between the SDK and the FPGA, a register for storing the filter coefficients is still reserved on the FPGA side. Through the communication protocol between the SDK and the FPGA, the SDK transmits the stored filter coefficients to the FPGA.

[0082] Step b3: The field-programmable gate array saves the filter coefficients to a pre-configured register for storing the filter coefficients.

[0083] Specifically, the FPGA can store the filter coefficients in the FPGA registers, and then perform filtering operations on the FPGA side based on the obtained filter coefficients.

[0084] In some optional implementations, step S302, "sending filter coefficients to the field-programmable gate array via a software development kit," further includes:

[0085] Step b4: Based on the computation request of the field-programmable gate array, the filter coefficients written into the software package file of the software development kit are changed in real time.

[0086] Specifically, during actual testing, the filter coefficients of the SDK can be changed at any time, thereby changing the filter coefficients on the FPGA side.

[0087] The data calibration method for analog-to-digital converters of the present invention enables the continuous updating of filter coefficients through software package files of a software development kit and registers of a field-programmable gate array, effectively improving the overall calibration effect of data calibration for analog-to-digital converters.

[0088] In step S303, the field-programmable gate array (FPGA) reads the original digital interleaved signal from its dedicated random access memory (RAM) and performs filtering calculations on the original digital interleaved signal to obtain the filtering result.

[0089] In some optional implementations, BRAM is used to store the data from the filtering calculation process. Specifically, during the filtering operation, the raw data acquired by the ADC and the filter coefficients are used for filtering. To reduce the overall resource consumption during the filtering operation, BRAM is used to store the data acquired by the FPGA. During the filtering process, one cycle of data is read from the BRAM for calculation. Although using BRAM to store data for filtering will increase the filtering time, it will significantly save resource consumption.

[0090] Figure 6 This diagram illustrates the data transformation process of obtaining the filtered result from the filtering calculation of the original digital interleaved signal using an FPGA. (Reference) Figure 6 Each cycle, the BRAM outputs the raw ADC data. Each cycle performs filtering on only one sub-ADC of each of the four channels, which is equivalent to filtering only on four sub-ADCs per cycle. Subsequently, each cycle changes a filter parameter and a sub-ADC data. That is, the current cycle calculates the filter parameters corresponding to sub-ADC1, and the next cycle calculates the filter parameters corresponding to sub-ADC2. After the filtering operation of each channel's sub-ADC is completed, the BRAM outputs the data of the next cycle. The data output by the BRAM is then filtered with the filter coefficients obtained by the FPGA. Specifically, the acquired raw data and the filter coefficients are multiplied and accumulated. The number of raw data multiplied is equal to the number of filter coefficients of different orders. Finally, the accumulated data is used to obtain the filtering result.

[0091] Specifically, in some optional implementations, step S303 may include:

[0092] Step S3031: For the original digitally interleaved signal of a sub-ADC, multiply and accumulate the data of each channel of the original digitally interleaved signal with the corresponding filter coefficients.

[0093] Step S3032: Based on the calculation results of each channel, obtain the sub-filtering results of the sub-ADC.

[0094] This embodiment also provides a data calibration device for an analog-to-digital converter, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0095] This embodiment provides a data calibration device for an analog-to-digital converter, such as... Figure 7 As shown, it includes:

[0096] The acquisition module 701 is used to acquire the raw digital interleaved signal output by the analog-to-digital converter from the field-programmable gate array and send the raw digital interleaved signal to the simulation system.

[0097] Simulation module 702 is used to simulate the original digitally interleaved signal in the simulation system, obtain filter coefficients, and send the filter coefficients to the field-programmable gate array via a software development kit.

[0098] The filtering module 703 is used to read the original digital interleaved signal from the dedicated random access memory of the field programmable gate array (FPGA), and to perform filtering calculations on the original digital interleaved signal to obtain the filtering result.

[0099] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0100] In this embodiment, the data calibration device for the analog-to-digital converter is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0101] This invention also provides a computer device having the above-described features. Figure 7 The data calibration device for the analog-to-digital converter shown.

[0102] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 8 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 8 Take a processor 10 as an example.

[0103] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0104] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0105] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0106] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0107] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0108] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0109] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0110] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended technical solutions.

Claims

1. A data calibration method for an analog-to-digital converter, characterized in that, The method includes: The field-programmable gate array acquires the raw digital interleaved signal output by the analog-to-digital converter and sends the raw digital interleaved signal to the simulation system; The simulation system simulates the original digitally interleaved signal to obtain filter coefficients, and sends the filter coefficients to the field-programmable gate array via a software development kit. The field-programmable gate array (FPGA) reads the original digital interleaved signal from its dedicated random access memory (RAM) and performs filtering calculations on the original digital interleaved signal to obtain the filtering result.

2. The method according to claim 1, characterized in that, The simulation system simulates the original digitally interleaved signal to obtain filter coefficients, including: The simulation system analyzes the sub-ADC data of multiple channels in the original digitally interleaved signal; The clock signal deviation of the sub-ADC is obtained by calculating the data of the sub-ADC. Obtain the phase angle of the sub-ADC; Based on the phase angle, the phase deviation of the sub-ADC is determined; Convert the phase deviation into a time deviation; The filter coefficients of the sub-ADC are obtained based on the time deviation and the preset filter order.

3. The method according to claim 2, characterized in that, The step of obtaining the phase angle of the sub-ADC includes: Based on the data collected by the sub-ADC, the main frequency position of the sub-ADC is obtained; Based on the main frequency position, the phase angle of the sub-ADC is calculated.

4. The method according to claim 1, characterized in that, The step of sending the filter coefficients to the field-programmable gate array via a software development kit includes: Based on the array reserved in the software development kit for storing the filter coefficients, the filter coefficients are written into the software package file of the software development kit; The software development kit transmits the filter coefficients to the field-programmable gate array; The field-programmable gate array saves the filter coefficients to a pre-configured register for storing the filter coefficients.

5. The method according to claim 4, characterized in that, The step of sending the filter coefficients to the field-programmable gate array via a software development kit further includes: Based on the computation request of the field-programmable gate array, the filter coefficients written into the software package file of the software development kit are changed in real time.

6. The method according to claim 1, characterized in that, The filtering calculation of the original digitally interleaved signal to obtain the filtering result includes: For the raw digitally interleaved signal of a sub-ADC, the data of each channel of the raw digitally interleaved signal is multiplied and accumulated with the corresponding filter coefficients; Based on the calculation results of each channel, the sub-filtering results of the sub-ADC are obtained.

7. A data calibration device for an analog-to-digital converter, characterized in that, The device includes: The acquisition module is used to acquire the raw digital interleaved signal output by the analog-to-digital converter using a field-programmable gate array, and to send the raw digital interleaved signal to the simulation system. The simulation module is used by the simulation system to simulate the original digitally interleaved signal, obtain filter coefficients, and send the filter coefficients to the field-programmable gate array via a software development kit. The filtering module is used to read the original digital interleaved signal from the dedicated random access memory of the field-programmable gate array (FPGA), and to perform filtering calculations on the original digital interleaved signal to obtain the filtering result.

8. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory storing computer instructions, and the processor executing the computer instructions to perform the data calibration method for the analog-to-digital converter according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the data calibration method for the analog-to-digital converter according to any one of claims 1 to 6.

10. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the data calibration method for an analog-to-digital converter as described in any one of claims 1 to 6.

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