Digital-to-analog converter structure determination method and digital-to-analog converter structure

Abstract

The invention provides a digital-to-analog converter structure determination method and a digital-to-analog converter structure, and the method comprises the steps: building a combined resistor segment under the condition that a resistor simulation result does not meet a preset condition; random mismatch calibration is carried out on the combined resistor segments through directional element matching; under the condition that random mismatch calibration reaches a set calibration condition, resistance simulation is carried out on the combined resistor segments; under the condition that the simulation result of the resistance simulation does not meet the preset condition, resistance nonlinear calibration is carried out on the combined resistance segments; the structure of the digital-to-analog converter is determined through combination type resistor segmentation of resistor non-linear calibration. The digital-to-analog converter is arranged by adopting a combined resistor segmented resistor structure, compromise between the area and the precision can be realized, and the precision of the digital-to-analog converter is improved while the size of the digital-to-analog converter is reduced. In addition, the random mismatch of the resistor is calibrated by adopting a directional element matching technology, so that the calibration cost is relatively low.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuits, in particular to a digital-to-analog converter structure determination method and a digital-to-analog converter structure. BACKGROUND

[0002] In modern digital signal processing and analog circuit design, a digital-to-analog converter (DAC) plays a crucial role in converting digital signals into corresponding analog signals. A resistor-type DAC realizes digital-to-analog conversion through resistor voltage division, and its output noise is mainly determined by the thermal noise of the resistor, which decreases approximately linearly with temperature, so the resistor-type DAC has excellent noise performance at low temperatures. Most high-precision DACs rely on an accurate resistor array to complete data conversion, so the precision of the resistor network is very sensitive to the matching degree.

[0003] However, under low temperature conditions, the physical properties of the resistor element will change significantly, which will directly lead to a decrease in the accuracy of the DAC output analog signal. SUMMARY

[0004] Therefore, the purpose of the embodiments of the present application is to provide a digital-to-analog converter structure determination method and a digital-to-analog converter structure, which can reduce the size of the digital-to-analog converter while improving the precision of the digital-to-analog converter.

[0005] In a first aspect, the embodiments of the present application provide a digital-to-analog converter structure determination method, comprising: in the case that a resistance simulation result does not meet a preset condition, building a combined resistance section; through directional element matching, randomly calibrating the combined resistance section; in the case that the random mismatch calibration reaches a set calibration condition, performing resistance simulation on the combined resistance section; in the case that the simulation result of the resistance simulation does not meet the preset condition, performing resistance nonlinearity calibration on the combined resistance section; and determining a digital-to-analog converter structure through the combined resistance section calibrated by the resistance nonlinearity calibration.

[0006] In the above implementation process, the digital-to-analog converter is set by using the combined resistance section resistance structure. Since the combined resistance section combines the advantages of the thermometer type structure and the binary coding type structure, it can achieve a compromise between area and precision, reduce the size of the digital-to-analog converter while improving the precision of the digital-to-analog converter. In addition, the random mismatch of the resistor is calibrated by using the directional element matching technology. Since the directional element matching technology only needs to change the decoding method of the thermometer code section, the calibration cost is very low, and the cost of determining the digital-to-analog converter structure can be reduced.

[0007] In one embodiment, the combined resistance segment includes: higher weight bits and lower weight bits; the random mismatch calibration of the combined resistance segment by directional element matching includes: sorting resistance pins of all thermometer structures in the higher weight bits according to resistance values; pairing two resistance pins symmetrically distributed in the resistance pins sorted according to resistance values to obtain a folded higher weight bit; repeating from the sorting of all resistance pins of thermometer structures in the folded higher weight bit according to resistance values until an iteration termination condition is reached to obtain a completely folded higher weight bit; and the completely folded higher weight bit is a binary code type structure.

[0008] In the above implementation process, the complete folding of the resistance pins of the thermometer structure can greatly reduce the random mismatch error between the resistance pins of the thermometer structure and improve the random mismatch accuracy.

[0009] In one embodiment, the method further includes: constructing a calibration bit; and setting the calibration bit on a side of the lower weight bit away from the higher weight bit; wherein the calibration bit is configured to reserve a calibration space for the lower weight.

[0010] In the above implementation process, by setting the calibration bit on the side of the lower weight bit away from the higher weight bit, a calibration space can be reserved for the lower weight, and when the lower weight bit needs to be calibrated, the calibration bit can be used for calibration, thereby improving the calibration flexibility.

[0011] In one embodiment, the higher weight bit includes: a part of resistance pins in each region connected to a voltage and another part of resistance pins in each region grounded; the resistance pins are connected to PMOS transistors and NMOS transistors, gates of the PMOS transistors and the NMOS transistors are connected to two R-2R digital-to-analog converters, respectively; the PMOS transistors and the NMOS transistors constitute a complementary transmission gate switch; and the resistance nonlinearity calibration of the combined resistance segment includes: determining a conduction resistance that needs to be adjusted according to a relationship between an output voltage of the combined resistance segment and a preset voltage; wherein the conduction resistance is connected to the complementary transmission gate switch; the conduction resistance is adjusted by controlling the R-2R digital-to-analog converter bias; and the conduction resistance is configured to compensate for the nonlinearity of the corresponding resistance pins.

[0012] In the above implementation process, by determining the conduction resistance that needs to be adjusted according to the relationship between the output voltage and the preset voltage, and adjusting the conduction resistance by controlling the digital-to-analog converter bias, the nonlinearity of the corresponding resistance pins can be compensated, so that the nonlinearity of the sum of the switching resistance and the resistance value of the resistance pins in the digital-to-analog converter output voltage range is reduced, and the nonlinearity calibration capability is improved.

[0013] In one embodiment, the building of the combined resistance segment in the case that the resistance simulation result does not satisfy the preset condition comprises: building a plurality of combined resistance segments according to the respective digital-to-analog converters; wherein a higher weight bit in each of the combined resistance segments adopts a thermometer code type structure, and a lower weight bit in each of the combined resistance segments adopts a binary coding type structure; determining a main combined resistance segment according to the accuracy of the binary coding type structure in each of the combined resistance segments; the main combined resistance segment is configured to construct the digital-to-analog converter; and the random mismatch calibration of the combined resistance segment through the directional element matching comprises: the random mismatch calibration of the main combined resistance segment through the directional element matching.

[0014] In the above implementation process, the main combined resistance segment satisfying the accuracy requirement of the digital-to-analog converter can be determined by selecting the main combined resistance segment according to the accuracy, so as to improve the accuracy of the digital-to-analog converter.

[0015] In one embodiment, before the random mismatch calibration of the combined resistance segment through the directional element matching, the method further comprises: judging whether the main combined resistance segment needs to be further segmented according to the occupied area of the thermometer code type structure of the main combined resistance segment; and further segmenting the thermometer code type structure of the main combined resistance segment in the case that it is determined that the main combined resistance segment needs to be further segmented.

[0016] In the above implementation process, the thermometer code type structure can be further segmented in the case that the occupied area of the thermometer code type structure is large, so as to further reduce the occupied area of the thermometer code type structure.

[0017] In a second aspect, the embodiments of the present application further provide a digital-to-analog converter structure, comprising: the digital-to-analog converter structure is determined through the first aspect or any one of the methods of the first aspect, and comprises a combined resistance segment; wherein a higher weight bit in the combined resistance segment adopts a thermometer code type structure, and a lower weight bit in the combined resistance segment adopts a binary coding type structure; the thermometer code type structure comprises two thermometer code type substructures, and the two thermometer code type substructures are connected through a bridge resistance.

[0018] In the above implementation process, the digital-to-analog converter is set by using the combined resistance segment resistance structure, and since the combined resistance segment combines the advantages of the thermometer type structure and the binary coding type structure, the area and the accuracy can be compromised, the volume of the digital-to-analog converter is reduced, and the accuracy of the digital-to-analog converter is improved.

[0019] In one embodiment, a part of the resistance pins in each region in the higher weight bits is connected to a voltage, and another part of the resistance pins in each region is grounded; the digital-to-analog converter structure further comprises: a PMOS transistor and an NMOS transistor; the gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converter biases; the PMOS transistor and the NMOS transistor constitute a complementary transmission gate switch; the complementary transmission gate switch is connected to a turn-on resistance; the R-2R digital-to-analog converter biases are connected to the inputs of the resistance pins; wherein the R-2R digital-to-analog converter biases are configured to adjust the turn-on resistance, and the turn-on resistance is configured to compensate for the non-linear change of the corresponding resistance pin.

[0020] In the implementation process described above, by designing a complementary transmission gate switch composed of a PMOS transistor and an NMOS transistor, and connecting a turn-on switch, the non-linear change of the resistance pin is compensated through the turn-on switch, thereby reducing the non-linear change of the digital-to-analog converter.

[0021] In one embodiment, the digital-to-analog converter structure is an 18-bit digital-to-analog converter structure; the combined resistance segmentation is a 10-bit-2-bit-6-bit segmentation structure; wherein the low 10 bits are R-2R structure, and the middle 2 bits and the high 6 bits are thermometer code sub-structures.

[0022] In the implementation process described above, for an 18-bit digital-to-analog converter structure, designing its combined resistance segmentation as a 10-bit-2-bit-6-bit segmentation structure can greatly reduce the area occupied by the combined resistance segmentation.

[0023] In one embodiment, it further comprises a calibration bit; the calibration bit is arranged on the side of the low 10 bits away from the middle 2 bits; wherein the calibration bit is configured to reserve a calibration space for the low 10 bits.

[0024] In the implementation process described above, by arranging a calibration bit on the side of the lower weight bits away from the higher weight bits, a calibration space can be reserved for the lower weight bits, and when the lower weight bits need to be calibrated, the calibration bit can be used for calibration, thereby improving the calibration flexibility.

[0025] In a third aspect, the embodiments of the present application further provide a digital-to-analog converter structure determination apparatus, comprising: a building module configured to build a combined resistance segment in a case where a resistance simulation result does not satisfy a preset condition; a first calibration module configured to calibrate the combined resistance segment by directional element matching; a simulation module configured to perform resistance simulation on the combined resistance segment in a case where the random mismatch calibration reaches a set calibration condition; a second calibration module configured to perform resistance nonlinearity calibration on the combined resistance segment in a case where a simulation result of the resistance simulation does not satisfy the preset condition; and a determination module configured to determine a digital-to-analog converter structure by the combined resistance segment after the resistance nonlinearity calibration.

[0026] In a fourth aspect, the embodiments of the present application further provide an electronic device, comprising: a processor, a memory, wherein the memory stores machine readable instructions executable by the processor, and when the electronic device is running, the machine readable instructions are executed by the processor to perform the steps of the method of the first aspect or any possible implementation manner of the first aspect.

[0027] In a fifth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores a computer program, and when the computer program is run by a processor, the steps of the digital-to-analog converter structure determination method of the first aspect or any possible implementation manner of the first aspect are executed.

[0028] In order to make the above objectives, characteristics and advantages of the present application more apparent and understandable, the following embodiments are specifically described below, and the accompanying drawings are described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0030] Figure 1 The block diagram of the electronic device provided by the embodiments of the present application is shown in the figure; Figure 2 The flowchart of the digital-to-analog converter structure determination method provided by the embodiments of the present application is shown in the figure; Figure 3 The I / V characteristics of the resistance with a nominal resistance value of 110.8kΩ at 300K and 4K respectively provided by the embodiments of the present application are shown in the figure; Figure 4 The simulation result schematic diagram of the Monte Carlo simulation of the resistance with a nominal resistance value of 110.8kΩ provided by the embodiments of the present application is shown in the figure; Figure 5 A schematic diagram of thermometer type structure for random mismatch calibration provided by the embodiment of the present application; Figure 6 A schematic diagram of main structure of 18-bit DAC provided by the embodiment of the present application; Figure 7 A schematic diagram of digital-to-analog converter structure including PMOS transistor and NMOS transistor provided by the embodiment of the present application; Figure 8 A schematic diagram of resistance change of PMOS and NMOS with HP<9:0> and HN<9:0> provided by the embodiment of the present application; Figure 9 A schematic diagram of calibration of resistance nonlinearity provided by the embodiment of the present application; Figure 10 A schematic diagram of linearity simulation result after OEM calibration and resistance nonlinearity calibration of 18-bit digital-to-analog converter provided by the embodiment of the present application; Figure 11 A schematic diagram of functional module of digital-to-analog converter structure determination device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0032] It should be noted that: similar labels and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used for distinguishing description, and cannot be understood as indicating or implying relative importance.

[0033] Quantum computing is expected to achieve exponential speedup in solving some complex problems that are difficult for traditional computers to handle. This process may require the use of thousands or millions of qubits to solve useful problems, and a quantum control system is needed to generate high-precision and low-noise electrical signals to manipulate and read the state of qubits and control the interaction between qubits. Qubits need to be in a relatively stable state in an ultra-low temperature (<100 mK) environment, while traditional control systems are in a room temperature (300 K) environment, and a large number of signal cables are used to connect the qubit chip across the temperature zone to achieve the bias, drive and readout of the qubit. This traditional method cannot be expanded to future million-qubit computers due to the excessive number of cables required. In recent years, quantum control systems are moving from room temperature to low temperature (generally 4 K) environments, and are integrated with qubit chips in a near-temperature zone. Near-temperature integration greatly reduces the noise introduced by signal cables across the temperature zone and improves integration and reliability. Therefore, the development of a low-temperature quantum control system is expected to enable large-scale expansion of quantum control arrays.

[0034] A low-temperature quantum control system is composed of three parts: gate pulses, pulse generators and reflection measurements. Among them, the gate pulse generates a direct current pulse through digital control, which is used to set the potential of the quantum gate to control the initial state of a single qubit and the coupling state between different qubits, and the pulse generator and reflection measurement are used for dynamic driving and reading of qubits. The core problem in the quantum control process is to improve the fidelity of the quantum gate, i.e. to ensure the consistency of the quantum gate state before and after control, and high-precision and low-noise gate pulses are the primary condition for achieving high-fidelity quantum gates. In addition, since the refrigeration power of the refrigerator is limited, the gate pulse needs to ensure low power consumption so that it can be used in a large-scale qubit array control system.

[0035] A digital-to-analog converter is an electronic circuit that converts digital signals (such as binary signals) into analog signals (such as voltage, current, etc.). Currently, there are mainly three forms of implementation of low-temperature DACs: capacitive DAC, current steering DAC and resistive DAC.

[0036] Capacitive DACs implement the digital-to-analog conversion process through the charging and discharging of capacitors, and have high energy efficiency and low power consumption. However, due to the existence of parasitic capacitance, there is a serious mismatch between capacitors, making it difficult to achieve high precision, and the shot noise and flicker noise of transistors at low temperatures will worsen the output noise of capacitive DACs.

[0037] The current steering DAC changes the size of the total output current by controlling the on-off of the current source to complete the data conversion process. Its main advantage is that it can drive the resistance load without buffer, and the signal conversion speed is very fast, but the use of a large number of current sources leads to high power consumption. In addition, the thermal noise of the transistor in the current steering DAC is reduced by 2-3 times at low temperature (compared with room temperature 300K), but the flicker noise is about 10 times worse, resulting in the overall output noise worsening.

[0038] The resistance type DAC realizes digital-to-analog conversion by resistance voltage division, and its output noise is mainly determined by the thermal noise of the resistance, which presents an approximately linear reduction trend with the decrease of temperature, so the resistance type DAC has excellent noise performance at low temperature. Most high-precision DACs rely on accurate resistance arrays to complete data conversion, so the precision of the resistance network is very sensitive to the matching degree.

[0039] At present, the resistance type DAC at room temperature can already achieve very high precision. For example, the 20-bit R-2R DAC realized by ADI (Analog Device Inc.) has an ultra-high precision of 19μV, and the output noise spectral density is only 7.5nV / However, at low temperature, the precision of the resistance type DAC is greatly reduced. The R-2R DAC used by MIT to control the captured particles has a resolution of only 12-bit, and the output noise of the DAC is greatly increased due to the introduction of an amplifier at the output end.

[0040] Therefore, the present application provides a digital-to-analog converter structure determination method, which sets a digital-to-analog converter by using a combined resistance segmented resistance structure. Since the combined resistance segmentation combines the advantages of the thermometer type structure and the binary coding type structure, it can achieve a compromise between area and precision, reduce the size of the digital-to-analog converter, and improve the precision of the digital-to-analog converter. In addition, the random mismatch of the resistance is calibrated by using the directional element matching technology. Since the directional element matching technology only needs to change the decoding mode of the thermometer code segment, the calibration cost is very low, and the cost of determining the structure of the digital-to-analog converter can be reduced.

[0041] In order to facilitate the understanding of the present embodiment, first, the electronic device for executing the digital-to-analog converter structure determination method disclosed in the present application is introduced in detail.

[0042] As shown in Figure 1 , it is a block diagram of an electronic device. The electronic device 100 can include a memory 111, a processor 113. Those skilled in the art can understand that Figure 1 The structure shown is only for illustration, and does not limit the structure of the electronic device 100. For example, the electronic device 100 can include more or fewer components than those shown in Figure 1 , or have a different configuration from that shown inFigure 1 different configurations.

[0043] The memory 111 and the processor 113 are directly or indirectly electrically connected to each other to realize data transmission or interaction. For example, the elements can be electrically connected to each other through one or more communication buses or signal lines. The processor 113 is used to execute the executable modules stored in the memory.

[0044] The memory 111 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), etc. The memory 111 is used to store programs, and the processor 113 executes the programs after receiving an execution instruction. The method executed by the electronic device 100 defined by the processes disclosed in any of the embodiments of the present application can be applied to the processor 113 or implemented by the processor 113.

[0045] The processor 113 can be an integrated circuit chip having a signal processing capability. The processor 113 can be a general purpose processor, including a central processing unit (CPU), a network processor (NP), etc. It can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The general purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0046] The electronic device 100 in the embodiment can be used to execute each step in each method provided in the embodiments of the present application. The implementation process of the digital-to-analog converter structure determination method is described in detail in the following several embodiments.

[0047] Please refer to Figure 2 is a flowchart of the structure determination method of a digital-to-analog converter provided by the embodiment of the present application. The specific flowchart shown in Figure 2 will be described in detail below.

[0048] Step 201, in the case that the resistance simulation result does not satisfy the preset condition, a combined resistance section is built.

[0049] Optionally, Monte Carlo simulation can be used to simulate the resistance. Monte Carlo simulation is a method of simulating complex systems or processes through random sampling, and estimating the behavior or characteristics of the system based on these simulation results. It uses random number (or pseudo-random number) generators to simulate various possible system states or results, and evaluates the probability distribution of system performance or risk based on a large number of simulation results.

[0050] The resistance simulation result here includes the random mismatch of the resistance.

[0051] In an embodiment, before step 201, the method further comprises testing the I / V characteristics of the resistance at 300K and 4K to understand the nonlinear change of the resistance at low temperature.

[0052] Exemplarily, as shown in Figure 3 , the I / V characteristics of the resistance with a nominal resistance value of 110.8kΩ at 300K and 4K are shown in Figure 3 . The test structure is as follows: at 300K, the average resistance value of the resistance is 112.2kΩ, and the voltage nonlinearity is about 15.5Ω / V; at 4K, the average resistance value of the resistance rises to 121.6kΩ (about 12.4% increase), and the voltage nonlinearity is 664Ω / V (about 43 times worse).

[0053] Continuing with the example of the resistance with a nominal resistance value of 110.8kΩ, the simulation result of the Monte Carlo simulation of the resistance is shown in Figure 4 , and the random mismatch (i.e. standard deviation) of the resistance is 134Ω.

[0054] It should be understood that after obtaining the random mismatch and nonlinearity of the resistance, the resistance at low temperature can be modeled using verilog-a language.

[0055] Here, considering that the resistance mismatch intensifies at low temperature, the resistance mismatch is configured as three times the standard deviation. For example, the resistance mismatch of the resistance with a nominal resistance value of 110.8kΩ is 402Ω.

[0056] The preset condition here refers to the simulation result range corresponding to each resistance value set in advance. The preset condition can be determined through multiple experiments, or can be determined by setting a calculation formula. The determination method of the preset condition can be selected according to the actual situation.

[0057] The combined resistance segment refers to a resistance structure in which a binary coding type structure is used in lower weight bits and a thermometer type structure is used in higher weight bits. That is, the combined resistance segment includes higher weight bits and lower weight bits.

[0058] The thermometer type structure has good monotonicity but occupies a large area. The binary coding type structure has the advantage of saving area but generally has poor monotonicity. The combined resistance segment combines the advantages of the thermometer type structure and the binary coding type structure and can achieve a compromise between area and precision.

[0059] In step 202, the combined resistance segment is calibrated for random mismatch by directional element matching.

[0060] The directional element matching refers to a manner in which resistance pins of each segment are complementarily matched so that the resistance value after matching is close to the average resistance value of the segment resistance.

[0061] It should be understood that, in the process of calibrating the combined resistance segment for random mismatch, the relative size of each resistance pin of the thermometer type structure can be obtained by connecting the resistance pin to a power supply and connecting other resistance pins to ground, and then measuring the output voltage of the digital-to-analog converter.

[0062] The greater the output voltage, the smaller the resistance value of the resistance pin.

[0063] In step 203, resistance simulation is performed on the combined resistance segment when the random mismatch calibration reaches a set calibration condition.

[0064] Alternatively, the set calibration condition can be that each segment of the combined resistance segment reaches complete folding, or the output voltage of the digital-to-analog converter reaches a set voltage, and the set calibration condition can be adjusted according to actual conditions.

[0065] The resistance simulation can use the same simulation manner as step 201 or a different simulation manner from step 201. The simulation manner of the resistance simulation can be selected according to actual conditions.

[0066] In step 204, resistance nonlinearity calibration is performed on the combined resistance segment when the simulation result of the resistance simulation does not meet a preset condition.

[0067] In one embodiment, a part of the resistance pins in each region of the higher weight bits are connected to a voltage, and another part of the resistance pins in each region are grounded; the resistance pins are connected to PMOS transistors and NMOS transistors, the gates of the PMOS transistors and the NMOS transistors are connected to bias of two R-2R digital-to-analog converters, respectively; and the PMOS transistors and the NMOS transistors constitute a complementary transmission gate switch.

[0068] The on-resistance herein is connected with the complementary transmission gate switch.

[0069] The on-resistance of the transmission gate switch can be adjusted by controlling the output voltages of the two biasing digital-to-analog converters, thereby compensating for the nonlinear variation of the resistance pins.

[0070] The resistance nonlinear calibration configuration is configured to improve the accuracy of the digital-to-analog converter.

[0071] In step 205, the digital-to-analog converter structure is determined through the combined resistance segmentation of the resistance nonlinear calibration.

[0072] The combined resistance segmentation after the resistance nonlinear calibration is the resistance structure of the digital-to-analog converter.

[0073] In the implementation process described above, the digital-to-analog converter is set by using the combined resistance segmentation resistance structure. Since the combined resistance segmentation combines the advantages of the thermometer type structure and the binary coding type structure, it can achieve a compromise between area and accuracy, reduce the volume of the digital-to-analog converter, and improve the accuracy of the digital-to-analog converter. In addition, the random mismatch of the resistance is calibrated by using the directional element matching technology. Since the directional element matching technology only needs to change the decoding method of the thermometer code segment, the calibration cost is very low, and the cost of determining the structure of the digital-to-analog converter can be reduced.

[0074] In one possible implementation, step 202 includes: sorting all resistance pins of the thermometer type structure in the higher weight bit according to resistance values; pairing two resistance pins symmetrically distributed in the resistance pins sorted according to resistance values to obtain a folded higher weight bit; and repeating from sorting all resistance pins of the thermometer type structure in the folded higher weight bit according to resistance values until an iteration termination condition is reached to obtain a completely folded higher weight bit.

[0075] The combined resistance segmentation herein includes one or more thermometer type structures. When the combined resistance segmentation is calibrated for random mismatch, each thermometer type structure can be calibrated for random mismatch respectively.

[0076] In the calibration for random mismatch of each thermometer type structure, the resistance pins of the thermometer type structure are sorted according to resistance values; two resistance pins symmetrically distributed in the resistance pins sorted according to resistance values are paired to obtain a folded higher weight bit; and repeating from sorting all resistance pins of the thermometer type structure in the folded higher weight bit according to resistance values until an iteration termination condition is reached to obtain a completely folded higher weight bit.

[0077] For example, if the combined resistance segment includes an H<62:0> segment and an M<2:0> segment thermometer type structure. Wherein, the H<62:0> segment includes 63 thermometer code resistance pins, and the M<2:0> segment includes 3 thermometer code resistance pins. When performing random mismatch calibration, first sort the 63 thermometer code resistance pins of the H<62:0> segment according to their resistance values, then select the resistance pin whose resistance value is closest to the average value Ravg (such as the resistance pin with serial number 45 in Figure 5 ), and pair the remaining complementary resistance pins (such as pairing the resistance pin with serial number 5 with the smallest resistance value and the resistance pin with serial number 12 with the largest resistance value, a total of 31 pairs of complementary resistance pin combinations). Further convert the 63-bit thermometer code into a 1-bit binary code and a 31-bit thermometer code, completing a "folding". The resistance values of the folded thermometer code resistance pins are all close to 2Ravg. Continue to fold the 31-bit thermometer code according to the above steps until the 63-bit thermometer code is completely converted into a 6-bit binary code, realizing complete folding of the H<62:0> segment.

[0078] In the same way, the 3-bit thermometer code of the M<2:0> segment is completely converted into a 2-bit binary code.

[0079] Wherein, the completely folded higher weight bits are in binary code type structure.

[0080] In the above implementation process, the complete folding processing of the resistance pins of the thermometer type structure can greatly reduce the random mismatch error between the resistance pins of the thermometer type structure, and improve the random mismatch accuracy.

[0081] In a possible implementation, the method further includes: constructing a calibration bit; and setting the calibration bit on the side of the lower weight bits away from the higher weight bits.

[0082] Wherein, the calibration bit is configured to reserve a calibration space for the lower weight bits.

[0083] It can be understood that, since the lower weight bits have a small weight in the combined resistance segment, their nonlinearity contribution to the overall digital-to-analog converter is also small. Therefore, in general, there is no need to calibrate the lower weight bits.

[0084] However, in some special cases, for example, in cases where the accuracy and sensitivity of the digital-to-analog converter are required to be relatively strict, the lower weight bits need to be calibrated. By setting a calibration bit on one side of the lower weight bits, a calibration space can be reserved for the lower weight bits, so that the lower weight bits can be calibrated when needed.

[0085] For example, if the main structure of the 18-bit DAC is as shown in Figure 6As shown, it includes: the B<9:0> segment of the lower weight bit, the M<2:0> segment of the higher weight bit, and the H<62:0> segment. Among them, the B<9:0> segment of the lower weight bit has multiple calibration bits L<2:0> segments on one side of the higher weight bit. Figure 6 (Three are shown in the image).

[0086] In the above implementation process, by setting a calibration bit on the side of the lower weight bit that is far away from the higher weight bit, calibration space can be reserved for the lower weight bit. When the lower weight bit needs to be calibrated, it can be calibrated through this calibration bit, thus improving calibration flexibility.

[0087] In one possible implementation, step 204 includes: determining the on-resistance to be adjusted based on the relationship between the output voltage of the combined resistor segment and the preset voltage; and adjusting the on-resistance by controlling the bias of the R-2R digital-to-analog converter.

[0088] The preset voltage here can be the theoretical output voltage of the combined resistor segment.

[0089] In one embodiment, if the output voltage reaches the preset voltage, it indicates that the nonlinear calibration is in place, and the corresponding on-resistance does not need to be adjusted. If the output voltage does not reach the preset voltage, it indicates that the nonlinear calibration is not in place, and the corresponding on-resistance needs to be adjusted.

[0090] Specifically, when adjustment is required, the complementary transmission gate switch is closed. When no adjustment is required, the complementary transmission gate switch is opened.

[0091] The on-resistance configuration bit here compensates for the nonlinear changes of the corresponding resistor pin, thereby reducing the nonlinear changes of the sum of the resistance values ​​of the switching resistor and the resistor pin within the output voltage range of the digital-to-analog converter.

[0092] In the above implementation process, by determining the on-resistance to be adjusted based on the relationship between the output voltage and the preset voltage, and by adjusting the on-resistance by controlling the bias of the digital-to-analog converter, the nonlinear changes of the corresponding resistor pins can be compensated, thereby reducing the nonlinear changes of the sum of the resistance values ​​of the switching resistor and the resistor pins within the output voltage range of the digital-to-analog converter and improving the nonlinear calibration capability.

[0093] In one possible implementation, step 201 includes: constructing multiple combined resistor segments according to the digital-to-analog converter; and determining the main combined resistor segment based on the precision of the binary encoding structure in each combined resistor segment.

[0094] In each combined resistor segment, the higher weight bits adopt a thermometer code structure, while the lower weight bits adopt a binary code structure.

[0095] The precision of the binary coding type structure in each of the above-mentioned combined resistance segments can be different.

[0096] The main combined resistance segment herein can be a combined resistance segment that meets the precision requirement of the digital-to-analog converter. For example, the binary coding type structure in the combined resistance segment includes 16, 14, 12, 10, 8, 6, 4, 2, etc. respectively. Among them, the precision of the binary coding type structure equal to or greater than 10 meets the precision requirement of the digital-to-analog converter, and then the combined resistance segment in which the binary coding type structure of 16, 14, 12, and 10 is located can be determined as the main combined resistance segment.

[0097] For example, if the digital-to-analog converter is an 18-bit digital-to-analog converter, the combined resistance segments of 16-2, 14-4, 12-6, 10-8, etc. can be built respectively. Among them, the lower weight bits use the R-2R structure, and the higher weight bits use the thermometer code type structure.

[0098] The linearity simulation results of the digital-to-analog converters with different segment structures can be as shown in Table 1.

[0099] Table 1:

[0100] As can be seen from Table 1, the more the number of bits of the thermometer code type structure, the higher the precision of the digital-to-analog converter, but at the same time, the required area is also larger. The 12-6 segment structure requires 63 thermometers, and the 10-8 segment structure requires 255 thermometers, and the required area increases exponentially.

[0101] The above-mentioned main combined resistance segment is configured to build a digital-to-analog converter.

[0102] In one embodiment, step 202 includes: performing random mismatch calibration on the main combined resistance segment by directional element matching.

[0103] It should be understood that since the main combined resistance segment is a combined resistance segment that meets the precision requirement of the digital-to-analog converter. Therefore, when building a digital-to-analog converter, the main combined resistance segment is usually used for configuration. Thus, when performing random mismatch calibration, the main combined resistance segment can be calibrated only.

[0104] In the above implementation process, by selecting the main combined resistance segment according to the precision, and then building a digital-to-analog converter, the main combined resistance segment that meets the precision requirement of the digital-to-analog converter can be determined, so as to improve the precision of the digital-to-analog converter.

[0105] In a possible implementation, before step 202, the method further includes: determining whether the main combined resistance segment needs further segmentation according to an occupied area of the thermometer code type structure of the main combined resistance segment; and further segmenting the thermometer code type structure of the main combined resistance segment in a case where it is determined that the main combined resistance segment needs further segmentation.

[0106] In an embodiment, the further segmentation is determined in a case where the occupied area of the thermometer code type structure of the main combined resistance segment is greater than a preset area.

[0107] The preset area herein refers to a set optimal occupied area of resistance, or a set maximum occupied area of resistance. The preset area can be selected according to actual conditions.

[0108] The further segmentation described above refers to further segmenting the thermometer code type structure, and dividing the thermometer code type structure into multiple segments. For example, the thermometer code type structure is further divided into two segments, or the thermometer code type structure is further divided into three segments.

[0109] For example, in order to reduce the occupied area of the thermometer code structure, the thermometer code structure is divided into two segments: that is, the 8-bit thermometer code type structure in the 10-8 segment structure can also be divided into two segments of 2-6, and the two segments are connected by a bridge resistance. Thus, the originally required 255 thermometer codes are reduced to 3+63=66 thermometer codes after the further segmentation, greatly reducing the occupied area.

[0110] In the implementation process described above, the thermometer code type structure can be further segmented in a case where the occupied area of the thermometer code type structure is large, further reducing the occupied area of the thermometer code type structure.

[0111] For example, in order to reduce the occupied area of the thermometer code structure, the thermometer code structure is divided into two segments: that is, the 8-bit thermometer code type structure in the 10-8 segment structure can also be divided into two segments of 2-6, and the two segments are connected by a bridge resistance. Thus, the originally required 255 thermometer codes are reduced to 3+63=66 thermometer codes after the further segmentation, greatly reducing the occupied area. Figure 6 The digital-to-analog converter structure provided by the embodiment of the present application is determined by the method in the above embodiment.

[0112] In an embodiment, the digital-to-analog converter structure includes: a combined resistance segment.

[0113] In the combined resistance segment, a higher weight bit adopts a thermometer code type structure, and a lower weight bit adopts a binary code type structure. The combined resistance segment combines the advantages of the thermometer type structure and the binary code type structure, and can achieve a compromise between area and precision.

[0114] In the higher weight bit, a part of resistance pins in each region is connected to a voltage, and another part of resistance pins in each region is grounded.

[0115] Optionally, the thermometer code type structure comprises two thermometer code type sub-structures, and the two thermometer code type sub-structures are connected through a bridge resistance.

[0116] In the implementation process, the digital-to-analog converter is set by adopting the combined resistance segmentation resistance structure. Since the combined resistance segmentation combines the advantages of the thermometer type structure and the binary coding type structure, the area and the precision are compromised, the volume of the digital-to-analog converter is reduced, and the precision of the digital-to-analog converter is improved.

[0117] In a possible implementation manner, as shown in Figure 7 The digital-to-analog converter structure further comprises a PMOS transistor and an NMOS transistor.

[0118] The gate of the PMOS transistor and the gate of the NMOS transistor are connected to two R-2R digital-to-analog converter biases respectively; the PMOS transistor and the NMOS transistor constitute a complementary pass gate switch; the complementary pass gate switch is connected to an on-resistance; and the R-2R digital-to-analog converter bias is connected to the input of a resistance pin.

[0119] In an embodiment, the PMOS transistor is a W / L=8μm / 60nm PMOS transistor, and the NMOS transistor is a W / L=4μm / 60nm NMOS transistor.

[0120] The gate of the PMOS and the gate of the NMOS respectively comprise two 10bit R-2R digital-to-analog converter biases.

[0121] The R-2R digital-to-analog converter bias is configured to adjust the on-resistance, and the on-resistance is configured to compensate for the non-linear change of the corresponding resistance pin.

[0122] For example, if the digital-to-analog converter is an 8-bit digital-to-analog converter, the full output range of the 8-bit digital-to-analog converter can be divided into 64 equally spaced regions by H<62:0>, and in each region, i (i=0, 1, …, 63) resistance pins are connected to an analog voltage, and (63-i) resistance pins are connected to ground. By controlling the output voltage of the two 10-bit bias digital-to-analog converters, the on-resistance of the pass gate switch can be adjusted, thereby compensating for the non-linear change of the resistance pin, so that the non-linear change of the sum of the switch resistance and the resistance value of the resistance pin in the output voltage range of the digital-to-analog converter is reduced.

[0123] As shown in Figure 8 , Figure 8 The resistance of the PMOS and the NMOS is shown to change with HP<9:0> and HN<9:0>: the adjustable range of the transistor resistance exceeds the resistance non-linear change range shown in Figure 3 , that is, the resistance non-linear change at 4K can be compensated and calibrated.

[0124] The calibration of the resistance nonlinearity is shown as follows: Figure 9 Taking the resistance pin H<0> as an example, the sum of the resistance value of the resistance pin and the switch resistance is RH<0>, the red line represents the nonlinear change of RH<0> before calibration, the black line represents the ideal case without considering the resistance nonlinearity, and the green line represents the change of RH<0> after the nonlinear calibration of the 64 regions. It can be seen that the nonlinear change is greatly reduced after calibration, that is, the calibration is effective. In addition, the change amplitude of the front segment of the green line is slightly large because the resistance of the transistor changes exponentially with the gate voltage.

[0125] Similarly, the same transmission gate switch can be added after the thermometer type structure resistance pin of the M<2:0> segment, and the switch resistance is adjusted by another two 10bit R-2R digital-to-analog converters (corresponding to MP<9:0> and MN<9:0>). In this way, each of the 64 regions can be further divided into four equally spaced sub-regions, which can further reduce the residual nonlinear change in each region. In addition, the resistance nonlinear change of the B<9:0> segment can be compensated and calibrated by the fine calibration bits L<2:0>.

[0126] Exemplarily, as shown in Figure 10 , the linear simulation results of the 18bit digital-to-analog converter after the OEM calibration and the resistance nonlinearity calibration are shown. Figure 10 It can be seen that the INL is less than 1LSB after the calibration of the resistance mismatch and the nonlinearity, which can meet the design requirements of high precision.

[0127] In the above implementation process, the complementary transmission gate switch composed of PMOS transistors and NMOS transistors is designed, and the on-off switch is connected, and then the nonlinear change of the resistance pin is compensated by the on-off switch, so that the nonlinear change of the digital-to-analog converter can be reduced.

[0128] In a possible implementation, the structure of the digital-to-analog converter is an 18bit digital-to-analog converter structure.

[0129] Among them, the combined resistance segmentation is a 10bit-2bit-6bit segmentation structure.

[0130] The low 10bit here is an R-2R structure, and the middle 2bit and the high 6bit are both thermometer code sub-structures.

[0131] It can be understood that if the digital-to-analog converter is an 18-bit structure, the combined resistance segment can be 16-2, 14-4, 12-6, 10-8. Among them, 16-2 segment needs 3 thermometer codes, 14-4 segment needs 15 thermometer codes, 12-6 segment needs 63 thermometer codes, and 10-8 segment needs 255 thermometer codes. It can be seen that the area of 10-8 segment is too large compared with the area of 12-6 segment. In this case, the 10-8 segment can be further segmented to obtain 2 2-6 segments, and the structure after further segmentation only needs 3+63=66 thermometer codes. The structure originally needing 255 thermometer codes is reduced to only need 66 thermometer codes, realizing a large reduction in area.

[0132] In the above implementation process, for the 18-bit digital-to-analog converter structure, the combined resistance segment is designed as a 10-bit-2-bit-6-bit segment structure, which can greatly reduce the area occupied by the combined resistance segment.

[0133] In a possible implementation, the digital-to-analog converter further includes a calibration bit.

[0134] The calibration bit is arranged on the side away from the middle bit 2 bit of the low bit 10 bit.

[0135] The calibration bit here is configured to reserve a calibration space of the low bit 10 bit.

[0136] Optionally, the calibration bit can include one or more, and the number of calibration bits can be selected according to actual conditions.

[0137] Exemplarily, as shown in the figure, the calibration bit is three L<2:0> segments. Figure 6

[0138] In the above implementation process, the calibration bit is arranged on the side away from the higher weight bit of the lower weight bit, which can reserve a calibration space for the lower weight bit, and when the lower weight bit needs to be calibrated, the calibration bit can be used for calibration, improving the calibration flexibility.

[0139] Based on the same application concept, the present application embodiment also provides a digital-to-analog converter structure determination device corresponding to the digital-to-analog converter structure determination method. Since the principle of the device in the present application embodiment solves the problem similar to the above-mentioned digital-to-analog converter structure determination method embodiment, the implementation of the device in the present embodiment can be referred to the description of the above-mentioned method embodiments, and the repeated parts will not be repeated.

[0140] Please refer to Figure 11 ​FIG. 1 is a schematic diagram of a functional module of a digital-to-analog converter structure determination apparatus provided by an embodiment of the present application. Each module in the digital-to-analog converter structure determination apparatus in this embodiment is configured to perform each step in the method embodiments described above. The digital-to-analog converter structure determination apparatus comprises a building module 301, a first calibration module 302, a simulation module 303, a second calibration module 304, and a determination module 305. The building module 301 is configured to build a combined resistance segment if the resistance simulation result does not satisfy a preset condition. The building module 301 is configured to build a combined resistance segment if the resistance simulation result does not satisfy a preset condition.

[0141] The first calibration module 302 is configured to perform random mismatch calibration on the combined resistance segment by directional element matching.

[0142] The simulation module 303 is configured to perform resistance simulation on the combined resistance segment if the random mismatch calibration reaches a set calibration condition.

[0143] The second calibration module 304 is configured to perform resistance nonlinearity calibration on the combined resistance segment if the simulation result of the resistance simulation does not satisfy the preset condition.

[0144] The determination module 305 is configured to determine a digital-to-analog converter structure by the combined resistance segment after resistance nonlinearity calibration.

[0145] In one possible implementation, the first calibration module 302 is further configured to: sort resistance pins of all thermometer type structures in the higher weight bits according to resistance values; pair two resistance pins symmetrically distributed in the resistance pins sorted according to resistance values to obtain a folded higher weight bit; and repeat from the step of sorting resistance pins of all thermometer type structures in the folded higher weight bit according to resistance values until an iteration termination condition is reached to obtain a completely folded higher weight bit; wherein the completely folded higher weight bit is a binary code type structure.

[0146] In one possible implementation, the digital-to-analog converter structure determination apparatus further comprises a setting module configured to: build a calibration bit; and set the calibration bit on a side of the lower weight bit away from the higher weight bit; wherein the calibration bit is configured to reserve a calibration space of the lower weight bit.

[0147] In one possible implementation, the second calibration module 304 is specifically configured to: determine a conduction resistance that needs to be adjusted according to a relationship between an output voltage of the combined resistance segment and a preset voltage; wherein the conduction resistance is connected to the complementary transmission gate switch; and adjust the conduction resistance by controlling a bias of the R-2R digital-to-analog converter; wherein the conduction resistance is configured to compensate for nonlinearity of a corresponding resistance pin.

[0148] In a possible implementation, the building module 301 is specifically configured to: build multiple combined resistance segments according to a digital-to-analog converter; wherein a higher weight bit in each combined resistance segment adopts a thermometer code type structure, and a lower weight bit in each combined resistance segment adopts a binary code type structure; determine a main combined resistance segment according to the precision of the binary code type structure in each combined resistance segment; and configure the main combined resistance segment to construct the digital-to-analog converter. In a possible implementation, the first calibration module 302 is specifically configured to: perform random mismatch calibration on the main combined resistance segment by directional element matching.

[0149] In a possible implementation, the digital-to-analog converter structure determination apparatus further includes a segmenting module configured to determine whether the main combined resistance segment needs to be further segmented according to the occupied area of the thermometer code type structure of the main combined resistance segment; and further segment the thermometer code type structure of the main combined resistance segment in a case where it is determined that the main combined resistance segment needs to be further segmented.

[0150] In addition, the embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is run by a processor, the steps of the digital-to-analog converter structure determination method described in the method embodiment are executed.

[0151] The computer program product of the digital-to-analog converter structure determination method provided by the embodiment of the present application includes a computer readable storage medium storing program codes. The instructions included in the program codes can be used to execute the steps of the digital-to-analog converter structure determination method described in the method embodiment. For details, refer to the method embodiment described above, which will not be described here again.

[0152] It should be understood that all the functional units in the embodiments of the present application can be integrated into one processing unit, or each can exist alone, or two or more can be integrated into one function unit.

[0153] In addition, each functional unit in the embodiments of the present application can be integrated together to form a separate part, or each unit can exist alone, or two or more units can be integrated to form a separate part.

[0154] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes. It should be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the processes, methods, articles or devices that include the elements. The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0155] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

Claims

1. A method for determining the structure of a digital-to-analog converter, characterized in that, include: When the resistance simulation results do not meet the preset conditions, a combined resistor segmentation is constructed. Random mismatch calibration is performed on the combined resistor segments by directional element matching; When the random mismatch calibration meets the set calibration conditions, the combined resistor is segmented for resistance simulation. If the simulation results of the resistance simulation do not meet the preset conditions, the combined resistor is segmented and nonlinear resistance calibration is performed. The structure of the digital-to-analog converter is determined by a combination of resistor segments with nonlinear resistor calibration.

2. The method according to claim 1, characterized in that, in, The combined resistor segmentation includes: a higher weight bit and a lower weight bit; The step of performing random mismatch calibration on the combined resistor segments through directional element matching includes: Sort all thermometer-type resistor pins in the higher weighted position according to their resistance values; Pair two symmetrically distributed resistor pins from the resistor pins after sorting by resistance value to obtain the higher weighted pin after folding. The process begins by sorting all the resistor pins of the thermometer-type structure in the higher weighted bits after folding according to their resistance values, and repeats until the iteration termination condition is met, resulting in a fully folded higher weighted bit. Among them, the higher weight bits that are fully folded form a binary code structure.

3. The method according to claim 2, characterized in that, The method further includes: Construct calibration bits; The calibration bit is set on the side of the lower weight bit that is away from the higher weight bit; The calibration bit is configured to reserve calibration space for the lower weight.

4. The method according to claim 2, characterized in that, in, In each region of the higher weight bit, a portion of the resistor pins are connected to the voltage, and another portion of the resistor pins in each region are grounded; the resistor pins are connected to PMOS transistors and NMOS transistors, and the gates of the PMOS transistors and the NMOS transistors are respectively connected to two R-2R digital-to-analog converter biases; the PMOS transistors and NMOS transistors form a complementary transmission gate switch; The nonlinear calibration of the combined resistor segments includes: Based on the relationship between the output voltage of the combined resistor segment and the preset voltage, the on-resistance to be adjusted is determined; wherein, the on-resistance is connected to the complementary transmission gate switch; The on-resistance is adjusted by controlling the bias of the R-2R digital-to-analog converter; The on-resistance configuration bit compensates for nonlinear changes in the corresponding resistor pin.

5. The method according to any one of claims 1-4, characterized in that, The method for constructing a combined resistor segmentation when the resistance simulation results do not meet the preset conditions includes: Multiple combined resistor segments are constructed based on the digital-to-analog converter; wherein, the higher weight bits in each combined resistor segment adopt a thermometer code structure, and the lower weight bits in each combined resistor segment adopt a binary code structure. The main combined resistor segment is determined based on the precision of the binary encoding structure in each combined resistor segment; the main combined resistor segment is configured to construct the digital-to-analog converter; The step of performing random mismatch calibration on the combined resistor segments through directional element matching includes: The main body combined resistor segment is randomly mismatched and calibrated by directional element matching.

6. The method according to claim 5, characterized in that, Before performing random mismatch calibration on the combined resistor segments through directional element matching, the method further includes: The area occupied by the thermometer-type structure of the main body combined resistor segment is used to determine whether the main body combined resistor segment needs to be further segmented; If it is determined that the main body combined resistor segment needs to be further segmented, the thermometer code structure of the main body combined resistor segment is further segmented.

7. A digital-to-analog converter structure, characterized in that, The digital-to-analog converter structure, determined by any one of claims 1-6, includes: a combined resistor segmentation; The higher weight bits in the combined resistor segment adopt a thermometer code structure, and the lower weight bits in the combined resistor segment adopt a binary code structure. The thermometer code structure includes two thermometer code substructures, which are connected by a bridging resistor.

8. The digital-to-analog converter structure according to claim 7, characterized in that, In each region of the higher weight bit, a portion of the resistor pins are connected to the voltage, and another portion of the resistor pins in each region are grounded. The digital-to-analog converter structure also includes: PMOS transistors and NMOS transistors; The gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converters for biasing; the PMOS transistor and the NMOS transistor form a complementary transmission gate switch; The complementary transmission gate switch is connected to an on-resistance; The R-2R digital-to-analog converter is biased to the input of the resistor pin; The R-2R digital-to-analog converter bias configuration is used to adjust the on-resistance, and the on-resistance configuration bit compensates for the nonlinear changes of the corresponding resistor pin.

9. The digital-to-analog converter structure according to claim 7, characterized in that, The digital-to-analog converter structure is an 18-bit digital-to-analog converter structure; The combined resistor segmentation is a 10-bit-2-bit-6-bit segmentation structure; The lower 10 bits are of an R-2R structure, while the middle 2 bits and the upper 6 bits are both thermometer code structures.

10. The digital-to-analog converter structure according to claim 9, characterized in that, Also includes: Calibration bit; The calibration bit is located on the side of the lower 10 bits that is far from the middle 2 bits; The calibration bit is configured to reserve 10 bits of calibration space in the lower byte.

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