Multistage amplifier, analog-to-digital converter and electronic equipment

Abstract

The invention relates to a multi-stage amplifier, an analog-to-digital converter and electronic equipment, and the multi-stage amplifier comprises a first-stage amplifier which comprises a first step-down charge pump and is used for carrying out the first-stage amplification of a to-be-amplified signal and outputting a first amplified signal; the second-stage amplifier comprises a second step-down charge pump and a second amplifier and is used for carrying out second-stage amplification on the first amplification signal and outputting a second amplification signal; and the third-stage amplifier comprises a boost charge pump and a third amplifier and is used for carrying out third-stage amplification on the second amplification signal and outputting a third amplification signal. According to the multi-stage amplifier, low-power-consumption, high-gain and large-swing output can be achieved in the multi-stage amplifier, voltage rising and falling adjustment is achieved among different amplification stages through a multi-stage dynamic power supply framework, and therefore balance among gain, speed and power consumption is achieved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a multi-stage amplifier, an analog-to-digital converter, and an electronic device. Background Technology

[0002] Discrete-time amplifiers typically operate in two non-overlapping clock phases: a reset phase and an amplify phase, to achieve time-division control, dynamic biasing, and energy optimization.

[0003] Traditional discrete-time amplifiers are mostly implemented based on closed-loop capacitive feedback structures. Their forward gain amplifiers typically employ classic topologies, such as telescopic cascode amplifiers and folded cascode amplifiers. These structures exhibit stable performance in terms of accuracy, linearity, and common-mode control, and are therefore widely used in industry and academia. However, as CMOS process nodes scale down to lower voltages, traditional amplifiers are gradually showing bottlenecks in terms of gain and power consumption.

[0004] To address the higher energy efficiency requirements of amplifiers in low-voltage, low-power systems, researchers have proposed several novel amplifier architectures for discrete-time systems in recent years. Among them, the following two structures are representative:

[0005] A floating inverter amplifier (FIA) is a low-power amplification structure built based on inverter units (such as...). Figure 1 (As shown). The basic idea is to establish a bias power supply for the inverter in the reset phase by pre-charging it with a floating capacitor, and then disconnect the power rail in the amplification phase, allowing the floating capacitor to drive the inverter and thus provide amplification gain. This structure features a very simple circuit form, double current reuse, good power supply rejection and common-mode rejection, making it suitable for low-frequency, light-load, and energy-sensitive applications. However, its fixed and difficult-to-boost supply voltage limits its output swing and achievable gain, restricting its application in high-precision, high-dynamic-range systems.

[0006] A ring amplifier (Ring Amp) is typically constructed by cascading three inverters to form a closed-loop amplification structure (e.g., Figure 2As shown in the figure, it exhibits typical three-stage dominant pole compensation characteristics. In this structure, the first two stages operate in a high-bandwidth state, with the dominant pole located at the output node, enabling the system to maintain good stability while maintaining high speed. Ring amplifiers can provide a large output swing and fast response, and are widely used in high-speed, high-resolution analog-to-digital converters. Their disadvantages are that, to maintain output common-mode stability, a dedicated common-mode control path is usually required, which limits further reduction of the supply voltage; in addition, the first and second stages of the amplifier typically require a large current, resulting in high overall power consumption for the ring amplifier, which is not conducive to low-power design.

[0007] Meanwhile, due to the low supply voltage limitation, it is difficult to use a cascode structure with higher gain in the output stage, which limits the gain of the ring amplifier and thus affects the linearity of the system.

[0008] In summary, the current development of discrete-time amplifiers shows a trend towards balancing high performance and low power consumption. How to design a discrete-time amplifier structure that combines high gain, large swing, low power consumption, and good stability has become a key issue of concern in the field. Summary of the Invention

[0009] In view of this, the present disclosure proposes a multi-stage amplifier, said multi-stage amplifier comprising:

[0010] The first-stage amplifier includes a first buck charge pump and a first amplifier. The first buck charge pump is used to step down the power supply voltage and use the stepped-down power supply voltage to power the first amplifier. The first amplifier is used to amplify the signal to be amplified in the first stage and output a first amplified signal.

[0011] The second-stage amplifier includes a second buck charge pump and a second amplifier. The second buck charge pump is used to step down the power supply voltage and use the stepped-down power supply voltage to power the second amplifier. The second amplifier is used to amplify the first amplified signal in the second stage and output a second amplified signal.

[0012] The third-stage amplifier includes a boost charge pump and a third amplifier. The boost charge pump is used to boost the power supply voltage and use the boosted power supply voltage to power the third amplifier. The third amplifier is used to amplify the second amplified signal in the third stage and output the third amplified signal.

[0013] In one possible implementation, both the first step-down charge pump and the second step-down charge pump are used to connect to a first power supply voltage and a second power supply voltage, and output a third power supply voltage and a fourth power supply voltage. The first power supply voltage is greater than the second power supply voltage, the third power supply voltage is greater than the fourth power supply voltage, and the difference between the third power supply voltage and the fourth power supply voltage is less than the difference between the first power supply voltage and the second power supply voltage.

[0014] In one possible implementation, both the first buck charge pump and the second buck charge pump include a first buck switch, a second buck switch, a third buck switch, a fourth buck switch, a fifth buck switch, a sixth buck switch, a seventh buck switch, a first buck capacitor, and a second buck capacitor, wherein...

[0015] The first terminal of the first step-down switch is used to connect to the first power supply voltage.

[0016] The second terminal of the first step-down switch is connected to the first terminal of the first step-down capacitor and the first terminal of the second step-down switch.

[0017] The second terminal of the first step-down capacitor is connected to the first terminal of the fourth step-down switch and the first terminal of the fifth step-down switch.

[0018] The second terminal of the fourth step-down switch is connected to the first terminal of the second step-down capacitor and the first terminal of the third step-down switch.

[0019] The second terminal of the second step-down capacitor is connected to the first terminal of the sixth step-down switch and the first terminal of the seventh step-down switch.

[0020] The second terminal of the seventh step-down switch is connected to the second power supply voltage.

[0021] The common node of the second terminal of the second step-down switch and the second terminal of the third step-down switch is used to output the third power supply voltage.

[0022] The common node of the second terminal of the fifth step-down switch and the second terminal of the sixth step-down switch is used to output the fourth power supply voltage.

[0023] In one possible implementation, the first, fourth, and seventh step-down switches are controlled by a first switch control signal, while the second, third, fifth, and sixth step-down switches are controlled by a second switch control signal.

[0024] The first switch control signal and the second switch control signal are both square wave signals with opposite phases.

[0025] In one possible implementation, both the first amplifier and the second amplifier include a first transistor, a second transistor, a first level shifter, and a second level shifter, wherein...

[0026] The source of the first transistor and the source of the second transistor are used to connect to the stepped-down power supply voltage.

[0027] The drain of the first transistor is connected to the drain of the second transistor.

[0028] The gate of the first transistor is connected to the output of the first level converter.

[0029] The gate of the second transistor is connected to the output of the second level converter.

[0030] The input terminals of the first level converter and the second level converter are used to receive the signal to be amplified. The first level converter and the second level converter are used to perform level conversion on the signal to be amplified. The converted signal to be amplified is matched with the stepped-down power supply voltage.

[0031] In one possible implementation, the boost charge pump includes a first boost switch, a second boost switch, a third boost switch, a fourth boost switch, a fifth boost switch, a sixth boost switch, a seventh boost switch, a first boost capacitor, and a second boost capacitor, wherein...

[0032] The first terminal of the first boost switch and the first terminal of the second boost switch are used to receive a first power supply voltage, and the first terminals of the fifth boost switch and the sixth boost switch are used to receive a second power supply voltage.

[0033] The second terminal of the first boost switch is connected to the second terminal of the fourth boost switch and the first terminal of the second boost capacitor.

[0034] The second terminal of the second boost switch is connected to the first terminal of the third boost switch and the first terminal of the first boost capacitor.

[0035] The second terminal of the first boost capacitor is connected to the first terminal of the fourth boost switch and the second terminal of the fifth boost switch.

[0036] The second terminal of the second boost capacitor is connected to the second terminal of the sixth boost switch and the first terminal of the seventh boost switch.

[0037] The second terminal of the third boost switch and the second terminal of the seventh boost switch are respectively used to output the boosted fifth power supply voltage and the sixth power supply voltage.

[0038] The difference between the fifth power supply voltage and the sixth power supply voltage is greater than the difference between the first power supply voltage and the second power supply voltage.

[0039] In one possible implementation, the third amplifier includes a first upper-bridge transistor, a second upper-bridge transistor, a first lower-bridge transistor, a second lower-bridge transistor, and four level shifters, wherein...

[0040] The drain of the first upper-bridge transistor is connected to the source of the second upper-bridge transistor.

[0041] The source of the first upper-bridge transistor and the source of the second lower-bridge transistor are connected to the output terminal of the boost charge pump to receive the boosted power supply voltage.

[0042] The common node of the drain of the second upper-bridge transistor and the drain of the first lower-bridge transistor is used to output the third amplified signal.

[0043] The source of the first lower-bridge transistor is connected to the drain of the second lower-bridge transistor.

[0044] The gates of the first upper-bridge transistor, the second upper-bridge transistor, the first lower-bridge transistor, and the second lower-bridge transistor are all connected to the output terminals of their respective level shifters.

[0045] The input terminals of each level converter are used to receive the second amplified signal. Each level converter is used to perform level conversion on the second amplified signal, and the converted second amplified signal is matched with the boosted power supply voltage.

[0046] In one possible implementation, the first boost switch, the second boost switch, the fifth boost switch, and the sixth boost switch are controlled by a first switch control signal, and the third boost switch, the fourth boost switch, and the seventh boost switch are controlled by a second switch control signal.

[0047] The first switch control signal and the second switch control signal are both square wave signals with opposite phases.

[0048] According to another aspect of this disclosure, an analog-to-digital converter is provided, the analog-to-digital converter including the aforementioned multi-stage amplifier.

[0049] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned analog-to-digital converter.

[0050] This disclosure embodiment introduces a buck charge pump to provide buck power to the first-stage amplifier and the second-stage amplifier to reduce power consumption, and uses a boost charge pump to provide boost power to the third-stage amplifier to increase swing and gain. This can achieve low power consumption, high gain, and large swing output in a multi-stage amplifier. Furthermore, through a multi-stage dynamic power supply architecture, voltage boosting and scaling can be achieved between different amplification stages, thereby achieving a balance between gain, speed, and power consumption.

[0051] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0052] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0053] Figure 1 A schematic diagram of the structure of a floating inverting amplifier in related technologies is shown.

[0054] Figure 2 A schematic diagram of the structure of a ring amplifier in the related technology is shown.

[0055] Figure 3 A schematic diagram of a multistage amplifier according to an embodiment of the present disclosure is shown.

[0056] Figure 4 A schematic diagram of a multistage amplifier according to an embodiment of the present disclosure is shown.

[0057] Figure 5 A schematic diagram of the switch control signal waveform according to an embodiment of the present disclosure is shown.

[0058] Figure 6 A schematic diagram of the supply voltage and output waveform of the third amplifier in a multi-stage amplifier according to an embodiment of the present disclosure is shown.

[0059] Figure 7a A schematic diagram of a closed-loop bias circuit is shown. Figure 7b A schematic diagram of an open-loop bias circuit is shown. Detailed Implementation

[0060] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0061] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0062] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0063] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are used only to distinguish one element / operation from another. Therefore, without departing from the teachings of the conception of embodiments of this disclosure, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0064] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0065] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0066] As mentioned earlier, existing ring amplifiers and floating inverting amplifiers have the following main shortcomings:

[0067] Ring amplifiers: high power consumption, low gain. Ring amplifiers employ a three-stage dominant pole compensation structure, offering good speed and linearity. However, to maintain common-mode stability, additional common-mode feedback transistors are typically required. This makes it difficult to stack fewer than four transistors, hindering ring amplifier operation at low supply voltages. Furthermore, the first and second stages of the amplifier typically require significant current, resulting in high overall power consumption and hindering low-power designs. In the output stage, supply voltage limitations prevent the use of higher-gain cascode structures, limiting the overall gain of the ring amplifier and consequently affecting system linearity.

[0068] To reduce the power consumption and increase the gain of a ring amplifier, the ideal strategy is to use tiered power supply between each amplification stage, that is, to provide different supply voltages to different amplification stages to optimize energy efficiency.

[0069] However, most existing designs still employ a uniform power supply strategy, lacking cross-stage power regulation capabilities. In practical applications, preamplifiers typically have lower requirements for linearity and drive capability, making it difficult to balance the low power consumption requirements of the preamplifier with the drive capability requirements of the output stage, thus limiting further improvements in overall system energy efficiency.

[0070] Floating inverting amplifiers: low swing, low gain. The core structure of a floating inverting amplifier consists of a floating capacitor pre-charged inverter, which greatly reduces static power consumption. However, due to the fixed supply voltage, its output swing is very limited. Furthermore, floating inverting amplifiers are mostly single-stage or two-stage structures, which suppresses both driving capability and gain level, making them unsuitable for high-precision, large-swing applications.

[0071] In summary, the ring amplifier and floating inverting amplifier architectures have advantages in high-performance amplification and extremely low power consumption, respectively. However, there are still fundamental contradictions: "high-performance structures are difficult to compress power consumption" and "low power consumption is difficult to achieve in the same way as high gain and high swing".

[0072] In view of this, the present disclosure proposes a multi-stage amplifier that reduces power consumption by introducing a buck charge pump to supply power to the first and second stage amplifiers, and boosts power supply to the third stage amplifier by using a boost charge pump to increase swing and gain. This can achieve low power consumption, high gain, and large swing output in the multi-stage amplifier. Furthermore, through the multi-stage dynamic power supply architecture, voltage boosting and scaling can be achieved between different amplification stages, thereby achieving a balance between gain, speed, and power consumption.

[0073] Please see Figure 3 , Figure 3 A schematic diagram of a multistage amplifier according to an embodiment of the present disclosure is shown.

[0074] like Figure 3 As shown, the multi-stage amplifier includes:

[0075] The first-stage amplifier 10 includes a first buck charge pump 110 and a first amplifier 120. The first buck charge pump 110 is used to regulate the power supply voltage (e.g., V). DD / V SS The voltage is stepped down, and the stepped-down power supply voltage (V) is used. DDL / V SSH The first amplifier 120 is powered by the first amplifier 120, which is used to amplify the signal V to be amplified. IN Perform the first stage of amplification and output the first amplified signal V. OUT1 ;

[0076] The second-stage amplifier 20 includes a second buck charge pump 210 and a second amplifier 220. The second buck charge pump 210 is used to regulate the power supply voltage (e.g., V).DD / V SS The voltage is stepped down, and the stepped-down power supply voltage (V) is used. DDL / V SSH The second amplifier 220 is powered by the first amplified signal V. OUT1 Perform a second stage of amplification to output the second amplified signal V. OUT2 ;

[0077] The third-stage amplifier 30 includes a boost charge pump 310 and a third amplifier 320. The boost charge pump 310 is used to regulate the power supply voltage (e.g., V). DD / V SS ) boost the voltage and utilize the boosted power supply voltage (V DDL / V SSH The third amplifier 320 is powered to amplify the second amplified signal V. OUT2 Perform a third-stage amplification to output the third amplified signal V. OUT3 .

[0078] In one possible implementation, both the first step-down charge pump 110 and the second step-down charge pump 210 are used to connect to the first power supply voltage V. DD Second power supply voltage V SS And output the third power supply voltage V DDL Fourth power supply voltage V SSH The first power supply voltage V DD Greater than the second power supply voltage V SS The third power supply voltage V DDL Greater than the fourth power supply voltage V SSH The third power supply voltage V DDL Fourth power supply voltage V SSH The difference is less than the first power supply voltage V DD Second power supply voltage V SS difference.

[0079] This disclosure does not limit the specific implementation of the first-stage amplifier 10, the second-stage amplifier 20, and the third amplifier 320, nor does it limit the specific implementation of the first buck charge pump 110, the second buck charge pump 210, the first amplifier 120, the second amplifier 220, the boost charge pump 310, and the third amplifier 320. Those skilled in the art can adopt appropriate technical solutions according to actual conditions and needs. Preferred embodiments will be described by way of example below.

[0080] Please see Figure 4 , Figure 4 A schematic diagram of a multistage amplifier according to an embodiment of the present disclosure is shown.

[0081] In one possible implementation, such as Figure 4 As shown, both the first step-down charge pump 110 and the second step-down charge pump 210 may include a first step-down switch S11, a second step-down switch S12, a third step-down switch S13, a fourth step-down switch S14, a fifth step-down switch S15, a sixth step-down switch S16, a seventh step-down switch S17, a first step-down capacitor C11, and a second step-down capacitor C12, wherein...

[0082] The first terminal of the first step-down switch S11 is used to connect to the first power supply voltage V. DD ,

[0083] The second terminal of the first step-down switch S11 is connected to the first terminal of the first step-down capacitor C11 and the first terminal of the second step-down switch S12.

[0084] The second terminal of the first step-down capacitor C11 is connected to the first terminal of the fourth step-down switch S14 and the first terminal of the fifth step-down switch S15.

[0085] The second terminal of the fourth step-down switch S14 is connected to the first terminal of the second step-down capacitor C12 and the first terminal of the third step-down switch S13.

[0086] The second terminal of the second step-down capacitor C12 is connected to the first terminal of the sixth step-down switch S16 and the first terminal of the seventh step-down switch S17.

[0087] The second terminal of the seventh step-down switch S17 is connected to the second power supply voltage V. SS ,

[0088] The common node of the second terminal of the second step-down switch S12 and the second terminal of the third step-down switch S13 is used to output the third power supply voltage V. DDL ,

[0089] The common node of the second terminal of the fifth step-down switch S15 and the second terminal of the sixth step-down switch S16 is used to output the fourth power supply voltage V. SSH .

[0090] This disclosure embodiment relates to the first power supply voltage V. DD Second power supply voltage V SS And output the third power supply voltage V DDL Fourth power supply voltage V SSH The specific size is not limited; those skilled in the art can set it according to actual conditions and needs. First power supply voltage V DD It can be a high level, such as the supply voltage or the second supply voltage V. SSThis can be a low level, such as the ground voltage. For example, the first power supply voltage V. DD Second power supply voltage V SS The voltages are 0.9V and 0V respectively, and the third power supply voltage is V. DDL Fourth power supply voltage V SSH The voltages are 0.675V and 0.225V respectively. These are converted by the step-down charge pump 10, reducing the original first power supply voltage V... DD Second power supply voltage V SS The power supply level is adjusted to be higher than the first power supply voltage V. DD Lower and (For example, adjusting 0.9V / 0V to 0.675V / 0.225V) is equivalent to lowering the high level and raising the low level of the power supply voltage, thus compressing the difference between the high and low levels. This significantly reduces power consumption while maintaining the performance of the first amplifier 120.

[0091] The specific types of the first step-down switch S11, the second step-down switch S12, the third step-down switch S13, the fourth step-down switch S14, the fifth step-down switch S15, the sixth step-down switch S16, and the seventh step-down switch S17 are not limited in this embodiment. Those skilled in the art can select appropriate switches according to actual conditions and needs. For example, the switches include any one of relays, reed switches, silicon controlled rectifiers, switching transistors, electronic bidirectional switches, optocouplers, transistors, etc. The transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). The transistors can be based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.

[0092] Please see Figure 5 , Figure 5 A schematic diagram of the switch control signal waveform according to an embodiment of the present disclosure is shown.

[0093] In one possible implementation, such as Figure 4 and Figure 5 As shown, the first step-down switch S11, the fourth step-down switch S14, and the seventh step-down switch S17 are controlled by the first switch control signal φ1, and the second step-down switch S12, the third step-down switch S13, the fifth step-down switch S15, and the sixth step-down switch S16 are controlled by the second switch control signal φ2. The first switch control signal φ1 and the second switch control signal φ2 are both square wave signals with opposite phases.

[0094] For example, such as Figure 5 As shown, both the first switch control signal φ1 and the second switch control signal φ2 are square wave signals. When the first switch control signal φ1 is high, the second switch control signal φ2 is low; when the first switch control signal φ1 is low, the second switch control signal φ2 is high.

[0095] This disclosure does not limit the generation method of the first switch control signal φ1 and the second switch control signal φ2. Those skilled in the art can implement them using relevant technologies according to actual conditions and needs. The first switch control signal φ1 and the second switch control signal φ2 can be received from an external controller. Of course, the controller can also be located within the amplifier 20. This disclosure does not limit the specific implementation method of the amplifier 20. Those skilled in the art can implement it using appropriate technical means according to actual conditions and needs. In one example, the controller can include, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor can include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0096] For example, such as Figure 4 and Figure 5 As shown, when the first switch control signal φ1 is high, the second switch control signal φ2 is low. At this time, the first step-down switch S11, the fourth step-down switch S14, and the seventh step-down switch S17 are all turned on, while the second step-down switch S12, the third step-down switch S13, the fifth step-down switch S15, and the sixth step-down switch S16 are all turned off. The first step-down capacitor C11 and the second step-down capacitor C12 are connected in series. The voltages at the first and second terminals of the first step-down capacitor C11 are V and V, respectively. DD and V DD / 2, the voltages at the first and second terminals of the second step-down capacitor C12 are respectively V DD / 2 and V SSFor example, the first step-down capacitor C11 and the second step-down capacitor C12 have the same capacitance.

[0097] For example, such as Figure 4 and Figure 5 As shown, when the second switch control signal φ2 is high, the first switch control signal φ1 is low. At this time, the first step-down switch S11, the fourth step-down switch S14, and the seventh step-down switch S17 are all open, while the second step-down switch S12, the third step-down switch S13, the fifth step-down switch S15, and the sixth step-down switch S16 are all closed. The first step-down capacitor C11 and the second step-down capacitor C12 are connected in parallel, and the charge is redistributed between them. When a steady state is reached, the voltages across the first step-down capacitor C11 and the second step-down capacitor C12 are the same. Specifically, the voltages at the first terminals of both the first and second step-down capacitors are equal. The voltages at the second terminals of the first step-down capacitor C11 and the second step-down capacitor C12 are both... .

[0098] In this embodiment, the first switch control signal φ1 and the second switch control signal φ2 control the conduction state of the first step-down switch S11, the second step-down switch S12, the third step-down switch S13, the fourth step-down switch S14, the fifth step-down switch S15, the sixth step-down switch S16, and the seventh step-down switch S17, so that the charge is redistributed in the first step-down capacitor C11 and the second step-down capacitor C12, thereby reducing the operating voltage of the amplifier 20. This effectively achieves dynamic voltage reduction of the first step-down capacitor C11 and the second step-down capacitor C12, thereby reducing the energy consumption of charging and discharging the power supply capacitor and improving the overall energy efficiency of the system.

[0099] For example, Figure 4 The second step-down charge pump 210 in the second-stage amplifier 20 has the same circuit structure and control method as the first step-down charge pump 110 in the first-stage amplifier 10. For details, please refer to the above description, which will not be repeated here.

[0100] In one possible implementation, such as Figure 4 As shown, both the first amplifier 120 and the second amplifier 220 may include a first transistor Q01, a second transistor Q02, a first level shifter LS1, and a second level shifter LS2, wherein...

[0101] The source of the first transistor Q01 and the source of the second transistor Q02 are used to connect to the stepped-down power supply voltage (V). DDL / V SSH ),

[0102] The drain of the first transistor Q01 is connected to the drain of the second transistor Q02 (for outputting the first amplified signal VOUT1).

[0103] The gate of the first transistor Q01 is connected to the output of the first level converter LS1.

[0104] The gate of the second transistor Q02 is connected to the output of the second level converter LS2.

[0105] The input terminals of the first level converter LS1 and the second level converter LS2 are used to receive the signal V to be amplified. IN The first level converter LS1 and the second level converter LS2 are used to amplify the signal V. IN Level conversion is performed, and the converted signal to be amplified is V. IN It matches the power supply voltage after step-down.

[0106] For example, both the first transistor Q01 and the second transistor Q02 can be PMOS transistors.

[0107] This disclosure does not limit the specific implementation of the level converter. Those skilled in the art can adopt appropriate technical solutions according to actual conditions and needs. For example, the level converter (LS) can be implemented by a shift register resistor and a shift register capacitor. For instance, one end of the shift register resistor serves as the input terminal of the level converter (LS) (connected to a reference voltage V). B The other end of the shift register resistor is connected to one end of the shift register capacitor, and the other end of the shift register capacitor is grounded. Of course, the level shifter (LS) may also include a switch for clock control, or other implementations, which are not limited in this disclosure. For example, the level shifter can be configured by setting a suitable reference voltage V. B To amplify the signal V IN Convert to V B -V IN To achieve the connection with the third power supply voltage V DDL Fourth power supply voltage V SSH Matching (including common-mode level matching, signal swing matching, etc.), for example, can be achieved by switching the signal V to be amplified. IN Connected to the upper plate of the shift register capacitor, the corresponding reference voltage V B Alternatively, it can be connected via a switch. First, in the initial stage, the switch can be turned on to amplify the signal V. IN Connected to the upper plate of the shift register capacitor (at this time, the reference voltage V) B (Not connected), the voltage on the upper plate of the shift register capacitor is charged to V. INThe charge stored on the shift register capacitor is Q1 = C⋅V IN In the second stage, the switch can be controlled to disconnect the signal V to be amplified. IN The path is connected to the upper plate of the shift register capacitor, and the reference voltage V is applied. B Connect the upper plate of the shift register capacitor. The lower plate of the shift register capacitor can be used as the output (output Vin) of LS. Let the new voltage difference be (V B -Vin), then the charge stored on the shift register capacitor is Q2=C⋅(V B -Vin), due to charge conservation, Q1=Q2, we can obtain Vin=V B -V IN .

[0108] Of course, the above description is exemplary, and the specific operation of the level converter in this disclosure is not limited. Those skilled in the art can adopt the corresponding level conversion method according to the specific implementation of the level converter to amplify the signal V. IN Level conversion.

[0109] Wherein, the level-converted signal to be amplified V IN The third power supply voltage V output by the step-down charge pump 10 DDL Fourth power supply voltage V SSH Matching can include common-mode level matching. Common-mode level refers to the DC reference line of an AC signal, used to adjust the DC bias of the signal. For example, a level shifter can adjust the DC bias of the signal to be amplified, such as V. IN The common-mode level changes from the original level (e.g., V) DD / 2) Adjust to the common-mode range of the low-voltage amplifier 20 (e.g., 0~V). DD (A reasonable value within / 2). The amplified signal V after level conversion. IN The third power supply voltage V output by the step-down charge pump 10 DDL Fourth power supply voltage V SSH Matching can also include signal swing matching, where signal swing refers to the maximum range of signal variation (peak-to-peak value, e.g., the original signal swing is the second power supply voltage V). SS ~First power supply voltage V DD A level converter can amplify the signal V. IN The signal swing from the second power supply voltage V SS ~First power supply voltage V DD Compressed to the fourth power supply voltage V SSH ~Third power supply voltage V DDL .

[0110] This embodiment of the disclosure uses a level converter to amplify the signal V. INLevel conversion can be performed to amplify the signal V to be amplified. IN Matching with the operating level of amplifier 20, the converted signal to be amplified V IN Then, amplifier 20 is connected to achieve normal inverting amplification function, which can still maintain good gain and working stability under low voltage power supply conditions.

[0111] For example, such as Figure 4 As shown, the first and second stages are inverters connected in series, using a common differential or pseudo-differential structure, mainly to provide high gain.

[0112] In traditional ring amplifier structures, to meet the circuit's bias and stability requirements, current sources and common-mode feedback transistors are typically introduced. This leads to an increase in the number of transistor stacked layers and places higher demands on the supply voltage. For example, the current source and the common-mode feedback path must each retain the saturation voltage drop of at least one transistor. Therefore, the overall circuit's drain-source voltage stacking requirement means that the supply voltage is typically not less than 4× .

[0113] For example, such as Figure 4 As shown, this embodiment of the disclosure introduces a floating capacitor power supply mechanism, enabling the ring amplifier to operate without a current source and common-mode feedback circuit, thereby significantly reducing the number of transistor stacking layers and allowing the minimum supply voltage to be reduced to approximately 2× .

[0114] Specifically, embodiments of this disclosure employ a charge pump to charge the power rail V DD With V SS Step down to a lower voltage rail and It is used to power the first two stages of the amplifier, which significantly reduces the power consumption of the first two stages.

[0115] However, with the introduction of step-down power supply, the traditional method of directly driving the gate with the input signal in an inverter will face problems: NMOS and PMOS transistors cannot be effectively turned on at the same input level, affecting the normal operation of the circuit.

[0116] To address this issue, this embodiment introduces a level shifter at the input terminal to match the input signal with the operating level of the inverting amplifier. The converted signal is then connected to the gate terminal of the inverter, thereby achieving normal inverting amplification and maintaining good gain and operational stability even under low-voltage power supply conditions.

[0117] In one possible implementation, such as Figure 4As shown, the boost charge pump 310 may include a first boost switch S21, a second boost switch S22, a third boost switch S23, a fourth boost switch S24, a fifth boost switch S25, a sixth boost switch S26, a seventh boost switch S27, a first boost capacitor C21, and a second boost capacitor C22, wherein...

[0118] The first terminal of the first boost switch S21 and the first terminal of the second boost switch S22 are used to receive the first power supply voltage V. DD， The first terminal of the fifth boost switch S25 and the first terminal of the sixth boost switch S26 are used to receive the second power supply voltage V. SS ,

[0119] The second terminal of the first boost switch S21 is connected to the second terminal of the fourth boost switch S24 and the first terminal of the second boost capacitor C22.

[0120] The second terminal of the second boost switch S22 is connected to the first terminal of the third boost switch S23 and the first terminal of the first boost capacitor C21.

[0121] The second terminal of the first boost capacitor C21 is connected to the first terminal of the fourth boost switch S24 and the second terminal of the fifth boost switch S25.

[0122] The second terminal of the second boost capacitor C22 is connected to the second terminal of the sixth boost switch S26 and the first terminal of the seventh boost switch S27.

[0123] The second terminal of the third boost switch S23 and the second terminal of the seventh boost switch S27 are respectively used to output the boosted fifth power supply voltage V. DDH The sixth power supply voltage V SSL ,

[0124] Among them, the fifth power supply voltage V DDH The sixth power supply voltage V SSL The difference is greater than the first power supply voltage V. DD Second power supply voltage V SS difference.

[0125] In one possible implementation, such as Figure 4 , Figure 5 As shown, the first boost switch S21, the second boost switch S22, the fifth boost switch S25, and the sixth boost switch S26 are controlled by the first switch control signal φ1, and the third boost switch S23, the fourth boost switch S24, and the seventh boost switch S27 are controlled by the second switch control signal φ2.

[0126] The first switch control signal φ1 and the second switch control signal φ2 are both square wave signals with opposite phases.

[0127] The specific types of the first boost switch S21, the second boost switch S22, the third boost switch S23, the fourth boost switch S24, the fifth boost switch S25, the sixth boost switch S26, and the seventh boost switch S27 are not limited in this embodiment. Those skilled in the art can select appropriate switches according to actual conditions and needs. For example, the switches include any one of relays, reed switches, silicon controlled rectifiers, switching transistors, electronic bidirectional switches, optocouplers, transistors, etc. The transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). The transistors can be based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.

[0128] For example, such as Figure 4 and Figure 5 As shown, when the first switch control signal φ1 is high, the second switch control signal φ2 is low. At this time, the first boost switch S21, the second boost switch S22, the fifth boost switch S25, and the sixth boost switch S26 are all on, while the third boost switch S23, the fourth boost switch S24, and the seventh boost switch S27 are all off. The voltages across the first boost capacitor C21 and the second boost capacitor C22 are VDD and VSS, respectively. For example, the capacitances of the first boost capacitor C21 and the second boost capacitor C22 are equal. In this case, for example, if VSS = 0, the voltage difference between the first boost capacitor C21 and the second boost capacitor C22 is VDD.

[0129] For example, such as Figure 4 and Figure 5 As shown, when the second switch control signal φ2 is high, the first switch control signal φ1 is low. At this time, the first boost switch S21, the second boost switch S22, the fifth boost switch S25, and the sixth boost switch S26 are all open, while the third boost switch S23, the fourth boost switch S24, and the seventh boost switch S27 are all closed. The first boost capacitor C21 and the second boost capacitor C22 are connected in series, and the charge is redistributed between them. When a stable state is reached, the voltage across the first terminal of the first boost capacitor C21 is... The voltage at the second terminal of the second boost capacitor C22 is In this configuration, the first boost capacitor C21 and the second boost capacitor C22 are connected in series, resulting in a total voltage of 2 × VDD. The common-mode level of the output voltage is determined by the level during the reset phase. If the reset phase level is set to VCM (i.e., 0.5VDD), then the output voltage will have a total of 2VDD around 0.5VDD, with the voltage increasing upwards. Downwards is .

[0130] For example, such as Figure 4 As shown, the third-stage amplifier 30 can be a Cascode inverter, used to directly drive the subsequent sampling capacitor or subsequent circuitry.

[0131] Those skilled in the art understand that, under normal voltage supply, output stage design faces a contradiction between Cascode (common source, common gate) structure and large output swing. Using a Cascode stacking structure to improve gain will significantly compress the voltage swing of the output node; however, to obtain a larger output swing, a Cascode structure cannot be used, and only a common source structure can be used, thus limiting the improvement of gain.

[0132] For example, such as Figure 4 As shown, this embodiment of the disclosure introduces a charge pump boost circuit, as shown in the boost charge pump 310, to boost the power rail V. DD With V SS Extend to higher voltage rails and It is used to power the third amplifier 320.

[0133] Please see Figure 6 , Figure 6 A schematic diagram of the supply voltage and output waveform of the third amplifier 320 in a multi-stage amplifier according to an embodiment of the present disclosure is shown.

[0134] For example, Figure 6 In the diagram, VOP and VON represent the positive differential signal and negative differential signal of the amplified signal output by the third amplifier 320, respectively (differential signal is used as an example here, but it can also be a single-ended signal, which is not limited in this embodiment). VSP3 and VSN3 represent the positive power supply voltage and the negative power supply voltage after boosting, respectively.

[0135] For example, such as Figure 6 As shown, during the power supply setup phase (t≈0): VSP3 rapidly boosts and VSN3 rapidly pulls down, establishing a wide voltage rail for the third-stage amplifier circuit; VOP / VON synchronous response demonstrates the driving capability of power rail changes on the output (the charge pump rapidly supplies power to support the slew rate).

[0136] For example, such as Figure 6 As shown, during the stable operating phase (0.5~1.5ns): VSP3 / VSN3 remains stable, and VOP / VON outputs large-amplitude pulses, verifying the improvement of output swing and speed by the wide power supply rail.

[0137] As can be seen, the boost power supply mechanism provided by the boost charge pump 310 in this embodiment allows the output stage to obtain a larger voltage margin, thereby overcoming the limitation on the number of transistor stacking layers under normal voltage power supply conditions and enabling the third stage to adopt a Cascode structure with higher gain. At the same time, the increased supply voltage helps to improve the slew rate of this stage, significantly enhancing the speed performance and linearity of the amplifier when driving the subsequent sampling capacitor or subsequent circuits.

[0138] In one possible implementation, such as Figure 4 As shown, the third amplifier 320 may include a first upper-bridge transistor Q11, a second upper-bridge transistor Q12, a first lower-bridge transistor Q21, a second lower-bridge transistor Q22, and four level shifters (LS), wherein,

[0139] The drain of the first upper-bridge transistor Q11 is connected to the source of the second upper-bridge transistor Q12.

[0140] The source of the first upper-bridge transistor Q11 and the source of the second lower-bridge transistor Q22 are connected to the output terminal of the boost charge pump 310 to receive the boosted power supply voltage (V). DDH / V SSL ),

[0141] The common node of the drain of the second upper-bridge transistor Q12 and the drain of the first lower-bridge transistor Q21 is used to output the third amplified signal V. OUT3 ,

[0142] The source of the first lower-bridge transistor Q21 is connected to the drain of the second lower-bridge transistor Q22.

[0143] The gates of the first upper-bridge transistor Q11, the second upper-bridge transistor Q12, the first lower-bridge transistor Q21, and the second lower-bridge transistor Q22 are all connected to the output terminals of their respective level shifters.

[0144] The input terminal of each level converter is used to connect to the second amplified signal VOUT2. Each level converter is used to perform level conversion on the second amplified signal VOUT2. The converted second amplified signal VOUT2 is matched with the boosted power supply voltage.

[0145] For example, matching the converted second amplified signal VOUT2 with the boosted power supply voltage may include common-mode level matching and signal swing matching. For an introduction to voltage matching, please refer to the previous description; it will not be repeated here.

[0146] For example, the first upper bridge transistor Q11, the second upper bridge transistor Q12, the first lower bridge transistor Q21, and the second lower bridge transistor Q22 can all be PMOS transistors.

[0147] The embodiments disclosed herein do not limit the selection of bias circuits for the input transistors in each stage of the amplifier; those skilled in the art can set them according to actual conditions and needs.

[0148] Please see Figure 7a , Figure 7b , Figure 7a A schematic diagram of a closed-loop bias circuit is shown. Figure 7b A schematic diagram of an open-loop bias circuit is shown.

[0149] For example, such as Figure 7a As shown, the closed-loop bias circuit includes a first closed-loop transistor Q61, a second closed-loop transistor Q62, a third closed-loop transistor Q63, a fourth closed-loop transistor Q64, a fifth closed-loop transistor Q65, a sixth closed-loop transistor Q66, a seventh closed-loop transistor Q67, an eighth closed-loop transistor Q68, a closed-loop switch S61, and a closed-loop capacitor C61, wherein...

[0150] The gate of the first closed-loop transistor Q61 is connected to the reference voltage Vb, and the source of the first closed-loop transistor Q61 and the source of the second closed-loop transistor Q62 are connected to the power supply voltage.

[0151] The drain of the first closed-loop transistor Q61 is connected to the drain and gate of the third closed-loop transistor Q63.

[0152] The source of the third closed-loop transistor Q63 is connected to the gate of the fourth closed-loop transistor Q64 and the drain of the sixth closed-loop transistor Q66.

[0153] The drain of the second closed-loop transistor Q62 is connected to the source of the fourth closed-loop transistor Q64 and the source of the fifth closed-loop transistor Q65.

[0154] The drain of the fourth closed-loop transistor Q64 is connected to the gate of the sixth closed-loop transistor Q66 and the drain of the seventh closed-loop transistor Q67.

[0155] The drain of the fifth closed-loop transistor Q65 is connected to the gate of the seventh closed-loop transistor Q67, the gate of the eighth closed-loop transistor Q68, and the drain of the eighth closed-loop transistor Q68.

[0156] The gate of the fifth closed-loop transistor Q65 is connected to the first terminal of the closed-loop switch S61 and the first terminal of the closed-loop capacitor C61.

[0157] The sources of the sixth closed-loop transistor Q66, the seventh closed-loop transistor Q67, the eighth closed-loop transistor Q68, and the second terminal of the closed-loop capacitor C61 are all grounded.

[0158] The second terminal of the closed-loop switch S61 outputs a bias voltage VS.

[0159] For example, the first closed-loop transistor Q61, the second closed-loop transistor Q62, the fourth closed-loop transistor Q64, and the fifth closed-loop transistor Q65 can all be PMOS transistors, while the third closed-loop transistor Q63, the sixth closed-loop transistor Q66, the seventh closed-loop transistor Q67, and the eighth closed-loop transistor Q68 can all be NMOS transistors.

[0160] For example, such as Figure 7b As shown, the open-loop bias circuit includes a first open-loop transistor Q71, a second open-loop transistor Q72, a third open-loop transistor Q73, a fourth open-loop transistor Q74, a fifth open-loop transistor Q75, a sixth open-loop transistor Q76, a seventh open-loop transistor Q77, an open-loop switch S71, and an open-loop capacitor C71.

[0161] The gate of the first open-loop transistor Q71 is connected to the reference voltage Vb, and the source of the first open-loop transistor Q71 and the source of the second open-loop transistor Q72 are connected to the power supply voltage.

[0162] The drain of the first open-loop transistor Q71 is connected to the drain and gate of the third open-loop transistor Q73.

[0163] The source of the third open-loop transistor Q73 is connected to the gate of the fourth open-loop transistor Q74, the drain of the fourth open-loop transistor Q74, the drain of the seventh open-loop transistor Q77, and the drain of the sixth open-loop transistor Q76.

[0164] The drain of the second open-loop transistor Q72 is connected to the source of the fourth open-loop transistor Q74 and the source of the fifth open-loop transistor Q75.

[0165] The gate of the sixth open-loop transistor Q76 is connected to the gate of the seventh open-loop transistor Q77.

[0166] The gate of the fifth open-loop transistor Q75 is connected to the first terminal of the open-loop switch S71 and the first terminal of the open-loop capacitor C71.

[0167] The drain of the fifth open-loop transistor Q75, the source of the sixth open-loop transistor Q76, the source of the seventh open-loop transistor Q77, and the second terminal of the open-loop capacitor C71 are all grounded.

[0168] The second terminal of the open-loop switch S71 outputs a bias voltage VS.

[0169] For example, the first open-loop transistor Q71, the second open-loop transistor Q72, the fourth open-loop transistor Q74, and the fifth open-loop transistor Q75 can all be PMOS transistors, while the third open-loop transistor Q73, the sixth open-loop transistor Q76, and the seventh open-loop transistor Q77 can all be NMOS transistors.

[0170] The embodiments disclosed herein can be selected as needed. Figure 7a The closed-loop bias circuit shown or Figure 7b The open-loop bias circuit shown serves as the bias circuit for the input transistors in each stage of the amplifier. For example, Figure 7a The closed-loop bias circuit shown is suitable for scenarios with extremely high bias accuracy requirements and where stability issues can be resolved through phase compensation. Figure 7b The open-loop bias circuit shown is suitable for scenarios where stability is a higher priority (such as high-frequency, multi-stage systems) and where accuracy defects can be compensated for by structures such as "source follower".

[0171] Preferably, in order to improve robustness, embodiments of this disclosure may use the bias circuit of the input transistor in each stage of the amplifier as the bias circuit of the input transistor in each stage of the amplifier.

[0172] Compared to existing discrete-time amplifier architectures (such as floating inverting amplifiers and ring amplifiers), the embodiments disclosed herein have the following advantages:

[0173] Significantly reducing preamplifier power consumption and improving system energy efficiency: This embodiment of the disclosure uses a buck charge pump to power the first-stage amplifier 10 and the second-stage amplifier 20, thereby reducing their operating voltage to [value missing]. and This reduces power consumption by approximately 50% in the first two stages. Compared to low-power architectures such as floating inverting amplifiers, the embodiments of this disclosure provide higher gain and pole control capabilities while maintaining low power consumption; compared to ring amplifiers, the embodiments of this disclosure no longer rely on static bias and common-mode feedback transistors in the front stage, resulting in better overall power consumption.

[0174] Expanding the output swing and improving the dynamic range: This embodiment of the present disclosure adopts a switched capacitor boost power supply structure for the third-stage amplifier 30, providing an output drive capability higher than the main power supply voltage in the dynamic amplification phase, thereby significantly expanding the output voltage swing and effectively improving the dynamic range and signal-to-noise ratio of the signal chain;

[0175] Simplified common-mode control, improved stability and robustness: The amplifier structure of the embodiments disclosed herein does not require a precise common-mode feedback path. It only relies on the pre-charging of floating capacitors and the self-balancing mechanism of differential structure to maintain the voltage stability of each node, effectively improving the common-mode rejection capability (CMRR) under PVT environment and enhancing the robustness of the system.

[0176] Open-loop circuit biasing eliminates stability issues: An open-loop structure is used in the biasing design of the first and second stage input transistors, replacing the traditional closed-loop biasing method, thus avoiding stability problems caused by negative feedback.

[0177] This disclosure utilizes a charge pump to achieve graded power supply for different stages of the amplifier. The first and second stages use buck power supply to reduce power consumption, while the third stage uses boost power supply to improve output swing and drive capability. The input transistor bias design of the first and second stages employs a source follower biasing method, using an open-loop structure to avoid stability issues. This disclosure differs from traditional methods in achieving dynamic bandwidth: traditional structures typically adjust bandwidth by changing the transconductance of the output stage transistors. This disclosure, however, adjusts the transconductance by regulating the source voltage of the output stage, effectively simplifying the control path.

[0178] In summary, the multi-stage amplifier of this disclosure is a novel discrete-time amplifier structure. This structure combines a floating capacitor power supply mechanism with a three-stage dominant pole compensation architecture. By introducing a charge pump to step down the power supply for the first two stages to reduce power consumption, and to step up the power supply for the third stage to improve swing and gain, the following technical objectives can be achieved:

[0179] Achieving low power consumption, high gain, and large swing output simultaneously in a discrete-time amplifier: By introducing a floating capacitor power supply mechanism, high gain performance and large output dynamic range are achieved while maintaining low power consumption of the overall system, thereby meeting the needs of high-performance analog signal processing.

[0180] This invention enables flexible control of power supply at each stage of the amplifier, supporting system-level energy efficiency optimization: In traditional fixed power supply schemes, it is difficult for the preamplifier to balance current efficiency with the swing drive capability required by the subsequent stages. The embodiments disclosed herein utilize a multi-stage dynamic power supply architecture to achieve voltage rise and fall regulation between different amplification stages, thereby achieving a balance between gain, speed, and power consumption.

[0181] To achieve the above objectives, the present disclosure aims to provide a discrete-time amplifier structure based on a buck-boost capacitor power supply mechanism. By implementing differentiated power supply strategies for different amplification stages, the overall energy efficiency and performance of the amplifier can be significantly improved while maintaining its stability and linearity.

[0182] According to another aspect of this disclosure, an analog-to-digital converter is provided, the analog-to-digital converter including the aforementioned multi-stage amplifier.

[0183] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned analog-to-digital converter.

[0184] This disclosure does not limit the type of electronic device. For example, an electronic device may include a terminal device, which can be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, a server can be a local server or a cloud server.

[0185] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A multi-stage amplifier, characterized in that, The multi-stage amplifier includes: The first-stage amplifier includes a first buck charge pump and a first amplifier. The first buck charge pump is used to step down the power supply voltage and use the stepped-down power supply voltage to power the first amplifier. The first amplifier is used to amplify the signal to be amplified in the first stage and output a first amplified signal. The second-stage amplifier includes a second buck charge pump and a second amplifier. The second buck charge pump is used to step down the power supply voltage and use the stepped-down power supply voltage to power the second amplifier. The second amplifier is used to amplify the first amplified signal in the second stage and output a second amplified signal. The third-stage amplifier includes a boost charge pump and a third amplifier. The boost charge pump is used to boost the power supply voltage and use the boosted power supply voltage to power the third amplifier. The third amplifier is used to amplify the second amplified signal in the third stage and output the third amplified signal.

2. The multi-stage amplifier according to claim 1, characterized in that, Both the first step-down charge pump and the second step-down charge pump are used to connect to the first power supply voltage and the second power supply voltage, and output the third power supply voltage and the fourth power supply voltage. The first power supply voltage is greater than the second power supply voltage, the third power supply voltage is greater than the fourth power supply voltage, and the difference between the third power supply voltage and the fourth power supply voltage is less than the difference between the first power supply voltage and the second power supply voltage.

3. The multi-stage amplifier according to claim 2, characterized in that, Both the first and second step-down charge pumps include a first step-down switch, a second step-down switch, a third step-down switch, a fourth step-down switch, a fifth step-down switch, a sixth step-down switch, a seventh step-down switch, a first step-down capacitor, and a second step-down capacitor, wherein... The first terminal of the first step-down switch is used to connect to the first power supply voltage. The second terminal of the first step-down switch is connected to the first terminal of the first step-down capacitor and the first terminal of the second step-down switch. The second terminal of the first step-down capacitor is connected to the first terminal of the fourth step-down switch and the first terminal of the fifth step-down switch. The second terminal of the fourth step-down switch is connected to the first terminal of the second step-down capacitor and the first terminal of the third step-down switch. The second terminal of the second step-down capacitor is connected to the first terminal of the sixth step-down switch and the first terminal of the seventh step-down switch. The second terminal of the seventh step-down switch is connected to the second power supply voltage. The common node of the second terminal of the second step-down switch and the second terminal of the third step-down switch is used to output the third power supply voltage. The common node of the second terminal of the fifth step-down switch and the second terminal of the sixth step-down switch is used to output the fourth power supply voltage.

4. The multi-stage amplifier according to claim 3, characterized in that, The first, fourth, and seventh step-down switches are controlled by a first switch control signal, while the second, third, fifth, and sixth step-down switches are controlled by a second switch control signal. The first switch control signal and the second switch control signal are both square wave signals with opposite phases.

5. The multi-stage amplifier according to claim 1, characterized in that, Both the first amplifier and the second amplifier include a first transistor, a second transistor, a first level shifter, and a second level shifter, wherein, The source of the first transistor and the source of the second transistor are used to connect to the stepped-down power supply voltage. The drain of the first transistor is connected to the drain of the second transistor. The gate of the first transistor is connected to the output of the first level converter. The gate of the second transistor is connected to the output of the second level converter. The input terminals of the first level converter and the second level converter are used to receive the signal to be amplified. The first level converter and the second level converter are used to perform level conversion on the signal to be amplified. The converted signal to be amplified is matched with the stepped-down power supply voltage.

6. The multi-stage amplifier according to claim 1, characterized in that, The boost charge pump includes a first boost switch, a second boost switch, a third boost switch, a fourth boost switch, a fifth boost switch, a sixth boost switch, a seventh boost switch, a first boost capacitor, and a second boost capacitor, wherein... The first terminal of the first boost switch and the first terminal of the second boost switch are used to receive a first power supply voltage, and the first terminals of the fifth boost switch and the sixth boost switch are used to receive a second power supply voltage. The second terminal of the first boost switch is connected to the second terminal of the fourth boost switch and the first terminal of the second boost capacitor. The second terminal of the second boost switch is connected to the first terminal of the third boost switch and the first terminal of the first boost capacitor. The second terminal of the first boost capacitor is connected to the first terminal of the fourth boost switch and the second terminal of the fifth boost switch. The second terminal of the second boost capacitor is connected to the second terminal of the sixth boost switch and the first terminal of the seventh boost switch. The second terminal of the third boost switch and the second terminal of the seventh boost switch are respectively used to output the boosted fifth power supply voltage and the sixth power supply voltage. The difference between the fifth power supply voltage and the sixth power supply voltage is greater than the difference between the first power supply voltage and the second power supply voltage.

7. The multistage amplifier according to claim 6, characterized in that, The third amplifier includes a first upper-bridge transistor, a second upper-bridge transistor, a first lower-bridge transistor, a second lower-bridge transistor, and four level shifters, wherein... The drain of the first upper-bridge transistor is connected to the source of the second upper-bridge transistor. The source of the first upper-bridge transistor and the source of the second lower-bridge transistor are connected to the output terminal of the boost charge pump to receive the boosted power supply voltage. The common node of the drain of the second upper-bridge transistor and the drain of the first lower-bridge transistor is used to output the third amplified signal. The source of the first lower-bridge transistor is connected to the drain of the second lower-bridge transistor. The gates of the first upper-bridge transistor, the second upper-bridge transistor, the first lower-bridge transistor, and the second lower-bridge transistor are all connected to the output terminals of their respective level shifters. The input terminals of each level converter are used to receive the second amplified signal. Each level converter is used to perform level conversion on the second amplified signal, and the converted second amplified signal is matched with the boosted power supply voltage.

8. The multi-stage amplifier according to claim 6, characterized in that, The first boost switch, the second boost switch, the fifth boost switch, and the sixth boost switch are controlled by a first switch control signal, while the third boost switch, the fourth boost switch, and the seventh boost switch are controlled by a second switch control signal. The first switch control signal and the second switch control signal are both square wave signals with opposite phases.

9. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes the multi-stage amplifier as described in claim 7.

10. An electronic device, characterized in that, The electronic device includes the analog-to-digital converter as described in claim 9.

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