Circuit board structure and manufacturing method thereof
By employing a coaxial through-hole structure and a closed ground path design in the circuit board, the impedance matching and energy dissipation problems in high-frequency transmission are solved, and the material cost is reduced.
Patent Information
- Application Number
- CN202410616326.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-17
- Publication Date
- 2025-11-18
AI Technical Summary
Existing circuit boards suffer from poor impedance matching, energy dissipation, and signal interference in high-frequency transmission, and the use of low dielectric constant materials increases costs.
A coaxial through-hole structure is used to replace the traditional electroplated through-hole, combined with a well-sealed ground path design, and a non-full low dielectric constant material is used in the dielectric layer.
It achieves good transmission of high-frequency and high-speed signals, reduces noise interference and energy dissipation, and also reduces material costs.
Smart Images
Figure CN120980764A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a circuit board structure and a manufacturing method thereof. BACKGROUND
[0002] In the prior art, the plating through hole (PTH) is a conventional technology for cross-layer signal transmission. However, the PTH has problems of impedance mismatch, energy dissipation and signal interference in high-frequency transmission, which is not conducive to the signal integrity of the PCB high-frequency application. In addition, the PTH technology requires the use of multi-layer low dielectric constant (Dk) / low dielectric loss factor (Df) materials, which increases the manufacturing cost of the circuit board. Therefore, how to provide a circuit board structure to solve the above problems is still the goal of the researchers in this field. SUMMARY
[0003] Some embodiments of the present disclosure provide a circuit board structure and a manufacturing method thereof. The circuit board structure replaces the conventional PTH cross-layer signal line and the conventional antenna feeding method with a coaxial via. The present application can transmit high-frequency high-speed signals to the antenna area of the antenna layer through the inner hole. The coaxial via structure can provide a transmission line with good impedance matching, and a good ground path can be designed around the via. This design not only forms a good high-frequency high-speed loop, but also isolates noise and prevents energy dissipation. In addition, the dielectric layer material of this design does not need to use low dielectric constant (Dk) / low dielectric loss factor (Df) materials, which can greatly reduce the cost of materials.
[0004] Some embodiments of the present disclosure provide a circuit board structure. The circuit board structure includes a composite layer, a first dielectric layer, a second dielectric layer, an isolation layer, a first conductive layer, a second conductive layer, an antenna layer, and a signal layer. The composite layer includes a plurality of dielectric layers and a plurality of internal circuit layers disposed on surfaces of the dielectric layers. The first dielectric layer is disposed on a lower surface of the composite layer. The second dielectric layer is disposed on an upper surface of the composite layer. The isolation layer is disposed between the first dielectric layer and the second dielectric layer and adjacent to the composite layer, wherein the isolation layer, the first dielectric layer, and the second dielectric layer collectively have an opening extending from an upper surface of the second dielectric layer to a lower surface of the first dielectric layer. The first conductive layer is disposed between the isolation layer and the internal circuit layers and connects ground portions of the internal circuit layers. The second conductive layer covers inner walls of the opening, wherein the isolation layer separates the second conductive layer from the first conductive layer, and the second conductive layer, the isolation layer, and the first conductive layer form a coaxial via. The antenna layer is disposed on the upper surface of the second dielectric layer, wherein the antenna layer connects an upper end of the second conductive layer. The signal layer is disposed under the lower surface of the first dielectric layer, wherein a first portion of the signal layer connects a lower end of the second conductive layer.
[0005] According to some embodiments of the present disclosure, the circuit board structure further includes a first dielectric filler material disposed in the opening.
[0006] According to some embodiments of the present disclosure, the circuit board structure, wherein an upper surface of the first dielectric filler material is higher than the upper surface of the second dielectric layer, and a lower surface of the first dielectric filler material is lower than the lower surface of the first dielectric layer.
[0007] According to some embodiments of the present disclosure, the circuit board structure, wherein the antenna layer covers the upper surface of the first dielectric filler material, and the signal layer covers the lower surface of the first dielectric filler material.
[0008] According to some embodiments of the present disclosure, the circuit board structure further includes a ground via penetrating the first dielectric layer, wherein the ground via is separated from the isolation layer, and wherein the ground via connects a second portion of the signal layer to the ground portions of the internal circuit layers.
[0009] According to some embodiments of the present disclosure, the circuit board structure, wherein the isolation layer has opposite first and second side walls, the first side wall of the isolation layer contacts the second conductive layer, and the second side wall of the isolation layer contacts the ground portions of the internal circuit layers.
[0010] According to some embodiments of the present disclosure, the circuit board structure further includes a second dielectric filler material disposed in the ground via.
[0011] According to some embodiments of the present disclosure, the circuit board structure, wherein a dielectric constant (Dk) of the isolation layer is lower than a dielectric constant (Dk) of the dielectric materials.
[0012] In accordance with some embodiments of the present disclosure, the circuit board structure, wherein the dielectric constant (Dk) of the isolation layer is between 3 and 3.5.
[0013] In accordance with some embodiments of the present disclosure, the circuit board structure, wherein the antenna layer has an antenna trace, and the antenna trace overlaps the coaxial via.
[0014] In accordance with some embodiments of the present disclosure, the circuit board structure further comprises a trace on the upper end of the second conductive layer for connecting an antenna.
[0015] Some embodiments of the present disclosure provide a method for manufacturing a circuit board structure. The method comprises the following steps. Forming a first opening in a composite layer, wherein the composite layer comprises a plurality of dielectric layers and a plurality of internal trace layers disposed on the surfaces of the dielectric layers, and the first opening penetrates the dielectric layers and exposes the side surfaces of the dielectric layers. Forming a first conductive layer on the inner wall of the first opening, wherein the first conductive layer is electrically connected to the internal trace layers. Filling an isolation layer in the first opening. Disposing a first dielectric layer under the lower surface of the composite layer. Disposing a signal layer under the first dielectric layer. Disposing a second dielectric layer on the upper surface of the composite layer. Disposing an antenna layer on the second dielectric layer. Forming a second opening in the first dielectric layer, the isolation layer, and the second dielectric layer. Forming a second conductive layer on the inner wall of the second opening, wherein the second conductive layer connects the signal layer to the antenna layer. The second conductive layer, the isolation layer, and the first conductive layer form a coaxial via.
[0016] In accordance with some embodiments of the present disclosure, the method further comprises the following steps. After forming the second conductive layer, patterning the signal layer, and after forming the second conductive layer, patterning the antenna layer.
[0017] In accordance with some embodiments of the present disclosure, the method further comprises the following steps. Forming a first dielectric material in the second opening.
[0018] In accordance with some embodiments of the present disclosure, the method further comprises the following steps. Forming a ground via in the first dielectric layer to expose the ground portions of the internal trace layers. Forming a third conductive layer in the ground via to connect the ground portions of the internal trace layers.
[0019] In accordance with some embodiments of the present disclosure, the method further comprises the following steps. Forming a second dielectric material in the ground via. BRIEF DESCRIPTION OF DRAWINGS
[0020] FIG. 1A A schematic view of a circuit substrate mounted according to a circuit board structure of some embodiments of the present disclosure.
[0021] FIG. 1B For circuit board structure in FIG. 1A A magnified lower view of a portion of the circuit board.
[0022] FIG. 1C for FIG. 1B A cross-sectional view along line A-A'.
[0023] FIG. 1D for FIG. 1C The top view.
[0024] FIG. 2 This is a flowchart of a circuit board structure manufacturing method according to a partial embodiment of this disclosure.
[0025] FIG. 3A through FIG. 3I The figure shows a cross-sectional view of a circuit board structure according to an embodiment of the present disclosure at various stages of the manufacturing process.
[0026] FIG. 3J This is a cross-sectional view of a circuit board structure according to an embodiment of the present disclosure.
[0027] FIG. 3K This is a cross-sectional view of a circuit board structure according to an embodiment of the present disclosure.
[0028] FIG. 4A According to an embodiment of the present disclosure FIG. 1A Enlarged bottom view of the dashed section.
[0029] FIG. 4B for FIG. 4A A cross-sectional view along line B-B'.
[0030] FIG. 4C for FIG. 4B The top view.
[0031] FIG. 5A through FIG. 5K According to one embodiment of the present disclosure FIG. 4B Cross-sectional views of the circuit board structure at various stages of the manufacturing process.
[0032] FIG. 5J This is a cross-sectional view of a circuit board structure according to an embodiment of the present disclosure.
[0033] FIG. 5L This is a cross-sectional view of a circuit board structure according to an embodiment of the present disclosure.
[0034] FIG. 6 This is a schematic diagram of a horizontally fed antenna with a circuit board structure according to an embodiment of the present disclosure.
[0035] [Symbol Explanation]
[0036] 100: Circuit board
[0037] 110: Signal Unit
[0038] 120: signal line
[0039] 200: circuit board structure
[0040] 210: composite layer
[0041] 212, 212A, 212B, 212C, 212D: inner circuit layer
[0042] 214, 214A, 214B, 214C: dielectric layer
[0043] 220: first dielectric layer
[0044] 230: second dielectric layer
[0045] 220O: ground opening
[0046] 240: isolation layer
[0047] 242: first sidewall
[0048] 244: second sidewall
[0049] 250: first conductive layer
[0050] 260: second conductive layer
[0051] 270: signal layer
[0052] 272: first portion
[0053] 274: second portion
[0054] 280, 280': antenna layer
[0055] 282: antenna line
[0056] 290: third conductive layer
[0057] 300: method
[0058] 310, 320, 330, 340, 350, 360, 370, 372, 380, 390, 392, 394, 396: step 400: filling conductive material
[0059] 410: first filling dielectric material
[0060] 420: second filling dielectric material
[0061] 430: third filling dielectric material
[0062] 500: line
[0063] 900, 910: conductive layer, signal layer
[0064] O1: opening
[0065] O2: opening
[0066] R1: receiving area
[0067] R2: transmitting area
[0068] SV: signal via hole
[0069] CV: coaxial via hole
[0070] VH: ground via hole
[0071] PA: antenna
[0072] A-A', B-B': line DETAILED DESCRIPTION
[0073] Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed, disclosed, and taught herein are merely for illustration and are not intended to limit the scope of the disclosure. As used herein, the terms "first," "second," "third," etc. are not intended to denote a particular order or sequence, but are used merely to distinguish one component from another.
[0074] In addition, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, the terms "about", "approximately", "substantially", or "essentially" generally mean within 20% of a given value or range, or within 10% of a given value or range, or within 5% of a given value or range. Numerical values given herein are approximate, meaning that the terms "about", "approximately", "substantially", or "essentially" can be inferred in the absence of an explicit designation.
[0075] FIG. 1A A schematic diagram of a circuit substrate installed according to a circuit board structure of some embodiments of the present disclosure. In some embodiments, the circuit substrate 100 can include a signal unit 110 and a signal line 120. The signal line 120 can transmit high-frequency high-speed radio frequency signals from the receiving area R1 to the signal unit 110 or from the signal unit 110 to the transmitting area R2. It should be noted, however, that the signal line 120 can take any suitable configuration without being limited thereto.
[0076] FIG. 1B FIG. 1 shows a partial enlarged view of the receiving area Rl or the transmission area R2 of the circuit substrate 100. FIG. 1A FIG. 2 shows a partial enlarged view of the receiving area Rl or the transmission area R2 of the circuit substrate 100. FIG. 1C FIG. 3 shows a cross-sectional view along the line A-A'. FIG. 1B FIG. 4 shows a top view of the circuit substrate 100. FIG. 1D FIG. 5 shows a top view of the circuit substrate 100. FIG. 1C FIG. 6 shows a top view of the circuit substrate 100. FIG. 1B FIG. 7 shows a top view of the circuit substrate 100. FIG. 1C FIG. 8 shows a top view of the circuit substrate 100. FIG. 1D FIG. 9 shows a schematic diagram of the circuit board structure 200 in the vertical feed-in. Please refer to FIGS. 1-8 simultaneously. FIG. 1B FIG. 10 shows a schematic diagram of the circuit board structure 200 in the horizontal feed-in. Please refer to FIGS. 1-8 simultaneously. FIG. 1C FIG. 11 shows a schematic diagram of the circuit board structure 200 in the vertical feed-in. Please refer to FIGS. 1-8 simultaneously. FIG. 1D FIG. 12 shows a schematic diagram of the circuit board structure 200 in the horizontal feed-in. Please refer to FIGS. 1-8 simultaneously.
[0077] The circuit board structure 200 includes a composite layer 210, a first dielectric layer 220, a second dielectric layer 230, an isolation layer 240, a first conductive layer 250, a second conductive layer 260, a signal layer 270, and an antenna layer 280.
[0078] In some embodiments, the composite layer 210 includes a plurality of internal circuit layers 212 and a plurality of dielectric layers 214. In the present embodiment, the internal circuit layers 212 include internal circuit layers 212A, 212B, 212C, and 212D, and the plurality of dielectric layers 214 include dielectric layers 214A, 214B, and 214C. The number of internal circuit layers 212 and dielectric layers 214 can be changed according to functional requirements. However, it should be noted that the internal circuit layers 212 and dielectric layers 214 can adopt any suitable configuration, without being limited thereto. The dielectric layers 214A, 214B, and 214C can be any dielectric material. For example, in some embodiments, the dielectric layers 214A, 214B, and 214C can be polypropylene (PP), but it should be noted that the dielectric layers 214A, 214B, and 214C can adopt any suitable dielectric material, without being limited thereto.
[0079] In some embodiments, the internal circuit layers 212 can be disposed on the surface of the dielectric layers 214. For example, in the present embodiment, the internal circuit layer 212A covers the upper surface of the dielectric layer 214A, the internal circuit layer 212B covers the lower surface of the dielectric layer 214A and the upper surface of the dielectric layer 214B, the internal circuit layer 212C covers the lower surface of the dielectric layer 214B and the upper surface of the dielectric layer 214C, the internal circuit layer 212D covers the lower surface of the dielectric layer 214C, and are connected to each other, wherein the internal circuit layers 212 have a ground portion.
[0080] In some embodiments, a first dielectric layer 220 can be disposed on the lower surface of the composite layer 210, and a second dielectric layer 230 can be disposed on the upper surface of the composite layer 210. The first dielectric layer 220 and the second dielectric layer 230 can be any suitable dielectric material. In some embodiments, the first dielectric layer 220 and the second dielectric layer 230 can be any dielectric material having a lower dielectric constant (Dk) and a lower dissipation factor (Df) than the dielectric layer 214 to isolate noise in signal transmission.
[0081] In some embodiments, an isolation layer 240 can be disposed between the first dielectric layer 220 and the second dielectric layer 230, and adjacent to the composite layer 210. In some embodiments, the isolation layer 240 can be a low dielectric constant (Dk) and low dissipation factor (Df) dielectric material. For example, the isolation layer 240 can be a dielectric material having a lower dielectric constant (Dk) and a lower dissipation factor (Df) than the dielectric layer 214. In some embodiments, the isolation layer 240 can have a dielectric constant (Dk) between 3 and 3.5. It should be noted, however, that the isolation layer 240 can be any suitable dielectric material without being so limited.
[0082] Further, the height and thickness of the isolation layer 240 can be varied according to functional requirements. For example, in the present embodiment, the height of the isolation layer 240 is the same as the height of the composite layer 210. In some embodiments, the thickness of the isolation layer 240 can be varied according to the impedance requirements of the circuit board structure 200 to achieve better isolation.
[0083] In addition, in the present embodiment, the isolation layer 240, the first dielectric layer 220, and the second dielectric layer 230 collectively have an opening O1. The opening O1 extends from the upper surface of the second dielectric layer 230 to the lower surface of the first dielectric layer 220. The opening O1 penetrates through the isolation layer 240, the first dielectric layer 220, and the second dielectric layer 230, wherein the isolation layer 240 surrounds the opening O1 and is arranged concentrically with the opening O1.
[0084] In some embodiments, the first conductive layer 250 is located between the isolation layer 240 and the inner circuit layers 212, and connects the ground portions of the inner circuit layers 212. The second conductive layer 260 covers the inner wall of the opening O1, and forms a signal via SV. The isolation layer 240 separates the second conductive layer 260 from the first conductive layer 250, and the second conductive layer 260, the isolation layer 240 and the first conductive layer 250 form a coaxial via CV. In detail, in the present embodiment, the isolation layer 240 has opposite first and second side walls 242 and 244. The first side wall 242 of the isolation layer 240 contacts the second conductive layer 260. In some embodiments, the second side wall 244 of the isolation layer 240 contacts the first conductive layer 250 and the ground portions of the inner circuit layers 212, so that the circuit board structure 200 has a closed ground path, in which the second conductive layer 260, the isolation layer 240 and the first conductive layer 250 are arranged in concentric circles. This design allows the dielectric layer 214 of the composite layer 210 not to be particularly selected as a material with low dielectric constant (Dk) and low dielectric loss factor (Df), thereby reducing the manufacturing cost of the circuit board structure 200.
[0085] In some embodiments, the signal layer 270 is located below the lower surface of the first dielectric layer 220. The signal layer 270 can be subjected to additional processes according to functional requirements, such as a lithography process. In detail, the signal layer 270 can be patterned by a lithography process to divide the signal layer 270 into a first portion 272 and a second portion 274. The first portion 272 connects the lower end of the second conductive layer 260, in which the first portion 272 of the signal layer 270, the antenna layer 280 and the second conductive layer 260 define a signal transmission path.
[0086] In some embodiments, the antenna layer 280 is located above the upper surface of the second dielectric layer 230, in which the antenna layer 280 connects the upper end of the second conductive layer 260. The antenna layer 280 can include appropriate antenna lines 282 to form any appropriate antenna, such as a patch antenna. However, it should be noted that the antenna layer 280 can adopt any appropriate configuration, without being limited thereto.
[0087] In some embodiments, the circuit board structure 200 further includes a ground via VH. In this embodiment, the ground via VH penetrates the first dielectric layer 220, and the ground via VH is separated from the isolation layer 240, wherein the third conductive layer 290 can connect the second portion 274 of the signal layer 270 and cover an inner wall of the ground via VH. The ground via VH connects the second portion 274 of the signal layer 270 to a ground portion of the inner circuit layer 212. The ground via VH, the second portion 274 of the signal layer 270, and the ground portion of the inner circuit layer 212 define a ground path, wherein the ground path surrounds the signal transmission path. In addition, the number of the ground via VH can be changed according to the requirement. For example, in this embodiment, the number of the ground via VH is 7.
[0088] FIG. 2 A flow chart of a method for fabricating the circuit board structure 200 according to some embodiments of the present disclosure. FIG. 3A through FIG. 3I A cross-sectional view of the circuit board structure 200 at various stages of the process according to an embodiment of the present disclosure. This description is merely illustrative and is not intended to further limit the scope of the subsequent patent application. The method 300 includes steps 310-396. It should be appreciated that additional steps can be added before, during, and after steps 310-396, and for another embodiment of the method, some of the steps mentioned below can be replaced or removed. The order of the steps / programs can be changed.
[0089] First, refer to FIG. 2 and FIG. 3A A composite layer 210 is provided. The composite layer 210 includes a plurality of dielectric layers 214 (e.g., dielectric layers 214A, 214B, and 214C) and a plurality of inner circuit layers 212 (e.g., inner circuit layers 212A, 212B, 212C, and 212D) disposed on the surfaces of the dielectric layers 214, which are laminated together in a press-bonding manner.
[0090] Next, refer to FIG. 2 and FIG. 3B The method 300 proceeds to step 310. In the composite layer 210, an opening O2 is formed. For example, an opening process, such as a mechanical drilling process, is performed on the middle portion of the composite layer 210. The opening O2 penetrates the plurality of dielectric layers 214 and the plurality of inner circuit layers 212, and exposes the side surfaces of the dielectric layers 214.
[0091] Next, refer to FIG. 2 and FIG. 3CAfter forming the opening O2, a first conductive layer 250 is formed on the inner wall of the opening O2, wherein the first conductive layer 250 is electrically connected to the inner circuit layer 212 (e.g., the inner circuit layers 212A, 212B, 212C and 212D). For example, in the present embodiment, the first conductive layer 250 can be formed by an electroplating process. However, it should be noted that the first conductive layer 250 can be formed by any suitable process without limitation.
[0092] Next, referring to FIG. 3B, the method 300 proceeds to step 330. The insulating layer 240 is filled in the opening O2. For example, in the present embodiment, the insulating layer 240 can be formed by a brushing or staking process. However, it should be noted that the insulating layer 240 can be formed by any suitable process without limitation. FIG. 2 FIG. 3D After filling the insulating layer 240 in the opening O2, in some embodiments, the inner circuit layer 212 can be patterned according to the functional requirement. For example, the inner circuit layer 212 can be patterned by a photolithography process or any suitable process. However, it should be noted that the inner circuit layer 212 can be formed by any suitable process without limitation.
[0093] Next, referring to FIG. 3B, the method 300 proceeds to step 330. The insulating layer 240 is filled in the opening O2. For example, in the present embodiment, the insulating layer 240 can be formed by a brushing or staking process. However, it should be noted that the insulating layer 240 can be formed by any suitable process without limitation.
[0094] Next, referring to FIG. 3B, the method 300 proceeds to step 330. The insulating layer 240 is filled in the opening O2. For example, in the present embodiment, the insulating layer 240 can be formed by a brushing or staking process. However, it should be noted that the insulating layer 240 can be formed by any suitable process without limitation. FIG. 2 FIG. 3E After filling the insulating layer 240 in the opening O2, in some embodiments, the inner circuit layer 212 can be patterned according to the functional requirement. For example, the inner circuit layer 212 can be patterned by a photolithography process or any suitable process. However, it should be noted that the inner circuit layer 212 can be formed by any suitable process without limitation.
[0095] Next, the method 300 proceeds to step 350. On the second dielectric layer 230, an antenna layer 280 is disposed. For example, in the present embodiment, the antenna layer 280 can be formed by an electroplating process. However, it should be noted that the antenna layer 280 can be formed by any suitable process without limitation.
[0096] Next, the method 300 proceeds to step 360. On the lower surface of the composite layer 210, a first dielectric layer 220 is disposed. For example, in the present embodiment, the first dielectric layer 220 can be formed by the same process as the second dielectric layer 230, such as a lamination process. However, it should be noted that the first dielectric layer 220 can be formed by any suitable process without limitation.
[0097] Next, the method 300 proceeds to step 370. The signal layer 270 is formed under the first dielectric layer 220. For example, in the present embodiment, the signal layer 270 can be formed by the same process as the antenna layer 280, such as an electroplating process. However, it should be noted that the signal layer 270 can be formed by any suitable process.
[0098] In some other embodiments, the order of steps 340, 350, 370 and 360 can be changed. For example, the first dielectric layer 220 can be formed by a lamination process after the formation of the isolation layer 240. Next, the second dielectric layer 230 can be formed by the same or any suitable process after the formation of the first dielectric layer 220. Next, the antenna layer 280 and the signal layer 270 are formed on the second dielectric layer 230 and the first dielectric layer 220.
[0099] In some other embodiments, steps 340, 350, 370 or 360 can be performed simultaneously. For example, the first dielectric layer 220 and the second dielectric layer 230 can be formed by a lamination process or any suitable process after the formation of the isolation layer 240. Next, the antenna layer 280 and the signal layer 270 are formed on the second dielectric layer 230 and the first dielectric layer 220.
[0100] Referring to FIG. 2 and FIG. 3F , the method 300 proceeds to step 372. The ground openings 220O are formed in the first dielectric layer 220 to expose the ground portions of the inner circuit layers 212. For example, in the present embodiment, the ground openings 220O can be formed by a laser process. However, it should be noted that the ground openings 220O can be formed by any suitable process.
[0101] Next, referring to FIG. 2 and FIG. 3G , the method 300 proceeds to step 380. The opening O1 is formed in the first dielectric layer 220, the isolation layer 240 and the second dielectric layer 230. For example, the middle portion of the isolation layer 240 is subjected to an opening process, such as a mechanical drilling process. The opening O1 penetrates through the first dielectric layer 220, the isolation layer 240 and the second dielectric layer 230.
[0102] Next, referring to FIG. 2 and FIG. 3HAt step 390, a second conductive layer 260 is formed on the inner wall of the opening Ol, wherein the second conductive layer 260 connects the signal layer 270 to the antenna layer 280 to form a signal via SV, and the second conductive layer 260, the isolation layer 240 and the first conductive layer 250 form a coaxial via CV. For example, the second conductive layer 260 can be formed by an electroplating process. However, it should be noted that the second conductive layer 260 can be formed by any suitable process.
[0103] At step 392, a third conductive layer 290 is formed in the ground opening 220O to form a ground via VH to connect the ground portions of the inner circuit layers 212. For example, in the present embodiment, the third conductive layer 290 can be formed by an electroplating process. However, it should be noted that the third conductive layer 290 can be formed by any suitable process.
[0104] In the present embodiment, steps 390 and 392 can be performed simultaneously. For example, after forming the opening Ol and the ground opening 220O, the second conductive layer 260 and the third conductive layer 290 can be formed by a same electroplating process or any suitable process. In some other embodiments, the order of steps 372, 380, 390 and 392 can be changed. For example, after forming the signal via SV, the ground opening 220O can be formed in the first dielectric layer 220 by a laser process, and then the third conductive layer 290 can be electroplated to form the ground via VH.
[0105] Thereafter, please refer to FIG. 2 and FIG. 3I At step 394, after forming the second conductive layer 260, the signal layer 270 is patterned. For example, the signal layer 270 can be patterned by a lithography process or any suitable process. However, it should be noted that the signal layer 270 can be patterned by any suitable process.
[0106] At step 396, after forming the second conductive layer 260, the antenna layer 280 is patterned to form the antenna line 282. For example, the antenna layer 280 can be patterned by a lithography process or any suitable process. However, it should be noted that the antenna layer 280 can be patterned by any suitable process.
[0107] In some embodiments, the order of steps 394 and 396 can be changed or performed simultaneously. For example, after forming the second conductive layer 260, the signal layer 270 and the antenna layer 280 can be patterned simultaneously by a lithography process or any suitable process.
[0108] FIG. 3JFIG. 7 is a cross-sectional view of a circuit board structure 200 according to an embodiment of the present disclosure. The embodiment is similar to the embodiments of FIGS. 1-6. FIG. 3A through FIG. 3I The difference between the embodiment and the embodiments of FIGS. 1-6 is that, in the embodiment, the method 300 further includes forming a first fill dielectric material 410 in the ground via VH. For example, after forming the ground via VH, the first fill dielectric material 410 can be formed in the ground via VH by a tree plug process. It should be noted that the fill dielectric material 410 can be formed by any suitable process without being limited thereto. FIG. 3J
[0109] FIG. 8 is a cross-sectional view of a circuit board structure 200 according to an embodiment of the present disclosure. The embodiment is similar to the embodiments of FIGS. 1-7. FIG. 3K The difference between the embodiment and the embodiments of FIGS. 1-7 is that, in the embodiment, the method 300 further includes forming a first fill dielectric material 410 in the ground via VH. For example, after forming the ground via VH, the first fill dielectric material 410 can be formed in the ground via VH by a tree plug process. It should be noted that the fill dielectric material 410 can be formed by any suitable process without being limited thereto. FIG. 3A through FIG. 3I FIG. 3K In some embodiments, after forming the first fill dielectric material 410, the first fill dielectric material 410 can be capped. For example, after forming the first fill dielectric material 410, a conductive layer (or a signal layer) 900 can be formed to cap the first fill dielectric material 410 by an electroplating process. In some embodiments, the first portion 272, the second portion 274 of the signal layer 270, and the conductive layer 900 collectively are referred to as a signal layer 270'. It should be noted that the first fill dielectric material 410 can be capped by any suitable process without being limited thereto.
[0110] FIG. 9 is an enlarged bottom view of the dashed portion of FIG. 8.
[0111] FIG. 10 is a top view of FIG. 9. Please refer to FIGS. 1-8. FIG. 4A FIG. 11 is a cross-sectional view along line B-B' of FIG. 9. FIG. 1A FIG. 12 is a top view of FIG. 11. Please refer to FIGS. 1-10. FIG. 4B FIG. 13 is a cross-sectional view along line B-B' of FIG. 12. FIG. 4A FIG. 14 is a top view of FIG. 13. Please refer to FIGS. 1-12. FIG. 4C FIG. 15 is a cross-sectional view along line B-B' of FIG. 14. FIG. 4B FIG. 16 is a top view of FIG. 15. Please refer to FIGS. 1-14. FIG. 4A FIG. 4B FIG. 4C The circuit board structure 200 of the embodiment is similar to the circuit board structures 200 in FIGS. 1-15. The difference between the embodiment and the circuit board structures 200 in FIGS. 1-15 is that:
[0112] The circuit board structure 200 of the embodiment is similar to the circuit board structures 200 in FIGS. 1-15. The difference between the embodiment and the circuit board structures 200 in FIGS. 1-15 is that: FIG. 1A FIG. 1B FIG. 1A The circuit board structure 200 of the embodiment is similar to the circuit board structures 200 in FIGS. 1-15. The difference between the embodiment and the circuit board structures 200 in FIGS. 1-15 is that: FIG. 4A FIG. 4B FIG. 4C The circuit board structure 200 further includes a third filler dielectric material 430 and a second filler dielectric material 420.
[0113] In some embodiments, the third filler dielectric material 430 may be located in the opening O1, wherein the upper surface of the third filler dielectric material 430 is higher than the upper surface of the second dielectric layer 230, and the lower surface of the third filler dielectric material 430 is lower than the lower surface of the first dielectric layer 220.
[0114] Furthermore, in some embodiments, the second filling dielectric material 420 is located in the ground via VH. The lower surface of the second filling dielectric material 420 is coplanar with the second portion 274 of the signal layer 270.
[0115] FIG. 5A through FIG. 5J According to one embodiment of the present disclosure FIG. 4B The circuit board structure 200 is shown in cross-sectional views at various stages of the manufacturing process. This description is illustrative only and is not intended to further limit the scope of the following patent application. Please refer to... FIG. 5A through FIG. 5J .
[0116] FIG. 5A through FIG. 5J Circuit board structure 200 and FIG. 3A through FIG. 3I The circuit board structure is similar to 200. In this embodiment, in FIG. 5A In this process, multiple dielectric layers 214 and multiple internal circuit layers 212 are laminated together to form a composite layer 210. FIG. 5B In the composite layer 210, an opening O2 is formed. FIG. 5C In the process, after the opening O2 is formed, a first conductive layer 250 is formed on the inner wall of the opening O2, wherein the first conductive layer 250 is electrically connected to the internal circuit layer 212. FIG. 5D In the middle, the insulating layer 240 is filled into the opening O2. FIG. 5E In this structure, a second dielectric layer 230 is disposed on the upper surface of the composite layer 210. A first dielectric layer 220 is disposed on the lower surface of the composite layer 210. A signal layer 270 is disposed below the first dielectric layer 220. FIG. 5F In this process, a ground via VH is formed in the first dielectric layer 220 to expose the grounded portions of these internal wiring layers 212. FIG. 5G An opening O1 is formed in the first dielectric layer 220, the insulating layer 240, and the second dielectric layer 230. FIG. 5H In the middle, a second conductive layer 260 is formed on the inner wall of the opening O1, wherein the second conductive layer 260 connects the signal layer 270 to the antenna layer 280, and a third conductive layer 290 is formed in the grounding via VH to connect the grounding portion of these internal circuit layers 212.
[0117] FIG. 5A through FIG. 5J Circuit board structure 200 andFIG. 3A through FIG. 3I The difference between the circuit board structure 200 of FIG. 5I is that in the opening Ol, a third filling dielectric material 430 is formed. In the ground via VH, a second filling dielectric material 420 is formed. In detail, in the present embodiment, the third filling dielectric material 430 and the second filling dielectric material 420 can be formed by brushing or staking process. However, it should be noted that the third filling dielectric material 430 and the second filling dielectric material 420 can be formed by any suitable process without limitation.
[0118] Further, the third filling dielectric material 430 and the second filling dielectric material 420 can be formed separately. For example, in some embodiments, after the third filling dielectric material 430 is formed in the opening Ol, the second filling dielectric material 420 is formed in the ground via VH by the same process as that for forming the third filling dielectric material 430.
[0119] Next, in FIG. 5J , the signal layer 270 is patterned to form a first portion 272 and a second portion 274. In FIG. 5J , the antenna layer 280 is patterned to form an antenna line 282.
[0120] FIG. 5K is a cross-sectional view of the circuit board structure 200 according to an embodiment of the present disclosure. In some embodiments, the above-mentioned process further includes capping the second filling dielectric material 420 and the third filling dielectric material 430. For example, after the third filling dielectric material 430 and the second filling dielectric material 420 are formed, the lower end of the third filling dielectric material 430 and the lower end of the second filling dielectric material 420 can be capped by an electroplating process of the conductive layer (or signal layer) 900. The upper end of the third filling dielectric material 430 can be capped by an electroplating process of the conductive layer (or signal layer) 910. The first portion 272, the second portion 274 of the signal layer 270 and the conductive layer 900 are collectively referred to as the signal layer 270'. The antenna layer 280 and the conductive layer 910 are collectively referred to as the antenna layer 280'. In this way, the antenna layer 280' covers the upper surface of the third filling dielectric material 430, and the signal layer 270' covers the lower surface of the third filling dielectric material 430 and the lower surface of the second filling dielectric material 420. However, it should be noted that the third filling dielectric material 430 and the second filling dielectric material 420 can be capped by any suitable capping process without limitation.
[0121] FIG. 5L is a cross-sectional view of the circuit board structure 200 according to an embodiment of the present disclosure. The present embodiment is similar to the embodiment of FIG. 5A through FIG. 5J . FIG. 5LThe difference lies in the fact that, in this embodiment, the above-described method further includes forming a conductive filler 400 in the grounding via VH. For example, the conductive filler 400 can be formed in the grounding via VH by an electroplating process. However, it should be noted that the conductive filler 400 can be formed using any suitable process, and is not limited thereto.
[0122] FIG. 6 This is a schematic diagram of a horizontally fed antenna PA (PA) based on a circuit board structure 200 according to an embodiment of this disclosure. FIG. 6 As shown, the circuit board structure 200 further includes a line 500 located at the upper end of the second conductive layer 260 for connecting the antenna PA. For example, the antenna layer 280 can be horizontally fed into the antenna PA through the line 500, wherein the line 500 can overlap with the upper end of the second conductive layer 260, so that the second conductive layer 260 is connected to the antenna PA through the antenna layer 280 and the horizontally fed line 500. This allows the signal to be horizontally fed into the antenna PA. In some embodiments disclosed herein, horizontal and vertical feeding methods are used as examples; in practice, the circuit board structure 200 can employ any suitable feeding method, and is not limited thereto. Furthermore, the antenna PA can be any suitable antenna. In some embodiments, the antenna PA can be a patch antenna.
[0123] This disclosure provides a circuit board structure and its fabrication method in some embodiments. This circuit board structure replaces traditional PTH (Pulse-Through-Layer) signal lines and traditional feed antenna methods with coaxial vias. This invention allows high-frequency, high-speed signals to be transmitted to the antenna region of the antenna layer through the vias. This coaxial via structure provides a transmission line with good impedance matching and allows for the design of a well-sealed path to ground around the vias. In addition to forming a good high-frequency, high-speed loop, this design also isolates noise and prevents energy dissipation. Furthermore, the dielectric layer material of this design does not need to be entirely composed of low dielectric constant (Dk) / low dielectric loss factor (Df) materials, which can significantly reduce material costs.
[0124] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A circuit board structure, characterized by, The composite layer includes a plurality of dielectric layers and a plurality of inner circuit layers disposed on surfaces of the dielectric layers. A first dielectric layer is disposed on the lower surface of the composite layer. A second dielectric layer is disposed on the upper surface of the composite layer. An isolation layer is disposed between the first dielectric layer and the second dielectric layer and adjacent to the composite layer, wherein the isolation layer, the first dielectric layer, and the second dielectric layer collectively have an opening extending from an upper surface of the second dielectric layer to a lower surface of the first dielectric layer. A first conductive layer is disposed between the isolation layer and the inner circuit layers and connects a ground portion of the inner circuit layers. A second conductive layer covers inner walls of the opening, wherein the isolation layer separates the second conductive layer from the first conductive layer, the second conductive layer, the isolation layer, and the first conductive layer form a coaxial via. An antenna layer is disposed on the upper surface of the second dielectric layer, wherein the antenna layer connects an upper end of the second conductive layer. A signal layer is disposed under the lower surface of the first dielectric layer, wherein a first portion of the signal layer connects a lower end of the second conductive layer. Further comprising:
2. The circuit board structure of claim 1, wherein, A first filling dielectric material is disposed in the opening. An upper surface of the first filling dielectric material is higher than the upper surface of the second dielectric layer, and a lower surface of the first filling dielectric material is lower than the lower surface of the first dielectric layer.
3. The circuit board structure of claim 2, wherein, The antenna layer covers the upper surface of the first filling dielectric material, and the signal layer covers the lower surface of the first filling dielectric material.
4. The circuit board structure of claim 2, wherein, Further comprising:
5. The circuit board structure of claim 1, wherein, A ground via penetrates the first dielectric layer, wherein the ground via is separated from the isolation layer, and wherein the ground via connects a second portion of the signal layer to the ground portion of the inner circuit layers. The isolation layer has opposite first and second side walls, the first side wall of the isolation layer contacts the second conductive layer, and the second side wall of the isolation layer contacts the ground portion of the inner circuit layers.
6. The circuit board structure of claim 5, wherein, Further comprising:
7. The circuit board structure of claim 5, wherein, A second filling dielectric material is disposed in the ground via. A dielectric constant of the isolation layer is lower than dielectric constants of the dielectric layers.
8. The circuit board structure of claim 1, wherein, The dielectric constant of the isolation layer is between 3 and 3.
5.
9. The circuit board structure of claim 8, wherein, The antenna layer has an antenna circuit that overlaps the coaxial via.
10. The circuit board structure of claim 1, wherein, Further comprising:
11. The circuit board structure of claim 1, wherein, A circuit is disposed on the upper end of the second conductive layer to connect an antenna. The composite layer includes a plurality of dielectric layers and a plurality of inner circuit layers disposed on surfaces of the dielectric layers.
12. A method of manufacturing a circuit board structure, characterized by: A first conductive layer is formed on an inner wall of the first opening, wherein the first conductive layer is electrically connected to the inner circuit layers. An isolation layer is filled in the first opening. A first dielectric layer is disposed under a lower surface of the composite layer. A signal layer is disposed under the first dielectric layer. A second dielectric layer is disposed on an upper surface of the composite layer. An antenna layer is disposed on the second dielectric layer. A second opening is formed in the first dielectric layer, the isolation layer, and the second dielectric layer. and A second conductive layer is formed on an inner wall of the second opening, wherein the second conductive layer connects the signal layer to the antenna layer, and the second conductive layer, the isolation layer and the first conductive layer form a coaxial via.
13. The method of claim 12, wherein, Further comprising: After forming the second conductive layer, patterning the signal layer; And After forming the second conductive layer, patterning the antenna layer.
14. The method of claim 12, wherein, Further comprising: In the second opening, a first filling dielectric material is formed.
15. The method of claim 12, wherein, Further comprising; A ground via is formed in the first dielectric layer to expose ground portions of the internal line layers; And A third conductive layer is formed in the ground via to connect the ground portions of the internal line layers.
16. The method of claim 15, wherein, Further comprising: In the ground via, a second filling dielectric material is formed.