Semiconductor device, manufacturing method thereof, read-write method and electronic equipment
By designing a semiconductor device with a 2T0C structure, the second gate of the second transistor extends into the first transistor, solving the problems of current crosstalk and leakage in integrated circuits, and achieving low-power and high-efficiency memory cell operation.
Patent Information
- Application Number
- CN202410605380.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-15
- Publication Date
- 2025-11-18
AI Technical Summary
In integrated circuits, as device size shrinks, the impact of minute differences on device performance becomes increasingly significant. The challenge lies in how to efficiently integrate more devices on a limited substrate while avoiding current crosstalk and leakage problems when reading memory cells.
The semiconductor device design employs a 2T0C structure, in which the second gate of the second transistor extends into the first gate of the first transistor to act as a gate for the memory cell. This avoids crosstalk between the current of the memory cell and other memory cells sharing the same bit line when reading the memory cell, and reduces leakage current through the control of the second transistor.
This achieves low leakage current, reduces the refresh frequency and power consumption of the storage cells, avoids current sharing issues, and improves the read efficiency and reliability of the storage cells.
Smart Images
Figure CN120980870A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a semiconductor device and a manufacturing method, a read-write method, and an electronic device thereof. BACKGROUND
[0002] With the development of integrated circuit technology, the critical dimension of a device is increasingly reduced, and the types and number of devices contained in a single chip are increased, so that any slight difference in the process production can affect the performance of the device.
[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY
[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0005] Embodiments of the present disclosure provide a semiconductor device, comprising at least one memory cell column, the memory cell column comprising a plurality of memory cells arranged at intervals along a column direction, the memory cell comprising a first transistor and a second transistor disposed on a substrate, the first transistor comprising a first gate electrode perpendicular to the substrate, a first semiconductor layer surrounding a side surface of the first gate electrode, and a first gate insulating layer disposed between the first gate electrode and the first semiconductor layer, the second transistor comprising a second gate electrode perpendicular to the substrate, a second semiconductor layer surrounding a side surface of the second gate electrode, and a second gate insulating layer disposed between the second gate electrode and the second semiconductor layer, one end of the second gate electrode extending into the first gate electrode from a side of the first gate electrode away from the substrate, and connected to an inner surface of the first gate electrode through the second gate insulating layer and the second semiconductor layer.
[0006] In an exemplary embodiment, a first hole extending in a direction perpendicular to the substrate is further included, the first semiconductor layer and the first gate insulating layer are sequentially disposed on an inner surface of the first hole, and the first gate electrode fills the first hole.
[0007] In an example embodiment, further comprising a source line disposed on the substrate, a second insulating layer disposed on a side of the source line distal to the substrate, a first bit line disposed on a side of the second insulating layer distal to the substrate, a third insulating layer disposed on a side of the first bit line distal to the substrate, the first hole extending along a direction towards the substrate from a surface of the third insulating layer distal to the substrate, sequentially penetrating the third insulating layer, the first bit line, the second insulating layer, and extending into the source line, the first hole exposing at least part of the first bit line and at least part of the source line, the first semiconductor layer on an inner surface of the first hole being connected with the first bit line and the source line exposed by the first hole.
[0008] In an example embodiment, the first hole forms a first recess at the source line, at least part of the first semiconductor layer covering a sidewall and a bottom wall of the first recess.
[0009] In an example embodiment, a projection of the first hole on the substrate is located in a projection of the source line and the first bit line on the substrate.
[0010] In an example embodiment, further comprising a second hole extending along a direction perpendicular to the substrate, one end of the second hole being located on a side of the first gate distal to the substrate and extending into the first gate, the second semiconductor layer and the second gate insulating layer being sequentially disposed on an inner surface of the second hole, the second gate filling the second hole and extending into the first gate.
[0011] In an example embodiment, the second hole forms a second recess at the first gate, the second semiconductor layer and the second gate insulating layer being sequentially disposed on an inner surface of the second recess, the second gate filling the second recess and extending into the first gate.
[0012] In an example embodiment, further comprising a fourth insulating layer disposed on a side of the first gate distal to the substrate, a second bit line disposed on a side of the fourth insulating layer distal to the substrate, a fifth insulating layer disposed on a side of the second bit line distal to the substrate, the second hole extending along a direction towards the substrate from a surface of the fifth insulating layer distal to the substrate, sequentially penetrating the fifth insulating layer, the second bit line, and the fourth insulating layer, and extending into the first gate, the second hole exposing at least part of the second bit line and an inner surface of at least part of the first gate, the second semiconductor layer on an inner surface of the second hole being connected with the second bit line and the inner surface of the first gate exposed by the second hole.
[0013] In an example embodiment, a plurality of word lines are further included, disposed on a side of the second gate distal to the substrate, one of the word lines connected to the second gate of one of the memory cells in one of the columns of memory cells.
[0014] In an example embodiment, a projection of the second recess on the substrate is located in a projection of the first gate on the substrate.
[0015] In an example embodiment, a projection of the second hole on the substrate is located in a projection of the second bit line on the substrate.
[0016] In an example embodiment, the memory cells of each of the columns of memory cells share one of the first bit lines.
[0017] Embodiments of the present disclosure further provide a method for manufacturing a semiconductor device, comprising:
[0018] forming a source line and a first bit line on a substrate in sequence;
[0019] forming a first hole on the substrate, the first hole extending along a direction perpendicular to the substrate, the first hole at least penetrating the first bit line and extending into the source line, the first hole exposing the first bit line and the source line;
[0020] forming a first semiconductor layer and a first gate insulating layer on an inner surface of the first hole in sequence, the first hole being filled by a first gate, the first semiconductor layer surrounding a side surface of the first gate through the first gate insulating layer, the first semiconductor layer connected to the first bit line and the source line exposed by the first hole;
[0021] forming a second bit line on a side of the first gate distal to the substrate;
[0022] forming a second hole on the substrate, the second hole extending along a direction perpendicular to the substrate, the second hole at least penetrating the second bit line and extending into the first gate, the second hole exposing the second bit line and an inner surface of the first gate;
[0023] forming a second semiconductor layer and a second gate insulating layer on an inner surface of the second hole in sequence, the second hole being filled by a second gate, the second semiconductor layer surrounding a side surface of the second gate through the second gate insulating layer, the second semiconductor layer connected to the second bit line exposed by the second hole and the inner surface of the first gate, one end of the second gate in the second hole being distal to the substrate and extending into the first gate through the second gate insulating layer and the second semiconductor layer, and connected to the inner surface of the first gate.
[0024] The semiconductor device is also provided by the embodiment of the present disclosure.
[0025] The semiconductor device is also provided by the embodiment of the present disclosure.
[0026] In the data writing stage, an opening voltage is applied to the second gate of the memory cell in the memory cell column to be written, so as to open the second transistor of the memory cell; the charge information corresponding to the data to be written is written into the memory cell through the second bit line of the second transistor; and the second gate of the second transistor is used as the gate of the first transistor, so as to keep the first transistor of the memory cell in an open state through the second gate.
[0027] In the data reading stage, a reference voltage is applied to the source line corresponding to the first transistor of the memory cell in the memory cell column to be read, so as to read the charge information in the memory cell; and a closing voltage is applied to the second gate of the other memory cells in the memory cell column, so as to keep the other memory cells in a closed state.
[0028] The semiconductor device of the embodiment of the present disclosure makes the second gate of the second transistor extend into the first gate of the first transistor, so that the second transistor serves as a switch of the memory cell, and the current of the memory cell to be read and the current of the other memory cells sharing the same bit line do not interfere with each other.
[0029] The semiconductor device of the embodiment of the present disclosure includes the first transistor and the second transistor, forms a 2T0C structure, has low leakage, does not need to additionally set a back gate or a capacitor, and reduces the refresh frequency and power consumption of the memory cell.
[0030] The semiconductor device of the embodiment of the present disclosure makes the second gate of the second transistor extend into the first gate of the first transistor, so that the second semiconductor layer of the second transistor extends into the first gate of the first transistor and directly contacts the inner surface of the first gate, increases the contact area between the second semiconductor layer and the first gate, makes the second transistor serve as a switch of the memory cell to realize the writing of the memory cell in the writing, and makes the second transistor serve as a switch of the memory cell to avoid the current interference between the memory cell to be read and the other memory cells sharing the same first bit line in the reading.
[0031] The reading and writing method of the semiconductor device of the embodiment of the present disclosure makes the second gate of the second transistor serve as the gate of the first transistor, can close the second transistor of the other memory cells in the reading of a specific memory cell, reduces the potential of the first transistor of the other memory cells, and thus makes the first transistor of the other memory cells closed, so as to solve the current sharing problem.
[0032] Other features and advantages of the present application will be set forth in the following specification, and in part will be apparent from the description, or can be learned by practice of the application. The objects and advantages of the application can be realized and attained by the structure particularly pointed out in the specification.
[0033] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS
[0034] The accompanying drawings are included to provide a further understanding of the present technology, and constitute a part of this specification that is included to illustrate the embodiments of the present technology and to explain the principles of the present technology, and do not limit the present technology in any way.
[0035] Figure 1 Equivalent circuit diagram of a memory cell in a semiconductor device according to an exemplary embodiment;
[0036] Figure 2 Equivalent circuit diagram of a semiconductor device according to an exemplary embodiment;
[0037] Figure 3 Structure schematic diagram of a semiconductor device according to an exemplary embodiment;
[0038] Figure 4 Cross-sectional structure schematic of a semiconductor device according to an exemplary embodiment Figure 1 ;
[0039] Figure 5 Cross-sectional structure schematic of a semiconductor device according to an exemplary embodiment Figure 2 ;
[0040] Figure 6a Cross-sectional structure schematic of a semiconductor device according to an exemplary embodiment
[0041] Figure 6b Cross-sectional structure schematic of a semiconductor device according to an exemplary embodiment
[0042] Figure 6c Cross-sectional structure schematic of a semiconductor device according to an exemplary embodiment
[0043] Figure 6d Cross-sectional structure schematic of a semiconductor device according to an exemplary embodiment
[0044] Figure 7a Structure schematic of a semiconductor device according to an exemplary embodiment after forming a source line and a first bit line;
[0045] Figure 7b Cross-sectional structure schematic of a semiconductor device according to an exemplary embodiment after forming a source line and a first bit line;
[0046] Figure 8a Structure diagram of a semiconductor device after forming a first hole according to an embodiment of the present disclosure;
[0047] Figure 8b Longitudinal section structure diagram of a semiconductor device after forming a first hole according to an embodiment of the present disclosure;
[0048] Figure 9a Structure diagram of a semiconductor device after forming a first semiconductor layer, a first gate insulating layer and a first gate according to an embodiment of the present disclosure;
[0049] Figure 9b Longitudinal section structure diagram of a semiconductor device after forming a first semiconductor layer, a first gate insulating layer and a first gate according to an embodiment of the present disclosure;
[0050] Figure 10a Structure diagram of a semiconductor device after forming a second bit line according to an embodiment of the present disclosure;
[0051] Figure 10b Longitudinal section structure diagram of a semiconductor device after forming a second bit line according to an embodiment of the present disclosure;
[0052] Figure 11a Structure diagram of a semiconductor device after forming a second hole according to an embodiment of the present disclosure;
[0053] Figure 11b Longitudinal section structure diagram of a semiconductor device after forming a second hole according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0054] The embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.
[0055] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings thereof by those having ordinary skills in the art to which the present disclosure belongs.
[0056] The embodiments of the present disclosure are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.
[0057] The ordinal numbers "first", "second", "third" and the like in the present disclosure are set in order to avoid confusion of the constituent elements, and do not represent any order, number or importance.
[0058] In the present disclosure, the words of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to refer to the positional relationship of the components with reference to the drawings for the purpose of convenience and simplicity of the description and the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.
[0059] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connect", "connection" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.
[0060] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.
[0061] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity, or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.
[0062] In the present disclosure, "electrically connected" includes the case where the components are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
[0063] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, a state in which two straight lines form an angle of -10° or more and 10° or less, and thus, a state in which the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means approximately perpendicular, for example, a state in which two straight lines form an angle of 80° or more and 100° or less, and thus, a state in which the angle is 85° or more and 95° or less is also included.
[0064] In the present disclosure, "film" and "layer" can be exchanged with each other. For example, "conductive layer" can be sometimes replaced with "conductive film". Similarly, "insulating film" can be sometimes replaced with "insulating layer".
[0065] In the present disclosure, "A and B are provided in the same layer" means that A and B are formed at the same time by the same patterning process. "The orthogonal projection of B is within the orthogonal projection of A" means that the boundary of the orthogonal projection of B falls within the boundary of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.
[0066] In the present disclosure, "A and B are provided in the same layer" means that A and B are formed at the same time by the same patterning process. "The orthogonal projection of B is within the orthogonal projection of A" means that the boundary of the orthogonal projection of B falls within the boundary of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.
[0067] A semiconductor device according to an embodiment of the present disclosure includes at least one memory cell column disposed on a substrate, the memory cell column including a plurality of memory cells spaced apart along a column direction, the memory cell including a first transistor and a second transistor, the first transistor including a first gate electrode perpendicular to the substrate, a first semiconductor layer surrounding a side surface of the first gate electrode, and a first gate insulating layer disposed between the first gate electrode and the first semiconductor layer, the second transistor including a second gate electrode perpendicular to the substrate, a second semiconductor layer surrounding a side surface of the second gate electrode, and a second gate insulating layer disposed between the second gate electrode and the second semiconductor layer, one end of the second gate electrode being extended into the first gate electrode from a side of the first gate electrode away from the substrate, and the second semiconductor layer being connected to an inner surface of the first gate electrode.
[0068] The semiconductor device according to the present disclosure will be described below with reference to some exemplary embodiments.
[0069] Figure 1 An equivalent circuit diagram of a memory cell in a semiconductor device according to an exemplary embodiment is provided. In an exemplary embodiment, as shown in FIG. 1, a memory cell 100 includes a first transistor 110 and a second transistor 120. The first transistor 110 includes a first gate electrode 111, a first semiconductor layer 112 surrounding a side surface of the first gate electrode 111, and a first gate insulating layer 113 disposed between the first gate electrode 111 and the first semiconductor layer 112. The second transistor 120 includes a second gate electrode 121, a second semiconductor layer 122 surrounding a side surface of the second gate electrode 121, and a second gate insulating layer 123 disposed between the second gate electrode 121 and the second semiconductor layer 122. One end of the second gate electrode 121 is extended into the first gate electrode 111 from a side of the first gate electrode 111 away from the substrate, and the second semiconductor layer 122 is connected to an inner surface of the first gate electrode 111. Figure 1As shown, this disclosure provides a semiconductor device including at least one memory cell. The memory cell can be a 2TOC structure and may include: a first bit line 11, a second bit line 12, a word line WL, a source line 10, a first transistor T1, and a second transistor T2. The first transistor T1 can be configured as a read transistor, and includes a first terminal, a second terminal, and a first gate. One of the first and second terminals serves as the source of the first transistor T1, and the other of the first and second terminals serves as the drain of the first transistor T1. For example, the first terminal of the first transistor T1 serves as the source and is connected to the source line 10, and the second terminal of the first transistor T1 serves as the drain and is connected to the first bit line 11. The second transistor T2 can be configured as a write transistor, and includes a third terminal, a fourth terminal, and a second gate. One of the third and fourth terminals serves as the source of the second transistor T2, and the other of the third and fourth terminals serves as the drain of the second transistor T2. For example, the third terminal of the second transistor T2 serves as the drain and is connected to the second bit line 12, and the fourth terminal of the second transistor T2 serves as the source and is connected to the first gate of the first transistor T1. The second gate of the second transistor T2 is configured to be connected to the word line WL.
[0070] Figure 2 An equivalent circuit diagram of a semiconductor device is provided for an exemplary embodiment. In an exemplary embodiment, as shown... Figure 2 As shown, the semiconductor device in this embodiment includes at least one column of memory cells. The column of memory cells includes a first memory cell P1, a second memory cell P2, and a third memory cell P3 arranged at intervals along the column direction. The first memory cell P1, the second memory cell P2, and the third memory cell P3 can share a first bit line 11, a second bit line 12, and a source line 10. The second terminals of the first transistor T1 of the first memory cell P1, the first transistor T1 of the second memory cell P2, and the first transistor T1 of the third memory cell P3 are all connected to a first bit line 11. The third terminals of the second transistor T2 of the first memory cell P1, the second transistor T2 of the second memory cell P2, and the second transistor T2 of the third memory cell P3 are all connected to a second bit line 12. The first terminals of the first transistor T1 of the first memory cell P1, the first transistor T1 of the second memory cell P2, and the first transistor T1 of the third memory cell P3 are all connected to a source line 10.
[0071] When the first memory cell P1 performs a write operation, the second transistor T2 of the first memory cell P1 acts as a switch to write a bit to either 0 or 1. When the first memory cell P1 performs a read operation, the second transistor T2 of the first memory cell P1 acts as a selector for the first transistor T1 of the first memory cell P1. No bias voltage is applied to the second gate of the second transistor T2 of the first memory cell P1, so that the second transistor T2 of the first memory cell P1 is turned on and the information of the first memory cell P1 is read. At the same time, a negative bias voltage is applied to the second gate of the second transistor T2 of the second memory cell P2 and the third memory cell P3, so that the second transistor T2 of the second memory cell P2 and the third memory cell P3 are both turned off, so as to avoid the second memory cell P2 and the third memory cell P3 sharing the current of the first memory cell P1 and to prevent the current of the first memory cell P1 from causing crosstalk to the second memory cell P2 and the third memory cell P3.
[0072] In one exemplary embodiment, each storage cell in the storage cell column shares the first bit line 11.
[0073] In this embodiment of the semiconductor device, the second gate of the second transistor extends into the first gate of the first transistor, so that the second transistor acts as a gate for the memory cell, thereby avoiding crosstalk between the current of the memory cell being read and other memory cells sharing the same bit line when reading the memory cell.
[0074] Figure 3 A schematic diagram of the structure of a semiconductor device provided as an exemplary embodiment; Figure 4 A schematic cross-sectional structure of a semiconductor device provided for an exemplary embodiment. Figure 1 ; Figure 5 A schematic cross-sectional structure of a semiconductor device provided for an exemplary embodiment. Figure 2 ;in, Figure 3 It can be Figure 5 A sectional view along the a-a' direction. Figure 3 It can be Figure 3 A cross-sectional view along the b-b' direction. In an exemplary embodiment, as shown... Figure 4 , Figure 5 and Figure 6aAs shown, the semiconductor device according to embodiments of the present disclosure can include a first insulating layer 51 disposed on a substrate 101, a source line 10 disposed on a side of the first insulating layer 51 distal from the substrate 101, a second insulating layer 52 disposed on a side of the source line 10 distal from the substrate 101, a first bit line 11 disposed on a side of the second insulating layer 52 distal from the substrate 101, a third insulating layer 53 disposed on a side of the first bit line 11 distal from the substrate 101, a fourth insulating layer 54 disposed on a side of the third insulating layer 53 distal from the substrate 101, a second bit line 12 disposed on a side of the fourth insulating layer 54 distal from the substrate 101, a fifth insulating layer 55 disposed on a side of the second bit line 12 distal from the substrate 101, a word line WL disposed on a side of the fifth insulating layer 55 distal from the substrate 101, and a sixth insulating layer 56 disposed between adjacent word lines WL.
[0075] In an exemplary embodiment, the substrate can be a semiconductor substrate, such as a silicon substrate. The silicon substrate can be a substrate on which a peripheral circuit is fabricated.
[0076] In an exemplary embodiment, the semiconductor device according to embodiments of the present disclosure further includes a first transistor, which can be configured as a read transistor. The first transistor includes a first gate 22 extending in a direction perpendicular to the substrate 101, a first semiconductor layer 21 surrounding a side surface of the first gate 22 and insulated from the first gate 22, and a first gate insulating layer 23 disposed between the first gate 22 and the first semiconductor layer 21.
[0077] In an exemplary embodiment, the semiconductor device can further include a first hole 41 extending in a direction perpendicular to the substrate 101. The first hole 41 extends from a surface of the third insulating layer 53 distal from the substrate 101, in a direction close to the substrate 101, sequentially through the third insulating layer 53, the first bit line 11, and the second insulating layer 52, and into the source line 10. The first hole 41 exposes a side wall of the first bit line 11, and does not completely pass through the source line 10, forming a first recess 43 at the source line 10.
[0078] In some embodiments, the first hole can extend from a surface of the third insulating layer distal from the substrate, in a direction perpendicular to the substrate, sequentially through the third insulating layer, the first bit line, and the second insulating layer, and to a surface of the source line distal from the substrate.
[0079] In an exemplary embodiment, the main part of the first gate 22 fills the first hole 41, and the main part of the first gate 22 is connected to the inner surface of the first hole 41 through the first gate insulating layer 23 and the first semiconductor layer 21. At least part of the first gate 22 fills the first recess 43, and the main part of the first gate 22 is connected to the inner surface of the first recess 43 through the first gate insulating layer 23 and the first semiconductor layer 21. The main part of the first gate 22 is linear along the direction perpendicular to the substrate 101. The top end of the main part of the first gate 22 is provided with a first extension part extending along the direction parallel to the substrate 101, and the first extension part is arranged on the side of the third insulating layer 53 away from the substrate 101.
[0080] In an exemplary embodiment, the first gate 22 extends along the direction perpendicular to the substrate. The first gate 22 includes a side surface perpendicular to the substrate and end surfaces parallel to the substrate at the upper and lower ends thereof, and the side surface is perpendicular to the substrate 101 as a whole. The side surface may, in actual production, have a locally curved region, which is also included in the above-mentioned case.
[0081] In an exemplary embodiment, the inner surface of the first hole 41 is sequentially provided with the first semiconductor layer 21 and the first gate insulating layer 23. The main part of the first semiconductor layer 21 covers the inner surface of the first hole 41, and at least part of the first semiconductor layer 21 covers the side wall and the bottom wall of the first recess 43. The main part of the first semiconductor layer 21 includes at least a side wall perpendicular to the substrate and a bottom wall at the end of the side wall close to the substrate. The inner surface of the side wall of the first semiconductor layer 21 surrounds the side surface of the first gate 22 through the first gate insulating layer 23, and the inner surface of the bottom wall of the first semiconductor layer 21 is connected to the bottom of the first gate 22 through the first gate insulating layer 23. The outer surface of the side wall of the first semiconductor layer 21 directly contacts the inner surface of the first hole 41. The first semiconductor layer 21 covers the side wall and the bottom wall of the first recess. The first semiconductor layer 21 can be understood as a film layer. The inner surface of the side wall of the first semiconductor layer 21 extends along the outer surface of the first gate 22, and the thickness direction of the side wall of the first semiconductor layer 21 is parallel to the substrate.
[0082] The inner surface of the side wall of the first semiconductor layer 21 surrounds the side surface of the first gate 22 through the first gate insulating layer 23, which can be understood as that the side wall of the first semiconductor layer 21 surrounds the side surface of the first gate 22 in whole or in part. In some embodiments, the surrounding can be in whole, and the cross section of the first semiconductor layer 21 after the surrounding is a closed ring. The cross section is taken along the direction parallel to the substrate. In some embodiments, the surrounding can be in part, and the cross section after the surrounding is not closed but presents a ring shape, for example, an open ring.
[0083] In an example embodiment, the outer surface of the first semiconductor layer 21 includes a first contact region and a second contact region, the first contact region is located on a side of the second contact region close to the substrate 101, the first contact region is an end of the first semiconductor layer 21 close to the substrate, and the first contact region of the outer surface of the first semiconductor layer 21 directly contacts the inner wall of the first recess 43 in the source line 10; the second contact region is a middle region of the first semiconductor layer 21, and the second contact region is located on a side of the first contact region away from the substrate 101, and the second contact region of the outer surface of the first semiconductor layer 21 directly contacts the first bit line 11 exposed by the first hole 41.
[0084] In an example embodiment, the first gate insulating layer 23 is arranged between the first semiconductor layer 21 and the first gate 22 to separate the first semiconductor layer 21 and the first gate 22.
[0085] In an example embodiment, the semiconductor device of the present disclosure further includes a second transistor, which can be arranged as a write transistor. The second transistor includes a second gate 32 extending in a direction perpendicular to the substrate 101, a second semiconductor layer 31 surrounding and insulated from the second gate 32, and a second gate insulating layer 33 arranged between the second gate 32 and the second semiconductor layer 31.
[0086] In an example embodiment, the semiconductor device can further include a second hole 42 extending in a direction perpendicular to the substrate 101. The second hole 42 extends from the surface of the fifth insulating layer 55 away from the substrate 101 in a direction close to the substrate 101, successively penetrates the fifth insulating layer 55, the second bit line 12, and the fourth insulating layer 54, and extends into the first gate 22. The second hole 42 does not completely penetrate the first gate 22, and forms a second recess 44 at the first gate 22. The second hole 42 exposes at least part of the second bit line 12, and the second recess 44 exposes at least part of the inner surface of the first gate 22. The side wall and the bottom wall of the second recess 44 are both the inner surface of the first gate 22.
[0087] In an example embodiment, the second recess 44 has a projection on the substrate 101, and the projection is located in the projection of the first gate 22 on the substrate 101.
[0088] In some embodiments, the bottom wall of the second recess can extend to the first gate insulating layer, and the bottom wall of the second recess can be the first gate insulating layer.
[0089] In an example embodiment, the second recess has a projection on the substrate 101, and the projection is located in the projection of the first gate on the substrate 101.
[0090] In an exemplary embodiment, a main portion of the second gate 32 is filled in the second hole 42, and the main portion of the second gate 32 is connected to an inner surface of the second hole 42 through the second gate insulating layer 33 and the second semiconductor layer 31. At least a portion of the second gate 32 is filled in the second recess 44, and at least a portion of the second gate 32 is connected to an inner surface of the second recess 44 through the second gate insulating layer 33 and the second semiconductor layer 31. That is, at least a portion of the second gate 32 is connected to an inner surface of the first gate 22 exposed by the second recess 44 through the second gate insulating layer 33 and the second semiconductor layer 31.
[0091] In an exemplary embodiment, a main portion of the second gate 32 is in a linear shape extending in a direction perpendicular to the substrate 101. A top end of the main portion of the second gate 32 is provided with a second extension extending in a direction parallel to the substrate 101, and the second extension is provided on a side of the fifth insulating layer 55 away from the substrate 101. A bottom end of the main portion of the second gate 32 is on a side of the first gate away from the substrate, and extends into the second recess 44 in the first gate.
[0092] In an exemplary embodiment, the second gate 32 extends only in a direction perpendicular to the substrate. The second gate 32 includes a side surface perpendicular to the substrate and end surfaces parallel to the substrate at both upper and lower ends thereof, and the side surface is perpendicular to the substrate 101 as a whole. A locally curved region of the side surface in an actual product manufacturing process is also included in the above-described case.
[0093] In an exemplary embodiment, an inner surface of the second hole 42 is provided with the second semiconductor layer 31 and the second gate insulating layer 33 in sequence. An inner surface of the second recess 44 is provided with the second semiconductor layer 31 and the second gate insulating layer 33 in sequence. The second gate 32 is filled in the second recess 44 and extends into the first gate.
[0094] In an exemplary embodiment, a main portion of the second semiconductor layer 31 is located in the second hole 42, and at least a portion of the second semiconductor layer 31 is located in the second recess 44, and at least a portion of the second semiconductor layer 31 directly contacts an inner surface of the first gate 22 exposed by the second recess 44. The main portion of the second semiconductor layer 31 includes a side wall perpendicular to the substrate and a bottom wall located at an end of the side wall close to the substrate. An inner surface of the side wall of the second semiconductor layer 31 surrounds a side surface of the second gate 32 through the second gate insulating layer 33, and an inner surface of the bottom wall of the second semiconductor layer 31 is connected to a bottom of the second gate 32 through the second gate insulating layer 33.
[0095] In an example embodiment, an outer surface of the sidewall of the second semiconductor layer 31 directly contacts a sidewall of the second hole 42, an outer surface of at least part of the sidewall of the second semiconductor layer 31 directly contacts a sidewall of the second recess 44, and an outer surface of the bottom wall of the second semiconductor layer 31 directly contacts a bottom wall of the second recess 44. The second semiconductor layer 31 can be understood as a film layer. An inner surface of the sidewall of the second semiconductor layer 31 extends along an outer surface of the second gate 32, and a thickness direction of the sidewall of the second semiconductor layer 31 is parallel to the substrate.
[0096] The inner surface of the sidewall of the second semiconductor layer 31 can be understood as that the sidewall of the second semiconductor layer 31 surrounds the side surface of the second gate 32 through the second gate insulating layer 33. In some embodiments, the surrounding can be overall surrounding, and a cross section of the second semiconductor layer 31 after the surrounding is a closed ring shape. The cross section is taken along a direction parallel to the substrate. In some embodiments, the surrounding can be partial surrounding, and the cross section after the surrounding is not closed but presents a ring shape, for example, a ring shape with an opening.
[0097] In an example embodiment, the outer surface of the second semiconductor layer 31 includes a third contact region and a fourth contact region. The third contact region is located in the second recess 44 and directly contacts an inner wall of the second recess 44. At least part of the third contact region directly contacts an inner surface of the first gate 22 exposed by the second recess 44. The fourth contact region is located on a side of the third contact region away from the substrate 101, and the fourth contact region directly contacts the second bit line 12 exposed by the second hole 42.
[0098] In an example embodiment, the second gate insulating layer 33 is arranged between the second semiconductor layer 31 and the second gate 32 to separate the second semiconductor layer 31 from the second gate 32.
[0099] In an example embodiment, a word line WL is arranged on a side of the second gate 32 away from the substrate 101, and the word line WL is connected to the second gate.
[0100] In an example embodiment, the material of the first gate 22 and the second gate 32 can include, but is not limited to, at least one of the following: Indium Tin Oxide (ITO), metal tungsten, titanium nitride, titanium-aluminum alloy, tantalum nitride, Aluminum doped Zinc Oxide (AZO), and Indium Zinc Oxide (IZO).
[0101] In an exemplary embodiment, the material of the first semiconductor layer 21 and the second semiconductor layer 31 can be metal oxide. The material of the metal oxide can be Indium Gallium Zinc Oxide (IGZO). When the material of the metal oxide is IGZO, the leakage current of the transistor 11 is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In203, InWO, Sn02, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.
[0102] In an exemplary embodiment, the material of the first gate insulating layer 23 and the second gate insulating layer 33 can be high-K dielectric material. For example, the high-K dielectric material can include, but is not limited to, at least one of the following: aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide. In some embodiments, the material of the second gate insulating layer 33 can be low-K material, for example, silicon dioxide.
[0103] In an exemplary embodiment, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, the fourth insulating layer 54, the fifth insulating layer 55, and the sixth insulating layer 56 can all be silicon oxide, such as silicon dioxide (Si02) and the like.
[0104] In an exemplary embodiment, the first insulating layer 51 is disposed between the substrate 101 and the source line 10. The second insulating layer 52 is disposed between the first insulating layer 51 and the third insulating layer 53, and at least part of the second insulating layer 52 is disposed between adjacent source lines 10 and between the first semiconductor layers 21 of adjacent first transistors. The third insulating layer 53 is disposed between the second insulating layer 52 and the fourth insulating layer 54, and at least part of the third insulating layer 53 is disposed between adjacent first bit lines 11 and between the first semiconductor layers 21 of adjacent first transistors. The fourth insulating layer 54 is disposed between the third insulating layer 53 and the fifth insulating layer 55, and at least part of the fourth insulating layer 54 is disposed between the first gates 22 of adjacent first transistors. The fifth insulating layer 55 is disposed between the fourth insulating layer 54 and the sixth insulating layer 56, and at least part of the fifth insulating layer 55 is disposed between adjacent second bit lines 12 and between the second semiconductor layers 31 and the second gates 32 of adjacent second transistors. The sixth insulating layer 56 is disposed on the surface of the fifth insulating layer 55 away from the substrate 101, and at least part of the sixth insulating layer 56 is disposed between adjacent word lines WL.
[0105] The semiconductor device of the embodiment of the present disclosure includes the first transistor and the second transistor, forms a 2T0C structure, has lower leakage current, and does not need to additionally dispose a back gate or a capacitor, thereby reducing the refresh frequency and power consumption of the memory cell.
[0106] The semiconductor device of the embodiment of the present disclosure makes the second gate of the second transistor extend into the first gate of the first transistor, makes the second semiconductor layer of the second transistor extend into the first gate of the first transistor, and directly contact the inner surface of the first gate, thereby increasing the contact area between the second semiconductor layer and the first gate. In the writing, the second transistor is used as a switch of the memory cell, thereby realizing the writing of the memory cell. In the reading, the second transistor is used as a selector of the memory cell, thereby avoiding the current interference between the memory cell to be read and other memory cells sharing the same first bit line.
[0107] Compared with the memory cell using a back gate or a capacitor, the memory cell of the semiconductor device of the embodiment of the present disclosure has a simple structure, a smaller device size, and a higher density.
[0108] Figure 6a A sectional structure diagram of a source line of a semiconductor device is provided for an exemplary embodiment; wherein, Figure 3 may be Figure 6a A sectional view in the c-c' direction. In an exemplary embodiment, as Figure 6bAs shown, in this embodiment of the semiconductor device, the source line 10 is linear, extending along a first direction D1, and multiple source lines 10 are spaced apart along a second direction D2. The orthogonal projection of the first groove 43 onto the substrate includes a circular shape. The orthogonal projection of the first groove 43 onto the substrate is located within the orthogonal projection of the source line 10 onto the substrate. The diameter of the first groove 43 is smaller than the linewidth of the source line 10, and the linewidth of the source line 10 is its length along the second direction D2. Multiple first grooves 43 are spaced apart along the first direction D1 within the source line 10. Both the first direction D1 and the second direction D2 are parallel to the substrate 101, and the first direction D1 and the second direction D2 intersect each other. For example, the first direction D1 and the second direction D2 are perpendicular to each other.
[0109] Figure 6b A cross-sectional view of the first line of a semiconductor device provided for an exemplary embodiment; wherein, Figure 3 It can be Figure 6b A cross-sectional view along the d-d' direction. In an exemplary embodiment, as shown... Figure 6c As shown, in this embodiment of the semiconductor device, the first line 11 is linear, extending along a first direction D1, and a plurality of first lines 11 are spaced apart along a second direction D2. The orthographic projection of the first hole 41 onto the substrate includes a circular shape, and the orthographic projection of the first hole 41 onto the substrate is located within the orthographic projection of the first line 11 onto the substrate. The diameter of the first hole 41 is smaller than the linewidth of the first line 11, and the linewidth of the first line 11 is its length along the second direction D2. A plurality of first holes 41 are spaced apart within the first line 11 along the first direction D1. The orthographic projection of the second groove 44 onto the substrate includes a circular shape, and the orthographic projection of the second groove 44 onto the substrate is located within the orthographic projection of the first line 11 onto the substrate. The diameter of the second groove 44 is smaller than the linewidth of the first line 11, and a plurality of second grooves 44 are spaced apart within the first line 11 along the first direction D1.
[0110] Figure 6c A cross-sectional view of the second bit line of a semiconductor device provided as an exemplary embodiment; wherein... Figure 3 It can be Figure 6c A cross-sectional view along the e-e' direction. In an exemplary embodiment, as shown... Figure 6dAs shown, the second bit line 12 of the semiconductor device of the embodiment of the present disclosure is in a linear shape, the second bit line 12 extends along the first direction D1, and a plurality of second bit lines 12 are arranged along the second direction D2 at intervals.
[0111] Figure 6d A cross-sectional structure diagram of a word line of a semiconductor device is provided for an exemplary embodiment; wherein, Figure 3 may be Figure 6d A cross-sectional view in the f-f' direction. In an exemplary embodiment, as Figure 7a As shown, the word line WL of the semiconductor device of the embodiment of the present disclosure is in a linear shape, the word line WL extends along the second direction D2, and a plurality of word lines WL are arranged along the first direction D1 at intervals.
[0112] In an exemplary embodiment, the source line 10, the first bit line 11, the second bit line 12, and the word line WL can all be made of a material with low resistivity, such as titanium nitride (TiN), tungsten, molybdenum, etc.
[0113] The technical solution of the embodiment will be further described below through the manufacturing process of the semiconductor device of the embodiment. The "patterning process" mentioned in the embodiment includes deposition of a film layer, coating photoresist, mask exposure, development, etching, stripping photoresist, etc., which are mature manufacturing processes in the related art. The "photolithography process" mentioned in the embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not specifically limited here. In the description of the embodiment, it should be understood that "thin film" refers to a thin film of a certain material made on a substrate using deposition or coating processes. If the "thin film" does not need to be patterned or photolithographed during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still needs to be patterned or photolithographed during the entire manufacturing process, it is referred to as a "thin film" before patterning, and a "layer" after patterning. The "layer" after patterning or photolithography includes at least one "pattern".
[0114] In an exemplary embodiment, the semiconductor device can be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device can include:
[0115] Step 101, forming a source line and a first bit line.
[0116] In an example embodiment, forming the source lines and the first bit lines can include: sequentially depositing the first insulating layer 51, the first conductive film, the second insulating layer 52, the second conductive film and the third insulating layer 53 on the substrate 101 to form a stack structure; then, forming first grooves extending along a direction perpendicular to the substrate 101 in the stack structure by an etching process, the first grooves sequentially penetrating through the third insulating layer 53, the second conductive film, the second insulating layer 52, the first conductive film and the first insulating layer 51, so that the first conductive film forms the source lines 10 and the second conductive film forms the first bit lines 11, the first grooves extending along the first direction D1 and being located between adjacent source lines 10 and between adjacent first bit lines 11; then, filling the first grooves with an insulating material and polishing the insulating material, as shown in Figure 7b and Figure 7a wherein, Figure 7b is a schematic diagram of a structure of a semiconductor device after forming source lines and first bit lines according to an embodiment of the present disclosure; Figure 8a is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor device after forming source lines and first bit lines according to an embodiment of the present disclosure.
[0117] In an example embodiment, the first insulating layer 51, the first conductive film, the second insulating layer 52, the second conductive film and the third insulating layer 53 can be deposited by a chemical vapor deposition method (CVD), an atomic layer deposition method (ALD) or a physical vapor deposition method (PVD).
[0118] Step 102, forming first holes.
[0119] In an example embodiment, forming the first holes includes: on the basis of the substrate 101 with the foregoing pattern, forming first holes 41 extending along a direction perpendicular to the substrate 101 in the stack structure by a photolithography process, the first holes 41 penetrating through the third insulating layer 53, the first bit lines 11 and the second insulating layer 52 from a surface of the third insulating layer 53 away from the substrate 101 and extending into the source lines 10, the first holes 41 not penetrating through the source lines 10 completely and forming first recesses 43 at the source lines 10, as shown in Figure 8b and Figure 8a wherein, Figure 8b is a schematic diagram of a structure of a semiconductor device after forming first holes according to an embodiment of the present disclosure; Figure 9a is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor device after forming first holes according to an embodiment of the present disclosure.
[0120] Step 103, forming a first semiconductor layer, a first gate insulating layer and a first gate.
[0121] In an exemplary embodiment, forming the first semiconductor layer, the first gate insulating layer and the first gate includes: on the basis of the substrate 101 formed with the aforementioned pattern, using an atomic layer deposition process (ALD), depositing a first semiconductor thin film and a first gate insulating thin film on the stack structure in sequence, the first semiconductor thin film directly covering the inner wall of the first hole 41, the first gate insulating thin film covering the inner wall of the first hole 41 through the first semiconductor thin film, the first semiconductor thin film being in direct contact with the first bit line 11 and the source line 10 exposed by the first hole 41; then, using a chemical deposition process, depositing a third conductive thin film on the stack structure, the third conductive thin film filling the first hole 41; then, through an etching process, etching and removing the first semiconductor thin film, the first gate insulating thin film and the third conductive thin film on the surface of the stack structure, retaining the first semiconductor thin film, the first gate insulating thin film and the third conductive thin film in the first hole 41 and at the edge of the opening of the first hole 41, so that the first semiconductor thin film forms the first semiconductor layer 21, the first gate insulating thin film forms the first gate insulating layer 23, and the third conductive thin film forms the first gate 22, at least part of the first gate 22 filling the first hole 41, as shown in Figure 9b and Figure 9a wherein, Figure 9b is a structural schematic diagram of the semiconductor device after forming the first semiconductor layer, the first gate insulating layer and the first gate according to the embodiment of the present disclosure;
[0122] Figure 10a is a longitudinal sectional structural schematic diagram of the semiconductor device after forming the first semiconductor layer, the first gate insulating layer and the first gate according to the embodiment of the present disclosure.
[0123] Step 104, forming a second bit line.
[0124] In an exemplary embodiment, forming the second bit line can include: on the basis of the substrate 101 formed with the aforementioned pattern, depositing a fourth insulating layer 54, a fourth conductive thin film and a fifth insulating layer 55 on the stack structure in sequence; then, through an etching process, forming a second groove extending along a direction perpendicular to the substrate 101, the second groove penetrating the fifth insulating layer 55, the fourth conductive thin film and the fourth insulating layer 54 in sequence, so that the fourth conductive thin film forms the second bit line 12, the second groove extends along the first direction D1, and the second groove is located between adjacent second bit lines 12; then, filling the second groove with an insulating material and grinding the insulating material, as shown in Figure 10b and Figure 10a wherein, Figure 10b is a structural schematic diagram of the semiconductor device after forming the second bit line according to the embodiment of the present disclosure; Figure 11a is a longitudinal sectional structural schematic diagram of the semiconductor device after forming the second bit line according to the embodiment of the present disclosure.
[0125] Step 105, forming a second hole.
[0126] In an exemplary embodiment, forming the second hole can include: on the basis of the substrate 101 with the foregoing pattern, using a photolithography process, a second hole 42 extending along a direction perpendicular to the substrate 101, the second hole 42 penetrating the fifth insulating layer 55, the second bit line 12, and the fourth insulating layer 54 in sequence along a direction perpendicular to the substrate 101, and extending into the first gate 22, the second hole 42 not penetrating the first gate 22 completely, and the second hole 42 forming a second groove 44 at the first gate 22. The second hole 42 exposes at least part of the second bit line 12 and at least part of the first gate 22. The second groove 44 exposes an inner surface of at least part of the first gate 22, as shown in FIG. 4B. Figure 11b and Figure 11a As shown in FIG. 4B. Figure 11b FIG. 4B is a structure diagram of a semiconductor device after forming a second hole according to an embodiment of the present disclosure; Figure 4 FIG. 4B is a structure diagram of a semiconductor device after forming a second hole according to an embodiment of the present disclosure.
[0127] Step 106, forming a second semiconductor layer, a second gate insulating layer, a second gate, and a word line.
[0128] In an exemplary embodiment, forming the second semiconductor layer, the second gate insulating layer, the second gate, and the word line includes: on the basis of the substrate 101 with the foregoing pattern, using an atomic layer deposition process (ALD) to deposit a second semiconductor thin film and a second gate insulating thin film in sequence, the second semiconductor thin film directly covering the inner wall of the second hole 42, the second gate insulating thin film covering the inner wall of the second hole 42 through the second semiconductor thin film, and the second semiconductor thin film being in direct contact with the second bit line 12 and the first gate 22 exposed by the second hole 42; then, using a chemical deposition process to deposit a fifth conductive thin film, the fifth conductive thin film filling the second hole 42 and the second groove 44; then, using an etching process to form the second semiconductor thin film into the second semiconductor layer 31, to form the second gate insulating thin film into the second gate insulating layer 33, and to form the fifth conductive thin film into the second gate 32, at least part of the second gate 32 filling the second hole 42 and the second groove 44; then, depositing a sixth conductive thin film on the side of the second gate 32 away from the substrate, using an etching process to form the sixth conductive thin film into the word line WL, the word line WL being in direct contact with the second gate 32; and then, forming a sixth insulating layer 56, the sixth insulating layer 56 being arranged between adjacent word lines WL, as shown in FIG. 4C. .
[0129] The embodiment of the present disclosure further provides a manufacturing method of a semiconductor device, including:
[0130] forming a source line and a first bit line in sequence on a substrate;
[0131] forming a first hole extending along a direction perpendicular to the substrate on the substrate, the first hole at least penetrating the first bit line and extending into the source line, the first hole exposing the first bit line and the source line;
[0132] forming a first semiconductor layer and a first gate insulating layer on the inner surface of the first hole in sequence, filling the first hole with a first gate, the first semiconductor layer surrounding the side surface of the first gate through the first gate insulating layer, the first semiconductor layer being connected with the first bit line and the source line exposed by the first hole;
[0133] forming a second bit line on the side of the first gate away from the substrate;
[0134] forming a second hole extending along a direction perpendicular to the substrate on the substrate, the second hole at least penetrating the second bit line and extending into the first gate, the second hole exposing the second bit line and the inner surface of the first gate;
[0135] forming a second semiconductor layer and a second gate insulating layer on the inner surface of the second hole in sequence, filling the second hole with a second gate, the second semiconductor layer surrounding the side surface of the second gate through the second gate insulating layer, the second semiconductor layer being connected with the second bit line and the inner surface of the first gate exposed by the second hole, one end of the second gate in the second hole being extended into the first gate from the side of the first gate away from the substrate and being connected with the inner surface of the first gate through the second gate insulating layer and the second semiconductor layer.
[0136] The disclosure also provides a reading and writing method of the semiconductor device.
[0137] in the data writing stage, an opening voltage is applied to the second gate of the storage unit in the storage unit column to which data is to be written, so as to open the second transistor of the storage unit; the second bit line of the second transistor is used to write the charge information corresponding to the data to be written into the storage unit; and the second gate of the second transistor is used as the gate of the first transistor, so as to keep the first transistor of the storage unit in an open state through the second gate;
[0138] At this time, the first transistor of the other storage units in the storage unit column keeps in a closed state due to no data writing;
[0139] in the data reading stage, a reference voltage is applied to the source line corresponding to the first transistor of the storage unit in the storage unit column to which data is to be read, so as to read the charge information in the storage unit; and a closing voltage is applied to the second gate of the other storage units in the storage unit column, so as to keep the other storage units in a closed state.
[0140] The read-write method of the semiconductor device provided by the embodiments of the present disclosure can close the second transistors of other memory cells when reading a specific memory cell by taking the second gate of the second transistor as the gate of the first transistor, and can reduce the potential of the first transistor of the other memory cells, so as to close the first transistor of the other memory cells, thereby solving the current sharing problem.
[0141] The embodiments of the present disclosure also provide an electronic device including the semiconductor device of any one of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.
[0142] Although the embodiments of the present disclosure are described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.
Claims
1. A semiconductor device, characterized by, The memory cell column includes a plurality of memory cells arranged at intervals along a column direction, the memory cell including a first transistor and a second transistor provided on a substrate, the first transistor including a first gate electrode perpendicular to the substrate, a first semiconductor layer surrounding a side surface of the first gate electrode, and a first gate insulating layer provided between the first gate electrode and the first semiconductor layer, the second transistor including a second gate electrode perpendicular to the substrate, a second semiconductor layer surrounding a side surface of the second gate electrode, and a second gate insulating layer provided between the second gate electrode and the second semiconductor layer, one end of the second gate electrode being inserted into the first gate electrode from a side of the first gate electrode away from the substrate and connected to an inner surface of the first gate electrode through the second gate insulating layer and the second semiconductor layer.
2. The semiconductor device according to claim 1, wherein The first hole has the first semiconductor layer and the first gate insulating layer sequentially provided on an inner surface of the first hole, and the first gate electrode fills the first hole.
3. The semiconductor device of claim 2, wherein, The memory cell column further includes a source line provided on the substrate, a second insulating layer provided on a side of the source line away from the substrate, a first bit line provided on a side of the second insulating layer away from the substrate, a third insulating layer provided on a side of the first bit line away from the substrate, the first hole extending along a direction close to the substrate from a surface of the third insulating layer away from the substrate, sequentially penetrating the third insulating layer, the first bit line, and the second insulating layer, and extending into the source line, the first hole exposing at least part of the first bit line and at least part of the source line, and the first semiconductor layer on the inner surface of the first hole being connected to the first bit line and the source line exposed by the first hole.
4. The semiconductor device according to claim 3, wherein The first hole forms a first recess at the source line, and at least part of the first semiconductor layer covers a side wall and a bottom wall of the first recess.
5. The semiconductor device of claim 3, wherein, The first hole has a projection on the substrate, and the projection is located in a projection of the source line and the first bit line on the substrate.
6. The semiconductor device of claim 1, wherein, The memory cell column further includes a second hole extending along a direction perpendicular to the substrate, one end of the second hole being inserted into the first gate electrode from a side of the first gate electrode away from the substrate, the second hole having the second semiconductor layer and the second gate insulating layer sequentially provided on an inner surface of the second hole, and the second gate electrode filling the second hole and being inserted into the first gate electrode.
7. The semiconductor device of claim 6, wherein, The second hole forms a second recess at the first gate electrode, the second recess having the second semiconductor layer and the second gate insulating layer sequentially provided on an inner surface of the second recess, and the second gate electrode filling the second recess and being inserted into the first gate electrode.
8. The semiconductor device of claim 6, wherein, Further comprising a fourth insulating layer disposed on a side of the first gate distal to the substrate, a second bit line disposed on a side of the fourth insulating layer distal to the substrate, a fifth insulating layer disposed on a side of the second bit line distal to the substrate, the second hole extending from a surface of the fifth insulating layer distal to the substrate, along a direction proximal to the substrate, sequentially penetrating the fifth insulating layer, the second bit line, the fourth insulating layer, and extending into the first gate, the second hole exposing at least part of the second bit line and at least part of an inner surface of the first gate, the second semiconductor layer on an inner surface of the second hole being connected to the inner surface of the first gate and the second bit line exposed by the second hole.
9. The semiconductor device of claim 6, wherein, Further comprising a plurality of word lines disposed on a side of the second gate distal to the substrate, one of the word lines being connected to the second gate of one of the memory cells in one of the columns of memory cells.
10. The semiconductor device of claim 7, wherein, A normal projection of the second recess on the substrate is located in a normal projection of the first gate on the substrate.
11. The semiconductor device of claim 8, wherein, A normal projection of the second hole on the substrate is located in a normal projection of the second bit line on the substrate.
12. The semiconductor device of claim 3, wherein The memory cells in each of the columns of memory cells share one of the first bit lines.
13. A method of manufacturing a semiconductor device, characterized by Further comprising: forming a source line and a first bit line on a substrate in sequence; forming a first hole on the substrate extending along a direction perpendicular to the substrate, the first hole penetrating at least the first bit line and extending into the source line, the first hole exposing the first bit line and the source line; forming a first semiconductor layer and a first gate insulating layer on an inner surface of the first hole in sequence, filling the first hole with a first gate, the first semiconductor layer surrounding a side surface of the first gate through the first gate insulating layer, the first semiconductor layer being connected to the first bit line and the source line exposed by the first hole; forming a second bit line on a side of the first gate distal to the substrate; forming a second hole on the substrate extending along a direction perpendicular to the substrate, the second hole penetrating at least the second bit line and extending into the first gate, the second hole exposing an inner surface of the second bit line and the first gate; forming a second semiconductor layer and a second gate insulating layer on an inner surface of the second hole in sequence, filling the second hole with a second gate, the second semiconductor layer surrounding a side surface of the second gate through the second gate insulating layer, the second semiconductor layer being connected to the inner surface of the first gate and the second bit line exposed by the second hole, one end of the second gate in the second hole being inserted into the first gate from a side of the first gate distal to the substrate and connected to the inner surface of the first gate through the second gate insulating layer and the second semiconductor layer.
14. An electronic device, comprising: The semiconductor device of any one of claims 1 to 12.
15. A method of reading and writing a semiconductor device as claimed in claim 1, characterized in that, Further comprising: a data writing stage, in which an opening voltage is applied to the second gate of the memory cell in the column of memory cells to which data is to be written, to open the second transistor of the memory cell. a data reading stage, in which a reading voltage is applied to the second gate of the memory cell in the column of memory cells from which data is to be read, to close the second transistor of the memory cell. The second transistor is used for writing the charge information corresponding to the data to be written into the storage unit through the second bit line, and the second gate of the second transistor is used as the gate of the first transistor, and the first transistor of the storage unit is kept in the open state through the second gate; In the data reading stage, a reference voltage is applied to the source line corresponding to the first transistor of the storage unit of the storage unit column where the data to be read is stored, so as to read the charge information in the storage unit; And a closing voltage is applied to the second gate of the other storage units in the storage unit column to keep the other storage units in the closed state.