Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The semiconductor structure comprises a capacitor contact structure, a capacitor, a dielectric layer and a first support layer. The capacitor is located at one side of the capacitor contact structure along the first direction and is connected with the capacitor contact structure. The dielectric layer is located on at least one side of the capacitor contact structure in the second direction. The first supporting layer is located on at least one side of the capacitor contact structure in the second direction and makes contact with the dielectric layer in the first direction. The second direction intersects the first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and more particularly, to a semiconductor structure, a method for manufacturing the semiconductor structure, a memory, and a storage system. BACKGROUND

[0002] With the rise and development of the fields of artificial intelligence, big data, Internet of Things, mobile communication, mobile devices, and cloud storage, the requirement for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices is also increasingly high. However, as the storage density of semiconductor structures increases, the size of most of the components becomes smaller and smaller, which in turn leads to increasingly difficult formation processes of semiconductor structures and increasingly more coupling phenomena between adjacent components, which has a great impact on the performance of semiconductor structures. SUMMARY

[0003] The embodiments provided in the present application can solve or partially solve the deficiencies proposed in the background section or other deficiencies in the prior art.

[0004] The present application provides a semiconductor structure. The semiconductor structure includes a capacitor contact structure, a capacitor, a dielectric layer, and a first support layer. The capacitor is located on one side of the capacitor contact structure along a first direction and connected to the capacitor contact structure. The dielectric layer is located on at least one side of the capacitor contact structure along a second direction. The first support layer is located on at least one side of the capacitor contact structure along the second direction and contacts the dielectric layer along the first direction. The second direction intersects the first direction.

[0005] In one embodiment, the materials of the dielectric layer and the first support layer are different.

[0006] In one embodiment, the materials of the dielectric layer and the first support layer both include nitride, and the hardness of the first support layer is greater than the hardness of the dielectric layer.

[0007] In one embodiment, the size of the capacitor contact structure along the first direction is less than the sum of the sizes of the dielectric layer and the first support layer along the first direction.

[0008] In one embodiment, the capacitor contact structure includes a contact layer, a connection layer, and a conductive layer. The connection layer is located on one side of the contact layer along the first direction. The conductive layer is located on one side of the connection layer away from the contact layer along the first direction. The dielectric layer is located on at least one side of the contact layer, the connection layer, and part of the conductive layer along the second direction. The first support layer is located on at least one side of the remaining part of the conductive layer along the second direction.

[0009] In one embodiment, the material of the contact layer includes a semiconductor material; the material of the connection layer includes a semiconductor compound material; and the material of the conductive layer includes at least one of a metal material and a metal compound material.

[0010] In one embodiment, the capacitor includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer. The first electrode layer is located at one side of the capacitor contact structure along a first direction and extends along the first direction. The capacitor dielectric layer is located between the first electrode layer and the second electrode layer.

[0011] In one embodiment, the first electrode layer is partially located at at least one side of the first support layer along a second direction.

[0012] In one embodiment, the material of the first electrode layer and the second electrode layer includes at least one of a metal, a metal compound, and a semiconductor material; and the material of the capacitor dielectric layer includes a high dielectric constant material.

[0013] In one embodiment, the semiconductor structure further includes a first layer and a second layer. The first layer is located at a side of the first electrode layer away from the capacitor dielectric layer. The material of the first layer includes at least one of a conductive material, a semiconductor material, and an insulating material. The second layer is located at a side of the second electrode layer away from the capacitor dielectric layer. The material of the second layer includes a conductive material.

[0014] In one embodiment, the semiconductor structure further includes a transistor located at a side of the capacitor contact structure away from the capacitor.

[0015] In one embodiment, the semiconductor structure further includes a second support layer located between two adjacent first electrode layers and in contact with a portion of the first electrode layer and a portion of the capacitor dielectric layer.

[0016] Another aspect of the present application provides a method of manufacturing a semiconductor structure. The method includes sequentially forming a dielectric layer and a first sacrificial layer along a first direction; forming a capacitor contact structure through the first sacrificial layer and the dielectric layer; removing the first sacrificial layer to form a first sacrificial gap; forming a first support layer in the first sacrificial gap and at a side of the capacitor contact structure along the first direction; and forming a capacitor through a portion of the first support layer and extending to the capacitor contact structure.

[0017] In one embodiment, the forming of the capacitor contact structure through the first sacrificial layer and the dielectric layer includes forming a capacitor contact hole through the first sacrificial layer and the dielectric layer; forming a contact layer of the capacitor contact structure in the capacitor contact hole; forming a connection layer of the capacitor contact structure at a side of the contact layer along the first direction; and forming a conductive layer of the capacitor contact structure at a side of the connection layer along the first direction away from the contact layer. The contact layer, the connection layer, and a portion of the conductive layer extend through the dielectric layer, and the portion of the conductive layer extends through the first sacrificial layer.

[0018] In one embodiment, the forming of the connection layer at the side of the contact layer along the first direction includes forming an intermediate conductive layer in contact with the contact layer at the side of the contact layer along the first direction; and reacting the intermediate conductive layer with the contact layer to form the connection layer.

[0019] In one embodiment, forming the conductive layer on the side of the connection layer away from the contact layer in the first direction includes: forming an initial conductive layer on the side of the connection layer away from the contact layer in the first direction and on the surface of the first sacrificial layer; and removing portions of the initial conductive layer on the surface of the first sacrificial layer using a grinding process, wherein remaining portions of the initial conductive layer form the conductive layer.

[0020] In one embodiment, the material of the first sacrificial layer includes an oxide and the material of the dielectric layer includes a nitride. Removing the first sacrificial layer includes: removing the first sacrificial layer using a wet removal process.

[0021] In one embodiment, forming the first support layer on the side of the first sacrificial gap and the capacitive contact structure in the first direction includes: forming a stack structure on the side of the first sacrificial gap and the capacitive contact structure in the first direction, wherein the stack structure includes an alternating stack of support layers and second sacrificial layers, the support layers including the first support layer.

[0022] In one embodiment, forming the capacitor through portions of the first support layer and extending to the capacitive contact structure includes: forming a capacitive hole through the stack structure and extending to the capacitive contact structure; forming a first electrode layer within the capacitive hole and extending to the capacitive contact structure; and forming a capacitive dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitive dielectric layer.

[0023] In one embodiment, forming the first electrode layer within the capacitive hole and extending to the capacitive contact structure includes: forming the first electrode layer on sidewalls of the capacitive hole; and forming a first layer in remaining space of the capacitive hole.

[0024] In one embodiment, forming the capacitive dielectric layer covering at least a portion of the first electrode layer and the second electrode layer covering at least a portion of the capacitive dielectric layer includes: removing the second sacrificial layer to expose the first electrode layer; forming the capacitive dielectric layer covering at least a portion of the first electrode layer; and forming the second electrode layer covering at least a portion of the capacitive dielectric layer on a side of the capacitive dielectric layer away from the first electrode layer.

[0025] In one embodiment, removing the second sacrificial layer includes: removing portions of the support layers to expose the second sacrificial layer; and removing the exposed second sacrificial layer to form a second sacrificial gap.

[0026] In one embodiment, forming the capacitive dielectric layer covering at least a portion of the first electrode layer includes: forming the capacitive dielectric layer covering at least a portion of the first electrode layer within the second sacrificial gap.

[0027] In one embodiment, the method further includes: forming a second layer on a side of the second electrode layer away from the capacitive dielectric layer.

[0028] In one embodiment, the method further comprises forming a transistor, wherein the transistor is located on a side of the capacitor contact structure away from the capacitor.

[0029] Another aspect of the present application provides a memory. The memory comprises: a memory cell array comprising the semiconductor structure as described above; and a peripheral circuit coupled to the memory cell array.

[0030] Another aspect of the present application provides a memory system. The memory system comprises: the memory as described above; and a controller coupled to the memory for controlling the memory to store data. BRIEF DESCRIPTION OF DRAWINGS

[0031] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as provided in conjunction with the accompanying drawings. In the drawings:

[0032] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0033] Figures 2 to 21 is a process step diagram for forming a semiconductor structure according to an exemplary embodiment of the present application;

[0034] Figure 22 is a partial structure schematic diagram of a semiconductor structure formed according to an exemplary embodiment of the present application;

[0035] Figures 23 to 28 is a process step diagram for forming a semiconductor structure according to another exemplary embodiment of the present application;

[0036] Figure 29 is a schematic block diagram of a memory according to an exemplary embodiment of the present application; and

[0037] Figure 30 is an exemplary block diagram of a system with a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0038] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely descriptive of exemplary embodiments of the present application and is not intended to limit the scope of the present application in any way.

[0039] It should be noted that the terms first, second, third, etc. are used herein only to distinguish one feature from another, and do not denote any order, quantity, or importance, but rather are used to distinguish one feature from another. Thus, a first electrode layer discussed herein can also be referred to as a second electrode layer, a first direction can also be referred to as a second direction, and vice versa, without departing from the teachings of the present application.

[0040] In the drawings, the thicknesses of components, sizes, and the like, are exaggerated for clarity. The drawings are merely schematic and are not intended to be drawn to scale. As used herein, the terms "substantially", "approximately", and the like, are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring or computing process.

[0041] Furthermore, in this document, when a part is described as being "on" another part, such as "on", "above", and "over", it can be interpreted in the broadest context as meaning not only "directly on the object", but also "on the object with intervening features or layers therebetween", and "above" or "over" does not mean absolutely above in the direction of gravity, but also can include the meaning of "above" or "over" the object (i.e., directly on the object) without intervening features or layers therebetween.

[0042] It should also be understood that expressions such as "include", "including", "have", "has", "contain", and / or "containing", and the like, are open-ended terms that are used to mean that other elements, components, and / or steps are optionally present, but not excluded. Furthermore, when such expressions as "at least one of", "one or more of", and / or the like, are applied to a list of elements, it is intended to mean that at least one of the elements from the list is present, but not excluding the presence of more than one of the elements from the list. Furthermore, when describing embodiments of the present application, the use of "can" means "one or more embodiments of the present application". Also, the use of the term "exemplary" is intended to present examples or illustrations, not a limitation.

[0043] The exemplary embodiments disclosed herein are described with reference to the drawings. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and dimensions of the structures shown, but rather, include various equivalents thereof and variations that are enabled by manufacturing tolerances and other factors. The positions shown in the drawings are schematic and are not intended to limit the positions of the components.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0045] As used herein, the term "layer" refers to a portion of material that includes an area with a height. A layer can be an area of a uniform or non-uniform continuous structure that has a height that is less than the height of the continuous structure. For example, a layer can be between any set of horizontal planes at the top and bottom surfaces of a continuous structure or between. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers.

[0046] Further, in this application, when using "connection" or "coupling", it can mean direct contact or indirect contact between the corresponding components, unless there is an explicit other limitation or can be derived from the context.

[0047] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict, unless otherwise limited. In addition, the specific steps contained in the methods described in the present application are not necessarily limited to the order described, but can be executed in any order or in parallel, unless explicitly limited or contradictory to the context. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0048] Figure 1 is a flowchart of a method 1000 of manufacturing a semiconductor structure according to an exemplary embodiment of the present application.

[0049] As shown in Figure 1 The method 1000 of manufacturing a semiconductor structure can include: S1100, sequentially forming a dielectric layer and a first sacrificial layer in a first direction; S1200, forming a capacitor contact structure penetrating through the first sacrificial layer and the dielectric layer; S1300, removing the first sacrificial layer to form a first sacrificial gap; S1400, forming a first support layer in the first sacrificial gap and on one side of the capacitor contact structure in the first direction; and S1500, forming a capacitor through part of the first support layer and extending to the capacitor contact structure. Steps S1100 to S1500 will be described in detail below.

[0050] As shown in Figures 2 to 21 An exemplary embodiment of the present application provides a process step diagram for forming a semiconductor structure. It should be understood that the process for forming a semiconductor structure provided by the present application is only an example and is not specifically limited.

[0051] Figure 2 is a schematic diagram of a structure after forming the semiconductor pillar 111, the gate structure 112, the isolation structure 120, the dielectric layer 1100 and the first sacrificial layer 1200 according to an example embodiment of the present application.

[0052] Exemplarily, the first direction Z, the second direction X and the third direction Y can intersect with each other. Exemplarily, the semiconductor pillar 111, the gate structure 112 and the isolation structure 120 can be formed. The semiconductor pillar 111 can be arrayed along the second direction X and the third direction Y. The gate structure 112 can be located at one side of the semiconductor pillar 111 along the second direction X. The isolation structure 120 can be located at one side of the semiconductor pillar 111 along the second direction X where the gate structure 112 is not arranged, for electrically insulating between adjacent semiconductor pillars 111 and reducing the coupling phenomenon between adjacent semiconductor pillars 111.

[0053] The semiconductor pillar 111 and the gate structure 112 can be used together to form a transistor 110, such as a vertical transistor. Exemplarily, the semiconductor pillar 111 can be used to form an active region of a plurality of channels in the vertical transistor 110. Exemplarily, the gate structure 112 can be located at least one side of the semiconductor pillar 111, i.e. the semiconductor pillar 111 can be at least partially surrounded by the gate structure 112. For example, the semiconductor pillar 111 and the gate structure 112 can be radially arranged in this order from the center of the vertical transistor.

[0054] It should be understood that, Figure 2 The case that the gate structure 112 is located at one side of the semiconductor pillar 111 shown in the above is only an example and is not specifically limited.

[0055] In an embodiment of the present application, the gate structure 112 can be located at multiple sides of the semiconductor pillar 111, in which case the semiconductor pillar 111 and the gate structure 112 can be used together to form a multi-gate transistor (e.g. a gate-all-around (GAA) transistor, a tri-gate transistor or a dual-gate transistor). The multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off state, the leakage current of the multi-gate transistor can also be significantly reduced due to the complete depletion of the channel. Therefore, using the multi-gate transistor can achieve better speed (saturated drain current) / leakage current performance.

[0056] In another embodiment of the present application, the gate structure 112 can be located at one side of the semiconductor pillar 111, and the semiconductor pillar 111 and the gate structure 112 can be used together to form a single-gate transistor. Exemplarily, the single-gate transistors adjacent along the second direction X can be symmetrically arranged. By providing the single-gate transistor, the present application can significantly increase the density of the semiconductor pillars 111 along the second direction X, and reduce the difficulty of the manufacturing process. In addition, the symmetric single-gate transistors can have a larger process window, which is beneficial to reducing the spacing between the bit lines, word lines and transistors, etc.

[0057] Exemplarily, the dielectric layer 1100 and the first sacrificial layer 1200 can be sequentially formed along the first direction Z. For example, the dielectric layer 1100 and the first sacrificial layer 1200 can be sequentially stacked at one side of the transistor 110 along the first direction Z. The dielectric layer 1100 can be located between and in contact with the transistor 110 and the first sacrificial layer 1200.

[0058] Exemplarily, the dielectric layer 1100 and the first sacrificial layer 1200 can be stacked by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0059] Exemplarily, the material of the dielectric layer 1100 can include any one or a combination of two or more of silicon nitride, silicon oxynitride, aluminum oxide, etc. In addition, the dielectric layer 1100 can be doped with boron, carbon or phosphorus. The material of the first sacrificial layer 1200 can include any one or a combination of two or more of silicon oxide, silicon oxynitride and polysilicon, etc. The material of the first sacrificial layer 1200 can be different from the material of the dielectric layer 1100, so as to achieve different etching rates of the two layers in the same etching process, such as in the same etching solution. Exemplarily, in the same etching process, such as in the same etching solution, the etching (such as etching) rate of the first sacrificial layer 1200 can be much greater than the etching rate of the dielectric layer 1100, so that when most of the first sacrificial layer 1200 is removed, the dielectric layer 1100 is almost completely retained or less removed. Exemplarily, the material of the first sacrificial layer 1200 can be, for example, silicon oxide, and the material of the dielectric layer 1100 can be, for example, silicon nitride. Subsequently, a wet etching process can be used to remove the first sacrificial layer 1200 and retain most of the dielectric layer 1100, wherein the etching solution used in the wet etching process can include at least one of a hydrofluoric acid solution and an ammonium hydrofluoride solution.

[0060] Figures 3 to 6is a process flow diagram of forming a capacitive contact structure 1300 according to an example embodiment of the present application. It should be understood that the process of forming the capacitive contact structure 1300 provided by the present application is merely an example and is not specifically limited. In actual processes, the process of forming the capacitive contact structure 1300 can be reasonably arranged according to actual needs.

[0061] As shown in the example, Figure 6 The capacitive contact structure 1300 can be formed through the first sacrificial layer 1200 and the dielectric layer 1100. As shown in the example, forming the capacitive contact structure 1300 can include: forming a capacitive contact hole 200 through the first sacrificial layer 1200 and the dielectric layer 1100; Figure 3 forming a contact layer 1310 of the capacitive contact structure 1300 in the capacitive contact hole 200; Figure 4 forming a connection layer 1320 of the capacitive contact structure 1300 on one side of the contact layer 1310 along the first direction Z; and Figure 5 forming a conductive layer 1330 of the capacitive contact structure 1300 on one side of the connection layer 1320 away from the contact layer 1310 along the first direction Z. Figure 6

[0062] As shown in the example, the first sacrificial layer 1200 and the dielectric layer 1100 can be removed along the second direction Z by using a photolithography process, one or more dry etching and / or wet etching processes, etc. to form the capacitive contact hole 200 extending to the semiconductor pillar 111.

[0063] As shown in the example, the contact layer 1310 can be formed in the capacitive contact hole 200 by using one or more thin film deposition processes. The contact layer 1310 can be in contact with the semiconductor pillar 111, and the material thereof includes but is not limited to at least one of a semiconductor material such as polysilicon poly, germanium silicon GeSi, etc. By setting the material of the contact layer 1310 to be germanium silicon GeSi for example, the present application can reduce the resistance between the semiconductor pillar 111 (the material thereof can be silicon Si for example) and the contact layer 1310 in contact.

[0064] As shown in the example, forming the connection layer 1320 on one side of the contact layer 1310 along the first direction Z can include: forming an intermediate conductive layer 1320-1 in contact with the contact layer 1310 on one side of the contact layer 1310 along the first direction Z; and Figure 4 reacting the intermediate conductive layer 1320-1 with the contact layer 1310 to form the connection layer 1320. Figure 5

[0065] ​​Exemplarily, one or more thin film deposition processes can be employed to form the intermediate conductive layer 1320-1 on the contact layer 1310. The material of the intermediate conductive layer 1320-1 includes, but is not limited to, a conductive material such as metallic cobalt Co.

[0066] Exemplarily, forming the conductive layer 1330 on the side of the connection layer 1320 facing away from the contact layer 1310 along the first direction Z can include: forming an initial conductive layer 1330-1 on the side of the connection layer 1320 facing away from the contact layer 1310 along the first direction Z and on the surface of the first sacrificial layer 1200 (1330-1); Figure 5 and employing a grinding process to remove the portion of the initial conductive layer 1330-1 on the surface of the first sacrificial layer 1200, wherein the remaining portion of the initial conductive layer 1330-1 forms the conductive layer 1330 (1330). Figure 6

[0067] Exemplarily, one or more thin film deposition processes and removal processes can be employed to form the conductive layer 1330. The material of the conductive layer 1330 includes, but is not limited to, one or more conductive materials such as metals and / or metal compounds. As shown, the conductive layer 1330 can be a composite layer, and the material thereof can include titanium nitride TiN and metallic tungsten W surrounded by the titanium nitride TiN. Figure 6

[0068] It is noted that in the process of forming the conductive layer 1330 on the side of the connection layer 1320 facing away from the contact layer 1310 along the first direction Z (i.e. forming the conductive layer 1330 in the capacitor contact hole 200), conductive materials such as titanium nitride TiN and metallic tungsten W are inevitably formed on the surface of the first sacrificial layer 1200 along the second direction Z as well to form the initial conductive layer 1330-1.

[0069] Exemplarily, a planarization process such as a chemical mechanical grinding process can be performed to remove the portion of the initial conductive layer 1330-1 on the surface of the first sacrificial layer 1200, i.e. to remove excess conductive materials such as titanium nitride TiN and metallic tungsten W on the first sacrificial layer 1200, to form the conductive layer 1330.

[0070] ​​In this application, by using silicon oxide as the material for the first sacrificial layer 1200, the density of the first sacrificial layer 1200 can be increased, giving it high density. Thus, when the conductive material such as titanium nitride (TiN) and tungsten W is removed from the surface of the first sacrificial layer 1200 by mechanical polishing, less conductive material penetrates into the first sacrificial layer 1200, thereby reducing coupling between adjacent capacitive contact structures 1300.

[0071] Furthermore, if the coupling phenomenon between adjacent capacitor contact structures 1300 is reduced, the size of the capacitor contact structure 1300 along the second direction X can be appropriately increased, which will help reduce the difficulty of forming the capacitor contact structure 1300.

[0072] This application uses semiconductor materials (such as germanium silicon GeSi), metal silicides (such as cobalt silicon CoSi), and various conductive materials (such as titanium nitride TiN and tungsten W) to make the contact layer 1310, the connecting layer 1320, and the conductive layer 1330 respectively. This helps to reduce the resistance between the contact layer 1310 and the connecting layer 1320, the connecting layer 1320 and the conductive layer 1330, and the different layers in the conductive layer 1330 that are in contact with each other.

[0073] On the other hand, by providing the capacitor contact structure 1300, this application facilitates the subsequent formation of the first electrode layer 1510. Figure 11 The connection between the first electrode layer 1510 and the transistor 110 can reduce the risk that the first electrode layer 1510 may be coupled to the word line (located on the side of the transistor 110 along the second direction X) due to direct contact between the first electrode layer 1510 and the transistor 110.

[0074] like Figure 6 As shown, the capacitor contact structure 1300 may include a contact layer 1310, a connection layer 1320, and a conductive layer 1330. Exemplarily, the contact layer 1310, the connection layer 1320, and a portion of the conductive layer 1330 may penetrate the dielectric layer 1100, and a portion of the conductive layer 1330 may penetrate the first sacrificial layer 1200. In other words, the contact layer 1310, the connection layer 1320, and a portion of the conductive layer 1330 may contact the dielectric layer 1100 along the second direction X, and the remaining conductive layer 1330 may contact the first sacrificial layer 1200 along the second direction X.

[0075] Figure 7 This is a schematic diagram of the structure after forming the first sacrificial gap 300 according to an exemplary embodiment of this application. Exemplarily, the first sacrificial layer 1200 can be removed to form the first sacrificial gap 300. Exemplarily, a wet removal process can be used to remove the first sacrificial layer 1200.

[0076] In the present application, by setting the material of the first sacrificial layer 1200 different from the material of the dielectric layer 1100 (e.g., the material of the first sacrificial layer 1200 can be, for example, silicon oxide, and the material of the dielectric layer 1100 can be, for example, silicon nitride), it is beneficial to achieve that the dielectric layer 1100 is almost completely retained or less removed when the first sacrificial layer 1200 is removed by using a wet removal process.

[0077] Figure 8 is a schematic diagram of a structure after forming the first support layer 1411 according to an exemplary embodiment of the present application. Exemplarily, the first support layer 1411 can be formed in the first sacrificial gap 300 and on one side of the capacitive contact structure 1300 along the first direction Z.

[0078] Exemplarily, the dimension H1 of the capacitive contact structure 1300 along the first direction Z can be less than the sum H2 of the dimensions of the dielectric layer 1100 and the first support layer 1411 along the first direction Z. In other words, the first support layer 1411 can cover the surface and part of the sidewall of the capacitive contact structure 1300 along the first direction Z away from the semiconductor pillar 111.

[0079] In the present application, by removing the first sacrificial layer 1200, for example, removing the first sacrificial layer 1200 to form the first sacrificial gap 300 and forming the first support layer 1411 in the first sacrificial gap 300, it is beneficial to further reduce the phenomenon of coupling between adjacent capacitive contact structures 1300 due to the penetration of conductive materials such as titanium nitride TiN and tungsten W into the first sacrificial layer 1200.

[0080] Exemplarily, forming the first support layer 1411 can include: forming a stack structure 1400 in the first sacrificial gap 300 and on one side of the capacitive contact structure 1300 along the first direction Z, wherein the stack structure 1400 includes alternately stacked support layers 1410 and second sacrificial layers 1420, and the support layers 1410 include the first support layer 1411.

[0081] Exemplarily, the stack structure 1400 can be formed by alternately stacking the support layers 1410 and the second sacrificial layers 1420 in the first sacrificial gap 300 and on one side of the capacitive contact structure 1300 along the first direction Z. For example, Figure 8As shown, the material layers at the two ends of the stack structure 1400 can be support layers 1410, and the number of the support layers 1410 can be greater than the number of the second sacrificial layers 1420. For example, the support layers 1410 can include a first support layer 1411, a second support layer 1412, and a third support layer 1413 distributed in the first direction Z in sequence, where the first support layer 1411 and the third support layer 1413 can be the material layers at the two ends of the stack structure 1400, and the first support layer 1411 can cover part of the capacitor contact structure 1300. The second sacrificial layers 1420 can include a first sub-sacrificial layer 1421 between the first support layer 1411 and the second support layer 1412, and a second sub-sacrificial layer 1422 between the second support layer 1412 and the third support layer 1413.

[0082] It should be understood that the number of the support layers 1410 and the second sacrificial layers 1420 defined in the present application is only an example and is not explicitly limited. In actual processes, the number of the support layers 1410 and the second sacrificial layers 1420 can be reasonably set according to the height required by the subsequently formed capacitor 1500. Figure 20 ).

[0083] For example, the stack structure 1400 can be formed by alternately stacking the support layers 1410 and the second sacrificial layers 1420 through one or more thin film deposition processes. For example, the stack structure 1400 can be formed by sequentially stacking the first support layer 1411, the first sub-sacrificial layer 1421, the second support layer 1412, the second sub-sacrificial layer 1422, and the third support layer 1413.

[0084] For example, the material of the support layers 1410 can include any one or a combination of two or more of silicon nitride, silicon oxynitride, aluminum oxide, etc. In addition, the support layers 1410 can be doped with boron, carbon, or phosphorus. The material of the second sacrificial layers 1420 can include any one or a combination of two or more of silicon oxide, silicon oxynitride, and polysilicon. The material of the second sacrificial layers 1420 can be different from the material of the support layers 1410 to achieve different etching rates of the two in the same etching process, such as in the same etchant. For example, in the same etching process, such as in the same etchant, the etching (such as etching) rate of the second sacrificial layers 1420 can be much greater than the etching rate of the support layers 1410, so that when most of the second sacrificial layers 1420 are removed, the support layers 1410 are almost completely retained or less removed. For example, the second sacrificial layers 1420 can be, for example, silicon oxide, and the material of the support layers 1410 can be, for example, boron- or carbon-doped silicon nitride. Subsequently, a wet etching process can be used to remove the second sacrificial layers 1420 and retain most of the support layers 1410, where the etchant used in the wet etching process can include at least one of a hydrofluoric acid solution and an ammonium hydrofluoride solution.

[0085] Exemplarily, the material of the first support layer 1411 can be different from that of the dielectric layer 1100. The hardness of the first support layer 1411 can be relatively large, for example, the hardness of the first support layer 1411 can be greater than that of the dielectric layer 1100. For example, the material of the first support layer 1411 can be, for example, boron-doped or carbon-doped silicon nitride, and the material of the dielectric layer 1100 can be, for example, silicon nitride.

[0086] Exemplarily, the material of the second support layer 1412 and the third support layer 1413 can also be, for example, boron-doped or carbon-doped silicon nitride. By setting the material of the support layer 1410 (including the first support layer 1411, the second support layer 1412, and the third support layer 1413) to be doped silicon nitride, the hardness of the support layer 1410 can be improved, and the consumption of the support layer 1410 during subsequent removal of the second sacrificial layer 1420 can be reduced. In addition, by setting the hardness of the support layer 1410, such as the first support layer 1411, to be relatively large, the support of the support layer 1410 after the second sacrificial layer 1420 is removed can be improved.

[0087] Figures 9 to 20 is a process step diagram for forming a capacitor 1500 according to an exemplary embodiment of the present application. It should be understood that the process for forming a capacitor 1500 provided by the present application is only an example and is not specifically limited. In actual processes, the process for forming a capacitor 1500 can be reasonably set according to actual needs.

[0088] Exemplarily, as shown in Figure 20 , a capacitor 1500 can be formed through part of the first support layer 1411 and extending to the capacitor contact structure 1300. Exemplarily, forming the capacitor 1500 can include: forming a capacitor hole 400 extending through the stack structure 1400 and extending to the capacitor contact structure 1300 Figure 9 ; forming a first electrode layer 1510 extending to the capacitor contact structure 1300 in the capacitor hole 400 Figure 11 ; and forming a capacitor dielectric layer 1520 covering at least part of the first electrode layer 1510 and a second electrode layer 1530 covering at least part of the capacitor dielectric layer 1520 Figure 19 and Figure 20 .

[0089] Figure 9 is a partial structure schematic diagram after forming a capacitor hole 400 according to an exemplary embodiment of the present application. Exemplarily, a capacitor hole 400 can be formed through the stack structure 1400 along a first direction Z and extending to the capacitor contact structure 1300.

[0090] Exemplarily, the patterned mask layer 410 with the arrayed windows can be formed on the third support layer 1413, and the capacitor holes 400 corresponding to the windows can be formed in the stack structure 1400 by taking the patterned mask layer 410 as a mask.

[0091] Specifically, a photoresist layer and / or a mask layer of other material (e.g., a silicon nitride hard mask layer, etc.) can be formed on the third support layer 1413 as a material layer of the patterned mask layer 410. Then, the material layer (e.g., the photoresist layer) can be patterned by a photolithography process to obtain the patterned mask layer 410 with the windows, wherein the windows can correspond to the capacitor contact structures 1300 along the first direction Z. Subsequently, the capacitor holes 400 can be formed in the stack structure 1400 by taking the patterned mask layer 410 as a mask. Exemplarily, a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process can be used to etch the stack structure 1400 to form the capacitor holes 400.

[0092] Figure 10 is a structural schematic diagram of the stack structure 1400 after the patterned mask layer 410 is removed. Exemplarily, the patterned mask layer 410 can be removed after the capacitor holes 400 are formed.

[0093] Figure 11 is a partial structural schematic diagram of the stack structure 1400 after the first electrode layer 1510 is formed according to an exemplary embodiment of the present application. Exemplarily, the first electrode layer 1510 extending to the capacitor contact structures 1300 can be formed in the capacitor holes 400. Exemplarily, the first electrode layer 1510 can be formed on the sidewalls of the capacitor holes 400. The first electrode layer 1510 can extend through the stack structure 1400 along the first direction Z and reach the capacitor contact structures 1300.

[0094] Exemplarily, the first electrode layer 1510 can be formed on the sidewalls and the bottom of the capacitor holes 400 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It should be understood that, in the process of forming the first electrode layer 1510 on the sidewalls and the bottom of the capacitor holes 400, the first electrode layer 1510 will inevitably also be formed on the third support layer 1413. Therefore, a chemical mechanical polishing or etching process can also be used to remove part of the first electrode layer 1510 on the third support layer 1413, and the first electrode layer 1510 on the sidewalls and the bottom of the capacitor holes 400 is retained. Figure 12 ).

[0095] Exemplarily, the first electrode layer 1510 can be at least part of a barrel structure Figure 12 and Figure 18 ). As Figure 12As shown, the cross section of the first electrode layer 1510 along the second direction X can have a U-shaped structure. It is noted that in actual process, part of the first electrode layer 1510 can be removed in a subsequent process of forming the second sacrificial gap 500 by removing the second sacrificial layer 1420 and part of the support layer 1410. Figure 18 As shown, the cross section of the first electrode layer 1510 along the second direction X can have a U-shaped structure. It is noted that in actual process, part of the first electrode layer 1510 can be removed in a subsequent process of forming the second sacrificial gap 500 by removing the second sacrificial layer 1420 and part of the support layer 1410.

[0096] Exemplarily, the material of the first electrode layer 1510 can include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the first electrode layer 1510 can include a compound formed by one or both of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicide nitride (TiSixNy), etc. Exemplarily, the material of the first electrode layer 1510 can be titanium nitride.

[0097] Figure 13 is a schematic diagram of a partial structure after forming the first layer 1610 according to an exemplary embodiment of the present application. Exemplarily, the first layer 1610 can be formed in the remaining space of the capacitor hole 400.

[0098] It is noted that in the process of forming the first layer 1610 in the remaining space of the capacitor hole 400, the first layer 1610 will inevitably also be formed on the third support layer 1413. The part of the first layer 1610 located in the remaining space of the capacitor hole 400 and the part of the first layer 1610 located on the third support layer 1413 can both provide support in a subsequent process of forming the second sacrificial gap 500.

[0099] Exemplarily, the material of the first layer 1610 can include at least one of a conductive material, a semiconductor material, and an insulating material. In an embodiment of the present application, the material of the first layer 1610 can include a conductive material such as titanium carbide, etc., to jointly serve as one electrode of the capacitor 1500 with the first electrode layer 1510. In another embodiment of the present application, the material of the first layer 1610 can include at least one of a semiconductor material and an insulating material such as polysilicon or an insulating material, etc., to provide support.

[0100] Figure 20 is a schematic diagram of a structure after forming the capacitor dielectric layer 1520 and the second electrode layer 1530 according to an exemplary embodiment of the present application. Exemplarily, the capacitor dielectric layer 1520 covering at least part of the first electrode layer 1510 and the second electrode layer 1530 covering at least part of the capacitor dielectric layer 1520 can be formed.

[0101] As shown, the cross section of the first electrode layer 1510 along the second direction X can have a U-shaped structure. It is noted that in actual process, part of the first electrode layer 1510 can be removed in a subsequent process of forming the second sacrificial gap 500 by removing the second sacrificial layer 1420 and part of the support layer 1410. Figures 14 to 20As shown, the exemplary embodiments provided by the present application provide a process flow diagram of forming the capacitor dielectric layer 1520 and the second electrode layer 1530. It should be understood that the process of forming the capacitor dielectric layer 1520 and the second electrode layer 1530 provided by the present application is only an example and is not specifically limited. In actual processes, the process of forming the capacitor dielectric layer 1520 and the second electrode layer 1530 can be reasonably arranged according to actual needs.

[0102] Exemplarily, forming the capacitor dielectric layer 1520 covering at least a portion of the first electrode layer 1510 and the second electrode layer 1530 covering at least a portion of the capacitor dielectric layer 1520 can include: removing the second sacrificial layer 1420 to expose the first electrode layer 1510 Figures 14 to 17 ) ; forming the capacitor dielectric layer 1520 covering at least a portion of the first electrode layer 1510 Figure 19 ) ; and forming the second electrode layer 1530 covering at least a portion of the capacitor dielectric layer 1520 on a side of the capacitor dielectric layer 1520 away from the first electrode layer 1510 Figure 20 ).

[0103] Exemplarily, removing the second sacrificial layer 1420 can include: removing a portion of the support layer 1410 to expose the second sacrificial layer 1420 Figure 14 and Figure 16 ) ; and removing the exposed second sacrificial layer 1420 to form the second sacrificial gap 500 Figure 15 and Figure 17 ).

[0104] Figure 14 is a structural schematic diagram of a structure after forming the first opening 510 according to the exemplary embodiments provided by the present application. Figure 15 is a structural schematic diagram of a structure after removing the second sub-sacrificial layer 1422 according to the exemplary embodiments provided by the present application.

[0105] Exemplarily, a portion of the first layer 1610 and a portion of the third support layer 1413 can be removed along the first direction Z to form the first opening 510, wherein the second sub-sacrificial layer 1422 can be exposed via the first opening 510. Exemplarily, a process such as a wet etching process can be used to remove the second sub-sacrificial layer 1422 via the first opening 510.

[0106] Exemplarily, the sum of the thicknesses of the third support layer 1413 and the portion of the first layer 1610 on the third support layer 1413 can be relatively large, such as greater than the thicknesses of the second support layer 1412 and / or the first support layer 1411. Since the third support layer 1413 and the first layer 1610 will be removed in part in the process of forming the first opening 510, in order to reduce the third support layer 1413 and the first layer 1610 from being etched through in the subsequent etching process and to ensure that the third support layer 1413 and the first layer 1610 have sufficient support strength, the sum of the thicknesses of the third support layer 1413 and the portion of the first layer 1610 on the third support layer 1413 can be set to be relatively large.

[0107] Exemplarily, one first opening 510 can overlap with multiple capacitor holes 400 at the same time. For example, as shown in FIG. 5A, one first opening 510 can overlap with four capacitor holes 400. Of course, one first opening 510 can also overlap with only one capacitor hole 400. Figure 18

[0108] Figure 16 FIG. 5B is a schematic diagram of a structure after a second opening 520 is formed according to an exemplary embodiment of the present application. Figure 17 FIG. 5C is a schematic diagram of a structure after the first sub-sacrificial layer 1421 is removed and the second sacrificial gap 500 is formed according to an exemplary embodiment of the present application.

[0109] Exemplarily, the second support layer 1412 can be removed to form the second opening 520, wherein the first sub-sacrificial layer 1421 can be exposed via the second opening 520. Exemplarily, the first sub-sacrificial layer 1421 can be removed via the second opening 520 by using a process such as a wet etching process.

[0110] Exemplarily, one second opening 520 can overlap with multiple capacitor holes 400 at the same time; or, one second opening 520 can overlap with only one capacitor hole 400. Exemplarily, the second opening 520 can be formed similar to the first opening 510, such as the second opening 520 can be disposed corresponding to the first opening 510 along the first direction Z.

[0111] Exemplarily, the first opening 510, the second opening 520, and the space formed after the second sacrificial layer 1420 (such as the first sub-sacrificial layer 1421 and the second sub-sacrificial layer 1422) is removed can be used to form the second sacrificial gap 500. In other words, the second sacrificial gap 500 can include the first opening 510, the second opening 520, and the space formed after the second sacrificial layer 1420 (such as the first sub-sacrificial layer 1421 and the second sub-sacrificial layer 1422) is removed. In addition, it should be understood that when the second sacrificial layer 1420 and the support layer 1410 are other numbers or more material layers, by analogy, the second sacrificial layer 1420 can be removed by setting openings and a wet etching process.

[0112] ​In the present application, part of the support layers 1410 (e.g., the first support layer 1411 located under the second sacrificial layer 1420, part of the second support layer 1412, and part of the third support layer 1413) are not removed. The remaining part of the support layers 1410 can play a supporting role in the process of removing the second sacrificial layer 1420, thereby facilitating the mechanical strength of the structure of the subsequently formed capacitor 1500 (including the first electrode layer 1510, the capacitor dielectric layer 1520, and the second electrode layer 1530), and reducing the damage to the capacitor 1500 in subsequent processes (e.g., grinding, etc.).

[0113] Figure 19 is a schematic diagram of the structure after forming the capacitor dielectric layer 1520 according to an exemplary embodiment of the present application. For example, the capacitor dielectric layer 1520 covering at least part of the first electrode layer 1510 can be formed in the second sacrificial gap 500. For example, the capacitor dielectric layer 1520 covering at least part of the first electrode layer 1510 can be formed in the second sacrificial gap 500 and on one side of the third support layer 1413 along the first direction Z.

[0114] For example, the material of the capacitor dielectric layer 1520 can include a high dielectric constant material. For example, the material of the capacitor dielectric layer 1520 can include, but is not limited to, at least one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and / or praseodymium oxide (Pr2O3), etc. or a combination thereof.

[0115] Figure 20 is a schematic diagram of the structure after forming the second electrode layer 1530 according to an exemplary embodiment of the present application. For example, the second electrode layer 1530 covering at least part of the capacitor dielectric layer 1520 can be formed on one side of the capacitor dielectric layer 1520 along the first direction Z in the second sacrificial gap 500, so as to form the capacitor 1500. The capacitor 1500 can include the first electrode layer 1510, the capacitor dielectric layer 1520, and the second electrode layer 1530.

[0116] Exemplarily, the material of the second electrode layer 1530 can include at least one of a metal, a metal compound, a semiconductor material. For example, the material of the second electrode layer 1530 can include a compound formed by one or both of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicide nitride (TiSixNy), etc. In addition, the material of the second electrode layer 1530 can also include one or more than two of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or a stack formed by two or more of the above-mentioned materials.

[0117] Figure 21 is a schematic diagram of a structure after forming the second layer 1620 according to an exemplary embodiment of the present application. Exemplarily, the second layer 1620 can be formed on the side of the second electrode layer 1530 away from the capacitor dielectric layer 1520.

[0118] Exemplarily, the second layer 1620 can be formed on the remaining space of the second sacrificial gap 500 and on the side of the second electrode layer 1530 along the first direction Z, so that the second layer 1620 covers the entire second electrode layer 1530. Exemplarily, the second layer 1620 can have a plurality of insulating gaps therein to reduce structural stress.

[0119] Exemplarily, the material of the second layer 1620 can include a conductive material such as a doped semiconductor material, etc. For example, the material of the second layer 1620 can include boron-doped germanium silicon. Exemplarily, the second layer 1620 can be connected to other conductive structures (not shown) for realizing the connection of the capacitor 1500 to other conductive structures such as a peripheral circuit.

[0120] Exemplarily, the capacitor dielectric layer 1520, the second electrode layer 1530 and the second layer 1620 can be sequentially formed by one or more thin film deposition processes including but not limited to CVD, PVD, ALD or any combination thereof. In addition, a doping process can also be used to dope the second layer 1620.

[0121] Figure 22 is a schematic diagram of a part of a semiconductor structure according to an exemplary embodiment of the present application.

[0122] Exemplarily, the manufactured semiconductor structure can include a storage device having a storage function. For example, the semiconductor structure can include a memory device having a memory function. Figure 22As shown, the storage device may include storage cells MC and word lines WL and bit lines BL coupled to the storage cells MC. Exemplarily, the storage device may include at least one of dynamic random access memory (DRAM), phase-change memory (PCM), and ferroelectric random access memory (FRAM). For ease of description, the following description primarily uses DRAM memory as an example.

[0123] The memory cell MC may include DRAM cells and may be arrayed along a second direction X and a third direction Y. Each DRAM cell may include a capacitor 1500 for storing bits of data as positive or negative charges and one or more transistors 110 (also known as via transistors 110) for controlling (e.g., switching and selecting) access to it. Exemplarily, transistors 110 may be vertical transistors such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) to facilitate the subsequent formation of capacitors 1500 on one side of transistor 110 along the first direction Z.

[0124] A word line WL can be coupled to a memory cell MC along a third direction Y to control the switching of a vertical transistor 110 in a memory cell MC located in a row along the third direction Y. A bit line BL can be coupled to a memory cell MC along a second direction X to send data to and / or receive data from a memory cell MC located in a column along the second direction X. That is, each word line WL can be coupled to a memory cell MC in the corresponding row and each bit line BL can be coupled to a memory cell MC in the corresponding column.

[0125] For example, the gate of transistor 110 may be connected to word line WL, the drain to bit line BL, and the source to capacitor 1500. The voltage signal on word line WL can control the transistor 110 to turn on or off, thereby reading data information stored in capacitor 1500 through bit line BL, or writing data information into capacitor 1500 for storage through bit line BL.

[0126] like Figures 23 to 28 The diagram illustrates a process step diagram for forming a semiconductor structure according to another exemplary embodiment of this application. It should be understood that the process for forming a semiconductor structure provided in this application is merely an example and not a specific limitation.

[0127] For example, such as Figure 23As shown, the first direction Z, the second direction X and the third direction Y can intersect with each other pairwise. Exemplarily, the semiconductor pillars 211, the gate structures 212 and the isolation structures 220 can be formed. The semiconductor pillars 211 can be arrayed along the second direction X and the third direction Y. The gate structures 212 can be located at one side of the semiconductor pillars 211 along the second direction X. The isolation structures 220 can be located at one side of the semiconductor pillars 211 along the second direction X where no gate structure 212 is disposed, for electrically insulating between adjacent semiconductor pillars 211 and reducing the coupling phenomenon between adjacent semiconductor pillars 211. The semiconductor pillars 211 and the gate structures 212 can be collectively used for forming the transistors 210 such as vertical transistors, wherein the semiconductor pillars 211 can be used for forming the active regions of multiple channels in the vertical transistors 210.

[0128] Exemplarily, the dielectric layer 2100 can be formed at one side of the transistors 210 along the first direction Z by one or more thin film deposition processes. The material of the dielectric layer 2100 can be, for example, silicon nitride.

[0129] Exemplarily, as shown, Figure 26 The capacitor contact structure 2300 can be formed through the dielectric layer 2100. Exemplarily, forming the capacitor contact structure 2300 can include: forming a capacitor contact hole 600 through the dielectric layer 2100; Figure 24 forming a contact layer 2310 of the capacitor contact structure 2300 within the capacitor contact hole 600; Figure 25 forming a connection layer 2320 of the capacitor contact structure 2300 at one side of the contact layer 2310 along the first direction Z; Figure 25 and forming a conductive layer 2330 of the capacitor contact structure 2300 at one side of the connection layer 2320 along the first direction Z away from the contact layer 2310. Figure 26

[0130] Exemplarily, part of the dielectric layer 2100 can be removed along the second direction Z by a photolithography process, one or more dry etching and / or wet etching processes, etc., to form the capacitor contact hole 600 extending to the semiconductor pillar 211.

[0131] Exemplarily, the contact layer 2310 can be formed within the capacitor contact hole 600 by one or more thin film deposition processes. The contact layer 2310 can be in contact with the semiconductor pillar 211, and its material can include but is not limited to at least one of semiconductor materials such as polysilicon poly, germanium silicon GeSi, etc. By setting the material of the contact layer 2310 to be, for example, germanium silicon GeSi, the present application can reduce the electrical resistance between the semiconductor pillar 211 (whose material can be, for example, silicon Si) and the contact layer 2310 in contact.

[0132] ​Exemplarily, forming the connection layer 2320 on the side of the contact layer 2310 along the first direction Z can include: forming an intermediate conductive layer (not shown) in contact with the contact layer 2310 on the side of the contact layer 2310 along the first direction Z; and reacting the intermediate conductive layer with the contact layer 2310 to form the connection layer 2320. Figure 25

[0133] Exemplarily, one or more thin film deposition processes can be employed to form the intermediate conductive layer on the contact layer 2310. The material of the intermediate conductive layer includes but is not limited to a conductive material such as metallic cobalt Co. Exemplarily, a reaction process such as an oxidation process can be employed to react the intermediate conductive layer with the contact layer 2310 to form the connection layer 2320. The material of the connection layer 2320 includes but is not limited to a metallic silicide such as cobalt silicide. For example, a reaction process such as an oxidation process can be employed to react the metallic cobalt Co with germanium-silicon GeSi to form the cobalt silicide CoSi.

[0134] Exemplarily, forming the conductive layer 2330 on the side of the connection layer 2320 away from the contact layer 2310 along the first direction Z can include: forming an initial conductive layer 2330-1 on the side of the connection layer 2320 away from the contact layer 2310 along the first direction Z and on the surface of the dielectric layer 2100 Figure 25 Figure 26

[0135] Exemplarily, one or more thin film deposition processes and removal processes can be employed to form the conductive layer 2330. The material of the conductive layer 2330 includes but is not limited to one or more conductive materials such as a metal and / or a metallic compound. For example Figure 26 As shown, the conductive layer 2330 can be a composite layer, and the material thereof can include titanium nitride TiN and metallic tungsten W surrounded by the titanium nitride TiN.

[0136] It is noted that in the process of forming the conductive layer 2330 on the side of the connection layer 2320 away from the contact layer 2310 along the first direction Z, conductive materials such as titanium nitride TiN and metallic tungsten W are inevitably formed on the surface of the dielectric layer 2100 along the second direction Z as well to form the initial conductive layer 2330-1.

[0137] Exemplarily, a planarization process such as a chemical mechanical polishing process can be performed to remove the portion of the initial conductive layer 2330-1 on the surface of the dielectric layer 2100, i.e. to remove excess conductive materials such as titanium nitride TiN and metallic tungsten W on the dielectric layer 2100, to form the conductive layer 2330.

[0138] Exemplarily, as shown Figure 27 ​​​As shown, a stacked structure 2400 can be formed on one side of the capacitor contact structure 2300 along the first direction Z, wherein the stacked structure 2400 includes alternately stacked support layers 2410 and sacrificial layers 2420.

[0139] like Figure 27 As shown, the material layers at both ends of the laminated structure 2400 can both be support layers 2410, and the number of support layers 2410 can be greater than the number of sacrificial layers 2420. It should be understood that the limitation on the number of support layers 2410 and sacrificial layers 2420 in this application is merely an example and not an explicit limitation. In actual processes, the number can be determined according to the subsequently formed capacitor 2500 (…). Figure 28 The required height should be reasonably set for the number of support layers 2410 and sacrificial layers 2420.

[0140] Exemplarily, a stacked structure 2400 can be formed by alternately stacking a support layer 2410 and a sacrificial layer 2420 through one or more thin-film deposition processes. Exemplarily, the material of the support layer 2410 may include any one or any combination of two or more of silicon nitride, silicon oxynitride, and aluminum oxide. Furthermore, the support layer 2410 may be doped with boron, carbon, or phosphorus. The material of the sacrificial layer 2420 may include any one or any combination of two or more of silicon oxide, silicon oxynitride, and polycrystalline silicon. The material of the sacrificial layer 2420 may be different from that of the support layer 2410 to achieve different etching rates in the same etching process using the same etchant. Exemplarily, in the same etching process using the same etchant, the etching (e.g., corrosion) rate of the sacrificial layer 2420 may be much greater than the etching rate of the support layer 2410, so that when most of the sacrificial layer 2420 is removed, the support layer 2410 is almost completely retained or only a small portion is removed. For example, the sacrificial layer 2420 may be made of silicon oxide, and the support layer 2410 may be made of silicon nitride doped with boron or carbon. The sacrificial layer 2420 may subsequently be removed using a wet etching process while retaining most of the support layer 2410. The wet etching solution may include at least one of a hydrofluoric acid solution and an ammonia solution of hydrofluoric acid.

[0141] For example, such as Figure 28 As shown, a capacitor 2500 can be formed that extends through the stacked structure 2400 and to the capacitor contact structure 2300. The capacitor 2500 may include a first electrode layer 2510 that extends through the stacked structure 2400 and to the capacitor contact structure 2300, a capacitor dielectric layer 2520 that covers at least a portion of the first electrode layer 2510, and a second electrode layer 2530 that covers at least a portion of the capacitor dielectric layer 2520.

[0142] For example, such as Figure 28As shown, a first layer 2610 extending in the first direction Z can also be formed on one side of the first electrode layer 2510 along the second direction X (e.g., the inner side of the first electrode layer 2510). For example, as... Figure 28 As shown, a second layer 2620 may also be formed on the side of the second electrode layer 2530 away from the capacitor dielectric layer 2520.

[0143] It should be noted that the processes for forming capacitor 2500, the first layer 2610, and the second layer 2620 are similar to those for forming capacitor 1500, the first layer 1610, and the second layer 1620. To avoid redundancy, this application will not describe these processes in detail here; however, please refer to the above description of the formation processes for capacitor 1500, the first layer 1610, and the second layer 1620. Figures 9 to 21 Related descriptions.

[0144] Figure 21 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of this application.

[0145] The semiconductor structure may include a capacitor contact structure 1300, a capacitor 1500, a dielectric layer 1100, and a first support layer 1411.

[0146] For example, such as Figure 21 As shown, the first direction Z, the second direction X, and the third direction Y can intersect each other. The semiconductor structure may further include semiconductor pillars 111, gate structures 112, and isolation structures 120. The semiconductor pillars 111 can be arrayed along the second direction X and the third direction Y. The gate structure 112 can be located on one side of the semiconductor pillars 111 along the second direction X. The isolation structure 120 can be located on the side of the semiconductor pillars 111 along the second direction X where the gate structure 112 is not provided, for electrically insulating adjacent semiconductor pillars 111 and reducing coupling between adjacent semiconductor pillars 111.

[0147] Semiconductor pillar 111 and gate structure 112 can be used together to form transistor 110, such as a vertical transistor, wherein semiconductor pillar 111 can be used to form active regions of multiple channels in vertical transistor 110. Exemplarily, gate structure 112 can be located on at least one side of semiconductor pillar 111, i.e., semiconductor pillar 111 can be at least partially surrounded by gate structure 112. For example, semiconductor pillar 111 and gate structure 112 can be arranged radially from the center of vertical transistor in this order.

[0148] It should be understood that Figure 21 The case shown where the gate structure 112 is located on one side of the semiconductor pillar 111 is merely an example and not a specific limitation.

[0149] In an embodiment of the present application, the gate structure 112 can be located on multiple sides of the semiconductor pillar 111, and the semiconductor pillar 111 and the gate structure 112 can be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off state, the leakage current of the multi-gate transistor can also be significantly reduced due to the complete depletion of the channel. Therefore, using the multi-gate transistor can achieve better speed (saturated drain current) / leakage current performance.

[0150] In another embodiment of the present application, the gate structure 112 can be located on one side of the semiconductor pillar 111, and the semiconductor pillar 111 and the gate structure 112 can be used together to form a single-gate transistor. Exemplarily, the single-gate transistors adjacent along the second direction X can be symmetrically arranged. By providing the single-gate transistor, the present application can significantly increase the density of the semiconductor pillars 111 in the second direction X, and reduce the difficulty of the manufacturing process. In addition, the symmetric single-gate transistors can have a larger process window, which is beneficial to reducing the spacing between the bit lines, word lines, and transistors, etc.

[0151] Exemplarily, the dielectric layer 1100 can be located on one side of the transistor 110 along the first direction Z and in contact with the transistor 110. The capacitive contact structure 1300 can penetrate the dielectric layer 1100 and extend to the semiconductor pillar 111. Exemplarily, the dielectric layer 1100 can be located on at least one side of the capacitive contact structure 1300 along the second direction X. For example, the dielectric layer 1100 can be located on both sides of the capacitive contact structure 1300 along the second direction X.

[0152] Exemplarily, the material of the dielectric layer 1100 can include any one or a combination of two or more of silicon nitride, silicon oxynitride, aluminum oxide, etc. In addition, the dielectric layer 1100 can be doped with boron, carbon, or phosphorus. Exemplarily, the material of the dielectric layer 1100 can be, for example, silicon nitride.

[0153] Exemplarily, the first support layer 1411 can be located on at least one side of the capacitive contact structure 1300 along the second direction X and in contact with the dielectric layer 1100 along the first direction Z. In other words, the first support layer 1411 can be located on one side of the dielectric layer 1100 along the first direction Z and in contact with the dielectric layer 1100. Part of the capacitive contact structure 1300 can pass through part of the first support layer 1411. The first support layer 1411, the dielectric layer 1100, and the transistor 110 can be sequentially distributed along the first direction Z.

[0154] Exemplarily, the material of the first support layer 1411 can include any one or a combination of two or more of silicon nitride, silicon oxynitride, aluminum oxide, etc. In addition, the first support layer 1411 can be doped with boron, carbon, or phosphorus. For example, the material of the first support layer 1411 can be, for example, boron- or carbon-doped silicon nitride.

[0155] Exemplarily, the material of the first support layer 1411 can be different from that of the dielectric layer 1100. The materials of the dielectric layer 1100 and the first support layer 1411 both include nitride, and the hardness of the first support layer 1411 can be relatively large, for example, the hardness of the first support layer 1411 can be greater than that of the dielectric layer 1100. For example, the material of the first support layer 1411 can be, for example, boron- or carbon-doped silicon nitride, and the material of the dielectric layer 1100 can be, for example, silicon nitride.

[0156] The capacitive contact structure 1300 can pass through the dielectric layer 1100 and part of the first support layer 1411 along the first direction Z. The capacitive contact structure 1300 can include a contact layer 1310, a connection layer 1320, and a conductive layer 1330. The contact layer 1310 can be in contact with the semiconductor column 111. The connection layer 1320 can be located on one side of the contact layer 1310 along the first direction Z. The conductive layer 1330 can be located on one side of the connection layer 1320 along the first direction Z away from the contact layer 1310.

[0157] Exemplarily, the dielectric layer 1100 can be located on at least one side of the contact layer 1310, the connection layer 1320, and part of the conductive layer 1330 along the second direction X. The first support layer 1411 can be located on at least one side of the remaining part of the conductive layer 1330 along the second direction X. In other words, the contact layer 1310, the connection layer 1320, and part of the conductive layer 1330 can pass through the dielectric layer 1100, and part of the conductive layer 1330 can pass through part of the first support layer 1411. The contact layer 1310, the connection layer 1320, and part of the conductive layer 1330 can be in contact with the dielectric layer 1100 along the second direction X, and the remaining conductive layer 1330 can be in contact with the first support layer 1411 along the second direction X.

[0158] Exemplarily, the size H1 of the capacitive contact structure 1300 along the first direction Z can be less than the sum H2 of the sizes of the dielectric layer 1100 and the first support layer 1411 along the first direction Z. In other words, the first support layer 1411 can cover the surface and part of the sidewall of the capacitive contact structure 1300 away from the semiconductor column 111 along the first direction Z.

[0159] In the present application, by arranging part of the conductive layer 1330 to be in contact with the first support layer 1411 along the second direction X, it is beneficial to realize the spacing of two adjacent capacitive contact structures 1300 along the second direction X by arranging the first support layer 1411, and thus it is beneficial to reduce the phenomenon of coupling between adjacent capacitive contact structures 1300.

[0160] In addition, the size of the capacitive contact structure 1300 along the second direction X can be larger in the case that the phenomenon of coupling between adjacent capacitive contact structures 1300 is reduced, thereby facilitating the reduction of the difficulty of the forming process of the capacitive contact structure 1300.

[0161] Exemplarily, the material of the contact layer 1310 can include a semiconductor material. For example, the material of the contact layer 1310 includes but is not limited to at least one of a semiconductor material such as polysilicon poly, germanium silicon GeSi, etc. By setting the material of the contact layer 1310 to be germanium silicon GeSi, for example, the present application can reduce the resistance between the semiconductor pillar 111 (the material of which can be silicon Si, for example) and the contact layer 1310 in contact. The material of the connecting layer 1320 can include a semiconductor compound material. For example, the material of the connecting layer 1320 includes but is not limited to a metal silicide such as cobalt silicide. The material of the conductive layer 1330 can include at least one of a metal material and a metal compound material. For example, the material of the conductive layer 1330 includes but is not limited to one or more conductive materials such as a metal and / or a metal compound. As shown, the conductive layer 1330 can be a composite layer, the material of which can include titanium nitride TiN and metal tungsten W surrounded by titanium nitride TiN. Figure 21

[0162] By setting the materials of the contact layer 1310, the connecting layer 1320 and the conductive layer 1330 to be a semiconductor material (such as germanium silicon GeSi), a metal silicide (such as cobalt silicon CoSi) and a plurality of conductive materials (such as titanium nitride TiN and metal tungsten W) respectively, the present application facilitates the reduction of the resistance between the contact layer 1310 and the connecting layer 1320 in contact, the connecting layer 1320 and the conductive layer 1330 in contact, and the different layers in contact in the conductive layer 1330.

[0163] On the other hand, by setting the capacitive contact structure 1300, the present application facilitates the connection of the first electrode layer 1510 in the capacitor 1500 to the transistor 110, and can reduce the risk that the first electrode layer 1510 and the word line (located on one side of the transistor 110 along the second direction X) are coupled together due to the direct contact of the first electrode layer 1510 to the transistor 110.

[0164] The capacitor 1500 can be located on one side of the capacitive contact structure 1300 along the first direction Z and connected to the capacitive contact structure 1300. Exemplarily, the transistor 110, the capacitive contact structure 1300 and the capacitor 1500 can be sequentially distributed along the first direction Z.

[0165] ​The capacitor 1500 can include a first electrode layer 1510, a capacitive dielectric layer 1520, and a second electrode layer 1530. The first electrode layer 1510 can be located on one side of the capacitive contact structure 1300 along the first direction Z and extend along the first direction Z. The capacitive dielectric layer 1520 can be located between the first electrode layer 1510 and the second electrode layer 1530.

[0166] Exemplarily, a portion of the first electrode layer 1510 can be located on at least one side of the first support layer 1411 along the second direction X. The first electrode layer 1510 can extend through the first support layer 1411 along the first direction Z and to the capacitive contact structure 1300. Exemplarily, the first electrode layer 1510 can be at least a portion of a barrel structure and extend along the first direction Z. Figure 18 and Figure 21 ) As shown, a cross-section of the first electrode layer 1510 along the second direction X can be in a U-shaped structure. It is noted that in an actual process, a portion of the first electrode layer 1510 can be removed, in which case the first electrode layer 1510 can be a portion of a barrel structure and extend along the first direction Z. Figure 21

[0167] Exemplarily, a material of the first electrode layer 1510 can include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the first electrode layer 1510 can include a compound formed by one or both of a metal nitride and a metal silicide, such as titanium nitride (TiN), titanium silicide (TiSi), nickel silicide (NiSi), titanium silicon nitride (TiSixNy), etc. Exemplarily, the material of the first electrode layer 1510 can be titanium nitride.

[0168] Exemplarily, the capacitive dielectric layer 1520 can cover at least a portion of the first electrode layer 1510. A material of the capacitive dielectric layer 1520 can include a high dielectric constant material. For example, the material of the capacitive dielectric layer 1520 can include, but is not limited to, at least one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), hafnium silicon oxynitride (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and / or praseodymium oxide (Pr2O3), etc., or a combination thereof.

[0169] ​The second electrode layer 1530 can cover at least a portion of the capacitor dielectric layer 1520. Illustratively, the second electrode layer 1530 can be located on a side of the capacitor dielectric layer 1520 away from the first electrode layer 1510 in the second direction X. Illustratively, the material of the second electrode layer 1530 can include at least one of a metal, a metal compound, a semiconductor material. For example, the material of the second electrode layer 1530 can include a compound formed by one or both of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride (TiSixNy), etc. In addition, the material of the second electrode layer 1530 can also include one or more than two of a stack formed by tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or a group consisting of the above materials.

[0170] Illustratively, the semiconductor structure can further include a second support layer 1412 and a third support layer 1413. The second support layer 1412 and the third support layer 1413 can be spaced apart in the first direction Z. The second support layer 1412 and / or the third support layer 1413 can be located between two adjacent first electrode layers 1510 and in contact with a portion of the first electrode layer 1510 and a portion of the capacitor dielectric layer 1520.

[0171] Illustratively, the material of the second support layer 1412 and the third support layer 1413 can also be, for example, silicon nitride doped with boron or carbon. By setting the material of the first support layer 1411, the second support layer 1412 and the third support layer 1413 to be doped silicon nitride, the present application is advantageous to improve the hardness of the three layers, and thus is advantageous to improve the support of the three layers, and thus is advantageous to improve the mechanical strength of the structure of the capacitor 1500, and reduce the damage to the capacitor 1500 in the manufacturing process (such as grinding, etc.).

[0172] Illustratively, the semiconductor structure can further include a first layer 1610 and a second layer 1620. The first layer 1610 can be located on a side of the first electrode layer 1510 away from the capacitor dielectric layer 1520. The second layer 1620 can be located on a side of the second electrode layer 1530 away from the capacitor dielectric layer 1520.

[0173] Illustratively, the material of the first layer 1610 can include at least one of a semiconductor material and an insulating material. In an embodiment of the present application, the material of the first layer 1610 can include a conductive material such as titanium carbide, etc., to serve as one electrode of the capacitor 1500 together with the first electrode layer 1510. In another embodiment of the present application, the material of the first layer 1610 can include at least one of a semiconductor material and an insulating material such as polysilicon or an insulating material, etc., to provide a support function.

[0174] Exemplarily, the second layer 1620 can cover the entire second electrode layer 1530. Exemplarily, the second layer 1620 can have a plurality of insulating gaps therein to relieve structural stress. Exemplarily, the material of the second layer 1620 can include a conductive material such as a doped semiconductor material or the like. For example, the material of the second layer 1620 can include boron-doped germanium silicon. Exemplarily, the second layer 1620 can be connected with other conductive structures (not shown) for enabling connection of the capacitor 1500 with other conductive structures such as a peripheral circuit.

[0175] Since the content and structures involved in the above-described method 1000 of fabricating a semiconductor structure can be fully or partially applicable to the semiconductor structures described herein, the content related thereto or similar thereto will not be repeated here.

[0176] Although exemplary structures and fabrication methods of semiconductor structures are described herein, it is understood that one or more features can be omitted, replaced, or added from the fabrication methods of the semiconductor structures. In addition, the exemplified layers and their materials are merely exemplary.

[0177] Figure 29 is a schematic block diagram of a memory 3000 according to an exemplary embodiment of the present application. The memory 3000 can include a memory cell array 3100 and a peripheral circuit 3200.

[0178] The memory cell array 3100 and the peripheral circuit 3200 can be separately formed on different substrates and then bonded to form the memory 3000.

[0179] The peripheral circuit 3200 can be coupled to the memory cell array 3100. The peripheral circuit 3200 (also referred to as a control and sensing circuit) can include any suitable digital, analog, and / or mixed-signal circuitry for facilitating operation of the memory cell array 3100. For example, the peripheral circuit 3200 can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion of the above functional circuitry (e.g., a sub-circuit), or any active or passive components of the circuitry (e.g., a transistor, a diode, a resistor, or a capacitor).

[0180] The memory cell array 3100 can include an array of memory cells (such as the semiconductor structure described above) that use transistors as switching and selection devices. In some implementations, the memory cell array 3100 includes an array of DRAM cells. For ease of description, an array of DRAM cells can be used as an example for describing the memory cell array 3100 in this disclosure. However, it is understood that the memory cell array 3100 is not limited to an array of DRAM cells, and can include any other suitable type of memory cell array that can use transistors as switching and selection devices, such as an array of PCM cells, an array of static random-access memory (SRAM) cells, an array of FRAM cells, an array of resistive memory cells, an array of magnetic memory cells, an array of spin transfer torque (STT) memory cells, just to name a few examples, or any combination thereof. The memory cell array 3100 can be a DRAM device in which memory cells are provided in the form of an array of DRAM cells. In some implementations, each DRAM cell is a transistor-capacitor (1T1C) cell. The DRAM cells can be refreshed, such as by the peripheral circuitry 3200, to maintain data.

[0181] Figure 30 is a block diagram of a system 10 having a storage system 12 of an example implementation of the present disclosure.

[0182] The system 10 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device that has a storage system 12 located therein. As shown, the system 10 can include a host 18 and a storage system 12 having one or more memories 3000 (such as can include a three-dimensional memory 14) and a controller 16. The host 18 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 18 can be configured to send or receive data to or from the three-dimensional memory 14. Figure 30

[0183] ​The three-dimensional memory 14 can include a semiconductor structure as described in any embodiment of the present disclosure. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14, and communicate with the host 18. For example, the controller 16 can communicate with external devices (e.g., the host 18) according to a particular communication protocol.

[0184] The above description is merely exemplary of the application and of the application of the principles of the application. It is not intended to limit the scope of the disclosure to the specific forms presented, but to cover all modifications and equivalents thereof which are within the scope of the concepts disclosed. For example, the features of the described embodiments can be combined in any combination desired to produce other embodiments which are within the scope of the present application.

Claims

1. A semiconductor structure, wherein, include: Capacitor contact structure; A capacitor is located on one side of the capacitor contact structure along the first direction and is connected to the capacitor contact structure; A dielectric layer is located on at least one side of the capacitor contact structure along the second direction; as well as A first support layer is located on at least one side of the capacitive contact structure along the second direction and is in contact with the dielectric layer along the first direction; Wherein, the second direction intersects with the first direction.

2. The semiconductor structure according to claim 1, wherein, The materials of the dielectric layer and the first support layer are different.

3. The semiconductor structure according to claim 2, wherein, Both the dielectric layer and the first support layer are made of nitrides, and the hardness of the first support layer is greater than that of the dielectric layer.

4. The semiconductor structure according to claim 1, wherein, The dimension of the capacitive contact structure along the first direction is smaller than the sum of the dimensions of the dielectric layer and the first support layer along the first direction.

5. The semiconductor structure according to claim 1, wherein, The capacitor contact structure includes: Contact layer; A connecting layer, located on one side of the contact layer along the first direction; and A conductive layer is located on the side of the connecting layer away from the contact layer along the first direction; The dielectric layer is located on at least one side of the contact layer, the connecting layer, and a portion of the conductive layer along the second direction, and the first support layer is located on at least one side of the remaining portion of the conductive layer along the second direction.

6. The semiconductor structure according to claim 5, wherein, The material of the contact layer includes semiconductor materials; The material of the connecting layer includes a semiconductor compound material; and The material of the conductive layer includes at least one of metallic materials and metallic compound materials.

7. The semiconductor structure according to claim 1, wherein, The capacitor includes: The first electrode layer is located on one side of the capacitor contact structure along the first direction and extends along the first direction; Second electrode layer; and A capacitor dielectric layer is located between the first electrode layer and the second electrode layer.

8. The semiconductor structure according to claim 7, wherein, A portion of the first electrode layer is located on at least one side of the first support layer along the second direction.

9. The semiconductor structure according to claim 7, wherein, The materials of the first electrode layer and the second electrode layer include at least one selected from metals, metal compounds, and semiconductor materials; and The dielectric layer of the capacitor is made of a material with a high dielectric constant.

10. The semiconductor structure according to claim 7, wherein, The semiconductor structure also includes: A first layer, located on the side of the first electrode layer away from the capacitor dielectric layer, wherein the material of the first layer includes at least one of a conductive material, a semiconductor material, and an insulating material; and The second layer is located on the side of the second electrode layer away from the capacitor dielectric layer, and the material of the second layer includes a conductive material.

11. The semiconductor structure according to any one of claims 1-10, wherein, The semiconductor structure also includes a transistor located on the side of the capacitive contact structure away from the capacitor.

12. The semiconductor structure according to any one of claims 7-10, wherein, The semiconductor structure also includes: The second support layer is located between two adjacent first electrode layers and is in contact with a portion of the first electrode layer and a portion of the capacitor dielectric layer.

13. A method for manufacturing a semiconductor structure, wherein, include: A dielectric layer and a first sacrificial layer are formed sequentially along a first direction; A capacitive contact structure is formed that extends through the first sacrificial layer and the dielectric layer; Remove the first sacrificial layer to form a first sacrificial gap; A first support layer is formed in the first sacrificial gap and on one side of the capacitor contact structure along the first direction; as well as A capacitor is formed that passes through a portion of the first support layer and extends to the capacitor contact structure.

14. The method according to claim 13, wherein, Forming a capacitive contact structure penetrating the first sacrificial layer and the dielectric layer includes: A capacitor contact hole is formed that penetrates the first sacrificial layer and the dielectric layer; A contact layer of the capacitor contact structure is formed inside the capacitor contact hole; A connection layer of the capacitor contact structure is formed on one side of the contact layer along the first direction; and A conductive layer of the capacitive contact structure is formed on the side of the connection layer away from the contact layer along the first direction. The contact layer, the connecting layer, and a portion of the conductive layer penetrate the dielectric layer, and a portion of the conductive layer penetrates the first sacrificial layer.

15. The method according to claim 14, wherein, A connecting layer is formed on one side of the contact layer along the first direction, comprising: An intermediate conductive layer in contact with the contact layer is formed on one side of the contact layer along the first direction; and The intermediate conductive layer reacts with the contact layer to form the connection layer.

16. The method of claim 14, wherein, A conductive layer is formed on the side of the connection layer away from the contact layer along the first direction, including: An initial conductive layer is formed on the side of the connecting layer away from the contact layer along the first direction and on the surface of the first sacrificial layer; and A grinding process is used to remove the portion of the initial conductive layer located on the surface of the first sacrificial layer, wherein the remaining portion of the initial conductive layer forms the conductive layer.

17. The method according to claim 13, wherein, The material of the first sacrificial layer includes an oxide, and the material of the dielectric layer includes a nitride, wherein removing the first sacrificial layer includes: The first sacrificial layer is removed using a wet removal process.

18. The method according to claim 13, wherein, A first support layer is formed on one side of the first sacrificial gap and the capacitive contact structure along the first direction, comprising: A stacked structure is formed on one side of the first sacrificial gap and the capacitive contact structure along the first direction, wherein the stacked structure includes alternately stacked support layers and second sacrificial layers, and the support layers include the first support layer.

19. The method according to claim 18, wherein, Forming a capacitor that passes through a portion of the first support layer and extends to the capacitor contact structure includes: A capacitor hole is formed that penetrates the stacked structure and extends to the capacitor contact structure; A first electrode layer extending to the capacitor contact structure is formed within the capacitor hole; and A capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer are formed.

20. The method according to claim 19, wherein, A first electrode layer extending to the capacitor contact structure is formed within the capacitor hole, comprising: The first electrode layer is formed on the sidewall of the capacitor hole; and A first layer is formed in the remaining space of the capacitor hole.

21. The method according to claim 19, wherein, Forming a capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer, comprising: Remove the second sacrificial layer to expose the first electrode layer; Forming the capacitor dielectric layer covering at least a portion of the first electrode layer; and A second electrode layer is formed on the side of the capacitor dielectric layer away from the first electrode layer, covering at least a portion of the capacitor dielectric layer.

22. The method according to claim 21, wherein, Removing the second sacrificial layer includes: Remove a portion of the support layer to expose the second sacrificial layer; and Remove the exposed second sacrificial layer to form a second sacrificial gap.

23. The method according to claim 22, wherein, Forming the capacitor dielectric layer covering at least a portion of the first electrode layer includes: A capacitor dielectric layer is formed within the second sacrificial gap, covering at least a portion of the first electrode layer.

24. The method according to any one of claims 19-23, wherein, The method further includes: A second layer is formed on the side of the second electrode layer away from the capacitor dielectric layer.

25. The method according to any one of claims 19-23, wherein, The method further includes: A transistor is formed, wherein the transistor is located on the side of the capacitor contact structure away from the capacitor.

26. A memory, wherein, include: A memory cell array, comprising the semiconductor structure as described in any one of claims 1 to 12; as well as The peripheral circuitry is coupled to the memory cell array.

27. A storage system, wherein, include: The memory as described in claim 26; as well as A controller, coupled to the memory, is used to control the memory to store data.

Images