Semiconductor device manufacturing method, semiconductor device and electronic equipment
By stacking layers on both sides of a substrate, the manufacturing method solves the problems of high process difficulty and performance degradation caused by excessive stacking layers on one side of semiconductor devices, enabling semiconductor devices with more stacked layers and improving device uniformity and performance.
Patent Information
- Application Number
- CN202410609202.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-16
- Publication Date
- 2025-11-18
AI Technical Summary
In existing semiconductor devices, as critical dimensions shrink and the number of devices increases, minute differences in the manufacturing process can affect device performance. Furthermore, stacking on one side can lead to excessive layers, resulting in increased manufacturing complexity and performance degradation.
A multilayer memory cell array is formed by stacking on both sides of a substrate. The first memory array is formed on the substrate and then flipped to thin it to the target thickness. A second memory array is then formed on the side facing the substrate. The thickness is controlled by techniques such as ion implantation and chemical mechanical polishing to form a continuously stacked multilayer memory cell array.
This enables semiconductor devices with more stacked layers, avoiding the problems of high process difficulty and performance degradation when there are too many stacked layers on one side, and improving the uniformity and performance of the devices.
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Figure CN120980873A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the present disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, in particular to a semiconductor device manufacturing method, a semiconductor device and an electronic device. BACKGROUND
[0002] With the development of integrated circuit technology, the critical dimension of the device is becoming smaller and smaller, and the types and quantities of devices contained in a single chip are increasing, so that any slight difference in process production may affect the performance of the device.
[0003] In order to reduce the cost of products as much as possible and improve the storage density, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY
[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the claims.
[0005] The present application provides a semiconductor device manufacturing method, a semiconductor device and an electronic device, which realizes more stacked layers of semiconductor devices and avoids performance degradation of the device.
[0006] The present application provides a semiconductor device manufacturing method, comprising:
[0007] providing a substrate, forming a first memory array on the substrate, the first memory array comprising a plurality of layers of memory cell arrays stacked in a direction perpendicular to the substrate, the memory cell array comprising a plurality of memory cells, the memory cell comprising a transistor, the transistor comprising a semiconductor pillar extending in a direction parallel to the substrate;
[0008] forming a protective layer completely covering the first memory array;
[0009] turning over the substrate on which the first memory array is formed, and thinning the substrate to a target thickness;
[0010] forming a second memory array on the side of the first memory array facing the substrate, the second memory array comprising a plurality of layers of the memory cell array stacked in a direction perpendicular to the substrate, and the thinned substrate forming a plurality of semiconductor pillars of a plurality of memory cells of a layer of memory cell arrays of the second memory array.
[0011] In some embodiments, the target thickness is the thickness of the semiconductor pillar in a direction perpendicular to the substrate.
[0012] In some embodiments, the thinning of the substrate to a target thickness comprises:
[0013] performing at least one chemical mechanical polishing thinning on the substrate to a preset thickness;
[0014] performing at least one of ion implantation to form microcavities, annealing and peeling from the microcavities on the substrate to thin the substrate from the preset thickness to the target thickness.
[0015] In some embodiments, the preset thickness is 2 microns to 7 microns, and the target thickness is 30 nanometers to 100 nanometers.
[0016] In some embodiments, the ion implantation includes implanting at least one of helium ions and hydrogen ions.
[0017] In some embodiments, the ion implantation has an implantation dose of 0.2e^17 / cm^2 to 1e^17 / cm^2.
[0018] In some embodiments, the annealing temperature is 400°C to 600°C.
[0019] In some embodiments, the forming a first memory array on the substrate includes:
[0020] forming a stack structure including alternately arranged sacrificial layers and semiconductor layers on the substrate;
[0021] etching the semiconductor layers to form a plurality of semiconductor pillars extending along a first direction parallel to the substrate;
[0022] forming word lines extending along a second direction parallel to the substrate, the word lines surrounding a plurality of semiconductor pillars distributed along the second direction, etching end portions of the semiconductor pillars along a direction perpendicular to the substrate to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, and forming bit lines connected to the end surface of the semiconductor pillars; or, forming word lines extending along a direction perpendicular to the substrate, the word lines surrounding a plurality of semiconductor pillars at the same position of different layers, etching end portions of the semiconductor pillars to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, and forming bit lines extending along the second direction connected to the end surface of the semiconductor pillars; the first direction and the second direction intersect.
[0023] In some embodiments, the forming a second memory array on a side of the first memory array facing the substrate includes:
[0024] forming a stack structure including alternately arranged sacrificial layers and semiconductor layers on a side of the substrate away from the first memory array;
[0025] etching the substrate and the semiconductor layer so that the substrate and the semiconductor layer are both formed into a plurality of semiconductor pillars extending along a first direction parallel to the substrate;
[0026] forming word lines extending along a second direction parallel to the substrate, the word lines surrounding a plurality of semiconductor pillars distributed along the second direction, etching end portions of the semiconductor pillars along a direction perpendicular to the substrate to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, forming bit lines connected to the end surface of the semiconductor pillars; or, forming word lines extending along a direction perpendicular to the substrate, the word lines surrounding a plurality of semiconductor pillars at the same position of different layers, etching end portions of the semiconductor pillars to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, forming bit lines extending along the second direction connected to the end surface of the semiconductor pillars; the first direction and the second direction intersect.
[0027] Embodiments of the present disclosure provide a semiconductor device, comprising: a multilayer memory cell array, and a part of layers of the multilayer memory cell array constitute a first memory array, and another part of layers of the multilayer memory cell array constitute a second memory array, wherein the multilayer memory cell array constituting the first memory array is stacked along a third direction, and the multilayer memory cell array constituting the second memory array is arranged on a side of the memory cell array of the bottom layer of the first memory array away from the first memory array and stacked in a direction opposite to the third direction; wherein the memory cell array comprises a plurality of memory cells, and the memory cell comprises a transistor, and the transistor comprises a semiconductor pillar extending along a first direction, and the first direction is perpendicular to the third direction. Embodiments of the present disclosure provide an electronic device comprising the above semiconductor device, or a semiconductor device formed by using a manufacturing method of the above semiconductor device.
[0028] This application includes a method for manufacturing a semiconductor device and a semiconductor device and electronic device. The method for manufacturing the semiconductor device includes: providing a substrate; forming a first memory array on the substrate, the first memory array including multiple memory cell arrays stacked along a direction perpendicular to the substrate; the memory array including multiple memory cells; each memory cell including a transistor; each transistor including a semiconductor pillar extending along a direction parallel to the substrate; forming a protective layer completely covering the first memory array; flipping the substrate on which the first memory array is formed; thinning the substrate to a target thickness; forming a second memory array on the side of the first memory array facing the substrate, the second memory array including multiple memory cell arrays stacked along a direction perpendicular to the substrate, and the thinned substrate forming multiple semiconductor pillars of multiple memory cells in a single memory cell array of the second memory array. The solution provided in this embodiment, by stacking on both sides of the substrate, can realize a device with a large number of stacked layers. Compared with the single-sided stacking solution, the number of layers stacked on the same side is greatly reduced, avoiding the problems of high process difficulty and performance degradation when stacking too many layers on one side. Furthermore, the substrate also forms a memory cell array, so the first memory array and the second memory array can form a continuously stacked multi-layer memory cell array.
[0029] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.
[0030] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0031] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0032] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device, provided as an exemplary embodiment;
[0033] Figure 2 A cross-sectional view along the BB' direction perpendicular to the substrate after forming a stacked structure, provided for an exemplary embodiment;
[0034] Figure 3A A cross-sectional view along a direction parallel to the substrate after the formation of the first trench, provided as an exemplary embodiment. Figure 3B For along Figure 3A A cross-sectional view perpendicular to the substrate along the AA' direction. Figure 3C For along Figure 3Aa cross-sectional view perpendicular to the substrate in the BB' direction;
[0035] Figure 4A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the first and second insulating layers, Figure 4B a cross-sectional view perpendicular to the substrate in the BB' direction after forming the first and second insulating layers, Figure 4A a cross-sectional view perpendicular to the substrate in the AA' direction, Figure 4C a cross-sectional view perpendicular to the substrate in the AA' direction after forming the first and second insulating layers, Figure 4A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the first and second insulating layers, Figure 4D a cross-sectional view perpendicular to the substrate in the BB' direction after forming the first and second insulating layers, Figure 4A a cross-sectional view perpendicular to the substrate in the CC' direction after forming the first and second insulating layers;
[0036] Figure 5A a cross-sectional view perpendicular to the substrate in the BB' direction after exposing the channel region, Figure 5B a cross-sectional view perpendicular to the substrate in the BB' direction after exposing the channel region, Figure 5A a cross-sectional view perpendicular to the substrate in the AA' direction after exposing the channel region, Figure 5C a cross-sectional view perpendicular to the substrate in the AA' direction after exposing the channel region, Figure 5A a cross-sectional view perpendicular to the substrate in the BB' direction after exposing the channel region;
[0037] Figure 6A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the third insulating layer, Figure 6B a cross-sectional view perpendicular to the substrate in the BB' direction after forming the third insulating layer, Figure 6A a cross-sectional view perpendicular to the substrate in the AA' direction after forming the third insulating layer, Figure 6C a cross-sectional view perpendicular to the substrate in the AA' direction after forming the third insulating layer, Figure 6A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the third insulating layer;
[0038] Figure 7A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the bit line, Figure 7B a cross-sectional view perpendicular to the substrate in the BB' direction after forming the bit line, Figure 7A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the bit line;
[0039] Figure 8A a cross-sectional view perpendicular to the substrate in the BB' direction after exposing the capacitor region, Figure 8B a cross-sectional view perpendicular to the substrate in the BB' direction after exposing the capacitor region, Figure 8A a cross-sectional view perpendicular to the substrate in the BB' direction after exposing the capacitor region;
[0040] Figure 9A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the first and second capacitor electrodes and the dielectric layer, Figure 9B a cross-sectional view perpendicular to the substrate in the BB' direction after forming the first and second capacitor electrodes and the dielectric layer, Figure 9A a cross-sectional view perpendicular to the substrate in the BB' direction after forming the first and second capacitor electrodes and the dielectric layer;
[0041] Figure 10 a perspective view of a protective layer according to an exemplary embodiment;
[0042] Figure 11AA front view of a device after flip and thinning is provided for an exemplary embodiment.
[0043] Figure 11B A front view of a device after ion implantation is provided for an exemplary embodiment.
[0044] Figure 11C A schematic view of a device after peeling is provided for an exemplary embodiment.
[0045] Figure 11D A schematic view of a device after substrate thinning is provided for an exemplary embodiment.
[0046] Figure 12 A schematic view of a device after forming a second memory array is provided for an exemplary embodiment. DETAILED DESCRIPTION
[0047] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The features of the embodiments of the present disclosure and the embodiments can be arbitrarily combined with each other unless they conflict.
[0048] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those understood by a person of ordinary skill in the art to which the present disclosure belongs.
[0049] The embodiments of the present disclosure are not necessarily limited to the shapes and sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings can be changed arbitrarily. The components of the embodiments of the present disclosure are not limited to the shapes and values shown in the drawings.
[0050] In the present disclosure, ordinal terms such as "first", "second", "third", and the like are used to avoid confusion among components, and do not indicate any order, number, or importance.
[0051] In the present disclosure, for convenience, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately changed according to the situation.
[0052] In the present disclosure, unless clearly specified and limited, the terms "mounting", "connection", and "linking" should be interpreted in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate element, or a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.
[0053] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.
[0054] In the present disclosure, "connection" includes a case where constituent elements are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
[0055] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.
[0056] In the present disclosure, "A and B are in an integral structure" can mean that there is no obvious boundary interface such as a fault or a gap in the microstructure. Generally, the connected film layers are in an integral structure when the film layers are patterned on one film layer. For example, A and B use the same material to form one film layer and are simultaneously formed into a structure having a connection relationship by the same patterning process.
[0057] In the present disclosure, "the orthographic projection of B is located within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
[0058] Based on low dislocation, full strain, and high number of layers, a silicon / silicon germanium (Si / SiGe) stack can realize multi-layer horizontal stacking of dynamic random access memory (DRAM). However, the number of layers of the Si / SiGe stack is limited due to a critical thickness. Since the lattice mismatch between Si and Ge is up to 4%, a direct epitaxial Si 1-x Ge x layer on Si is strained due to the lattice mismatch. When the strain exceeds a critical value, strain relaxation occurs, dislocations are generated, and the performance of the Si channel is affected. Moreover, the critical thickness decreases exponentially with the increase of the Ge concentration. In the process of realizing a 3D DRAM device by using a Si / SiGe stack, the Ge concentration cannot be infinitely reduced due to the requirement of a selective etching process of SiGe and Si. Furthermore, when the number of stacked layers is too high, the process difficulty of etching, thin film deposition, and the like is increased. In the embodiments of the present disclosure, the number of stacked layers of the 3D DRAM is increased by stacking on both sides of the substrate, and the problems of high process difficulty and performance degradation caused by too many stacked layers on one side are avoided.
[0059] Figure 1 A flowchart of a method for manufacturing a semiconductor device is provided for an exemplary embodiment. As shown in Figure 1 , the present disclosure provides a method for manufacturing a semiconductor device, comprising:
[0060] 101, providing a substrate, forming a first memory array on the substrate, the first memory array comprising a plurality of memory cell arrays stacked in a direction perpendicular to the substrate, the memory cell array comprising a plurality of memory cells, the memory cell comprising a transistor, the transistor comprising a semiconductor pillar extending in a direction parallel to the substrate;
[0061] 102, forming a protective layer completely covering the first memory array;
[0062] 103, flipping the substrate on which the first memory array is formed, and thinning the substrate to a target thickness;
[0063] 104, forming a second memory array on the side of the first memory array facing the substrate, the second memory array comprising a plurality of memory cell arrays stacked in a direction perpendicular to the substrate, and the thinned substrate forming a plurality of semiconductor pillars of a plurality of memory cells of one memory cell array of the second memory array.
[0064] The scheme provided by the embodiment can realize a device with a large number of stacked layers by stacking on both sides of the substrate, and compared with the implementation scheme of single-side stacking, the number of same-side stacked layers is greatly reduced, avoiding the problems of great process difficulty and performance degradation when the number of single-side stacked layers is too large, and the substrate also forms a memory cell array, so that the first memory array and the second memory array can form a continuous multi-layer memory cell array.
[0065] In some embodiments, the target thickness can be the same or substantially the same as the thickness of the semiconductor pillars in the vertical direction of the substrate. The scheme provided by the embodiment can improve the uniformity of the semiconductor device formed by stacking. However, the embodiments of the present disclosure are not limited thereto, and the target thickness can be other thicknesses, that is, the thickness of the semiconductor pillars after the substrate 1 is thinned to be used as memory cells.
[0066] In some embodiments, the thinning of the substrate to the target thickness can include:
[0067] Thinning the substrate to a preset thickness by at least one chemical mechanical polishing, for example, multiple chemical mechanical polishings can be performed; the preset thickness can be greater than and close to the target thickness, and cannot be thinned by chemical mechanical polishing (because the thickness thinned by chemical mechanical polishing is large, it is not conducive to control the thickness of the final substrate).
[0068] Thinning the substrate from the preset thickness to the target thickness by at least one of the following operations: forming a microcavity by ion implantation on the substrate, annealing, and peeling off from the microcavity.
[0069] The above thinning method is only an example, and other methods can be used for thinning.
[0070] In some embodiments, the preset thickness can be 2 microns to 7 microns.
[0071] In some embodiments, the target thickness can be 30 nanometers to 100 nanometers.
[0072] In some embodiments, forming the first memory array on the substrate can include:
[0073] forming a stack structure including alternately arranged sacrificial layers and semiconductor layers on the substrate;
[0074] etching the semiconductor layers to form a plurality of semiconductor pillars extending in a first direction parallel to the substrate;
[0075] forming word lines extending along a second direction parallel to the substrate, the word lines encircling a plurality of semiconductor pillars distributed along the second direction, the first direction and the second direction being crossed; etching end portions of the semiconductor pillars along a direction perpendicular to the substrate to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, forming bit lines connected to the end surface of the semiconductor pillars;
[0076] forming a capacitor encircling the semiconductor pillars on a side of the word line facing away from the bit line.
[0077] That is, a memory cell is formed as follows:
[0078] The transistor includes a semiconductor pillar distributed along a first direction, a gate electrode encircling the semiconductor pillar, a capacitor located on a side of the gate electrode and encircling the semiconductor pillar, a bit line located on a side of the gate electrode facing away from the capacitor, and the bit line is connected to one end surface of the semiconductor pillar (the semiconductor pillar can include two end surfaces and a sidewall extending along the first direction connecting the two end surfaces). The gate electrodes of the transistors distributed along a second direction are connected to form an integrated structure, i.e., the word line. The bit lines of the memory cells at the same position in different layers can be connected to form an integrated structure.
[0079] In another exemplary embodiment, the forming a first memory array on the substrate can include:
[0080] forming a stack structure including alternately arranged sacrificial layers and semiconductor layers on the substrate;
[0081] etching the semiconductor layers to form a plurality of semiconductor pillars extending along a first direction parallel to the substrate;
[0082] forming word lines extending along a direction perpendicular to the substrate, the word lines encircling a plurality of semiconductor pillars at the same position in different layers, etching end portions of the semiconductor pillars to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, forming bit lines extending along the second direction connected to the end surface of the semiconductor pillars, the bit lines can be connected to a plurality of semiconductor pillars distributed along the second direction in the same layer; the first direction and the second direction being crossed;
[0083] In some embodiments, the memory cell can further include a capacitor, the transistor and the capacitor being distributed along a direction parallel to the substrate;
[0084] The forming a first memory array on the substrate can further include forming a capacitor encircling the semiconductor pillars on a side of the word line facing away from the bit line.
[0085] That is, in this embodiment, a vertically extending word line and a horizontally extending bit line can be formed.
[0086] The forming method of the second memory array is similar to that of the first memory array, and will not be described again. When the second memory array is formed, the substrate is used as one of the semiconductor layers, and the other semiconductor layers are used to form the memory cell array.
[0087] In some embodiments, the forming of the second memory array on the side of the first memory array facing the substrate comprises:
[0088] forming a stack structure comprising alternatingly arranged sacrificial layers and semiconductor layers on the side of the substrate away from the first memory array;
[0089] etching the substrate and the semiconductor layers so that both the substrate and the semiconductor layers form a plurality of semiconductor pillars extending along a first direction parallel to the substrate;
[0090] forming word lines extending along a second direction parallel to the substrate, the word lines surrounding a plurality of semiconductor pillars distributed along the second direction, etching end portions of the semiconductor pillars along a direction perpendicular to the substrate to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, and forming bit lines connected to the end surface of the semiconductor pillars; or forming word lines extending along a direction perpendicular to the substrate, the word lines surrounding a plurality of semiconductor pillars at the same position of different layers, etching end portions of the semiconductor pillars to remove part of the semiconductor pillars and expose one end surface of the semiconductor pillars, and forming bit lines extending along the second direction connected to the end surface of the semiconductor pillars; the first direction and the second direction intersect.
[0091] In some embodiments, the memory cell can be a 2T0C memory cell.
[0092] The semiconductor device provided by the embodiments of the present disclosure comprises: a multilayer memory cell array, and a part of layers of the multilayer memory cell array form a first memory array, and another part of layers of the multilayer memory cell array form a second memory array, wherein the multilayer memory cell array forming the first memory array is stacked along a third direction, and the multilayer memory cell array forming the second memory array is arranged on the side of the memory cell array of the bottom layer of the first memory array away from the first memory array and is stacked in the opposite direction of the third direction; wherein the memory cell array comprises a plurality of memory cells, and each memory cell comprises a transistor, and the transistor comprises a semiconductor pillar extending along a first direction, and the first direction is perpendicular to the third direction.
[0093] The semiconductor device formed by the scheme provided by the embodiments can be stacked in two directions to form a memory cell array, the number of layers stacked on the same side is greatly reduced, and the problems of great process difficulty and performance decline caused by too many layers stacked on one side are avoided. The semiconductor device described above can be free of a substrate, or can be stacked on a substrate after manufacturing is completed.
[0094] In some embodiments, the first memory array can include a number of layers of memory cell arrays, and the second memory array can include a number of layers of memory cell arrays, which can be the same or different.
[0095] In some embodiments, the semiconductor device can further include: word lines extending in a second direction, the second direction being perpendicular to the first direction; the word lines encircling a plurality of semiconductor pillars distributed in the second direction; or, word lines extending in a third direction; the word lines encircling a plurality of semiconductor pillars in the same position in different layers.
[0096] The manufacturing process of the semiconductor device is described below by an example.
[0097] In some embodiments, the manufacturing process of the semiconductor device can include:
[0098] 1) forming a stack structure;
[0099] A stack structure including alternately arranged sacrificial layers 9 and semiconductor layers 10 is formed by sequentially and alternately depositing sacrificial layer thin films and semiconductor thin films on a substrate 1; as shown in Figure 2 Figure 2 A cross-sectional view of an exemplary embodiment provided after forming the stack structure along the BB' direction perpendicular to the substrate is shown.
[0100] In some embodiments, the sacrificial layer thin film can be silicon germanium (SiGe) or the like.
[0101] In some embodiments, the substrate 1 can be a semiconductor substrate. For example, it can be consistent with the semiconductor thin film material.
[0102] In some embodiments, the material of the semiconductor layer thin film can be silicon or polysilicon or the like with a band gap less than 1.65 eV, or can be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.
[0103] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, and the like; and can also include other small amounts of doped elements.
[0104] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.
[0105] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.
[0106] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.
[0107] Figure 2 The image only shows a stack of three sacrificial layers 9 and three semiconductor layers 10, which is just an example and could have more or fewer sacrificial layers 9 and semiconductor layers 10.
[0108] 2) Form the first trench T1;
[0109] A plurality of first trenches T1 are formed, penetrating the stacked structure and extending along a first direction X; the plurality of first trenches T1 divide the semiconductor layer 10 into a plurality of semiconductor pillars 20 extending along the first direction X; as Figure 3A , Figure 3B and Figure 3C As shown, where, Figure 3A A cross-sectional view along a direction parallel to the substrate 1 after the formation of the first trench T1 is provided as an exemplary embodiment. Figure 3B For along Figure 3A A cross-sectional view perpendicular to substrate 1 along the AA' direction. Figure 3C For along Figure 3A A cross-sectional view perpendicular to substrate 1 along the BB' direction.
[0110] In some embodiments, the semiconductor pillar 20 is, for example, a cuboid.
[0111] 3) Form the first insulating layer 11 and the second insulating layer 12;
[0112] A first insulating film is deposited to fill the first trench T1, forming a first insulating layer 11;
[0113] The first insulating layer 11 and the sacrificial layer 9 of the preset isolation region 100 are removed by etching, while the semiconductor pillars 20 in the preset isolation region 100 are retained; the orthogonal projection of the preset isolation region 100 onto the substrate 1 extends along the second direction Y.
[0114] A second insulating film is deposited to form a second insulating layer 12 that fills the predetermined isolation region 100, such as... Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown, where, Figure 4A A cross-sectional view provided for an exemplary embodiment after the formation of the first insulating layer 11 and the second insulating layer 12, along a direction parallel to the substrate 1. Figure 4B For along Figure 4A A cross-sectional view perpendicular to substrate 1 along the AA' direction. Figure 4C For along Figure 4A A cross-sectional view perpendicular to substrate 1 along the BB' direction. Figure 4D For along Figure 4A A cross-sectional view perpendicular to substrate 1 along the CC' direction.
[0115] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).
[0116] In some embodiments, the second insulating film may be a low-K dielectric layer with an etching selectivity ratio to the first insulating film, such as silicon nitride (SiN). In this step, the area to be subsequently formed into a capacitor is spaced out by the second insulating layer 12.
[0117] 4) Exposed trench area;
[0118] The first insulating layer 11 of the preset word line region 200 is etched away, exposing the channel regions of the multilayer semiconductor pillars 20 perpendicular to the sidewalls of the substrate 1; the sacrificial layer 9 of the preset word line region 200 is etched laterally, exposing the channel regions of the multilayer semiconductor pillars 20 parallel to the sidewalls of the substrate 1, as shown. Figure 5A , Figure 5B and Figure 5C As shown, where, Figure 5AA cross-sectional view along a direction parallel to substrate 1 after exposing the channel region, provided as an exemplary embodiment. Figure 5B For along Figure 5A A cross-sectional view perpendicular to substrate 1 along the AA' direction. Figure 5C For along Figure 5A A cross-sectional view perpendicular to substrate 1 in the BB' direction. The pre-defined word line region 200 extends along the second direction Y in the orthogonal projection of substrate 1.
[0119] 5) Form the gate insulating layer 24 and the word line 40;
[0120] A gate insulating film and a first conductive film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed to form a gate insulating layer 24 surrounding the semiconductor pillar 20 and a word line layer filling the preset word line region 200.
[0121] Multiple first holes K1 are formed extending along the second direction Y, and the multiple first holes K1 divide the word line layer into multiple independent word lines 40; the word lines 40 extend along the second direction Y and surround a row of semiconductor pillars 20 distributed along the second direction Y in the same layer; the word lines 40 in different layers are disconnected.
[0122] A third insulating film is deposited to form a third insulating layer 13, which fills the first hole K1, as shown below. Figure 6A , Figure 6B and Figure 6C As shown, where, Figure 6A A cross-sectional view provided for an exemplary embodiment after the formation of the third insulating layer, along a direction parallel to substrate 1. Figure 6B For along Figure 6A A cross-sectional view perpendicular to substrate 1 along the AA' direction. Figure 6C For along Figure 6A A cross-sectional view perpendicular to substrate 1 along the BB' direction.
[0123] In some embodiments, the first conductive film may be one or more of the following different types of materials:
[0124] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.
[0125] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
[0126] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.
[0127] The materials for the subsequent second, third, and fourth conductive films are similar and will not be described in detail.
[0128] In some embodiments, the gate insulating film may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.
[0129] 6) Form bit line 30;
[0130] One end of a plurality of semiconductor pillars 20 and a plurality of sacrificial layers 9 is etched along a direction perpendicular to the substrate 1 to form a plurality of grooves penetrating the stacked structure with the opening direction opposite to the semiconductor pillars 20;
[0131] The end face of the semiconductor pillar 20 exposed in the groove is subjected to metallization treatment to form a connection layer 31;
[0132] A second conductive film is deposited to fill the groove, forming bit line 30, as shown. Figure 7A and Figure 7B As shown, where, Figure 7A A cross-sectional view of bit line 30 after its formation, provided as an exemplary embodiment. Figure 7B For along Figure 7A A cross-sectional view perpendicular to substrate 1 along the BB' direction. It can be seen that a bit line 30 can be connected to semiconductor pillars 20 at the same location on different layers via multiple connecting layers 31. Different semiconductor pillars 20 on the same layer are connected to different bit lines 30.
[0133] In an exemplary embodiment, the interconnect layer 31 is, for example, a silicide of titanium (Ti), cobalt (Co), nickel (Ni), or nickel-platinum (NiPt), such as titanium disilicide (TiSi2), cobalt disilicide (CoSi2), and nickel-platinum silicide (NiPtSi). The interconnect layer 31 can reduce the contact resistance between the bit line 30 and the semiconductor pillar 20.
[0134] 7) Exposed capacitor area;
[0135] etching the first insulating layer 11 on the side of the second insulating layer 12 away from the bit line 30 to expose the sidewall of the semiconductor pillar 20 perpendicular to the substrate 1 on the side of the second insulating layer 12 away from the bit line 30, and Figure 8A and Figure 8B as shown in FIGS. Figure 8A is a cross-sectional view after exposing the capacitor region provided in an exemplary embodiment, Figure 8B is a cross-sectional view perpendicular to the substrate 1 along the direction of BB' in FIG. Figure 8A .
[0136] 8) forming the first capacitor electrode 41, the dielectric layer 43 and the second capacitor electrode 42;
[0137] on the substrate 1 with the foregoing structure, depositing a third conductive thin film, a dielectric thin film and a fourth conductive thin film in sequence to form the first capacitor electrode 41, the dielectric layer 43 and the second capacitor electrode 42 in sequence around the semiconductor pillar 20, as shown in FIGS. Figure 9A and Figure 9B as shown in FIGS. Figure 9A is a cross-sectional view after the first capacitor electrode 41, the dielectric layer 43 and the second capacitor electrode 42 provided in an exemplary embodiment, Figure 9B is a cross-sectional view perpendicular to the substrate 1 along the direction of BB' in FIG. Figure 9A .
[0138] In some embodiments, the second capacitor electrodes 42 in the same layer and the same column can be connected to form an integrated structure. The second capacitor electrodes 42 in the same column but different layers can be connected to form an integrated structure. However, the embodiments of the present disclosure are not limited thereto, and the second capacitor electrodes 42 of different memory cells can be independently provided.
[0139] In some embodiments, the dielectric layer 43 can be a Low-K material, such as silicon oxide. Or it can be a High-K material, such as a dielectric material with a dielectric constant K≥3.9. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it can include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. high-K materials.
[0140] The above manufacturing completes the multi-layer stacked memory cell array provided on one side of the substrate 1, i.e. the first memory array.
[0141] 9) forming a protective layer 14;
[0142] A protective layer film is deposited on the substrate 1 having the above structure to form a protective layer 14 covering the first memory array completely, so as to protect the first memory array in the subsequent manufacturing process, as shown in Figure 10 Figure 10 A perspective view of the device after forming the protective layer 14 is provided as an exemplary embodiment. The substrate 1 will be thinned subsequently, which increases the fragility of the chip and causes damage easily. Therefore, the protective layer is covered before thinning.
[0143] The protective layer 14 can be a material having etching selectivity with the material used in the above process of manufacturing the first memory array, such as polysilicon, etc.
[0144] 10) The substrate 1 is thinned;
[0145] The device formed by the above steps 1) to 9) is flipped and the substrate 1 is thinned to a preset thickness, such as 2 μm to 7 μm, by using multiple chemical mechanical polishing (CMP) methods, as shown in Figure 11A Figure 11A A front view of the device after flipping and thinning is provided as an exemplary embodiment. Multiple thinning can control the thickness of the substrate 1 accurately to ensure the performance and reliability of the device. In this embodiment, Figures 1 to 10 the thickness of the substrate 1 is only for illustration, and the actual thickness of the substrate 1 is greater than the thickness of the semiconductor layer 10.
[0146] Helium ions (He + ) or hydrogen ions (H + ) are implanted in the thinned substrate 1, and the implantation dose is, for example, 0.2e 2 17 / cm 2 2 to 1e + 17 / cm + 2, and the implantation depth is about 1 μm at most, and a microcavity P1 is formed at the implantation position, as shown in Figure 11B Figure 11B A front view after ion implantation is provided as an exemplary embodiment.
[0147] After implanting the helium ions (He + ) or hydrogen ions (H + ), low-temperature annealing (the annealing temperature is, for example, 400°C to 600°C) is performed, the internal pressure is generated in the microcavity P1 to foam, and a part of the substrate 1 is peeled off at the microcavity P1, as shown in Figure 11C Figure 11C A peeling diagram is provided as an exemplary embodiment. The scheme provided in this embodiment can avoid damaging the first memory array formed by low-temperature annealing.
[0148] Through multiple injections of helium ions (He) + ) or hydrogen ions (H + The substrate is then annealed and stripped, leaving a substrate 1 of the target thickness, which can be, for example, 30 nanometers (nm) to 100 nm. The side of substrate 1 facing away from the formed first memory array is then polished. Figure 11D As shown, Figure 11D This is a schematic diagram showing the substrate 1 after thinning, as provided in an exemplary embodiment. Polishing here can be performed using CMP (Continuous Metallurgical Processing), and the polishing time is controlled to avoid further thinning of the substrate 1. Compared to the previous process of thinning the substrate 1 to a preset thickness using CMP, the polishing time here is greatly reduced, resulting in a smooth surface.
[0149] The solution provided in this embodiment uses two thinning methods: initial coarse thinning via CMP followed by fine thinning via ion implantation and lift-off. This allows for better control of the substrate thickness, reduces costs, and improves efficiency. However, this embodiment is not limited to this; thinning can be achieved through other methods, such as using only ion implantation and lift-off, simply by increasing the number of thinning operations.
[0150] In some embodiments, the target thickness of the substrate 1 can be set according to the thickness of the semiconductor pillar 20 along the direction perpendicular to the substrate 1, that is, it can be the thickness of the semiconductor pillar 20 along the direction perpendicular to the substrate 1, so that the memory cells subsequently formed based on the substrate 1 are more consistent with the memory cells of the first memory array, thereby improving device uniformity. However, the embodiments of this disclosure are not limited to this, and the target thickness of the substrate 1 can be other thicknesses.
[0151] 11) Form a second storage array;
[0152] A multi-layer stacked memory cell array is formed on the substrate 1 on the side opposite to the first memory array, according to steps 1) to 8) above, i.e., a second memory array is formed. The substrate 1 also forms multiple semiconductor pillars 20 for multiple memory cells of a single layer of the second memory array. That is, when the sacrificial layer 9 and the semiconductor layer 10 are stacked on the substrate 1, the substrate 1 is used as one semiconductor layer 10 of the stacked structure. When the semiconductor pillars 20 are subsequently etched, the substrate 1 is etched to form multiple semiconductor pillars 20. Based on the semiconductor pillars 20 formed on the substrate 1 and the semiconductor pillars 20 formed by the other stacked semiconductor layers 10, corresponding transistors and capacitors are manufactured.
[0153] Remove the protective layer 14 to form a semiconductor device including a first memory array and a second memory array, such as... Figure 12 As shown, Figure 12A schematic diagram of the second storage array is provided for an exemplary embodiment. It can be seen that the multi-layer stacked storage unit arrays are formed on both sides of the substrate 1, and a layer of storage unit array is also formed based on the substrate 1. The scheme provided in this embodiment can realize a 2N-layer stacked storage unit array in the case of only supporting N-layer stacking on one side. Compared with the implementation scheme of stacking 2N layers on one side, the number of layers stacked on the same side is greatly reduced, and the problems of large process difficulty and performance degradation when the number of layers stacked on one side is too large are avoided.
[0154] In some embodiments, the number of layers of the first storage array and the second storage array can be the same or different.
[0155] In some embodiments, the bit lines 30 connected to the transistors of the storage units in the same position of different layers in the second storage array and the first storage array can be connected to each other. For example, the first bit line connected to the transistors of the storage units in the first row of different layers in the first storage array can be connected to the second bit line connected to the transistors of the storage units in the first row of different layers in the second storage array. Referring to Figure 12 , the first bit line 30a and the second bit line 30b can be connected to each other.
[0156] When the substrate 1 is subjected to CMP processing, the silicon compound will diffuse to the surrounding, and the substrate 1 can be broken or warped due to external force in this process, and the larger the area of the substrate 1, the more susceptible it is to this phenomenon. In some embodiments, before the CMP is performed, a protective tape film (Tape Lamination) such as an ultraviolet (UV) blue film or a bump film can be attached to the side of the substrate 1 away from the formed storage unit array to protect the substrate 1. After the CMP processing is performed, the adhesion of the UV blue film can be reduced by ultraviolet irradiation for peeling.
[0157] The scheme provided in this embodiment can realize a device with a large number of stacked layers, and avoid too many layers stacked on one side, effectively avoiding a series of problems such as strain accumulation in the epitaxial layer, dislocation density increase, and thin film relaxation when the number of epitaxial layers is too high, and reducing the difficulty of micro-nano processing technology when the number of 3D DRAM stacked layers is too high.
[0158] The semiconductor device manufacturing method described in the above embodiments is only an example, and the embodiments of the present disclosure are not limited thereto. The first storage array and the second storage array can be manufactured by other manners, and the structure of the first storage array and the second storage array can be changed. For example, the bit line 30 can surround the semiconductor pillar 20, and the like.
[0159] The embodiments of the present disclosure provide an electronic device comprising the semiconductor device described in any of the preceding embodiments, or a semiconductor device formed using the manufacturing method described in any of the preceding embodiments.
[0160] The embodiments of the present disclosure also provide an electronic device comprising the semiconductor device described in any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.
[0161] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, on which a first memory array is formed, the first memory array comprising a multilayer array of memory cells stacked along a direction perpendicular to the substrate, the memory cell array comprising a plurality of memory cells, the memory cells comprising transistors, the transistors comprising semiconductor pillars extending along a direction parallel to the substrate; Forming a protective layer that completely covers the first storage array; The substrate on which the first memory array is formed is flipped, and the substrate is thinned to the target thickness; A second memory array is formed on the side of the first memory array facing the substrate. The second memory array includes multiple layers of the memory cell array stacked along a direction perpendicular to the substrate, and the thinned substrate forms multiple semiconductor pillars of multiple memory cells of a layer of the memory cell array of the second memory array.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The target thickness is the thickness of the semiconductor pillar along the direction perpendicular to the substrate.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of thinning the substrate to the target thickness includes: The substrate is thinned to a predetermined thickness by at least one chemical mechanical polishing process; The substrate is subjected to at least one of the following operations to reduce the substrate from the preset thickness to the target thickness: ion implantation to form a microcavity, annealing, and peeling off from the microcavity.
4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The preset thickness is 2 micrometers to 7 micrometers, and the target thickness is 30 nanometers to 100 nanometers.
5. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The ion implantation includes implanting at least one of helium ions and hydrogen ions.
6. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The implantation dose of the ion implantation is from 0.2e^17 / cm² to 1e^17 / cm².
7. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The annealing temperature is 400°C to 600°C.
8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, characterized in that, The formation of the first memory array on the substrate includes: A stacked structure comprising alternating sacrificial layers and semiconductor layers is formed on the substrate; The semiconductor layer is etched to form a plurality of semiconductor pillars extending along a first direction parallel to the substrate; A word line is formed extending along a second direction parallel to the substrate, the word line surrounding a plurality of semiconductor pillars distributed along the second direction, and the ends of the semiconductor pillars are etched along a direction perpendicular to the substrate to remove a portion of the semiconductor pillar and expose one end face of the semiconductor pillar, forming a bit line connected to the end face of the semiconductor pillar; or, a word line is formed extending along a direction perpendicular to the substrate, the word line surrounding a plurality of semiconductor pillars at the same position in different layers, and the ends of the semiconductor pillars are etched to remove a portion of the semiconductor pillar and expose one end face of the semiconductor pillar, forming a bit line connected to the end face of the semiconductor pillar extending along the second direction; the first direction and the second direction intersect.
9. A method for manufacturing a semiconductor device according to any one of claims 1 to 7, characterized in that, The step of forming a second memory array on the side of the first memory array facing the substrate includes: A stacked structure comprising alternating sacrificial layers and semiconductor layers is formed on the side of the substrate opposite to the first memory array; The substrate and the semiconductor layer are etched such that both the substrate and the semiconductor layer form a plurality of semiconductor pillars extending along a first direction parallel to the substrate; A word line is formed extending along a second direction parallel to the substrate, the word line surrounding a plurality of semiconductor pillars distributed along the second direction, and the ends of the semiconductor pillars are etched along a direction perpendicular to the substrate to remove a portion of the semiconductor pillar and expose one end face of the semiconductor pillar, forming a bit line connected to the end face of the semiconductor pillar; or, a word line is formed extending along a direction perpendicular to the substrate, the word line surrounding a plurality of semiconductor pillars at the same position in different layers, and the ends of the semiconductor pillars are etched to remove a portion of the semiconductor pillar and expose one end face of the semiconductor pillar, forming a bit line connected to the end face of the semiconductor pillar extending along the second direction; the first direction and the second direction intersect.
10. A semiconductor device, characterized in that, include: A multi-layer memory cell array, wherein a portion of the memory cell arrays in the multi-layer memory cell array constitutes a first memory array, and another portion of the memory cell arrays constitutes a second memory array, wherein the multi-layer memory cell arrays constituting the first memory array are stacked along a third direction, and the multi-layer memory cell arrays constituting the second memory array are disposed on the side opposite to the first memory array at the bottom layer of the first memory array and stacked along the opposite direction of the third direction; wherein the memory cell array includes a plurality of memory cells, the memory cell includes a transistor, the transistor includes a semiconductor pillar extending along a first direction, the first direction being perpendicular to the third direction.
11. An electronic device, characterized in that, Includes the semiconductor device as described in claim 10, or includes a semiconductor device formed using the manufacturing method of the semiconductor device as described in any one of claims 1 to 9.