Semiconductor device and manufacturing method thereof

Abstract

Semiconductor devices including highly integrated memory cells and methods of manufacturing such semiconductor devices are provided. The semiconductor device includes: a vertical arrangement and a horizontal arrangement of nanosheets, the nanosheets including a horizontal sheet including a protruding sheet node and a tapered sheet continuous from the horizontal sheet in a first horizontal direction; a vertical arrangement of first conductive lines surrounding a portion of the horizontally arranged horizontal sheets and oriented in a second horizontal direction; a first contact node covering the protruding slice node of the horizontal slice; a horizontal arrangement of second conductive lines covering the first contact node and oriented in a vertical direction; a support member disposed between the horizontally arranged second wires and oriented in a vertical direction; and a data storage element coupled with the tapered plate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application Nos. 10-2024-0063738 and 10-2025–0062273, filed on May 16, 2024 and May 14, 2025, respectively, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to a semiconductor device, and more specifically, to a semiconductor device including a three-dimensional (3D) memory cell and a method of manufacturing such a semiconductor device. Background Technology

[0004] In recent years, in order to address the challenges of increasing the capacity and miniaturization of storage devices, three-dimensional (3D) storage devices that stack multiple storage cells have been proposed. Summary of the Invention

[0005] Embodiments of this disclosure relate to semiconductor devices including highly integrated memory cells, and methods for manufacturing such semiconductor devices.

[0006] According to one embodiment of the present invention, a semiconductor device may include: a vertically and horizontally arranged nanosheet, the nanosheet including a horizontal sheet and a tapered sheet, the horizontal sheet including protruding sheet nodes, and the tapered sheet being continuous with the horizontal sheet in a first horizontal direction; a vertically arranged first wire, the first wire surrounding a portion of the horizontally arranged horizontal sheet and oriented in a second horizontal direction; a first contact node covering the protruding sheet nodes of the horizontal sheet; a horizontally arranged second wire, the second wire covering the first contact node and oriented in a vertical direction; a support member disposed between the horizontally arranged second wires and oriented in a vertical direction; and a data storage element coupled to the tapered sheet.

[0007] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include: forming a vertical stack of mold layers; forming a sacrificial isolation layer between the vertically stacked mold layers; replacing one edge of the sacrificial isolation layer with a support member; forming a vertical and horizontal arrangement of pre-formed nanosheet layers, the pre-formed nanosheet layers including a horizontal sheet and a body sheet, the horizontal sheet having a protruding edge that contacts the support member through a recess in the mold layer, the body sheet being continuous with the horizontal sheet layer; replacing the sacrificial isolation layer with an inter-cell dielectric layer; forming a first conductor that surrounds a portion of the horizontal sheet between the inter-cell dielectric layer and the support member and is horizontally oriented; forming protruding sheet nodes between the support members by cutting the protruding edge of the horizontal sheet; and forming a horizontal arrangement of second conductors that are electrically coupled to the protruding sheet nodes and are vertically oriented between the support members in a direction intersecting with the first conductor. Attached Figure Description

[0008] FIG. 1A is a schematic perspective view showing a storage unit according to an embodiment of the present disclosure.

[0009] FIG. 1B is FIG. 1A is a schematic cross-sectional view of the storage unit shown.

[0010] FIG. 2 is a schematic perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0011] FIG. 3A is FIG. 2 is a schematic cross-sectional view of a vertical arrangement of the storage unit shown.

[0012] FIG. 3B is a schematic perspective view showing FIG. 2

[0013] FIG. 3C is a schematic perspective view showing FIG. 2

[0014] FIG. 3D is a schematic perspective view showing FIG. 2

[0015] FIG. 3E is a schematic perspective view showing FIG. 2

[0016] FIG. 4A is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

[0017] FIG. 4B is a schematic cross-sectional view of the semiconductor device taken along FIG. 4A line A-A' shown.

[0018] FIG. 4C is a schematic cross-sectional view of the semiconductor device taken along FIG. 4A line B-B' shown.

[0019] FIG. 4D is a cross-sectional view of the semiconductor device taken along FIG. 4A line C-C' shown.

[0020] FIG. 5A to 26B Various views of a semiconductor device formed using a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are shown.

[0021] FIG. 27 is a schematic cross-sectional view of a semiconductor device according to another embodiment. DETAILED DESCRIPTION ​​​​

[0022] Embodiments of the present disclosure can be described with reference to cross-sectional illustrations, plan illustrations, and block diagrams, which are idealized representations of semiconductor devices. It is noted that structures in the drawings can be changed due to manufacturing techniques and / or tolerances. Embodiments of the present disclosure are not limited to the specific structures described and shown in the described embodiments and drawings, but can include other embodiments, or modifications of the described embodiments, including any structural changes resulting from manufacturing processes. Thus, the regions shown in the drawings are of schematic nature, and the shapes of the regions shown in the drawings are intended to illustrate the specific structures of the regions of the elements, and are not intended to limit the scope of the present disclosure.

[0023] The following embodiments relate to three-dimensional memory cells, in which the memory cells are vertically stacked to increase memory cell density and reduce parasitic capacitance.

[0024] FIG. 1A is a schematic perspective view showing a memory cell MC according to an embodiment of the present disclosure. FIG. 1B is FIG. 1A is a schematic cross-sectional view of the memory cell MC.

[0025] Referring to FIG. 1A and 1B , the memory cell MC can include a switching element TR and a data storage element CAP.

[0026] The switching element TR has a function of controlling a voltage or a current supplied to the data storage element CAP during a data write operation and / or a data read operation, which is performed to the data storage element CAP. The switching element TR can include a nanosheet HL, a nanosheet dielectric layer GD, and a first wire WL. The first wire WL can include a horizontal wire or a horizontal word line, and the nanosheet HL can include an active layer. The switching element TR can include a transistor, in which case the first wire WL can function as a gate electrode. The switching element TR can also be referred to as a "nanosheet transistor", a "cell transistor", an "access element", or a "selection element". The first wire WL can be referred to as a "horizontal gate electrode" or a "horizontal word line".

[0027] The nanosheet HL can include a horizontal sheet HN and a tapered sheet HW, which are horizontally disposed along a second direction D2. The horizontal sheet HN and the tapered sheet HW can have a continuous, unitary structure along the second direction D2.

[0028] The tapered sheet HW can have a thickness that gradually increases from the horizontal sheet HN to the data storage element CAP between the horizontal sheet HN and the data storage element CAP in the second direction D2. An average vertical height or thickness of the tapered sheet HW in the first direction D1 can be greater than an average vertical height or thickness of the horizontal sheet HN. A horizontal length of the tapered sheet HW in the second direction D2 can be less than a horizontal length of the horizontal sheet HN. The tapered sheet HW can be a short sheet, and the horizontal sheet HN can be a long sheet.

[0029] The upper and lower surfaces of a horizontal sheet HN may include planes. The cross-section of a horizontal sheet HN may be flat. The upper and lower surfaces of a tapered sheet HW may have a tapered profile. That is, the cross-section of a tapered sheet HW may have a fan-shaped shape. A horizontal sheet HN may be referred to as a "flat sheet," and a tapered sheet HW may be referred to as a "fan-shaped sheet." The outer surface of the tapered sheet HW that contacts the data storage element CAP may have a flat side surface shape. A horizontal sheet HN may include protruding sheet nodes HNP.

[0030] The nanosheet HL may include a first doped region DR, a second doped region SR, and a channel CH disposed between the first doped region DR and the second doped region SR. The first doped region DR may be electrically connected to a second conductor BL, and the second doped region SR may be electrically connected to a data storage element CAP. The first doped region DR and the channel CH of the nanosheet HL may be formed in a horizontal sheet HN, and the second doped region SR of the nanosheet HL may be formed in a tapered sheet HW. The first doped region DR may be formed in a protruding sheet node HNP.

[0031] The second conductor BL can extend perpendicularly along the first direction D1, the nanosheet HL can extend horizontally along the second direction D2 intersecting the first direction D1, and the first conductor WL can extend horizontally along the third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend along the first horizontal direction, i.e., the second direction D2, and the first conductor WL can extend along the second horizontal direction, i.e., the third direction D3. The nanosheet HL can be referred to as a "horizontal layer" or a "nanoribbon".

[0032] The nanosheet HL can be horizontally oriented from the second conductor BL along the second direction D2. The first doped region DR, the channel CH, and the second doped region SR can be horizontally formed along the second direction D2. The height of the second doped region SR along the first direction D1 can be greater than the height of the channel CH along the first direction D1. The length of the second doped region SR along the second direction D2 can be less than the length of the channel CH along the second direction D2. The lengths of the channel CH and the second doped region SR along the third direction D3 can be equal. The average length of the first doped region DR along the third direction D3 can be less than the average length of the channel CH and the second doped region SR along the third direction D3.

[0033] The nanosheet HL can include a semiconductor material. For example, the nanosheet HL can include polysilicon, monocrystalline silicon, germanium, or silicon germanium. In some embodiments, the nanosheet HL can include an oxide semiconductor material. For example, the oxide semiconductor material can include indium gallium zinc oxide (IGZO), InSnZnO, ZnSnO, or a combination thereof. In some embodiments, the nanosheet HL can include a conductive metal oxide. In some embodiments, the nanosheet HL can include a two-dimensional material, such as molybdenum disulfide (MoS2), tungsten disulfide (WS2), or molybdenum selenide (MoSe2).

[0034] When the nanosheet HL is formed of an oxide semiconductor material, the channel CH can also be formed of an oxide semiconductor material, and the first doped region DR and the second doped region SR can be omitted. The nanosheet HL can also be referred to as an "active layer" or a "thin body."

[0035] The channel CH can be un-doped, and the first doped region DR and the second doped region SR can be doped with impurities of the same conductivity type. Each of the first doped region DR and the second doped region SR can be doped with N-type conductive impurities or P-type conductive impurities. Each of the first doped region DR and the second doped region SR can include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region DR can be connected to the second wire BL, and the second doped region SR can be connected to the data storage element CAP. One of the first doped region DR and the second doped region SR can be a drain region, and the other can be a source region.

[0036] The first wire WL can have a gate-all-around (GAA) structure. For example, the first wire WL can surround a portion of the nanosheet HL and extend along the third direction D3. The nanosheet dielectric layer GD can be formed between the nanosheet HL and the first wire WL. The nanosheet dielectric layer GD can surround all surfaces of the channel CH of the nanosheet HL. The first wire WL can surround the channel CH of the nanosheet HL on the nanosheet dielectric layer GD.

[0037] The first wire WL can include a metal-based material, a semiconductor material, or a combination thereof. The first wire WL can include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first wire WL can include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first wire WL can include an N-type work function material or a P-type work function material. The N-type work function material can have a low work function of about 4.5 eV or less, and the P-type work function material can have a high work function of about 4.5 eV or more. The first wire WL can include a stack of a low work function material and a high work function material.

[0038] A nanosheet dielectric layer GD can be disposed between the nanosheet HL and the first wire WL. The nanosheet dielectric layer GD can be referred to as a “gate dielectric layer” or a “channel side dielectric layer.” The nanosheet dielectric layer GD can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The nanosheet dielectric layer GD can include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The nanosheet dielectric layer GD can be formed by thermal oxidation of the nanosheet HL. In some embodiments, forming the nanosheet dielectric layer GD can include depositing a nanosheet dielectric material on the nanosheet HL and oxidizing a surface of the nanosheet HL.

[0039] The second wire BL can be vertically oriented along the first direction D1. The second wire BL can include a bit line. The second wire BL can be referred to as a “vertical wire,” a “vertically oriented bit line,” a “vertically extending bit line,” or a “pillar bit line.” The second wire BL can include an electrically conductive material. The second wire BL can include a silicon-based material, a metal-based material, or a combination thereof. The second wire BL can include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The second wire BL can include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the second wire BL can include a titanium nitride / tungsten (TiN / W) stack, in which titanium nitride and tungsten are stacked in sequence. The second wire BL can be electrically connected to the first doped region DR of the nanosheet HL.

[0040] The data storage element CAP can include a storage element such as a capacitor. The data storage element CAP can be horizontally disposed from the switching element TR along the second direction D2. The data storage element CAP can be electrically coupled to the second doped region SR of the nanosheet HL.

[0041] The data storage element CAP can include a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE disposed between the first electrode SN and the second electrode PN. The first electrode SN can extend horizontally from the nanosheet HL along the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN can be horizontally disposed on the second direction D2. The first electrode SN can be a storage node and the second electrode PN can be a plate node.

[0042] The first electrode SN can include an interior space and a plurality of outer surfaces, and the interior space of the first electrode SN can include a plurality of inner surfaces. The outer surfaces of the first electrode SN can include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN can extend vertically along the first direction D1, and the horizontal outer surfaces of the first electrode SN can extend horizontally along the second direction D2 or the third direction D3. The interior space of the first electrode SN can be a three-dimensional space. The dielectric layer DE can conformally cover the inner surfaces of the first electrode SN. The second electrode PN can be disposed in the interior space of the first electrode SN over the dielectric layer DE. Portions of the outer surfaces of the first electrode SN can be electrically connected with the second doped region SR of the nanosheet HL. The second electrode PN of the data storage element CAP can be coupled to the common plate PL.

[0043] The data storage element CAP can have a three-dimensional structure. The first electrode SN can have a three-dimensional structure that can have a horizontal three-dimensional structure oriented along the second direction D2. In an example of the three-dimensional structure, the first electrode SN can have a cylindrical shape. The cylindrical shape of the first electrode SN can include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN can be electrically coupled to the second doped region SR of the nanosheet HL. The dielectric layer DE and the second electrode PN can be disposed on the cylindrical inner surface and the cylindrical outer surface of the first electrode SN. The first electrode SN can include a metal cylinder.

[0044] In some embodiments, the first electrode SN can have a columnar shape or a columnar-cylindrical shape. The columnar-cylindrical shape can refer to a structure that is a fusion of a columnar shape and a cylindrical shape.

[0045] The first electrode SN and the second electrode PN can include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN can include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, a titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, a titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stack, or a combination thereof, respectively. The second electrode PN can also include a combination of a metal-based material and a silicon-based material.

[0046] The dielectric layer DE can be referred to as a "capacitor dielectric layer" or a "storage layer." The dielectric layer DE can include silicon oxide, silicon nitride, a high-k material, a perovskite material, or a combination thereof. The high-k material can include hafnium oxide (Hf02), zirconium oxide (Zr02), aluminum oxide (AI2O3), lanthanum oxide (La203), titanium oxide (Ti02), tantalum oxide (Ta205), niobium oxide (Nb205), strontium titanium oxide (SrTi03), or a combination thereof. In some embodiments, the dielectric layer DE can be formed of a composite layer including two or more layers of the above high-k materials.

[0047] The dielectric layer DE can be formed of a zirconium (Zr)-based oxide. The dielectric layer DE can have a stack structure including zirconium oxide (Zr02). The dielectric layer DE can include a ZA (Zr02 / AI2O3) stack or a ZAZ (Zr02 / AI2O3 / Zr02) stack. The ZA stack can have a structure in which aluminum oxide (AI2O3) is stacked on zirconium oxide (Zr02). The ZAZ stack can have a structure in which zirconium oxide (Zr02), aluminum oxide (AI2O3), and zirconium oxide (Zr02) are sequentially stacked. Each of the ZA stack and the ZAZ stack can be referred to as a "zirconium oxide (Zr02)-based layer." In some embodiments, the dielectric layer DE can be formed of a hafnium (Hf)-based oxide.

[0048] The dielectric layer DE can have a stack structure including hafnium oxide (Hf02). The dielectric layer DE can include a HA (Hf02 / AI2O3) stack or a HAH (Hf02 / AI2O3 / Hf02) stack. The HA stack can have a structure in which aluminum oxide (AI2O3) is stacked on hafnium oxide (Hf02). The HAH stack can have a structure in which hafnium oxide (Hf02), aluminum oxide (AI2O3), and hafnium oxide (Hf02) are sequentially stacked. Each of the HA stack and the HAH stack can be referred to as a "hafnium oxide (Hf02)-based layer."

[0049] In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, the aluminum oxide (AI2O3) can have a band gap energy greater than that of the zirconium oxide (Zr02) and the hafnium oxide (Hf02). The aluminum oxide (AI2O3) can have a dielectric constant lower than that of the zirconium oxide (Zr02) and the hafnium oxide (Hf02). Accordingly, the dielectric layer DE can include a stack of a high-k material and a high-band gap material having a band gap energy greater than that of the high-k material. The dielectric layer DE can include silicon oxide (Si02) as the high-band gap material other than the aluminum oxide (AI2O3). As the dielectric layer DE includes the high-band gap material, a leakage current can be suppressed. The high-band gap material can be thinner than the high-k material.

[0050] In some embodiments, the dielectric layer DE can include a stack structure of high-k materials and high bandgap materials stacked alternately. For example, the dielectric layer DE can include a ZAZA (Zr02 / Al203 / Zr02 / Al203) stack, a ZAZAZ (Zr02 / Al203 / Zr02 / Al203 / Zr02) stack, a HAHA (Hf02 / Al203 / Hf02 / Al203) stack, a HAHAH (Hf02 / Al203 / Hf02 / Al203 / Hf02) stack, a HZAZH (Hf02 / Zr02 / Al203 / Zr02 / Hf02) stack, a ZHZAZHZ (Zr02 / Hf02 / Zr02 / Al203 / Zr02 / Hf02 / Zr02) stack, a HZHZ (Hf02 / Zr02 / Hf02 / Zr02) stack, a AHZAZHA (Al203 / Hf02 / Zr02 / Al203 / Zr02 / Hf02 / Al203) stack, or a ZHZAZHZAT (Zr02 / Hf02 / Zr02 / Al203 / Zr02 / Hf02 / Zr02 / Al203 / Ti02) stack. In the above stack structures, aluminum oxide (Al203) can be thinner than zirconium oxide (Zr02) and hafnium oxide (Hf02).

[0051] In some embodiments, the dielectric layer DE can include a high-k material and a high bandgap material. The dielectric layer DE can have a multi-layer structure in which a plurality of high-k materials and a plurality of high bandgap materials are stacked, or a mixed structure in which a high-k material and a high bandgap material are mixed with each other.

[0052] In some embodiments, the dielectric layer DE can include a ferroelectric material, an anti-ferroelectric material, or a combination thereof. For example, the dielectric layer DE can include HfZrO.

[0053] In some embodiments, the dielectric layer DE can include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an anti-ferroelectric material, or a combination of a high-k material or a ferroelectric material and an anti-ferroelectric material.

[0054] In some embodiments, the data storage element CAP can also include a plurality of interface control layers to mitigate leakage current. Each interface control layer can include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The data storage element CAP can include a first interface control layer, a second interface control layer, or a combination thereof. The first interface control layer and the second interface control layer can be conductive or dielectric / insulative. The first interface control layer can be formed between the first electrode SN and the dielectric layer DE, and the second interface control layer can be formed between the dielectric layer DE and the second electrode PN. The first interface control layer and the second interface control layer can be the same material or different materials. For example, a structure of the data storage element CAP in which the first interface control layer, the dielectric layer DE, and the second interface control layer are sequentially stacked can include a NZHZAZHZATN (Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0055] The data storage element CAP can include a three-dimensional capacitor. The data storage element CAP can include a metal-insulator-metal (MIM) capacitor. The data storage element CAP can be replaced with other data storage materials. For example, the data storage material can be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0056] The memory cell MC can also include a first contact node BLC and a second contact node SNC. The first contact node BLC can be disposed between the first doped region DR of the nanosheet HL and the second wire BL. The first contact node BLC can include a metal, a metal-based material, or a semiconductor material. For example, the first contact node BLC can include titanium, titanium nitride, tungsten, or a combination thereof. Further, the first contact node BLC can include doped polysilicon, and the first doped region DR can include impurities diffused from the first contact node BLC. The first contact node BLC can cover the protruding sheet node HNP of the horizontal sheet HN.

[0057] The second contact node SNC can be disposed between the second doped region SR of the nanosheet HL and the first electrode SN of the data storage element CAP. The second contact node SNC can include a metal-based material or a semiconductor material. For example, the second contact node SNC can include titanium, titanium nitride, tungsten, or a combination thereof. Further, the second contact node SNC can include doped polysilicon, and the second doped region SR can include impurities diffused from the second contact node SNC. A height of the first contact node BLC in the first direction D1 can be less than a height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 can be greater than or equal to a height of the channel CH in the first direction D1.

[0058] In some embodiments, the second contact node SNC can be selectively grown from the conical sheet HW of the nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth (SEG). For example, the second contact node SNC can be a silicon epitaxial layer formed by SEG. The second contact node SNC can be a doped silicon epitaxial layer.

[0059] The nanosheet HL can include a first edge and a second edge. The first edge can refer to a portion of the first doped region DR or a portion of the horizontal sheet HN that is electrically coupled to the second wire BL, and the second edge can refer to a portion of the second doped region SR or a portion of the conical sheet HW that is electrically coupled to the first electrode SN of the data storage element CAP.

[0060] The memory cell MC can further include an ohmic contact layer BLM disposed between the first contact node BLC and the second wire BL. The ohmic contact layer BLM can include a metal silicide. The ohmic contact layer BLM can cover at least a portion of the first contact node BLC. A contact isolation layer CIL can be formed on the upper and lower surfaces of the first contact node BLC in the first direction D1. The contact isolation layer CIL can include a dielectric material.

[0061] The memory cell MC can further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 can be disposed between the first wire WL and the first electrode SN of the data storage element CAP. The second spacer SP2 can be disposed between the first wire WL and the second wire BL. The first spacer SP1 and the second spacer SP2 can each include a dielectric material. The first spacer SP1 and the second spacer SP2 can each include silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 can be referred to as a “word line spacer” and the second spacer SP2 can be referred to as a “bit line spacer”.

[0062] The first spacer SP1 can surround at least a portion of the second doped region SR of the nanosheet HL, i.e., the conical sheet HW, and the second spacer SP2 can surround at least a portion of the first doped region DR of the nanosheet HL, i.e., the horizontal sheet HN. The first spacer SP1 and the second spacer SP2 can be disposed on both sidewalls of the first wire WL. That is, the first spacer SP1 and the second spacer SP2 can extend in the third direction D3. The contact isolation layer CIL can be disposed between the second wire BL and the second spacer SP2.

[0063] The first wire WL can be disposed between the vertically stacked intercell horizontal dielectric layers HIL. The first spacer SP1 can cover a side of the intercell horizontal dielectric layer HIL, and the second spacer SP2 can be disposed between the intercell horizontal dielectric layers HIL. The intercell horizontal dielectric layers HIL can extend along the third direction D3. Each of the intercell horizontal dielectric layers HIL can include silicon oxide, silicon nitride, or a combination thereof.

[0064] The first spacer SP1 can have a cup shape covering a first side of the intercell horizontal dielectric layer HIL. The first spacer SP1 extending along the first direction D1 and the third direction D3 can have a frame structure surrounding a portion of the tapered sheet HW.

[0065] The second spacer SP2 extending along the first direction D1 and the third direction D3 can have a frame structure surrounding a portion of the horizontal sheet HN.

[0066] The first electrode SN of the data storage element CAP can be disposed between the storage node interdielectric layers SNIL. A horizontal length of the storage node interdielectric layer SNIL can be less than a horizontal length of the first electrode SN.

[0067] From another perspective, the memory cell MC can have a 1T-1C structure, where 1T can refer to one switching element TR and 1C can refer to one data storage element CAP. When the memory cell MC is a DRAM cell having a 1T-1C structure, 1T can refer to one cell transistor and 1C can refer to one capacitor. Thus, a gate of the cell transistor can be a word line, a drain region of the cell transistor can be coupled to a bit line, and a source region of the cell transistor can be coupled to the capacitor. The bit line can correspond to the second wire BL in FIG. 1A and 1B , the word line can correspond to the first wire WL in FIG. 1A and 1B , and the capacitor can correspond to the data storage element CAP in FIG. 1A and 1B . Furthermore, the drain region of the cell transistor can correspond to the first doped region DR in FIG. 1A and 1B , and the source region of the cell transistor can correspond to the second doped region SR in FIG. 1A and 1B .

[0068] FIG. 2 is a schematic perspective view of a semiconductor device 100V according to an embodiment of the present invention. FIG. 3A is a schematic cross-sectional view of a vertical arrangement VA of memory cells MC shown in FIG. 2 . FIG. 3B is a schematic perspective view of a first wire WL shown in FIG. 2 .FIG. 3C is a schematic perspective view showing FIG. 2 a first spacer SP1. FIG. 3D is a schematic perspective view showing FIG. 2 a second spacer SP2. FIG. 3E is FIG. 2 a schematic perspective view showing a support BLS.

[0069] Referring to FIG. 2 to 3E , the semiconductor device 100V can include a three-dimensional array of memory cells MC described above with reference to FIG. 1A and 1B The detailed description of each memory cell MC has been described above with reference to FIG. 1A and 1B .

[0070] Referring to FIG. 2 to FIG. 3D , the semiconductor device 100V can include a horizontal arrangement HA and a vertical arrangement VA of memory cells MC disposed above a lower structure LS. The memory cells MC in the horizontal arrangement HA can be horizontally spaced apart along a third direction D3. The memory cells MC in the vertical arrangement VA can be vertically stacked along a first direction D1. The memory cells MC in the horizontal arrangement HA can be vertically stacked along the first direction D1. The vertical arrangement VA of memory cells MC can refer to a structure in which the horizontal arrangement HA of memory cells MC is vertically stacked in the first direction D1. The semiconductor device 100V can include a horizontal arrangement of vertical wires in which the vertical wires are arranged along the third direction D3. The horizontal arrangement of vertical wires can include the horizontal arrangement HA of second wires BL. The semiconductor device 100V can include a vertical arrangement of horizontal wires in which the horizontal wires are arranged along the first direction D1. The vertical arrangement of horizontal wires can include the vertical arrangement VA of first wires WL.

[0071] The memory cells MC in the horizontal arrangement HA can be coupled to different second wires BL and share one first wire WL. The memory cells MC in the vertical arrangement VA can share different first wires WL and be coupled to one second wire BL. The support BLS can be disposed between adjacent second wires BL in the third direction D3.

[0072] The vertical arrangement VA can constitute a plurality of columns. Each inter-cell horizontal dielectric layer HIL can be formed between the memory cells MC in the vertical arrangement VA. Each inter-cell horizontal dielectric layer HIL can be disposed between the first wires WL along the first direction D1. The inter-cell horizontal dielectric layer HIL can include a protrusion HILE disposed on an outer wall of the support BLS.

[0073] Each memory cell MC can include a switching element TR and a data storage element CAP. The switching element TR can include a nanosheet HL, a nanosheet dielectric layer GD, and a first wire WL. The nanosheet HL can include a first doped region DR, a channel CH, and a second doped region SR. A first contact node BLC can be formed between the first doped region DR of the nanosheet HL and the second wire BL. A second contact node SNC can be formed between the second doped region SR of the nanosheet HL and the data storage element CAP. The nanosheet HL can be surrounded by the nanosheet dielectric layer GD. The first wire WL can extend in a third direction D3 and can also surround the channel CH of the nanosheet HL on the nanosheet dielectric layer GD. Each contact isolation layer CIL can be formed between the first contact nodes BLC along the first direction D1. The memory cell MC can also include an ohmic contact layer BLM disposed between the first contact nodes BLC and the second wire BL. The ohmic contact layer BLM can include a metal silicide.

[0074] The semiconductor device 100V can include a horizontal arrangement HA and a vertical arrangement VA of nanosheets HL. The semiconductor device 100V can include a horizontal arrangement HA and a vertical arrangement VA of switching elements TR. The semiconductor device 100V can include a horizontal arrangement HA of second wires BL. The semiconductor device 100V can include a vertical arrangement VA of first wires WL. The semiconductor device 100V can include a horizontal arrangement HA and a vertical arrangement VA of data storage elements CAP. Each storage node interlayer SNIL can be formed between first electrodes SN of data storage elements CAP in the first direction D1.

[0075] The semiconductor device 100V can also include a first spacer SP1 and a second spacer SP2, which have been described above with reference to FIG. 1B The first spacer SP1 can have a multi-layer structure, while the second spacer SP2 can have a single-layer structure. The first spacer SP1 can be disposed between the first wire WL and the first electrodes SN of the data storage elements CAP. The second spacer SP2 can be disposed between the first wire WL and the second wire BL. The first spacer SP1 and the second spacer SP2 can each include a dielectric material. The first spacer SP1 and the second spacer SP2 can each include silicon oxide, silicon nitride, or a combination thereof. The second spacer SP2 can include an extension SP2E disposed on upper and lower surfaces of the first doped region DR of a horizontal sheet HN of the nanosheet HL in the horizontal arrangement HA. The extension SP2E of the second spacer SP2 can not cover side surfaces of the first doped region DR.

[0076] Referring again to FIG. 3C and 3DIn the vertical arrangement VA, the first spacers SP1 can extend vertically along the first direction D1 and can also surround the conical sheet HW. Further, in the horizontal arrangement HA, the first spacers SP1 can extend horizontally in the third direction D3 and can also surround the conical sheet HW.

[0077] In the horizontal arrangement HA, the first spacers SP1 can surround the second doped regions SR of the conical sheets HW of the nanosheets HL. In the horizontal arrangement HA, the first wires WL can surround the channels CH of the horizontal sheets HN of the nanosheets HL. In the horizontal arrangement HA, the second spacers SP2 can surround the first doped regions DR of the horizontal sheets HN of the nanosheets HL. Specifically, in the horizontal arrangement HA, the first spacers SP1 can extend along the first direction D1 and the third direction D3 and can also surround the second doped regions SR of the nanosheets HL. In the horizontal arrangement HA, the second spacers SP2 can extend along the first direction D1 and the third direction D3 and can also surround the first doped regions DR of the nanosheets HL. In the horizontal arrangement HA, the first wires WL can extend in the third direction D3 and can also surround the channels CH of the nanosheets HL.

[0078] Thereby, the first wires WL, the first spacers SP1 and the second spacers SP2 can surround the nanosheets HL arranged on the same horizontal layer. The first spacers SP1 and the second spacers SP2 can each have a frame structure. In the horizontal arrangement HA and the vertical arrangement VA, the first spacers SP1 having the frame structure can surround all the second doped regions SR of the nanosheets HL. In the horizontal arrangement HA and the vertical arrangement VA, the second spacers SP2 having the frame structure can surround all the first doped regions DR of the nanosheets HL.

[0079] Referring back to FIG. 3D and FIG. 3E The extension SP2E of the second spacer SP2 can surround the protrusion HILE of the inter-cell horizontal dielectric layer HIL.

[0080] Each support BLS can be disposed between the second wires BL adjacent to each other along the third direction D3. The support BLS can extend vertically along the first direction D1. The support BLS can support a portion of the nanosheets HL. Each support BLS can include a dielectric material. Each support BLS can include silicon nitride. The second wire BL can be formed to be self-aligned with the support BLS. The second wire BL can be referred to as a “self-aligned bit line (SABL)”. The second wire BL can cover the first contact node BLC. An outer surface of the second wire BL can have a non-linear profile. In another embodiment, an outer surface of the second wire BL can have a linear profile.

[0081] The extension SP2E of the second spacer SP2 can cover the inner wall of the support BLS. The outer wall of the support BLS can be in contact with the second wire BL.

[0082] Referring to FIG. 1A to 3E , the semiconductor device 100V can include a vertical array VA and a horizontal array HA of nanosheets HL (each nanosheet HL including a horizontal sheet HN and a conical sheet HW, the horizontal sheet HN including a protruding sheet node HNP, the conical sheet HW being continuous with the horizontal sheet HN along a first horizontal direction D2), a vertical array VA of first wires WL (the first wires WL being oriented along a second horizontal direction D3 and also surrounding portions of the horizontal sheets HN in the horizontal array HA), first contact nodes BLC covering the protruding sheet nodes HNP of the horizontal sheets HN, a horizontal array HA of second wires BL (the second wires BL being oriented along a vertical direction D1 and also covering the first contact nodes BLC), supports BLS disposed between the second wires BL in the horizontal array HA and oriented along the vertical direction D1, and data storage elements CAP coupled to the conical sheets HW. The semiconductor device 100V can also include a contact isolation layer CIL disposed between the first contact nodes BLC along the vertical direction D1 and exposing outer surfaces of the first contact nodes BLC and an ohmic contact layer BLM disposed between the first contact nodes BLC and the second wires BL and covering the outer surfaces of the first contact nodes BLC. The supports BLS can directly contact the second wires BL, the first contact nodes BLC, and the protruding sheet nodes HNP.

[0083] FIG. 4A is a schematic plan view of a semiconductor device 100 according to embodiments of the present disclosure. FIG. 4B is a schematic cross-sectional view of the semiconductor device 100 taken along the line A-A’ shown in FIG. 4A FIG. 4C is a schematic cross-sectional view of the semiconductor device 100 taken along the line B-B’ shown in FIG. 4A FIG. 4D is a cross-sectional view of the semiconductor device 100 taken along the line C-C’ shown in FIG. 4A A detailed description of the overlapping components has been provided above with reference to FIG. 1A to FIG. 2

[0084] Referring to FIG. 4A to FIG. 4D , the semiconductor device 100 can include a lower structure LS and an array of memory cells MCA.

[0085] ​​​The lower structure LS can include a substrate. The lower structure LS can be a material suitable for semiconductor processing. The lower structure LS can include a semiconductor substrate, a conductive material, a dielectric material, a semiconductor material, or a combination thereof. The lower structure LS can include silicon, single crystalline silicon, poly crystalline silicon, amorphous silicon, silicon germanium, single crystalline silicon germanium, poly crystalline silicon germanium, carbon doped silicon, epitaxial silicon, a combination of the above materials, or multiple layers thereof. The lower structure LS can also include other semiconductor materials, such as germanium. The lower structure LS can also include a III-V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). In some embodiments, the lower structure LS can include a metal wiring structure, a dielectric structure, a conductive structure, a bond pad structure, other memory or peripheral circuitry portions. For example, the lower structure LS can include a structure in which a peripheral circuitry portion, a metal wiring structure, and a bond pad structure are stacked in sequence. The memory cell array MCA can be bonded to the peripheral circuitry portion of the lower structure LS by wafer bonding. The wafer bonding can include pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or a combination thereof.

[0086] The memory cell array MCA can include a plurality of memory cells MC1 and MC2 vertically stacked along a first direction D1. The memory cell array MCA can include a three-dimensional array of memory cells MC1 and MC2. Each memory cell MC1 and MC2 can include a switching element TR and a data storage element CAP. The switching element TR can include a first wire WL, a nanosheet dielectric layer GD, and a nanosheet HL. The nanosheet HL can include a horizontal sheet HN and a tapered sheet HW. The horizontal sheet HN of the nanosheet HL can include a protruding sheet node HNP. A first contact node BLC can be formed between the horizontal sheet HN of the nanosheet HL and a second wire BL. The first contact node BLC can cover the protruding sheet node HNP. A second contact node SNC can be formed between the tapered sheet HW of the nanosheet HL and the data storage element CAP. The nanosheet HL can be surrounded by the nanosheet dielectric layer GD. The first wire WL can extend in a third direction D3 and can also surround a portion of the horizontal sheet HN of the nanosheet HL on the nanosheet dielectric layer GD.

[0087] The memory cells MC1 and MC2 can each have the same structure as the memory cell MC described above with reference to FIG. 1A to 3E As described above with reference to FIG. 1B the nanosheet HL of the memory cells MC1 and MC2 can each include a first doped region DR, a second doped region SR, and a channel CH.

[0088] The memory cells MC1 and MC2 of the memory cell array MCA can be coupled to the second wire BL. The second wire can include a first vertical wire BLA and a second vertical wire BLB.

[0089] The memory cell array MCA can include a first sub-cell array MCA1 and a second sub-cell array MCA2. The first sub-cell array MCA1 can include a three-dimensional array of first memory cells MC1. The second sub-cell array MCA2 can include a three-dimensional array of second memory cells MC2. The first memory cells MC1 of the first sub-cell array MCA1 can share a second wire, i.e., a first vertical wire BLA. The second memory cells MC2 of the second sub-cell array MCA2 can share a second wire, i.e., a second vertical wire BLB. A bottom of the first vertical wire BLA can be electrically isolated from a bottom of the second vertical wire BLB.

[0090] The first memory cells MC1 and the second memory cells MC2 can each include a switching element TR and a data storage element CAP. The switching element TR can include a first wire WL and a nanosheet HL. The switching element TR of the first memory cells MC1 and the second memory cells MC2 can be a nanosheet transistor. Each of the first sub-cell array MCA1 and the second sub-cell array MCA2 can include a horizontal arrangement and a vertical arrangement of nanosheet transistors.

[0091] The first sub-cell array MCA1 can further include a horizontal arrangement of the first vertical wire BLA. The first vertical wire BLA can be coupled to a horizontal sheet HN of the nanosheet HL via a first contact node BLC. Each contact isolation layer CIL can be formed between the first contact nodes BLC along the first direction D1. The first memory cells MC1 can further include an ohmic contact layer BLM disposed between the first contact nodes BLC and the first vertical wire BLA. The ohmic contact layer BLM can include a metal silicide.

[0092] The second sub-cell array MCA2 can further include a horizontal arrangement of the second vertical wire BLB. The second vertical wire BLB can be coupled to a horizontal sheet HN of the nanosheet HL via a first contact node BLC. Each contact isolation layer CIL can be formed between the first contact nodes BLC along the first direction D1. The second memory cells MC2 can further include an ohmic contact layer BLM disposed between the first contact nodes BLC and the second vertical wire BLB. The ohmic contact layer BLM can include a metal silicide.

[0093] The first sub-cell array MCA1 and the second sub-cell array MCA2 can each include a horizontal arrangement and a vertical arrangement of the first wires WL. The first sub-cell array MCA1 and the second sub-cell array MCA2 can each include a horizontal arrangement and a vertical arrangement of the data storage elements CAP. Each data storage element CAP can include a first electrode SN, a dielectric layer DE, and a second electrode PN. The data storage element CAP can be coupled to the conical sheet HW of the nanosheet HL through a second contact node SNC. The first contact node BLC can be doped polysilicon. The second contact node SNC can be doped polysilicon or doped silicon epitaxial layer.

[0094] Each first inter-cell dielectric layer IL1 can be disposed between data storage elements CAP adjacent to each other in the third direction D3. Each second inter-cell dielectric layer IL2 can be disposed between first wires WL vertically stacked along the first direction D1. Each third inter-cell dielectric layer IL3 can be disposed between first electrodes SN of data storage elements CAP vertically stacked along the first direction D1. The first through third inter-cell dielectric layers IL1, IL2, and IL3 can include silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof, respectively. The first inter-cell dielectric layer IL1 can be referred to as an “inter-cell spacer layer.” The second inter-cell dielectric layer IL2 can correspond to FIG. 1B The illustrated inter-cell horizontal dielectric layer HIL. The third inter-cell dielectric layer IL3 can be a storage node inter-cell dielectric layer. The combination of the first inter-cell dielectric layer IL1 and the third inter-cell dielectric layer IL3 can define a slot in which the first electrode SN of the data storage element CAP can be formed.

[0095] Each of the first sub-cell array MCA1 and the second sub-cell array MCA2 can also include a first spacer SP1 and a second spacer SP2. The first spacer SP1 can be disposed between the first wire WL and the data storage element CAP. The second spacer SP2 can be disposed between the first wire WL and the first and second vertical wires BLA and BLB. The first spacer SP1 and the second spacer SP2 can extend vertically along the first direction D1 and can also extend horizontally along the third direction D3. The first spacer SP1 can extend horizontally along the third direction D3 and can also surround the conical sheet HW on the same horizontal layer. The second spacer SP2 can extend horizontally along the third direction D3 and can also surround a portion of the horizontal sheet HN on the same horizontal layer.

[0096] The first spacer SP1 and the second spacer SP2 can each include silicon oxide, silicon nitride, or a combination thereof.

[0097] The first spacers SP1 can have a cup shape covering one side of the second inter-cell dielectric layer IL2. The first spacers SP1 extending in the first direction D1 and the third direction D3 can have a frame structure surrounding a portion of the conical sheet HW.

[0098] The second spacers SP2 can contact side surfaces of the first wires WL located between the second inter-cell dielectric layers IL2. The second spacers SP2 extending in the first direction D1 and the third direction D3 can have a frame structure surrounding a portion of the horizontal sheet HN.

[0099] The memory cell array MCA can include a plurality of first wires WL vertically stacked in the first direction D1. The memory cell array MCA can include a plurality of nanosheets HL vertically stacked in the first direction D1. The memory cell array MCA can include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA can include a plurality of second wires BL spaced apart in the third direction D3.

[0100] The array isolation layer BLF can be disposed between the first vertical wire BLA and the second vertical wire BLB. The array isolation layer BLF can include a dielectric material. The first sub-cell array MCA1 and the second sub-cell array MCA2 can have a mirror image structure with the array isolation layer BLF disposed therebetween.

[0101] The nanosheet HL of the switching element TR horizontally disposed in the third direction D3 can share one first wire WL. The nanosheet HL of the switching element TR horizontally disposed in the third direction D3 can be coupled to different second wires BL. The switching elements TR stacked in the first direction D1 can share one second wire BL. The switching elements TR horizontally disposed in the third direction D3 can share one first wire WL.

[0102] The second electrode PN of the data storage element CAP can be coupled to the common plate PL.

[0103] The first vertical wire BLA and the second vertical wire BLB can be formed in a self-alignment manner with the second spacers SP2.

[0104] As described above, the first wires WL can be isolated from each other in the first direction D1 by the second inter-cell dielectric layer IL2, and the second wires BLA and BLB can be isolated from each other in the third direction D3 by the support BLS.

[0105] In one embodiment, since the first vertical wire BLA and the second vertical wire BLB are formed in a self-alignment manner, the stack height of the memory cells MC1 and MC2 can be increased (high stack height), and a high integration process of a three-dimensional memory cell having a small cell pitch can be implemented.

[0106] FIG. 5A to 26B Various views of a semiconductor device formed by a method of manufacturing a semiconductor device according to an embodiment of the present application are shown.

[0107] FIG. 5A is a plan view of a structure at a second mold layer height for describing a method of forming a mold stack SB. FIG. 5B is a cross-sectional view of a structure taken along the line A-A' shown in FIG. 5A FIG. 5C is a cross-sectional view of a structure taken along the line B-B' shown in FIG. 5A

[0108] Referring to FIG. 5A to FIG. 5C , a mold stack SB can be formed on a substrate 11. The mold stack SB can include an alternating stack of sacrificial mold layers 12 and mold layers 13.

[0109] The substrate 11 can be a material suitable for semiconductor processing. The substrate 11 can include a semiconductor substrate, a conductive material, a dielectric material, a semiconductor material, or a combination thereof. The substrate 11 can include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, epitaxial silicon, a combination of the above materials, or a multilayer structure of the above materials. The substrate 11 can also include another semiconductor material, such as germanium. The substrate 11 can also include a III-V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The mold stack SB can include an alternating stack of sacrificial mold layers 12 and mold layers 13.

[0110] The mold stack SB can be formed by an epitaxial growth process. To form the mold stack SB, the sacrificial mold layers 12 can be alternately stacked with the mold layers 13, and the sacrificial mold layers 12 and the mold layers 13 can be epitaxially grown.

[0111] The sacrificial mold layers 12 and the mold layers 13 can be different semiconductor materials. For example, the sacrificial mold layers 12 can each include silicon germanium or monocrystalline silicon germanium. Additionally, as an example, the mold layers 13 can each include monocrystalline silicon. The sacrificial mold layers 12 and the mold layers 13 can be formed by an epitaxial growth process. The lowermost sacrificial mold layer 12 can act as a seed layer during the epitaxial growth process. Each sacrificial mold layer 12 can be thinner than each mold layer 13. The sacrificial mold layers 12 can include a first epitaxial growth layer, and the mold layers 13 can include a second epitaxial growth layer.

[0112] ​​In one embodiment, in the mold stack SB, a plurality of single-crystal silicon germanium layers can be alternately stacked with a plurality of single-crystal silicon layers. For example, the sacrificial mold layers 12 can be single-crystal silicon germanium layers, and the mold layers 13 can be single-crystal silicon layers. The stack of single-crystal silicon germanium layers and single-crystal silicon layers (SiGe / Si stack) can be stacked multiple times. The sacrificial mold layers 12 can be referred to as “sacrificial layers,” and the mold layers 13 can be referred to as “nanosheet target layers.”

[0113] The mold stack SB can be referred to as a “vertical stack.” The mold stack SB can be formed by alternately stacking a plurality of sacrificial layers and a plurality of nanosheet target layers. The sacrificial layers can be single-crystal silicon germanium layers, and the nanosheet target layers can be single-crystal silicon layers.

[0114] The thickness ratio of the sacrificial mold layers 12 and the thickness ratio of the mold layers 13 can be variously modified. For example, the thickness of each sacrificial mold layer 12 can be 5 nm to 20 nm, and the thickness of each mold layer 13 can be 50 nm to 80 nm. In addition, the number (or quantity) of the sacrificial mold layers 12 and the number (or quantity) of the mold layers 13 in the mold stack SB can be variously modified.

[0115] Subsequently, a plurality of cell-spacing openings 15 can be formed by etching portions of the mold stack SB. The cell-spacing openings 15 can be openings for storage cell isolation. The cross sections of the cell-spacing openings 15 can each have a rectangular shape from a top view. In some embodiments, the cross sections of the cell-spacing openings 15 can each have a circular or elliptical shape. In some embodiments, the cell-spacing openings 15 can be referred to as “cell-isolation trenches.” The cell-spacing openings 15 can vertically extend in the first direction D1 and longitudinally extend in the second direction D2. The cell-spacing openings 15 can be disposed at a predetermined interval in the third direction D3. The bottom surfaces of the cell-spacing openings 15 can extend to the inside of the substrate 11.

[0116] Next, a sacrificial isolation layer 16 can be formed to fill the cell-spacing openings 15. The sacrificial isolation layers 16 can include the same material. The sacrificial isolation layers 16 can each be formed of a dielectric material. The sacrificial isolation layers 16 can have etching selectivity with respect to the mold stack SB. For example, the sacrificial isolation layers 16 can each include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. Forming the sacrificial isolation layers 16 can include forming a cell-isolation material to fill the cell-spacing openings 15 and planarizing the cell-isolation material.

[0117] The sacrificial isolation layers 16 can vertically extend in the first direction D1 and longitudinally extend in the second direction D2. The sacrificial isolation layers 16 can be disposed at a predetermined interval in the third direction D3. The sacrificial isolation layers 16 can penetrate the mold stack SB in the first direction D1.

[0118] FIG. 6A is a plan view showing the structure at the level of the mold layer, for describing a method of forming the sacrificial linear openings 18L and 19L. FIG. 6B is a cross-sectional view of the structure taken along the line A-A’ shown in FIG. 6A

[0119] Referring to FIG. 6A and FIG. 6B , portions of the mold stack SB that do not form the sacrificial isolation layer 16 can be etched to form a plurality of sacrificial linear openings 18L and 19L. The sacrificial linear openings can include first sacrificial linear openings 18L and second sacrificial linear openings 19L. The mold stack SB can be etched using the hard mask layer 17 to form the sacrificial linear openings 18L and 19L. The first sacrificial linear openings 18L and the second sacrificial linear openings 19L can be linear openings extending along a third direction D3, from a plan view. The first sacrificial linear openings 18L and the second sacrificial linear openings 19L can extend vertically along a first direction D1. The sacrificial isolation layer 16 can be disposed between the first sacrificial linear openings 18L and the second sacrificial linear openings 19L along a second direction D2. The first sacrificial linear openings 18L and the second sacrificial linear openings 19L can each have a rectangular shape, from a plan view. In some embodiments, the first sacrificial linear openings 18L and the second sacrificial linear openings 19L can each have a circular or elliptical shape. The first sacrificial linear openings 18L and the second sacrificial linear openings 19L can each have a width along the second direction D2 that is less than a width along the third direction D3. The first sacrificial linear openings 18L and the second sacrificial linear openings 19L can be referred to as “sacrificial linear trenches”. The sacrificial isolation layer 16 can not contact the first sacrificial linear openings 18L and the second sacrificial linear openings 19L.

[0120] FIG. 7A is a plan view showing the structure at the level of the mold layer, for describing a method of forming the sacrificial linear openings 18L and 19L. FIG. 7B is a cross-sectional view of the structure taken along the line A-A’ shown in FIG. 7A

[0121] Referring to FIG. 7A and FIG. 7B ​​Linear sacrificial layers 18 and 19 can be formed to fill the first linear sacrificial openings 18L and the second linear sacrificial openings 19L. The linear sacrificial layers can include the first linear sacrificial layers 18 and the second linear sacrificial layers 19. The first linear sacrificial layers 18 and the second linear sacrificial layers 19 can have a linear shape extending along the third direction D3 as viewed from the top. The first linear sacrificial layers 18 and the second linear sacrificial layers 19 can extend vertically along the first direction D1. The sacrificial isolation layer 16 can be disposed between the first linear sacrificial layers 18 and the second linear sacrificial layers 19 along the second direction D2. The cross-section of each of the first linear sacrificial layers 18 and the second linear sacrificial layers 19 can have a rectangular shape as viewed from the top. In some embodiments, the cross-section of each of the first linear sacrificial layers 18 and the second linear sacrificial layers 19 can have a circular or an elliptical shape. The first linear sacrificial layers 18 and the second linear sacrificial layers 19 can include the same material. The first linear sacrificial layers 18 and the second linear sacrificial layers 19 can each be formed of a dielectric material. For example, the first linear sacrificial layers 18 and the second linear sacrificial layers 19 can each include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. The sacrificial isolation layer 16 can not contact the first linear sacrificial layers 18 and the second linear sacrificial layers 19.

[0122] FIG. 8A FIG. 1C is a plan view showing a structure at a mold layer level, for describing recesses of the sacrificial mold layer 12. FIG. 8B FIG. 1D is a cross-sectional view of the structure taken along the line A-A’ shown in FIG. 1C. FIG. 8A FIG. 1E is a plan view showing a structure at a mold layer level, for describing recesses of the sacrificial mold layer 12.

[0123] Referring to FIGS. 1A to 1E, the first linear sacrificial layers 18 and the second linear sacrificial layers 19 can be formed to fill the first linear sacrificial openings 18L and the second linear sacrificial openings 19L. The first linear sacrificial layers 18 and the second linear sacrificial layers 19 can include the same material. The first linear sacrificial layers 18 and the second linear sacrificial layers 19 can each be formed of a dielectric material. For example, the first linear sacrificial layers 18 and the second linear sacrificial layers 19 can each include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. The sacrificial isolation layer 16 can not contact the first linear sacrificial layers 18 and the second linear sacrificial layers 19. FIG. 8A and FIG. 8B Among the first linear sacrificial layers 18 and the second linear sacrificial layers 19, the first linear sacrificial layers 18 can be selectively removed. The first linear sacrificial layers 18 can be removed using a hard mask layer (not shown) as an etch stopper. After the first linear sacrificial layers 18 are removed, the sacrificial mold layer 12 and the mold layer 13 can be partially trimmed. As a result, the first linear openings 20 can be formed.

[0124] As viewed from the top, the first linear openings 20 can be disposed horizontally spaced apart from the second linear sacrificial layers 19 in the second direction D2.

[0125] The first linear openings 20 can have the same size as the first sacrificial linear openings 18L, or can be larger than the first sacrificial linear openings 18L, as described with reference to FIG. 6A FIGS. 1A to 1E. A bottom surface of the first linear openings 20 can be at the same level as a bottom surface of the first sacrificial linear openings 18L. A bottom surface of the first linear openings 20 can be at the same level as a bottom surface of the sacrificial isolation layer 16.

[0126] FIG. 9Ais a plan view showing the structure at the horizontal slice level, for describing a method of forming the support openings 21. FIG. 9B is a cross-sectional view of the structure taken along the line B-B' shown in FIG. 9A

[0127] Referring to FIG. 9A and FIG. 9B , portions of the sacrificial isolation layers 16 can be horizontally recessed along the second direction D2 through the first linear openings 20. Thus, a plurality of support openings 21 can be formed. The support openings 21 can extend vertically along the first direction D1 and can also be disposed between the mold layers 13.

[0128] FIG. 10A is a plan view showing the structure at the horizontal slice level, for describing a method of forming the supports 22. FIG. 10B is a cross-sectional view of the structure taken along the line B-B' shown in FIG. 10A

[0129] Referring to FIG. 10A and FIG. 10B , the supports 22 can be formed to fill the support openings 21. The supports 22 can be formed by depositing and etching a dielectric material. The supports 22 can each include silicon oxide, silicon nitride, or a combination thereof. The supports 22 and the sacrificial isolation layers 16 can include different materials. The supports 22 can be silicon nitride while the sacrificial isolation layers 16 can be silicon oxide. The supports 22 can extend vertically along the first direction D1 and can also be disposed between the mold layers 13.

[0130] FIG. 11A is a plan view showing the structure at the horizontal slice level, for describing a method of forming the horizontal slice 13N. FIG. 11B is a cross-sectional view of the structure taken along the line A-A' shown in FIG. 11A FIG. 11C is a cross-sectional view of the structure taken along the line C-C' shown in FIG. 11A

[0131] Referring to FIG. 11A to FIG. 11C , the sacrificial mold layers 12 can be locally recessed. The local recessing process of the sacrificial mold layers 12 can be referred to as a cutting process of the sacrificial mold layers 12.

[0132] A difference in etch selectivity between the sacrificial mold layers 12 and the mold layers 13 can be used to selectively recess the sacrificial mold layers 12. The sacrificial mold layers 12 can be removed using a wet etch process or a dry etch process. For example, when the sacrificial mold layers 12 include a silicon germanium layer and the mold layers 13 include a single-crystal silicon layer, an etchant or an etch gas that is selective with respect to the single-crystal silicon layer can be used to etch the silicon germanium layer.

[0133] ​​​​Subsequently, a portion (first portion) of each mold layer 13 can be recessed. The mold layer 13 can be recessed using either a wet etching process or a dry etching process.

[0134] A pre-formed nanosheet layer can be formed by localized recesses in the mold layer 13. The pre-formed nanosheet layer may include a host sheet 13A and a horizontal sheet 13N. The horizontal sheet 13N extends horizontally from the host sheet 13A. A tapered profile 13T can be defined between the horizontal sheet 13N and the host sheet 13A. The horizontal sheet 13N and the host sheet 13A may have an integral structure that is continuous in a second direction D2.

[0135] Each main sheet 13A can maintain its original thickness T1, while each horizontal sheet 13N can have a thickness T2 that is smaller than the original thickness T1. The tapered profile 13T can have a thickness that gradually increases from the horizontal sheet 13N to the main sheet 13A.

[0136] The horizontal length of the main body sheet 13A in the second direction D2 may be equal to or different from the horizontal length of the horizontal sheet 13N in the second direction D2. Each horizontal sheet 13N may be disposed between the sacrificial isolation layers 16 along the third direction D3. Furthermore, each main body sheet 13A may be disposed between the sacrificial isolation layers 16 along the third direction D3.

[0137] The recessing process used to form the horizontal wafer 13N can be referred to as a "thinning process" or "trimming process" of the mold layer 13. To form the horizontal wafer 13N, the upper surface, lower surface, and side surfaces of the mold layer 13 can be recessed. The horizontal wafer 13N may include a monocrystalline silicon layer. The recessing process used to form the horizontal wafer 13N may use an etchant selective relative to the sacrificial mold layer 13 and the sacrificial isolation layer 16.

[0138] The horizontal sheet 13N can be formed by a partial recessing process of the mold layer 13 as described above, and each horizontal sheet recess 13NS can be formed between the horizontal sheets 13N along the first direction D1. Both the upper and lower surfaces of the horizontal sheet 13N can include flat surfaces. The tapered profile 13T disposed between the main sheet 13A and the horizontal sheet 13N can have a curved shape or an angled shape. Each sacrificial mold layer 12 can be disposed between the vertically stacked main sheets 13A. Each horizontal sheet recess 13NS can be formed between the sacrificial isolation layers 16 along the third direction D3.

[0139] FIG. 12A It is a plan view showing the structure at the horizontal sheet level. FIG. 12B It is along FIG. 12A The cross-sectional view of line C-C' shown.

[0140] refer to FIG. 12A and FIG. 12BThe sacrificial isolation layer 16 can be selectively removed along the second direction D2. Thus, each interpiece opening 23 can be formed between the horizontal pieces 13N along the third direction D3. The interpiece openings 23 can extend vertically along the first direction Dl.

[0141] Each interpiece opening 23 can include a horizontal interpiece opening 23N and a body interpiece opening 23A. The horizontal interpiece opening 23N and the body interpiece opening 23A can have an integrated structure. The horizontal interpiece opening 23N can be formed between the horizontal pieces 13N along the third direction D3, and the body interpiece opening 23A can be formed between the body pieces 13A along the third direction D3.

[0142] FIG. 13A is a plan view showing the structure at the horizontal piece level for describing a method of forming the first intercell dielectric layer 24. FIG. 13B is a cross-sectional view of the structure taken along the line A-A' shown in FIG. 13A FIG. 13C is a cross-sectional view of the structure taken along the line B-B' shown in FIG. 13A FIG. 13D is a cross-sectional view of the structure taken along the line C-C' shown in FIG. 13A

[0143] Referring to FIG. 13A to FIG. 13D The first intercell dielectric layer 24 can be formed to fill the body interpiece openings 23A. The step of forming the first intercell dielectric layer 24 can include forming a dielectric material filling the interpiece openings 23, and horizontally recessing the dielectric material to form the first intercell dielectric layer 24 filling the body interpiece openings 23A. The first intercell dielectric layer 24 can each include silicon oxide, silicon nitride, or a combination thereof. The first intercell dielectric layer 24 can not be formed in the horizontal interpiece recesses 13NS and the horizontal interpiece openings 23N.

[0144] As described above, the combination of the horizontal interpiece recesses 13NS and the horizontal interpiece openings 23N can open all of the horizontal pieces 13N. That is, the combination of the horizontal interpiece recesses 13NS and the horizontal interpiece openings 23N can become a horizontal piece full-open recess 25. The horizontal piece full-open recess 25 can include a plurality of surrounding recesses 25S. The surrounding recesses 25S can expose all of the horizontal pieces 13N at the same horizontal level along the third direction D3. For example, any one of the surrounding recesses 25S extending along the third direction D3 can surround all surfaces of the horizontal pieces 13N at the same horizontal level.

[0145] Referring to FIG. 12A to FIG. 13D The sacrificial isolation layer 16 can be replaced by the first intercell dielectric layer 24. After the replacement process by the first intercell dielectric layer 24, a horizontal piece full-open recess 25 can be formed between the first intercell dielectric layer 24 and the support 22 to expose the horizontal pieces 13N.​​​

[0146] FIG. 14A is a plan view showing the structure at the horizontal sheet level, for describing the method of forming the first spacer layer 27A. FIG. 14B is a cross-sectional view of the structure taken along the line A-A' shown in FIG. 14A FIG. 14C is a cross-sectional view of the structure taken along the line C-C' shown in FIG. 14A

[0147] Referring to FIG. 14A to FIG. 14C , a nanosheet dielectric layer 26 can be formed on the exposed portions of the horizontal sheets 13N. The nanosheet dielectric layer 26 can be referred to as a "gate dielectric layer".

[0148] The nanosheet dielectric layer 26 can be formed by oxidizing the surfaces of the horizontal sheets 13N. In some embodiments, the nanosheet dielectric layer 26 can be formed by a deposition and oxidation process of silicon oxide. The nanosheet dielectric layer 26 can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The nanosheet dielectric layer 26 can include silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), aluminum oxynitride (AlON), hafnium oxynitride (HfON), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), or a combination thereof. The nanosheet dielectric layer 26 can be formed on all surfaces of the horizontal sheets 13N.

[0149] Subsequently, a first spacer layer 27A can be formed in the recesses 25S around. The first spacer layer 27A can include, for example, silicon nitride. The first spacer layer 27A can serve as a sacrificial material to define a space in which a first wire will be subsequently formed. The first spacer layer 27A can include a single-layer structure or a multi-layer structure. The first spacer layer 27A can include silicon oxide, silicon nitride, or a combination thereof. The first spacer layer 27A can fill all other spaces of the horizontal sheet inter-opening 23N on the nanosheet dielectric layer 26.

[0150] The first spacer layer 27A can surround and cover the horizontal sheets 13N on the nanosheet dielectric layer 26. The first spacer layer 27A can be thicker than the nanosheet dielectric layer 26.

[0151] A second inter-cell dielectric layer 28A can be formed on the first spacer layer 27A. The second inter-cell dielectric layer 28A can fill the recesses 25S around on the first spacer layer 27A.

[0152] Referring to FIG. 11A to FIG. 14C , the horizontal sheet inter-recesses (​​FIG. 11B The second inter-unit dielectric layer 28A can include silicon oxide. The first spacer layer 27A and the second inter-unit dielectric layer 28A can not fill the first linear opening 20.

[0153] FIG. 15A is a plan view of the structure showing a method of forming the first spacers 27. FIG. 15B is a cross-sectional view of the structure taken along FIG. 15A line B-B' shown in FIG. 1B. FIG. 15C is a cross-sectional view of the structure taken along FIG. 15A line C-C' shown in FIG. 1C.

[0154] Referring to FIG. 15A to FIG. 15B , a recessing process can be performed on the first spacer layer 27A. The recessing process can include a side recessing process or a horizontal recessing process. When the recessing process is performed, the first spacers 27 can be formed. The first spacers 27 can be referred to as "recessed spacers" or "horizontally recessed spacers".

[0155] The recessing process for the first spacer layer 27A can include an oxide recessing process, a nitride recessing process, or a combination thereof. For example, when the first spacer layer 27A is silicon nitride, the first spacers 27 can be formed by side recessing of the nitride.

[0156] The first spacers 27 can vertically extend along the first direction D1 and can also surround the boundary portion of the horizontal sheet 13N and the main body sheet 13A, i.e., the tapered profile 13T. In addition, the first spacers 27 can horizontally extend along the third direction D3 and can also surround the tapered profile 13T disposed between the horizontal sheet 13N and the main body sheet 13A.

[0157] Due to the formation of the first spacers 27, linear surrounding recesses 29 around the horizontal sheet 13N can be formed on the nanosheet dielectric layer 26. Each second inter-unit dielectric layer 28 can be disposed between the vertically disposed linear surrounding recesses 29. Each first spacer 27 can have a cup shape covering one side of each second inter-unit dielectric layer 28. Each first spacer 27 extending along the first direction D1 and the third direction D3 can have a frame structure surrounding each tapered profile 13T.

[0158] FIG. 16A is a plan view of the structure showing a method of forming the first spacers 27. FIG. 16B is a cross-sectional view of the structure taken along FIG. 16A line A-A' shown in FIG. 2A. FIG. 16C is a cross-sectional view of the structure taken along FIG. 16A line C-C' shown in FIG. 2C. FIG. 16D is a cross-sectional view of the structure taken along FIG. 16Aa cross-sectional view of the structure taken along the line D-D' shown in FIG. 1. FIG. 16E is along FIG. 16A a cross-sectional view of the structure taken along the line E-E' shown in FIG. 1. FIG. 16F is along FIG. 16A a cross-sectional view of the structure taken along the line F-F' shown in FIG. 1.

[0159] Referring to FIG. 1, FIG. 16A to FIG. 16F The first conductive lines 30 can be formed to fill the linear enclosures around the recesses 29. The first conductive lines 30 can extend horizontally along the third direction D3.

[0160] Forming the first conductive lines 30 can include depositing a conductive material to fill the linear enclosures around the recesses 29 on the nanosheet dielectric layer 26, and performing a horizontal recess process on the conductive material. The first conductive lines 30 can each include a metal-based material, a semiconductor material, or a combination thereof. The first conductive lines 30 can each include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first conductive lines 30 can each include a titanium nitride and tungsten (TiN / W) stack, in which the titanium nitride and tungsten are sequentially stacked. The first conductive lines 30 can each include an N-type work function material or a P-type work function material. The N-type work function material can have a low work function of about 4.5 eV or less, while the P-type work function material can have a high work function of about 4.5 eV or more.

[0161] Each second intercell dielectric layer 28 can be disposed between the plurality of first conductive lines 30 along the first direction D1. Each first conductive line 30 extending horizontally along the third direction D3 can simultaneously enclose a horizontal sheet 13N at the same level. The first conductive line 30 enclosing the horizontal sheet 13N can be referred to as a “gate-all-around (GAA) electrode”. The horizontal sheet 13N can be referred to as a “nanosheet channel”, a “nanowire”, or a “nanowire channel”.

[0162] Each side gap 30G can be defined between the first conductive line 30 and the support 22 along the second direction D2.

[0163] Referring to FIG. 1, FIG. 14A to FIG. 16F A portion of the first spacer layer 27A can be replaced by the first conductive line 30, while other portions can remain as the first spacer 27.

[0164] Referring again to FIG. 1, FIG. 16A and FIG. 16D The side gap 30G can expose all of the horizontal sheets 13N and the nanosheet dielectric layer 26 adjacent to each other along the third direction D3.

[0165] Referring again to FIG. 1, FIG. 16A and FIG. 16E Each horizontal sheet 13N can be disposed between the supports 22 adjacent to each other along the third direction D3. In other words, edges of the horizontal sheets 13N can be supported by the supports 22.

[0166] FIG. 17A is a plan view showing a structure at a horizontal sheet level, for describing a method of forming a second spacer 31B. FIG. 17B is a cross-sectional view of the structure taken along FIG. 17A line A-A' shown in FIG. 17C . FIG. 17A is a cross-sectional view of the structure taken along FIG. 17D line D-D' shown in FIG. 17A . FIG. 17E is a cross-sectional view of the structure taken along FIG. 17A line E-E' shown in .

[0167] Referring to FIG. 17A to FIG. 17E , a second spacer 31B can be formed on one side of each first wire 30. The second spacer 31B can include silicon oxide, silicon nitride, silicon oxynitride, embedded air gap, or a combination thereof. A process for forming the second spacer 31B can include first depositing a spacer material, and then performing a side recess process on the spacer material. The second spacer 31B can fill a side gap (reference numeral "30G" of FIG. 16A ) located on a side surface of the first wire 30. Portions of the second unit interlayer dielectric layer 28 and portions of the nanosheet dielectric layer 26 can be recessed at the same time or after the second spacer 31B is formed. The second spacer 31B can be self-aligned with edges of the second unit interlayer dielectric layer 28. As the second unit interlayer dielectric layer 28 and the nanosheet dielectric layer 26 are recessed, protruding edges 13E1 of the horizontal sheets 13N can be exposed.

[0168] The second spacer 31B can be disposed on upper and lower surfaces of portions of the horizontal sheets 13N located between the second unit interlayer dielectric layer 28. The second spacer 31B can include inner spacers 31S disposed between the horizontal sheets 13N in a third direction D3, and outer spacers 31E disposed on side surfaces of the support 22. The outer spacers 31E can be continuous with the inner spacers 31S. The inner spacers 31S can extend vertically in the first direction D1. The outer spacers 31E can be disposed on upper and lower surfaces of portions of the horizontal sheets 13N located on the nanosheet dielectric layer 26. That is, the outer spacers 31E can be discontinuous with each other in the first direction D1. The first spacer 27 and the second spacer 31B can have different shapes.

[0169] The second spacer 31B extending along the first direction D1 and the third direction D3 can have a frame structure around the portion of the horizontal sheet 13N. The second spacer 31B can include a horizontal segment 31H. The horizontal segment 31H of the second spacer 31B can refer to a portion extending along the third direction D3 by the combination of the inner spacer 31S and the outer spacer 31E. The horizontal segment 31H of the second spacer 31B can surround the portion of the horizontal sheet 13N arranged along the third direction D3 at the same horizontal level.

[0170] As described above, the second spacer 31B can extend along the first direction D1 and the third direction D3, and can also surround the portion of the horizontal sheet 13N by the horizontal segment 31H and the inner spacer 31S.

[0171] The second spacer 31B, the first wire 30, and the first spacer 27 can be disposed between the horizontal sheets 13N at the same horizontal level along the second direction D2. In addition, the second spacer 31B, the first wire 30, and the first spacer 27 can be disposed between the support 22 and the first unit inter-de dielectric layer 24 along the second direction D2.

[0172] After the second spacer 31B is formed, the initial support inter-opening 32' exposing the protruding edge 13E1 of the horizontal sheet 13N can be defined.

[0173] FIG. 18A is a plan view showing a structure at a horizontal sheet level for describing a method of forming a support inter-opening 32. FIG. 18B is a cross-sectional view of the structure taken along the line A-A' shown in FIG. 18A FIG. 18C is a cross-sectional view of the structure taken along the line E-E' shown in FIG. 18A

[0174] Referring to FIG. 18A to FIG. 18C The protruding edge 13E1 of the horizontal sheet 13N can be cut to form the support inter-opening 32. By cutting the protruding edge 13E1 of the horizontal sheet 13N, the initial support inter-opening 32' can be horizontally expanded. The expanded initial support inter-opening 32' can become the support inter-opening 32.

[0175] Forming the support inter-opening 32 can include cutting the protruding edge 13E1 of the horizontal sheet 13N from the first linear opening 20 along the second direction D2. A series of processes for forming the support inter-opening 32 can be performed using the second spacer 31B as a barrier layer.

[0176] ​​The horizontal length of the horizontal sheet 13N can be shortened due to the formation of the support-to-support opening 32. The support-to-support opening 32 can include an inner side surface, and the inner side surface of the support-to-support opening 32 can expose a side surface of the horizontal sheet 13N. The support-to-support opening 32 can be formed to be self-aligned with the support 22 and the outer spacer 31E of the second spacer 31B. The support-to-support opening 32 can be referred to as a "self-aligned opening."

[0177] FIG. 19A is a plan view showing a structure at a horizontal sheet layer, for describing a method of forming a first contact node 33. FIG. 19B is a cross-sectional view of the structure taken along the A-A' line in FIG. 19A .

[0178] Referring to FIG. 19A and FIG. 19B , the support-to-support opening 32 can be horizontally expanded (referring to reference numeral "32A"). The second spacer 31B can be horizontally recessed to form the expanded support-to-support opening 32A. Accordingly, the horizontal length of the second spacer can be reduced, as indicated by reference numeral "31". The support-to-support opening 32A can expose the protruding sheet node 13E of the horizontal sheet 13N. The protruding sheet node 13E can not be aligned with the outer surface of the second spacer 31, but have a shape protruding horizontally.

[0179] FIG. 20A is a plan view showing a structure at a horizontal sheet layer, for describing a method of forming a first contact node 33. FIG. 20B is a cross-sectional view of the structure taken along the A-A' line in FIG. 20A .

[0180] Referring to FIG. 20A and FIG. 20B , the first contact node 33 can be formed in the support-to-support opening 32A. The first contact node 33 can be formed by depositing and etching doped polysilicon. For example, forming the first contact node 33 can include depositing doped polysilicon such that a first thickness covering the protruding sheet node 13E is greater than a second thickness formed on other surfaces, and etching the doped polysilicon to form the first contact node 33. In another embodiment, the first contact node 33 can be selectively formed on the protruding sheet node 13E by epitaxial growth.

[0181] The first contact node 33 can be disposed in the support-to-support opening 32A and cover the protruding sheet node 13E of the horizontal sheet 13N.

[0182] Each first contact node 33 can contain a dopant. Each first contact node 33 can contain an N-type dopant. The N-type dopant can include phosphorus, arsenic, antimony, or a combination thereof.

[0183] In some embodiments, a first doped region (referenced by reference symbol "DR") can be formed in the horizontal sheet 13N. A thermal treatment process can be performed to form the first doped region, allowing dopants to diffuse from the first contact nodes 33. FIG. 1B

[0184] FIG. 21A To show a plan view of the structure at the horizontal sheet level, which is used to describe the method of forming the second conductive lines 34A and 34B. FIG. 21B To show a cross-sectional view of the structure taken along the A-A' line in FIG. 21A

[0185] Referring to FIG. 21A and FIG. 21B A contact isolation layer 33A can be formed on the first contact nodes 33. The contact isolation layer 33A can be formed between the first contact nodes 33 along the first direction Dl. The contact isolation layer 33A can isolate the first contact nodes 33 from each other along the first direction Dl. The contact isolation layers 33A can each comprise a dielectric material. The step of forming the contact isolation layer 33A can comprise forming a dielectric material on the first contact nodes 33, and etching the dielectric material.

[0186] The contact isolation layer 33A can expose the outer surfaces of the first contact nodes 33.

[0187] Subsequently, an ohmic contact layer 33M can be formed on the first contact nodes 33. Each ohmic contact layer 33M can comprise a metal silicide. The process of forming the ohmic contact layer 33M can comprise forming a metal material on the outer surfaces of the first contact nodes 33, performing a thermal treatment to induce a silicidation reaction between the metal material and the outer surfaces of the first contact nodes 33, and removing unreacted metal material. In some embodiments, unreacted metal material can remain without being removed.

[0188] Subsequently, a second conductive line can be formed on the ohmic contact layer 33M and the contact isolation layer 33A. The second conductive line can comprise a first vertical conductive line 34A and a second vertical conductive line 34B. The first vertical conductive line 34A and the second vertical conductive line 34B can be spaced apart from each other. The first vertical conductive line 34A can be commonly coupled to the first contact nodes 33 and the ohmic contact layers 33M arranged along the first direction Dl. The second vertical conductive line 34B can be commonly coupled to the first contact nodes 33 and the ohmic contact layers 33M arranged along the first direction Dl.

[0189] ​​The first vertical conductor 34A and the second vertical conductor 34B may each comprise a metal base material. The first vertical conductor 34A and the second vertical conductor 34B may each comprise titanium nitride, tungsten, or a combination thereof. The first vertical conductor 34A and the second vertical conductor 34B may cover the first contact node 33 and the ohmic contact layer 33M. The first vertical conductor 34A and the second vertical conductor 34B may correspond to... FIG. 4A and FIG. 4B The first vertical conductor BLA and the second vertical conductor BLB are shown in the figure.

[0190] Forming the first vertical conductor 34A and the second vertical conductor 34B may include depositing vertical conductor material and performing an etch-back process on the vertical conductor material. That is, the first vertical conductor 34A and the second vertical conductor 34B can be formed to be self-aligned with the support member 22 by a global etch-back process without a mask.

[0191] The bottom of the first vertical conductor 34A and the bottom of the second vertical conductor 34B may be discontinuous or merged. The first vertical conductor 34A and the second vertical conductor 34B may extend perpendicularly along a first direction D1. The outer surfaces of the first vertical conductor 34A and the second vertical conductor 34B may have non-linear profiles. In another embodiment, the outer surfaces of the first vertical conductor 34A and the second vertical conductor 34B may have linear profiles.

[0192] The first vertical conductor 34A and the second vertical conductor 34B can be configured to be self-aligned with the second spacer 31 and the support member 22. The first vertical conductor 34A and the second vertical conductor 34B can be disposed between the support members 22 along a third direction D3. The support member 22 can support the first vertical conductor 34A and the second vertical conductor 34B. The support member 22 can serve as an isolation layer between the first vertical conductor 34A and the second vertical conductor 34B that are adjacent to each other in the third direction D3.

[0193] The first vertical guide 34A and the second vertical guide 34B, which are self-aligned with the support member 22 and the second spacer 31, can be referred to as a "self-aligned alignment line (SABL) structure".

[0194] FIG. 22A A plan view of the structure at the horizontal lamellae is shown, which is used to describe the method of forming the second linear opening 35; FIG. 22B For along FIG. 22A The cross-sectional view of the structure intercepted by line A-A' is shown.

[0195] refer to FIG. 22A and FIG. 22BAn array isolation layer 34F can be formed to fill the first linear openings 20 over the first vertical conductive lines 34A and the second vertical conductive lines 34B. The array isolation layer 34F can vertically extend along the first direction D1 and horizontally extend along the third direction D3. The first vertical conductive lines 34A and the second vertical conductive lines 34B adjacent to each other in the third direction D3 can be isolated from each other by the array isolation layer 34F. The array isolation layer 34F can include a dielectric material. The array isolation layer 34F can include silicon oxide, silicon nitride, air gap, or a combination thereof.

[0196] Subsequently, the second linear sacrificial layer 19L can be removed, and thus, the second linear openings 35 can be formed.

[0197] After the second linear openings 35 are formed, the sacrificial mold layer 12 can be selectively recessed through the second linear openings 35. To selectively recess the sacrificial mold layer 12, an etch selectivity difference between the sacrificial mold layer 12 and the bulk sheet 13A can be utilized. The sacrificial mold layer 12 can be removed using a wet etch or dry etch process. For example, when the sacrificial mold layer 12 includes a silicon germanium layer and the bulk sheet 13A includes a single crystalline silicon layer, an etchant or etch gas selective to the single crystalline silicon layer can be used to etch the silicon germanium layer.

[0198] Subsequently, the bulk sheet 13A can be recessed in the vertical direction and the horizontal direction. To recess the bulk sheet 13A, a wet etch or dry etch process can be employed. The vertical thickness of the bulk sheet 13A can be reduced, as indicated by reference numeral “13S”.

[0199] A respective inter-bulk recess 13G can be formed between the vertically disposed bulk sheets 13A. An inner side of the inter-bulk recess 13G can expose a surface of the nanosheet dielectric layer 26.

[0200] FIG. 23A To show a plan view of the structure at the horizontal sheet layer, which is used to describe a method of forming the tapered sheet 13W. FIG. 23B To show a cross-sectional view of the structure along FIG. 23A A cross-sectional view of the structure taken along line A-A’.

[0201] Referring to FIG. 23A and FIG. 23B A third inter-cell dielectric layer 36 can be formed to fill the inter-bulk recess 13G. The third inter-cell dielectric layer 36 can each include silicon oxide. The third inter-cell dielectric layer 36 can be referred to as a “data storage element inter-cell dielectric layer”.

[0202] The combination of the third inter-cell dielectric layer 36 and the first inter-cell dielectric layer 24 can be inter-cell dielectric layers each having a frame structure of a lattice shape.

[0203] After the third inter-cell dielectric layer 36 is formed, the memory slots 37 can be formed by horizontal recessing (or trimming) of the bulk sheet 13S. The memory slots 37 can be referred to as “capacitor openings.” The tapered sheet 13W can be formed by horizontal recessing of the bulk sheet 13S. The tapered sheet 13W can include a tapered profile 13T.

[0204] The combination of the horizontal sheet 13N and the tapered sheet 13W can form a nanosheet HL. In some embodiments, the bulk sheet 13S can be fully recessed such that the upper and lower surfaces of the tapered sheet 13W can consist of only the tapered profile 13T.

[0205] Each nanosheet HL can include the horizontal sheet 13N and the tapered sheet 13W, and the tapered sheet 13W can refer to the bulk sheet 13S remaining after recessing. The average vertical height of the tapered sheet 13W of the nanosheet HL in the first direction D1 can be greater than the average vertical height of the horizontal sheet 13N. The thickness of the tapered sheet 13W of the nanosheet HL can gradually increase along the second direction D2. The horizontal length of the tapered sheet 13W in the second direction D2 can be less than the horizontal length of the horizontal sheet 13N. The cross-section of the tapered sheet 13W of the nanosheet HL can have a sector shape. The tapered sheet 13W can be referred to as a “sector sheet,” and the horizontal sheet 13N can be referred to as a “flat sheet.”

[0206] To form the nanosheet HL (each nanosheet including the tapered sheet 13W), isotropic or anisotropic etching can be performed on the bulk sheet 13S. One side of the tapered sheet 13W, i.e., the side exposed by each memory slot 37, can have a planar shape. One side of the tapered sheet 13W can have a variety of shapes.

[0207] Each nanosheet HL can include a first edge and a second edge. The first edge can refer to the side of the horizontal sheet 13N electrically coupled to the first vertical wire 34A, the second vertical wire 34B, and the first contact node 33. The second edge can refer to the side of the tapered sheet 13W exposed by the memory slot 37.

[0208] Each memory slot 37 can be disposed in a grid-shaped frame structure combined by the third inter-cell dielectric layer 36 and the first inter-cell dielectric layer 24.

[0209] In some embodiments, the horizontal recessing of the bulk sheet 13S to form the tapered sheet 13W can stop at a boundary region between the horizontal sheet 13N and the tapered sheet 13W. That is, the horizontal recessing of the bulk sheet 13S can be performed until the vertical thickness of the tapered sheet 13W is formed to be equal to the vertical thickness of the horizontal sheet 13N.

[0210] FIG. 24A To show a plan view of the structure at the nanosheet layer, a method of forming the second contact node 38 and the first electrode 39 is described.FIG. 24B to show a cross-sectional view of the structure taken along line A-A' in FIG. 24A

[0211] Referring to FIG. 24A and FIG. 24B A pre-cleaning process can be performed on the exposed surfaces of the tapered fins 13W.

[0212] Subsequently, second contact nodes 38 can be formed on the tapered fins 13W. The step of forming the second contact nodes 38 can include selective epitaxial growth (SEG). For example, a semiconductor material can be grown from the side surfaces of the tapered fins 13W by SEG. The second contact nodes 38 can each include SEG Si. Since the tapered fins 13W each include single crystalline silicon, a silicon layer can be epitaxially grown along the crystal planes of the side surfaces of the tapered fins 13W.

[0213] Each of the second contact nodes 38 can include a dopant. When the silicon layer is grown using SEG, the dopant can be doped in-situ. Thus, each of the second contact nodes 38 can be a doped epitaxial layer. Each of the second contact nodes 38 can include an N-type dopant as the dopant. The N-type dopant can include phosphorus, arsenic, antimony, or a combination thereof. Each of the second contact nodes 38 can include a phosphorus-doped silicon epitaxial layer formed by SEG, i.e., a doped SEG SiP.

[0214] Since the second contact nodes 38 are formed by employing SEG, the second contact nodes 38 can be formed without voids or seams. Since the second contact nodes 38 are formed by employing SEG, the process of forming the second contact nodes 38 can be simplified.

[0215] Each of the second contact nodes 38 can be disposed between the third inter-cell dielectric layers 36 of the vertical stack.

[0216] In some embodiments, the second contact nodes 38 can be formed by depositing and etching doped polysilicon.

[0217] In some embodiments, a second doped region (see reference sign “SR” in FIG. 1) can be formed in the tapered fins 13W. A thermal process can be performed to form the second doped region, such that the dopant can diffuse from the second contact nodes 38. FIG. 1B

[0218] Each of the nanosheets HL can include a horizontal fin 13N and a tapered fin 13W. The nanosheet HL can correspond to the nanosheet HL described above with reference to FIG. 1A to FIG. 4D FIG. 1B

[0219] ​​​​In some embodiments, after forming the second contact node 38, an ohmic contact layer comprising a metal silicide can also be formed.

[0220] Subsequently, a storage node, i.e., a first electrode 39 of a data storage element, can be formed on the second contact node 38. Each first electrode 39 can be horizontally oriented cylindrical, and each first electrode 39 can be disposed in a different storage slot 37. First electrodes 39 adjacent to each other in the second direction D2 can be spaced apart from each other by the second linear opening 35. First electrodes 39 adjacent to each other in the third direction D3 can be spaced apart from each other by the first intercell dielectric layer 24. First electrodes 39 adjacent to each other in the first direction D1 can be spaced apart from each other by the third intercell dielectric layer 36. The step of forming the first electrode 39 can include depositing a metal material, gap filling a sacrificial material, and isolating the metal material in the vertical / horizontal direction. The sacrificial material can include an oxide or polysilicon.

[0221] Each first electrode 39 can include an interior space and a plurality of outer surfaces. The interior space of the first electrode 39 can include a plurality of inner surfaces. The outer surfaces of the first electrode 39 can include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 39 can extend vertically along the first direction D1. The horizontal outer surfaces of the first electrode 39 can extend horizontally along the second direction D2 or the third direction D3. The interior space of the first electrode 39 can be a three-dimensional space, and the first electrode 39 can be cylindrical.

[0222] The first electrode 39 can include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 39 can include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium / tungsten nitride (TiN / W) stack, a tungsten / tungsten nitride (WN / W) stack, a titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, or a combination thereof.

[0223] FIG. 25A is a plan view showing the structure at the nanosheet level, which is used to describe a method of recessing the first intercell dielectric layer 24 and the third intercell dielectric layer 36. FIG. 25B is a cross-sectional view of the structure taken along the line A-A' in FIG. 25A .

[0224] Referring to FIG. 25A and FIG. 25BA portion of the first inter-unit dielectric layer 24 and the third inter-unit dielectric layer 36 can be horizontally recessed (refer to reference numeral "40"). Accordingly, outer walls of the first electrodes 39 can be partially exposed. The first electrodes 39 can each be semi-cylindrical. The horizontal recess depth of the first inter-unit dielectric layer 24 and the third inter-unit dielectric layer 36 can be a depth that does not expose the second contact nodes 38. The semi-cylindrical shape of each first electrode 39 can include a cylindrical inner surface and a semi-cylindrical outer surface.

[0225] FIG. 26A is a plan view showing a structure at a nanosheet layer, which is used to describe a method of forming the second electrodes 42 of the data storage elements. FIG. 26B is a cross-sectional view of the structure taken along the A-A' line in FIG. 26A .

[0226] Referring to FIG. 26A and FIG. 26B , the dielectric layer 41 and the second electrodes 42 can be sequentially formed on the first electrodes 39. The first electrodes 39, the dielectric layer 41, and the second electrodes 42 can be data storage elements CAP. The second electrodes 42 of the data storage elements CAP can be fused to each other and form a common plate PL. The dielectric layer 41 and the second electrodes 42 can correspond to the dielectric layer DE and the second electrodes PN shown in FIG. 4A and FIG. 4B . The second electrodes 42 can be plate-type nodes.

[0227] The dielectric layer 41 and the second electrodes 42 can be disposed on the cylindrical inner surface of the first electrodes 39. A portion of the dielectric layer 41 and a portion of the second electrodes 42 can extend to be disposed on the semi-cylindrical outer surface of the first electrodes 39.

[0228] The dielectric layer 41 can be referred to as a "capacitor dielectric layer" or a "memory layer." The dielectric layer 41 can include silicon oxide, silicon nitride, high-k materials, ferroelectric materials, anti-ferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 41 can include hafnium oxide (Hf02), zirconium oxide (Zr02), aluminum oxide (AI2O3), lanthanum oxide (La203), titanium oxide (Ti02), tantalum oxide (Ta205), niobium oxide (Nb205), or strontium titanium oxide (SrTi03). The dielectric layer 41 can include a ZA (Zr02 / AI2O3) stack, a ZAZ (Zr02 / AI2O3 / Zr02) stack, a ZAZA (Zr02 / AI2O3 / Zr02 / AI2O3) stack, a ZAZAZ (Zr02 / AI2O3 / Zr02 / AI2O3 / Zr02) stack, a HA (Hf02 / AI2O3) stack, a HAH (Hf02 / AI2O3 / Hf02) stack, a HAHA (Hf02 / AI2O3 / Hf02 / AI2O3) stack, a HAHAH (Hf02 / AI2O3 / Hf02 / AI2O3 / Hf02) stack, a HZAZH (Hf02 / Zr02 / AI2O3 / Zr02 / Hf02) stack, a ZHZAZHZ (Zr02 / Hf02 / Zr02 / AI2O3 / Zr02 / Hf02 / Zr02) stack, a HZHZ (Hf02 / Zr02 / Hf02 / Zr02) stack, or an AHZAZHA (AI2O3 / Hf02 / Zr02 / AI2O3 / Zr02 / Hf02 / AI2O3) stack.

[0229] The second electrode 42 can include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or combinations thereof. For example, the second electrode 42 can include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (Ru02), iridium (Ir), iridium oxide (Ir02), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, a titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, a titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stack, or combinations thereof. The second electrode 42 can also include a combination of metal-based materials and silicon-based materials. For example, titanium nitride, tungsten, and polysilicon can be sequentially stacked in the second electrode 42.

[0230] In some embodiments, a plurality of interface control layers can be further included between the first electrode 39 and the dielectric layer 41 and between the dielectric layer 41 and the second electrode 42 to mitigate leakage current. Each interface control layer can include titanium dioxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The data storage element CAP can include a first interface control layer, a second interface control layer, or a combination thereof. The first interface control layer and the second interface control layer can be conductive layers or dielectric layers. The first interface control layer can be formed between the first electrode 39 and the dielectric layer 41, and the second interface control layer can be formed between the dielectric layer 41 and the second electrode 42. The first interface control layer and the second interface control layer can be composed of the same material or different materials. For example, a structure in which the first interface control layer, the dielectric layer 41, and the second interface control layer of the data storage element CAP are sequentially stacked can include a NZHZAZHZATN (Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0231] In some embodiments, the recesses of the first intercell dielectric layer 24 and the third intercell dielectric layer 36 shown in FIG. 25A and FIG. 25B may be omitted. Thereafter, the dielectric layer 41 and the second electrode 42 can be formed as shown in FIG. 26A and FIG. 26B . Thus, the data storage element CAP including the first electrode 39 having a concave shape can be formed.

[0232] The first electrode 39 of the data storage element CAP can be disposed in the storage trench 37 and can also be coupled to the tapered fin 13W.

[0233] Referring to FIG. 5A to FIG. 26BThe method of manufacturing a semiconductor device can include forming vertically stacked mold layers 13; forming sacrificial isolation layers 16 between the vertically stacked mold layers 13; replacing edges of the sacrificial isolation layers 16 with support pieces 22; forming vertical and horizontal arrangements of preliminary nanosheet layers, each of which includes a horizontal sheet 13N including a protruding edge 13E1 in contact with the support pieces 22, and a main body sheet 13A continuous with the horizontal sheet 13N by a recess of the mold layer 13; replacing the sacrificial isolation layers 16 with a second intercell dielectric layer 28; forming horizontal oriented first wires 30, and the first wires 30 surround portions of the horizontal sheets 13N between the second intercell dielectric layer 28 and the support pieces 22; forming protruding sheet nodes 13E between the support pieces 22 by cutting the protruding edges 13E1 of the horizontal sheets 13N; and forming horizontal arrangements of second wires 34A and 34B electrically coupled to the protruding sheet nodes 13E and vertically oriented to the support pieces 22 in a direction intersecting the first wires 30.

[0234] According to various embodiments of the disclosure, since the second wires 34A and 34B are formed to be self-aligned with the support pieces 22 and the second spacers 31, a high-aspect-ratio etching process is not required. Thus, the integration can be improved, and the manufacturing cost of the semiconductor device can be reduced.

[0235] According to various embodiments of the disclosure, due to the presence of the support pieces 22, the electrical isolation between the second wires 34A and 34B adjacent to each other is stable.

[0236] According to various embodiments of the disclosure, since the first contact nodes 33 are formed of doped polysilicon, the effective area of the ohmic contact layer 33M can be increased. Thus, the contact resistance between the second wires 34A and 34B and the first contact nodes 33 can be improved.

[0237] According to various embodiments of the disclosure, since the gaps between the first wires 30 are partially filled with the second intercell dielectric layer 28, the parasitic capacitance between the first wires 30 can be reduced. Thus, the size of the memory cell block can be increased, which is advantageous for increasing the number of effective dies and reducing the manufacturing cost of the semiconductor device. In addition, since the parasitic capacitance between the first wires 30 is reduced, the timing characteristics tRCD (time between an activate command and a read command) of a semiconductor memory device such as a DRAM can be improved.

[0238] FIG. 27 is a schematic cross-sectional view of a semiconductor device according to another embodiment. FIG. 27 The semiconductor device 200 of can be similar to the semiconductor device 100 of FIG. 4A to FIG. 4D The semiconductor device 100 of can be similar to the semiconductor device 100 of FIG. 4A to FIG. 4DA description is made.

[0239] As FIG. 27 illustrated, the semiconductor device 200 can include a lower structure LS and a memory cell array MCA. The memory cell array MCA can include a first sub-cell array MCA1 and a second sub-cell array MCA2. The first sub-cell array MCA1 can include a three-dimensional array of first memory cells MC1, and the second sub-cell array MCA2 can include a three-dimensional array of second memory cells MC2. The first memory cells MC1 of the first sub-cell array MCA1 can share a second wire, i.e., a first vertical wire BLA. The second memory cells MC2 of the second sub-cell array MCA2 can share a second wire, i.e., a second vertical wire BLB. A bottom of the first vertical wire BLA can be electrically isolated from a bottom of the second vertical wire BLB. An outer surface of the first vertical wire BLA and the second vertical wire BLB can have a linear profile.

[0240] According to various embodiments of the disclosure, since the support is formed between the vertical wires, the electrical isolation between the vertical wires can be easily achieved.

[0241] According to various embodiments of the disclosure, since the contact node is formed of doped polysilicon, the effective area of the ohmic contact layer can be increased.

[0242] According to various embodiments of the disclosure, the electrical characteristics and reliability of the semiconductor device can be improved.

[0243] While the embodiments of the disclosure have been illustrated and described with respect to specific embodiments and drawings, the disclosed embodiments are not intended to be limiting. In addition, it is noted that the embodiments can be implemented in various manners by substitution, change, and modification without departing from the spirit and / or scope of the disclosure and the appended claims, as will be appreciated by those skilled in the art in light of the disclosure. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: a vertical arrangement and a horizontal arrangement of nanosheets, the nanosheets comprising horizontal sheets and tapered sheets, the horizontal sheets comprising protruding sheet nodes, the tapered sheets continuous from the horizontal sheets in a first horizontal direction; a vertical arrangement of first conductive lines, the first conductive lines surrounding a portion of the horizontal sheets of the horizontal arrangement and oriented along a second horizontal direction; first contact nodes overlying the protruding sheet nodes of the horizontal sheets; a horizontal arrangement of second conductive lines, the second conductive lines overlying the first contact nodes and oriented along a vertical direction; supports disposed between the horizontal arrangement of second conductive lines and oriented along the vertical direction; and data storage elements coupled with the tapered sheets.

2. The semiconductor device of claim 1, further comprising contact isolation layers disposed between the first contact nodes along the vertical direction and exposing outer surfaces of the first contact nodes.

3. The semiconductor device of claim 2, further comprising ohmic contact layers disposed between the first contact nodes and the second conductive lines and overlying the outer surfaces of the first contact nodes. the supports directly contacting the second conductive lines, the first contact nodes, and the protruding sheet nodes.

4. The semiconductor device of claim 1, wherein, each of the supports comprises a dielectric material.

5. The semiconductor device of claim 1, wherein, each of the first contact nodes comprises doped polysilicon.

6. The semiconductor device of claim 1, wherein, 7. The semiconductor device of claim 1, further comprising: first spacers disposed between the data storage elements and the first conductive lines and surrounding the tapered sheets; and second spacers disposed between the first conductive lines and the first contact nodes and surrounding a portion of the horizontal sheets. the second spacers comprise extensions overlying inner walls of the supports.

9. The semiconductor device of claim 1, further comprising second contact nodes formed between the tapered sheets and the data storage elements.

8. The semiconductor device of claim 7, wherein, the data storage elements comprise: first electrodes, each of the first electrodes having a cylindrical shape and coupled with the tapered sheets; 10. The semiconductor device of claim 1, wherein, a dielectric layer disposed on the first electrodes; and second electrodes disposed on the dielectric layer.

11. A method of fabricating a semiconductor device, the method comprising: forming a vertical stack of mold layers; forming sacrificial isolation layers between the mold layers of the vertical stack; replacing a lateral edge of the sacrificial isolation layers with supports; forming a vertical arrangement and a horizontal arrangement of preliminary nanosheet layers, the preliminary nanosheet layers comprising horizontal sheets having protruding edges in contact with the supports through recesses of the mold layers and body sheets continuous from the horizontal sheets; replacing the sacrificial isolation layers with intercell dielectric layers; forming first conductive lines surrounding a portion of the horizontal sheets between the intercell dielectric layers and the supports and horizontally oriented; forming protruding sheet nodes between the supports by cutting the protruding edges of the horizontal sheets; and ​ ​ ​ forming a horizontal arrangement of second conductive lines electrically coupled to the protruding tab nodes and oriented perpendicularly between the supports in a direction intersecting the first conductive lines.

12. The method of claim 11, further comprising: prior to forming second conductive lines, forming a vertical arrangement of first contact nodes overlying the protruding tab nodes; forming a contact isolation layer exposing outer surfaces of the first contact nodes between the vertical arrangement of first contact nodes; and forming an ohmic contact layer overlying the outer surfaces of the first contact nodes.

13. The method of claim 12, wherein, forming the vertical arrangement of first contact nodes includes depositing and etching doped polysilicon.

14. The method of claim 12, wherein each of the ohmic contact layers comprises a metal silicide.

15. The method of claim 11, wherein, replacing the one side edge of the sacrificial isolation layer with the supports includes: forming linear openings exposing one side edge of the mold layers in the vertical stack and the one side edge of the sacrificial isolation layer; recessing a portion of the sacrificial isolation layer from the linear openings to form support openings between the one side edge of the mold layers in the vertical stack; and forming a support material filling the support openings.

16. The method of claim 11, wherein, the supports and the sacrificial isolation layer comprise different materials.

17. The method of claim 11, wherein, replacing the sacrificial isolation layer with the intercell dielectric layer includes: lifting off the sacrificial isolation layer using the supports as a barrier to form interbody tab openings exposing the body tabs and interhorizontal tab openings exposing the horizontal tabs; and forming the intercell dielectric layer filling the interbody tab openings.

18. The method of claim 11, further comprising forming first spacers around a tapered profile prior to forming the first conductive lines, wherein the tapered profile is disposed between the horizontal tabs and the body tabs.

19. The method of claim 11, wherein, forming the protruding tab nodes includes: forming second spacers exposing the protruding edges and around a portion of the horizontal tabs; cutting the protruding edges; and recessing the second spacers horizontally to form the protruding tab nodes.

20. The method of claim 11, further comprising: after forming the second conductive lines, forming tapered tabs by recessing the body tabs horizontally; forming second contact nodes on the tapered tabs; and forming data storage elements on the second contact nodes.

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