Semiconductor packaging structure, preparation method thereof and storage system

Abstract

The invention discloses a semiconductor packaging structure, a preparation method thereof and a storage system. The semiconductor packaging structure comprises a stacking structure which comprises a plurality of first chips which are sequentially stacked along a first direction, and the stacking structure is provided with a first surface and a second surface which are arranged back to back along the first direction; the plurality of first connecting structures extend from the second surface along the first direction and are respectively connected with different first chips; wherein the number of the first connection structures connected with different first chips is different, and / or the maximum sizes of the first connection structures connected with different first chips along a second direction are different, and the first direction intersects with the second direction.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a semiconductor package structure, a preparation method thereof, and a storage system. BACKGROUND

[0002] With the continuous development of integrated circuit (IC) level, 2D-IC has been unable to meet the requirements of miniaturization, high density and low power consumption, and 3D-IC has emerged. HBM (High Bandwidth Memory) is a representative semiconductor package structure in 3D-IC, which usually includes a plurality of DRAM chips (Dynamic Random Access Memory Die) and a logic chip (Logic Die). The plurality of DRAM chips are stacked on one side of the logic chip, and the DRAM chips are interconnected with the logic chip through a TSV (Trough-Silicon Via) structure.

[0003] At present, how to improve the signal transmission speed of the semiconductor package structure is one of the technical problems to be solved by those skilled in the art. SUMMARY

[0004] The semiconductor package structure, the preparation method thereof, and the storage system provided by the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in related art or other deficiencies in related art.

[0005] According to the semiconductor package structure provided by the first aspect of the present application, the semiconductor package structure comprises:

[0006] a stack structure comprising a plurality of first chips stacked in a first direction, the stack structure having a first surface and a second surface arranged back to each other along the first direction; and

[0007] a plurality of first connection structures each extending from the second surface along the first direction and connected to different first chips, respectively.

[0008] wherein the number of the first connection structures connected to different first chips is different, and / or the maximum dimension of the first connection structures connected to different first chips along a second direction is different, the first direction intersecting the second direction.

[0009] According to the preparation method of the semiconductor package structure provided by the second aspect of the present application, the preparation method comprises:

[0010] form a stack structure including a plurality of first chips stacked in a first direction in sequence, the stack structure having a first surface and a second surface oppositely arranged along the first direction;

[0011] form a plurality of first connection holes each extending along the first direction from the second surface; and

[0012] form a first connection structure in each of the first connection holes, the first connection structure being connected to a different one of the first chips;

[0013] wherein the number of the first connection structures connected to different ones of the first chips is different, and / or the maximum dimension of the first connection structures connected to different ones of the first chips along a second direction is different, the first direction intersecting the second direction.

[0014] According to a third aspect of the present application, a storage system is provided, including a controller and the semiconductor package structure according to the first aspect of the present application, the controller being coupled to the semiconductor package structure and configured to control the semiconductor package structure to store data.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become more readily apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0016] Other features, objects, and advantages of the present application will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. The drawings are not intended to limit the scope of the application. In the drawings:

[0017] Figure 1 is a cross-sectional view of an HBM according to an embodiment of the present application;

[0018] Figures 2 to 11 is a process flow diagram of a method for manufacturing a semiconductor package structure according to an embodiment of the present application;

[0019] Figure 12 is a cross-sectional view of a semiconductor package structure according to an embodiment of the present application;

[0020] Figure 13 is a cross-sectional view of a semiconductor package structure according to another embodiment of the present application;

[0021] Figure 14 is a process flow diagram of a method for manufacturing a semiconductor package structure according to an embodiment of the present application; and

[0022] is a process flow diagram of a method for manufacturing a semiconductor package structure according to an embodiment of the present application; andFigure 15 is a block diagram of a system having a semiconductor package structure according to one embodiment of the present application.

[0023] Reference Signs:

[0024] 100, stacked structure; 101, first surface; 102, second surface;

[0025] 103, first connection hole; 110, first chip; 111, DRAM chip;

[0026] 111-1, first DRAM chip; 111-2, second DRAM chip;

[0027] 111-3, third DRAM chip; 111-4, fourth DRAM chip;

[0028] 120, first connection structure; 121, first conductive structure; 122, first isolation layer;

[0029] 123, first aperture; 130, first bonding layer; 131, first dielectric layer;

[0030] 132, first bonding contact; 200, second chip; 201, logic chip;

[0031] 210, second connection structure; 211, second conductive structure; 212, second isolation layer;

[0032] 220, second bonding layer; 221, second dielectric layer; 222, second bonding contact;

[0033] 230, third bonding layer; 231, third dielectric layer; 232, third bonding contact;

[0034] 300, substrate; 310, fourth bonding layer; 311, fourth dielectric layer;

[0035] 312, fourth bonding contact; 400, solder ball; 500, TSV structure;

[0036] 501, first TSV structure; 502, second TSV structure;

[0037] 503, third TSV structure; 600, system; 601, memory system;

[0038] 602, semiconductor package structure; 603, memory controller; 604, host. DETAILED DESCRIPTION

[0039] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It is to be noted that the detailed description is merely descriptive of exemplary embodiments of the present application and is not intended, in any way, to limit the scope of the present application. Throughout the specification, like drawing reference numerals refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It should be noted that the expressions first, second, third and the like in this description merely serve to distinguish one feature from another feature, and do not indicate any limitation on the features, in particular do not indicate any chronological order.

[0041] In the drawings, the thicknesses of components, sizes, and shapes are slightly adjusted for the convenience of explanation. The drawings are merely examples and are not strictly drawn to scale. As used in this document, the words "substantially", "approximately", and similar expressions are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring or calculating value that would be recognized by those of ordinary skill in the art.

[0042] It should also be understood that expressions such as "include", "including", "have", "has", "contain" and / or "containing" and the like, are open-ended expressions that are used to specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of" appear after a list of two or more items, it is meant that any of the listed items can be present, individually or in combination with one or more of the other listed items. Furthermore, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". Also, the word "exemplary" is intended to mean an example or an illustration.

[0043] Unless otherwise defined, all terms used in this document including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that the words "comprise", "comprising", "comprises", "including", "include", "includes" and / or the like are used herein to specify the presence of stated features, elements, and / or components but do not preclude the presence or addition of one or more other features, elements, components and / or combinations thereof.

[0044] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. In addition, unless explicitly limited or contrary to the context, the specific steps in the methods described in the present application can not be limited to the order described and can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0045] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0046] like Figure 1 As shown, an HBM (High Bandwidth Memory) typically includes a substrate 300, a logic die 201, and multiple DRAM chips 111 (Dynamic Random Access Memory Dies). The logic die 201 is located on one side of the substrate 300. Multiple DRAM chips 111 are stacked sequentially along a first direction (z-direction) on the side of the logic die 201 away from the substrate 300. A TSV (Trough-Silicon Via) structure is formed in the DRAM chip 111 closest to the logic die 201 among two adjacent DRAM chips 111. Two adjacent TSV structures 500 are connected by solder balls 400. Thus, the DRAM chip 111 can be connected to the logic die 201 through at least one TSV structure 500 and / or solder balls 400.

[0047] by Figure 1As shown in the HBM, four DRAM chips 111 are stacked in the first direction (z direction) on one side of the logic chip 201. For ease of description, the four DRAM chips 111 can be referred to in order as a first DRAM chip 111-1, a second DRAM chip 111-2, a third DRAM chip 111-3, and a fourth DRAM chip 111-4 in a direction away from the logic chip 201. Among them, the first TSV structure 501 is formed in the first DRAM chip 111-1 and penetrates the first DRAM chip 111-1 in the first direction (z direction), the second TSV structure 502 is formed in the second DRAM chip 111-2 and penetrates the second DRAM chip 111-2 in the first direction (z direction), and the third TSV structure 503 is formed in the third DRAM chip 111-3 and penetrates the third DRAM chip 111-3 in the first direction (z direction). Among them, the fourth DRAM chip 111-4 is connected to the logic chip 201 through the third TSV structure 503, the second TSV structure 502, the first TSV structure 501, and the plurality of solder balls 400, the third DRAM chip 111-3 is connected to the logic chip 201 through the second TSV structure 502, the first TSV structure 501, and the plurality of solder balls 400, the second DRAM chip 111-2 is connected to the logic chip 201 through the first TSV structure 501 and the plurality of solder balls 400, and the first DRAM chip 111-1 does not need to pass through the TSV structure 500 and can be directly connected to the logic chip 201 through the solder ball 400. It can be seen that the farther the DRAM chip 111 is from the logic chip 201 in the first direction, the longer the signal transmission path between the DRAM chip 111 and the logic chip 201, the longer the length of the TSV structure 500 required between the DRAM chip 111 and the logic chip 201 in the first direction (z direction), the greater the resistance, and the slower the signal transmission speed.

[0048] Based on this, in order to solve at least part of the above problems, the embodiments of the present application provide a semiconductor packaging structure. Figure 5 A cross-sectional view of a semiconductor packaging structure according to an embodiment of the present application is shown. As shown in the figure, Figure 5 The semiconductor packaging structure includes a stack structure 100 and a plurality of first connection structures 120. The stack structure 100 has a first surface 101 and a second surface 102 arranged opposite to each other in a first direction (z direction), and the first connection structures 120 extend from the second surface 102 of the stack structure 100 to the stack structure 100 in the first direction (z direction).

[0049] The stack structure 100 comprises a plurality of first chips 110 stacked in sequence along a first direction (z direction), and a plurality of first connection structures 120 each extending from the second surface 102 of the stack structure 100 along the first direction (z direction) and connected with a different first chip 110. The number of the first connection structures 120 connected with different first chips 110 is different, and / or the maximum dimension of the first connection structures 120 connected with different first chips 110 along a second direction (x direction) is different, the first direction intersecting the second direction.

[0050] It should be noted that the above "the first direction intersects the second direction" can be generally understood as having an included angle between the first direction and the second direction, for example, the first direction and the second direction are perpendicular or approximately perpendicular to each other. As an example, as shown in Figure 5 the first direction in the embodiments of the present application can be the thickness direction of the first chip 110, i.e. the z direction, and the second direction can be the width or length direction of the first chip 110, i.e. the x direction or the y direction. In addition, the semiconductor package structure provided by the embodiments of the present application can be a memory or a part of a memory.

[0051] Thus, as shown in Figures 11 to 13 if the stack structure 100 is subsequently connected with other structures such as logic chips or substrates 300, then the number of the first connection structures 120 connected with different first chips 110 and / or the maximum dimension of the first connection structures 120 along the second direction (x direction) can be set according to the distance of each first chip 110 from the other structures, so that the number of the first connection structures 120 connected with different first chips 110 is different, and / or the maximum dimension of the first connection structures 120 connected with different first chips 110 along the second direction (x direction) is different. Since the number of the first connection structures 120 connected with the same first chip 110 and / or the maximum dimension of the first connection structures 120 along the second direction (x direction) will affect the equivalent resistance of all the first connection structures 120 connected with the first chip 110, the present application can compensate for the resistance difference between different first connection structures 120 caused by the different distances of the first chips 110 from other structures such as logic chips or substrates 300 (i.e. different extension lengths of the first connection structures 120 along the first direction (z direction)) by making the number of the first connection structures 120 connected with different first chips 110 and / or the maximum dimension along the second direction (x direction) different, so as to improve the signal transmission speed of the first connection structures 120 connected with the first chips 110 farther away.

[0052] As an example, as shown in Figure 12As shown, the number of first connecting structures 120 connected with one of the two adjacent first chips 110 is greater than the number of first connecting structures 120 connected with the other first chip 110; for example, Figure 11 As shown, the maximum dimension of the first connecting structures 120 connected with one of the two adjacent first chips 110 along the second direction (x direction) is greater than the maximum dimension of the first connecting structures 120 connected with the other first chip 110 along the second direction (x direction); for example, Figure 13 As shown, the number of first connecting structures 120 connected with one of the two adjacent first chips 110 is greater than the number of first connecting structures 120 connected with the other first chip 110, and the maximum dimension of the first connecting structures 120 connected with one of the two adjacent first chips 110 along the second direction (x direction) is greater than the maximum dimension of the first connecting structures 120 connected with the other first chip 110 along the second direction (x direction). The one of the two adjacent first chips 110 is located on the side of the other first chip 110 along the direction from the second surface 102 to the first surface 101.

[0053] For the convenience of description, one of the two adjacent first chips 110 will be referred to as a first stacked chip, and the other will be referred to as a second stacked chip, with the first stacked chip being located on the side of the second stacked chip along the direction from the second surface 102 to the first surface 101. It should be noted that the first stacked chip and the second stacked chip are introduced in this application only for the convenience of distinguishing the relative positions of the two adjacent first chips 110 along the first direction (z direction), and the first stacked chip or the second stacked chip does not specifically refer to a certain first chip 110. For example, Figure 5 As shown in the semiconductor package structure, the stacking structure 100 of the semiconductor package structure includes four first chips 110, and the upper surface of the stacking structure 100 is the first surface 101, and the lower surface of the stacking structure 100 is the second surface 102. For the two uppermost first chips 110, i.e., the first chip 110 located at the fourth layer and the first chip 110 located at the third layer, the first chip 110 located at the fourth layer can be referred to as the first stacked chip, and the first chip 110 located at the third layer can be referred to as the second stacked chip. For the two middle first chips 110, i.e., the first chip 110 located at the third layer and the first chip 110 located at the second layer, the first chip 110 located at the third layer can be referred to as the first stacked chip, and the first chip 110 located at the second layer can be referred to as the second stacked chip.

[0054] As described above, the first stacked chip is located on one side of the second stacked chip along the direction from the second surface 102 to the first surface 101 of the stacked structure 100. In other words, the first stacked chip is farther away from other structures such as logic chips or substrate 300 compared to the second stacked chip. Therefore, the extension length of the first connection structure 120 connected to the first stacked chip along the first direction (z direction) is greater than the extension length of the first connection structure 120 connected to the second stacked chip along the first direction (z direction). The longer the extension length of the first connection structure 120 along the first direction (z direction), the greater its resistance and the slower the signal transmission speed. Figure 12 As shown, in some embodiments, in order to improve the overall signal transmission speed of the first connection structure 120 connected to the first stacked chip, the number of first connection structures 120 connected to the first stacked chip is greater than the number of first connection structures 120 connected to the second stacked chip. For multiple first connection structures 120 connected to the same first chip 110, one end of each of these first connection structures 120 is connected to the first chip 110, and the other end extends along the first direction (z direction) and penetrates the second surface 102 of the stacked structure 100 and is connected to other structures such as logic chips or substrate 300. Thus, the multiple first connection structures 120 connected to the same first chip 110 are connected in parallel. As the number of parallel first connection structures 120 increases, the overall equivalent resistance of these first connection structures 120 decreases. Based on this, the embodiments of this application increase the number of first connection structures 120 connected to the first stacked chip, making the number of first connection structures 120 connected to the first stacked chip greater than the number of first connection structures 120 connected to the second stacked chip. This not only increases the signal transmission width but also reduces the overall equivalent resistance of all the first connection structures 120 connected to the first stacked chip, thereby increasing the overall signal transmission speed of the first connection structures 120 connected to the first stacked chip. This makes the signal transmission speed between the first stacked chip and a logic chip, and the transmission speed between the second stacked chip and a logic chip, approximately the same.

[0055] like Figure 11As shown, in some other embodiments, in order to improve the overall signal transmission speed of the first connection structure 120 connected to the first stacked chip, the maximum dimension of the first connection structure 120 connected to the first stacked chip along the second direction (x direction) is greater than the maximum dimension of the first connection structure 120 connected to the second stacked chip along the second direction (x direction). Since the resistance of the first connection structure 120 is inversely proportional to its dimension along the second direction (x direction), the embodiments of this application can reduce the resistance of the first connection structure 120 connected to the first stacked chip by increasing the maximum dimension of the first connection structure 120 connected to the first stacked chip along the second direction (x direction), thereby improving the overall signal transmission speed of the first connection structure 120 connected to the first stacked chip, so that the signal transmission speed between the first stacked chip and such as the logic chip 201, and the transmission speed between the second stacked chip and such as the logic chip 201 are approximately the same. It should be noted that the dimensions of the first connection structure 120 along the first direction (z direction) and the second direction (x direction) can be the same. In this case, the maximum dimension of the first connection structure 120 along the second direction (x direction) is its average dimension along the second direction (x direction). However, due to limitations of current etching processes, the dimensions of the first connecting structure 120 in the second direction (x-direction) may gradually decrease from the second surface 102 of the stacked structure 100 to its first surface 101. In this case, the maximum dimension of the first connecting structure 120 in the second direction (x-direction) is greater than its average dimension in the second direction (x-direction).

[0056] like Figure 13 As shown, in some other embodiments, the number of first connection structures 120 connected to the first stacked chip and their dimensions along the second direction (x direction) can be increased simultaneously, such that the number of first connection structures 120 connected to the first stacked chip is greater than the number of first connection structures 120 connected to the second stacked chip, and at the same time, the maximum dimension of the first connection structure 120 connected to the first stacked chip along the second direction (x direction) is greater than the maximum dimension of the first connection structure 120 connected to the second stacked chip along the second direction (x direction).

[0057] As mentioned above, Figure 1 Two adjacent TSV structures 500 are connected by solder balls 400. However, due to limitations in the solder ball 400 forming process, the solder ball 400 has a relatively large dimension along the first direction (z-direction). Furthermore, the area around the solder ball 400, i.e., between two adjacent DRAM chips 111, is filled with dielectric material. This not only increases the spacing between the two adjacent TSV structures 500, thereby increasing the resistance between them and reducing signal transmission speed, but also increases the thickness of the entire semiconductor package structure along the first direction (z-direction). Therefore, as... Figure 2As shown, in order to reduce the thickness of the whole semiconductor package structure along the first direction (z direction) and further improve the signal transmission speed, two adjacent first chips 110 are bonded in the embodiments of the present application. The two adjacent first chips 110 can be bonded by direct bonding or adhesive bonding, but are not limited thereto.

[0058] In some embodiments, as shown in Figure 5 As shown, the first connecting structure 120 includes a first conductive structure 121 and a first isolation layer 122. The first conductive structure 121 extends along the first direction (z direction) from the second surface 102 of the stack structure 100 and is connected to the corresponding first chip 110. The first isolation layer 122 covers the sidewall of the first conductive structure 121 extending along the first direction (z direction). The material of the first conductive structure 121 can include at least one of a metal such as tungsten, copper, gold, aluminum, chromium, tin, nickel, titanium, zinc, a metal alloy such as a tin-lead alloy, and a metal silicide, but is not limited thereto. The material of the first isolation layer 122 can include silicon oxide, silicon oxynitride, or silicon nitride, but is not limited thereto. It should be noted that one end of the first connecting structure 120 penetrates the second surface 102 of the stack structure 100, and the other end can extend to the surface of the corresponding first chip 110 or extend to the inside of the corresponding first chip 110. As an example, as shown in Figure 5 As shown, the plurality of first connecting structures 120 respectively extend into different first chips 110 along the first direction (z direction).

[0059] In some embodiments, as shown in Figure 6 and Figure 8 As shown, the semiconductor package structure can further include a second chip 200 and a plurality of second connecting structures 210. The second chip 200 is located on one side of the stack structure 100 along the direction from the first surface 101 to the second surface 102 of the stack structure 100. The second connecting structure 210 penetrates the second chip 200 along the first direction (z direction). The plurality of second connecting structures 210 are respectively connected to different first connecting structures 120. As an example, as shown in Figure 7 As shown, the second connecting structure 210 includes a second conductive structure 211 and a second isolation layer 212. The second conductive structure 211 penetrates the second chip 200 along the first direction (z direction). The second isolation layer 212 covers the sidewall of the second conductive structure 211 extending along the first direction (z direction). The material of the second conductive structure 211 can include at least one of a metal, a metal alloy, and a metal silicide, but is not limited thereto. The material of the second isolation layer 212 can include silicon oxide, silicon oxynitride, or silicon nitride, but is not limited thereto.

[0060] It should be noted that the multiple first chips 110 can be of the same or different types. The first chip 110 may include a memory chip and / or peripheral circuitry. The memory chip is mainly used for storing data and can be a non-volatile chip such as a NAND chip, a PROM (Programmable Read-Only memory) chip, or a NOR chip, or a volatile chip such as a DRAM (Dynamic Random Access Memory) chip or an SRAM (Static Random-Access Memory) chip. The peripheral circuitry may include, but is not limited to, at least one of high-voltage devices, low-voltage devices, and ultra-low-voltage devices. High-voltage devices may include, but are not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver; low-voltage devices may include, but are not limited to, page buffers or logic devices; and ultra-low-voltage devices may include, but are not limited to, I / O circuitry. The second chip 200 may include a logic chip, which is mainly used for digital logic operations and performs tasks such as logic control, decision specification and signal processing. The logic chip may include at least one of a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a security chip, an interface chip or a memory control chip.

[0061] In some embodiments, such as Figure 12 As shown, the number of first connection structures 120 connected to different first chips 110 gradually increases, and among two adjacent first chips 110, the number of first connection structures 120 connected to the first chip 110 farther from the second chip 200 is greater than the number of first connection structures 120 connected to the first chip 110 closer to the second chip 200. Figure 12As shown in the semiconductor package structure, the stack structure 100 includes four first chips 110 and ten first connection structures 120, one of which is connected with the lowermost first chip 110, i.e., the first chip 110 on the first layer, two of which are connected with the first chips 110 on the second layer, three of which are connected with the first chips 110 on the third layer, and four of which are connected with the uppermost first chip 110, i.e., the first chip 110 on the fourth layer. Similarly, the first connection structures 120 connected with different first chips 110 gradually increase in size along the second direction (x direction), and the maximum size of the first connection structure 120 connected with the first chip 110 away from the second chip 200 along the second direction (x direction) is greater than that of the first connection structure 120 connected with the first chip 110 close to the second chip 200 along the second direction (x direction) in the adjacent two first chips 110.

[0062] In some embodiments, as shown in the stack structure 100 of the present application, the first bonding layer 130 is arranged on the side of the stack structure 100 facing the second chip 200, and the second bonding layer 220 is arranged on the side of the second chip 200 facing the stack structure 100. The first bonding layer 130 is connected with the first connection structure 120, the second bonding layer 220 is connected with the second connection structure 210, and the first bonding layer 130 is combined with the second bonding layer 220. Figures 6 to 8 Figure 5 and Figure 6 As shown in the stack structure 100 of the present application, the first bonding layer 130 can be formed on the second surface 102 of the stack structure 100 after the stack structure 100 is formed. As shown in the second chip 200 of the present application, Figure 7 As shown in the second chip 200 of the present application, the second bonding layer 220 can be formed on the side of the second chip 200 after the second chip 200 is formed. Then, as shown in the stack structure 100 of the present application, Figure 8 The first bonding layer 130 and / or the second bonding layer 220 can be a single-layer structure or a multi-layer structure, and the structures of the two can be the same or different, which is not limited in the present application.

[0063] As an example, the second chip 200 is bonded to the stack structure 100. The second chip 200 and the stack structure 100 can be bonded by direct bonding, adhesive bonding, hybrid bonding, etc., but are not limited thereto. For example, the second chip 200 and the stack structure 100 are hybrid bonded, and the first bonding layer 130 and the second bonding layer 220 are both bonding layers. As shown in the stack structure 100 of the present application, Figure 6 ​As shown, the first bonding layer 130 can include a first dielectric layer 131 and a plurality of first bonding contacts 132, the first bonding contacts 132 penetrating the first dielectric layer 131 along a first direction (z direction), and the plurality of first bonding contacts 132 are respectively connected with different first connection structures 120. As an example, the first bonding contacts 132 and the first connection structures 120 can be one-to-one correspondence, in other words, the number of the first bonding contacts 132 is the same as the number of the first connection structures 120, one end of the first bonding contacts 132 is in contact with the corresponding first connection structure, and the other end penetrates the first dielectric layer 131 along the first direction (z direction). Wherein, the material of the first bonding contacts 132 can include but is not limited to at least one of metal, metal alloy and metal silicide. As shown, Figure 7 As shown, the second bonding layer 220 can include a second dielectric layer 221 and a plurality of second bonding contacts 222, the second bonding contacts 222 penetrating the second dielectric layer 221 along a first direction (z direction), and the plurality of second bonding contacts 222 are respectively connected with different second connection structures 210. As an example, the second bonding contacts 222 and the second connection structures 210 can be one-to-one correspondence, one end of the second bonding contacts 222 is in contact with the corresponding second connection structure, and the other end penetrates the second dielectric layer 221 along the first direction (z direction). Wherein, the material of the second bonding contacts 222 can include but is not limited to at least one of metal, metal alloy and metal silicide. As shown, Figures 6 to 8 As shown, the first bonding layer 130 is bonded with the second bonding layer 220, the first dielectric layer 131 and the second dielectric layer 221 are at least partially in contact, and the plurality of first bonding contacts 132 are respectively in contact with different second bonding contacts 222. In addition, taking the first bonding contacts 132 as an example, when the first bonding contacts 132 are contacts including metal elements, in order to avoid the diffusion of metal particles of the first bonding contacts 132 to the stacked structure 100, i.e., the first chip 110, the first bonding layer 130 can further include a first barrier layer (not shown), the first barrier layer is located between the first dielectric layer 131 and the stacked structure 100, and the first bonding contacts 132 penetrate the first dielectric layer 131 and the first barrier layer along the first direction (z direction) in sequence. Similarly, the second bonding layer 220 can further include a second barrier layer (not shown), the second barrier layer is located between the second dielectric layer 221 and the second chip 200, and the second bonding contacts 222 penetrate the second dielectric layer 221 and the second barrier layer along the first direction (z direction) in sequence. Wherein, the material of the first barrier layer and the second barrier layer can include but is not limited to silicon nitride and / or doped silicon nitride.

[0064] In some embodiments, as shown, Figure 10 As shown, the semiconductor package structure can further include a substrate 300, the substrate 300 is located on the side of the second chip 200 away from the stacked structure 100, and the substrate 300 is connected with the second connection structure 210. As shown, Figures 8 to 10As shown, the second chip 200 is provided with a third bonding layer 230 on a side away from the stack structure 100, the substrate 300 is provided with a fourth bonding layer 310 on a side facing the second chip 200, the third bonding layer 230 is connected with the second connection structure 210, the fourth bonding layer 310 is connected with the substrate 300, and the third bonding layer 230 is bonded with the fourth bonding layer 310. For example, as shown in FIG. 2B, the third bonding layer 230 is formed on the side of the second chip 200 after the second chip 200 is formed. Figure 7 As shown, the third bonding layer 230 can be formed on a side of the second chip 200 after the second chip 200 is formed. In addition, as shown in FIG. 2C, the fourth bonding layer 310 can be formed on a side of the substrate 300. Then, as shown in FIG. 2D, the third bonding layer 230 and the fourth bonding layer 310 are bonded together. Figure 9 As shown, the third bonding layer 230 can be formed on a side of the second chip 200 after the second chip 200 is formed. In addition, as shown in FIG. 2C, the fourth bonding layer 310 can be formed on a side of the substrate 300. Then, as shown in FIG. 2D, the third bonding layer 230 and the fourth bonding layer 310 are bonded together. Figure 10 As shown, the third bonding layer 230 can be formed on a side of the second chip 200 after the second chip 200 is formed. In addition, as shown in FIG. 2C, the fourth bonding layer 310 can be formed on a side of the substrate 300. Then, as shown in FIG. 2D, the third bonding layer 230 and the fourth bonding layer 310 are bonded together. The third bonding layer 230 and / or the fourth bonding layer 310 can be a single-layer structure or a multi-layer structure, and the structures of the two can be the same or different, which is not limited in the present application. In the case where the semiconductor package structure includes the second bonding layer 220 and the third bonding layer 230, the second bonding layer 220 and the third bonding layer 230 are respectively located on two sides of the second chip 200 along the first direction (z direction). The second bonding layer 220 can be formed on one side of the second chip 200 first, and then the third bonding layer 230 can be formed on the other side of the second chip 200. Alternatively, the third bonding layer 230 can be formed on one side of the second chip 200 first, and then the second bonding layer 220 can be formed on the other side of the second chip 200, which is not limited in the present application.

[0065] As an example, the second chip 200 is bonded with the substrate 300. The second chip 200 and the substrate 300 can be bonded by direct bonding, adhesive bonding, hybrid bonding, etc., but are not limited thereto. For example, the second chip 200 and the substrate 300 are hybrid bonded, and the third bonding layer 230 and the fourth bonding layer 310 are both bonding layers. As shown in FIG. 2E, the third bonding layer 230 includes a third dielectric layer 231 and a plurality of third bonding contacts 232, the third bonding contacts 232 penetrate the third dielectric layer 231 along the first direction (z direction), and the plurality of third bonding contacts 232 are respectively connected with different second connection structures 210. Figure 7 As an example, the second chip 200 is bonded with the substrate 300. The second chip 200 and the substrate 300 can be bonded by direct bonding, adhesive bonding, hybrid bonding, etc., but are not limited thereto. For example, the second chip 200 and the substrate 300 are hybrid bonded, and the third bonding layer 230 and the fourth bonding layer 310 are both bonding layers. As shown in FIG. 2E, the third bonding layer 230 includes a third dielectric layer 231 and a plurality of third bonding contacts 232, the third bonding contacts 232 penetrate the third dielectric layer 231 along the first direction (z direction), and the plurality of third bonding contacts 232 are respectively connected with different second connection structures 210. Figure 9As shown, the fourth bonding layer 310 can include a fourth dielectric layer 311 and a plurality of fourth bonding contacts 312, the fourth bonding contacts 312 penetrating the fourth dielectric layer 311 along the first direction (z direction) and connecting with the substrate 300. The material of the third bonding contacts 232 and / or the fourth bonding contacts 312 can include, but is not limited to, at least one of a metal, a metal alloy, and a metal silicide. Figures 8 to 10 As shown, the third bonding layer 230 is bonded with the fourth bonding layer 310, the third dielectric layer 231 at least partially contacts the fourth dielectric layer 311, and the plurality of third bonding contacts 232 respectively contacts different fourth bonding contacts 312. In addition, taking the third bonding contacts 232 as an example, when the third bonding contacts 232 are contacts including metal elements, in order to avoid the diffusion of metal particles of the third bonding contacts 232 to the second chip 200, the third bonding layer 230 can further include a third barrier layer (not shown), the third barrier layer is located between the third dielectric layer 231 and the second chip 200, and the third bonding contacts 232 penetrate the third dielectric layer 231 and the third barrier layer along the first direction (z direction) in sequence and connect with the corresponding second connection structure 210. Similarly, the fourth bonding layer 310 can further include a fourth barrier layer (not shown), the fourth barrier layer is located between the fourth dielectric layer 311 and the substrate 300, and the fourth bonding contacts 312 penetrate the fourth dielectric layer 311 and the fourth barrier layer along the first direction (z direction) in sequence and connect with the substrate 300. The material of the third barrier layer and the fourth barrier layer can include, but is not limited to, silicon nitride and / or doped silicon nitride.

[0066] In addition, as Figure 14 As shown, the application embodiment further provides a preparation method of a semiconductor packaging structure, the preparation method 1000 includes:

[0067] S100, a stacking structure 100 is formed, the stacking structure 100 includes a plurality of first chips 110 stacked along a first direction (z direction) in sequence, and the stacking structure 100 has a first surface 101 and a second surface 102 (see Figure 2 ) arranged oppositely along the first direction (z direction);

[0068] S200, a plurality of first connection holes 103 extending along the first direction (z direction) are formed from the second surface 102 of the stacking structure 100 (see Figure 3 ); wherein the plurality of first connection holes 103 can extend from the second surface 102 to the surface of different first chips 110, or extend from the first surface 101 to the inside of different first chips 110;

[0069] S300, a plurality of first connection structures 120 are formed in the first connection holes 103, and the plurality of first connection structures 120 are respectively connected with different first chips 110 (see Figure 5 ).

[0070] As shown in Figures 11 to 13 , the number of first connection structures 120 connected with different first chips 110 is different, and / or the maximum dimension of first connection structures 120 connected with different first chips 110 along the second direction (x direction) is different, the first direction intersects with the second direction.

[0071] If the stacked structure 100 is connected with other structures such as a logic chip 201 or a substrate 300 in the future, when the first connection hole 103 is formed, the number of first connection holes 103 corresponding to different first chips 110 and / or the maximum dimension of first connection holes 103 corresponding to different first chips 110 along the second direction (x direction) can be set according to the distance of each first chip 110 from other structures, so that the number of first connection structures 120 connected with different first chips 110 is different, and / or the maximum dimension of first connection structures 120 connected with different first chips 110 along the second direction (x direction) is different. Since the number of first connection structures 120 connected with the same first chip 110 and / or the maximum dimension of first connection structures 120 connected with the same first chip 110 along the second direction (x direction) will affect the equivalent resistance of all first connection structures 120 connected with the first chip 110 as a whole, the embodiments of the present application can compensate for the resistance difference between different first connection structures 120 caused by the different distances of different first chips 110 from other structures such as a logic chip 201 or a substrate 300, i.e. the different extension lengths of first connection structures 120 along the first direction (z direction), by making the number of first connection structures 120 connected with different first chips 110 and / or the maximum dimension of first connection structures 120 connected with different first chips 110 along the second direction (x direction) different, so that the signal transmission speed of first connection structures 120 connected with the first chip 110 far away can be improved.

[0072] In some embodiments, as shown in Figure 2 , the stacked structure 100 can be formed by sequentially bonding and connecting a plurality of first chips 110 along the first direction (z direction). Wherein, the adjacent two first chips 110 can be but not limited to bonded and connected by direct bonding or adhesive bonding and the like.

[0073] In some embodiments, as shown in Figure 5 , the first connection structure 120 includes a first insulating layer 122 and a first conductive structure 121, whereby the first connection structure 120 can be formed in the first connection hole 103 in the following manner: as shown in Figure 4 , the first insulating layer 122 is formed on the side wall of the first connection hole 103 extending along the first direction (z direction); wherein, the material of the first insulating layer 122 can include but is not limited to silicon oxide, silicon oxynitride or silicon nitride; as shown in Figure 4 and Figure 5As shown, the first conductive structure 121 is formed in the first aperture 123 formed by the first isolation layer 122; wherein the material of the first conductive structure 121 can include, but is not limited to, at least one of a metal such as tungsten, copper, gold, aluminum, chromium, tin, nickel, titanium, zinc, etc., a metal alloy such as a tin-lead alloy, etc., and a metal silicide. In the embodiments of the present application, the first isolation layer 122 and the first conductive structure 121 can be formed in the first connecting hole 103 by a thin film deposition process, which can include, but is not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes.

[0074] In some embodiments, the preparation method can further include: Figure 7 As shown, a plurality of second connecting structures 210 are formed in the second chip 200, the second connecting structures 210 penetrating the second chip 200 along the first direction (z direction); as shown in Figure 8 As shown, the second chip 200 is combined with the stacked structure 100. For example, as shown in Figure 5 and Figure 6 As shown, a first dielectric layer 131 is formed on the second surface 102 of the stacked structure 100; a plurality of first bonding contacts 132 are formed in the first dielectric layer 131, the first bonding contacts 132 penetrating the first dielectric layer 131 along the first direction (z direction), and the plurality of first bonding contacts 132 are respectively connected to different first connecting structures 120; as shown in Figure 7 As shown, a second dielectric layer 221 is formed on one side of the second chip 200; a plurality of second bonding contacts 222 are formed in the second dielectric layer 221, the second bonding contacts 222 penetrating the second dielectric layer 221 along the first direction (z direction), and the plurality of second bonding contacts 222 are respectively connected to different second connecting structures 210; as shown in Figure 8 As shown, the first dielectric layer 131 is combined with the second dielectric layer 221, and the plurality of first bonding contacts 132 are respectively in contact with different second bonding contacts 222. Thus, the second surface 102 of the stacked structure 100 faces the second chip 200, and the first connecting structure 120 is connected to the corresponding second connecting structure 210 through the corresponding first bonding contact 132 and second bonding contact 222 in sequence. The first dielectric layer 131 can be formed on one side of the stacked structure 100 by a thin film deposition process, and the second dielectric layer 221 can also be formed on one side of the second chip 200 by a thin film deposition process.

[0075] In some embodiments, as shown in Figure 10As shown, the preparation method can further include: combining the substrate 300 with the second chip 200. For example, as shown in FIG. 2B, the substrate 300 is combined with the second chip 200. Figure 7 As shown, a third dielectric layer 231 is formed on one side of the second chip 200; a plurality of third bonding contacts 232 are formed in the third dielectric layer 231, and each of the plurality of third bonding contacts 232 penetrates the third dielectric layer 231 along the first direction (z direction) and is connected with a different second connection structure 210; as shown in FIG. 2C, the third dielectric layer 231 is combined with the substrate 300. Figure 9 As shown, a fourth dielectric layer 311 is formed on one side of the substrate 300; a plurality of fourth bonding contacts 312 are formed in the fourth dielectric layer 311, and each of the plurality of fourth bonding contacts 312 penetrates the fourth dielectric layer 311 along the first direction (z direction) and is connected with the substrate 300; as shown in FIG. 2D, the fourth dielectric layer 311 is combined with the substrate 300. Figure 10 As shown, the third dielectric layer 231 is combined with the fourth dielectric layer 311, and each of the plurality of third bonding contacts 232 is in contact with a different fourth bonding contact 312. In this way, the substrate 300 and the stacked structure 100 are respectively located on two sides of the second chip 200 along the first direction (z direction), and the second connection structure 210 is connected with the substrate 300 through the corresponding third bonding contact 232 and fourth bonding contact 312 in sequence.

[0076] In addition, the application also provides a storage system, which includes a controller and the above semiconductor package structure, the controller is coupled to the semiconductor package structure and is used to control the semiconductor package structure to store data.

[0077] Figure 15 A block diagram of a system having a semiconductor package structure according to an embodiment of the application is shown. The system 600 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. As shown in FIG. 6, the system 600 can include a host 604 and a memory system 601 having one or more semiconductor package structures 602 and a memory controller 603. The host 604 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on a chip (SoC), such as an application processor (AP). The host 604 can be configured to send or receive data to or from the semiconductor package structure 602. Figure 15 As shown in FIG. 6, the system 600 can include a host 604 and a memory system 601 having one or more semiconductor package structures 602 and a memory controller 603. The host 604 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on a chip (SoC), such as an application processor (AP). The host 604 can be configured to send or receive data to or from the semiconductor package structure 602.

[0078] The semiconductor package structure 602 can be any semiconductor package structure disclosed in the application, such as the semiconductor package structure 100 shown in FIG. 2D. Figures 11 to 13A semiconductor package structure is shown. According to some embodiments, a memory controller 603 is coupled to the semiconductor package structure 602 and a host 604, and is configured to control the semiconductor package structure 602. The memory controller 603 can manage data stored in the semiconductor package structure 602, and communicate with the host 604.

[0079] In some embodiments, the memory controller 603 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 603 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 603 can be configured to control operations of the semiconductor package structure 602, such as read, erase, and program operations. The memory controller 603 can also be configured to manage various functions related to data stored in or to be stored into the semiconductor package structure 602, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 603 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor package structure 602. Any other appropriate functions can also be performed by the memory controller 603, for example, formatting the semiconductor package structure 602. The memory controller 603 can communicate with external devices (e.g., the host 604) according to a specific communication protocol. For example, the memory controller 603 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0080] It should be understood that the various forms of flow shown above can be reordered, steps added or removed. As an example, the steps recited in this disclosure can be performed in parallel, in series, in different orders, without limitation herein, so long as the desired results of the technology disclosed herein are achieved.

[0081] The above detailed description does not limit the scope of the application. Various modifications, combinations, sub-combinations and alternatives can occur to one skilled in the art without departing from the spirit and scope of the application. Any modification, equivalent replacement or improvement made within the spirit and principle of the application should be included within the scope of the application.

Claims

1. A semiconductor packaging structure, wherein, include: A stacked structure includes a plurality of first chips stacked sequentially along a first direction, the stacked structure having a first surface and a second surface disposed opposite to each other along the first direction; as well as Multiple first connection structures extend from the second surface along the first direction and are respectively connected to different first chips; The number of first connection structures connected to different first chips is different, and / or the maximum size of the first connection structures connected to different first chips along the second direction is different, where the first direction intersects the second direction.

2. The semiconductor packaging structure according to claim 1, wherein, One of two adjacent first chips is a first stacked chip, and the other is a second stacked chip. The first stacked chip is located on one side of the second stacked chip along the direction from the second surface to the first surface. Wherein, the number of first connection structures connected to the first stacked chip is greater than the number of first connection structures connected to the second stacked chip, and / or, the maximum dimension of the first connection structure connected to the first stacked chip along the second direction is greater than the maximum dimension of the first connection structure connected to the second stacked chip along the second direction.

3. The semiconductor packaging structure according to claim 1, wherein, The first connection structure includes: A first conductive structure extends from the second surface along the first direction and is connected to the corresponding first chip; and A first insulating layer covers the sidewall of the first conductive structure extending along the first direction.

4. The semiconductor packaging structure according to claim 1, wherein, Multiple first connection structures extend along the first direction into different first chips.

5. The semiconductor packaging structure according to claim 1, wherein, The two adjacent first chips are bonded together.

6. The semiconductor packaging structure according to any one of claims 1 to 5, wherein, The semiconductor packaging structure further includes: A second chip is located on one side of the stacked structure along a direction from the first surface to the second surface; and Multiple second connection structures penetrate the second chip along the first direction and are respectively connected to different first connection structures.

7. The semiconductor packaging structure according to claim 6, wherein, The semiconductor packaging structure further includes: A first bonding layer is located on the side of the stacked structure facing the second chip and is connected to the first connection structure; and The second bonding layer is located on the side of the second chip facing the stacked structure and is connected to the second connection structure; The first bonding layer is bonded to the second bonding layer.

8. The semiconductor packaging structure according to claim 7, wherein, The first bonding layer includes a first dielectric layer and a plurality of first bonding contacts, wherein the plurality of first bonding contacts penetrate the first dielectric layer along the first direction and are respectively connected to different first connection structures; The second bonding layer includes a second dielectric layer and a plurality of second bonding contacts. The plurality of second bonding contacts penetrate the second dielectric layer along the first direction and are respectively connected to different second connection structures. The plurality of first bonding contacts are respectively in contact with different second bonding contacts.

9. The semiconductor packaging structure according to claim 6, wherein, The first chip includes a memory chip and / or peripheral circuitry, and the second chip includes a logic chip.

10. The semiconductor packaging structure according to claim 6, wherein, The semiconductor packaging structure further includes: A substrate is located on the side of the second chip away from the stacked structure, and the substrate is connected to the second connection structure.

11. The semiconductor packaging structure according to claim 10, wherein, The semiconductor packaging structure further includes: A third bonding layer is located on the side of the second chip away from the stacked structure and is connected to the second connection structure; and A fourth bonding layer is located on the side of the substrate facing the second chip and is connected to the substrate; The third bonding layer is bonded to the fourth bonding layer.

12. The semiconductor packaging structure according to claim 11, wherein, The third bonding layer includes a third dielectric layer and a plurality of third bonding contacts, wherein the plurality of third bonding contacts penetrate the third dielectric layer along the first direction and are respectively connected to different second connection structures; The fourth bonding layer includes a fourth dielectric layer and a plurality of fourth bonding contacts. The plurality of fourth bonding contacts penetrate the fourth dielectric layer along the first direction and are connected to the substrate. The plurality of third bonding contacts are in contact with different fourth bonding contacts.

13. A method for fabricating a semiconductor packaging structure, characterized in that, include: A stacked structure is formed, the stacked structure comprising a plurality of first chips stacked sequentially along a first direction, the stacked structure having a first surface and a second surface disposed opposite to each other along the first direction; From the second surface, a plurality of first connection holes are formed, all extending along the first direction; as well as A first connection structure is formed in the first connection hole, and multiple first connection structures are respectively connected to different first chips; The number of first connection structures connected to different first chips is different, and / or the maximum size of the first connection structures connected to different first chips along the second direction is different, where the first direction intersects the second direction.

14. The method for fabricating a semiconductor packaging structure according to claim 13, wherein, The formation of the stacked structure includes: Multiple first chips are sequentially bonded together along the first direction.

15. The method for fabricating a semiconductor packaging structure according to claim 13, wherein, Forming a first connection structure within the first connection hole includes: A first isolation layer is formed on the sidewall of the first connection hole extending along the first direction; and A first conductive structure is formed within the first pore formed by the first isolation layer; The first connection structure includes the first isolation layer and the first conductive structure.

16. The method for fabricating a semiconductor packaging structure according to claim 13, wherein, The plurality of first connection holes extend along the first direction into different first chips.

17. The method for fabricating a semiconductor packaging structure according to any one of claims 13 to 16, wherein, The preparation method further includes: A plurality of second connection structures are formed in the second chip, and the second connection structures penetrate the second chip along the first direction; and The second chip is combined with the stacked structure, the second surface of the stacked structure faces the second chip, and a plurality of second connection structures are respectively connected to different first connection structures.

18. The method for fabricating a semiconductor packaging structure according to claim 17, wherein, Combining the second chip with the stacked structure includes: A first dielectric layer is formed on the second surface of the stacked structure; Multiple first bonding contacts are formed in the first dielectric layer, and each of the multiple first bonding contacts penetrates the first dielectric layer along the first direction and is respectively connected to different first connection structures. A second dielectric layer is formed on one side of the second chip; A plurality of second bonding contacts are formed in the second dielectric layer, each of the plurality of second bonding contacts penetrating the second dielectric layer along the first direction and respectively connected to different second connection structures; and The first dielectric layer is bonded to the second dielectric layer, and multiple first bonding contacts are respectively in contact with different second bonding contacts.

19. The method for fabricating a semiconductor packaging structure according to claim 17, wherein, The preparation method further includes: The substrate is combined with the second chip, and the substrate and the stacked structure are respectively located on both sides of the second chip along the first direction.

20. The method for preparing a semiconductor packaging structure according to claim 19, wherein, Combining the substrate with the second chip includes: A third dielectric layer is formed on one side of the second chip; A plurality of third bonding contacts are formed in the third dielectric layer, and each of the plurality of third bonding contacts penetrates the third dielectric layer along the first direction and is respectively connected to different second connection structures; A fourth dielectric layer is formed on one side of the substrate; A plurality of fourth bonding contacts are present in the fourth dielectric layer, each of the plurality of fourth bonding contacts penetrating the fourth dielectric layer along the first direction and connected to the substrate; and The third dielectric layer is combined with the fourth dielectric layer, and the plurality of third bonding contacts respectively contact different fourth bonding contacts.

21. A storage system, wherein, The storage system includes a controller and a semiconductor package structure according to any one of claims 1 to 12, wherein the controller is coupled to the semiconductor package structure and is used to control the semiconductor package structure to store data.

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