Transistor, preparation method thereof and field effect transistor

Abstract

The invention belongs to the technical field of transistors, and particularly relates to a transistor, a preparation method thereof and a field effect transistor. The transistor comprises a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged; a first electrode is arranged on the first surface, a second electrode and a plurality of grid electrodes are arranged on the second surface, and the second electrode is connected with the epitaxial layer through a Schottky contact part and an electrode ohmic contact part. The design mode provided by the invention is beneficial to improving the reliability of the device.

Description

Technical Field

[0001] This application belongs to the field of transistor technology, specifically relating to a transistor and its fabrication method and a field-effect transistor. Background Technology

[0002] Transistors, with their low power consumption, high switching speed, and excellent integration characteristics, are widely used in various electronic systems, such as spacecraft, satellites, and nuclear reactor monitoring systems. However, these electronic systems need to operate in high-radiation environments. For example, high-energy particles (such as protons, heavy ions, and neutrons) in such environments can easily affect the electrical performance of field-effect transistors, leading to decreased device reliability and reduced lifespan. Summary of the Invention

[0003] The technical objective of this application is to at least solve the technical problems of decreased reliability and reduced lifespan of existing transistors when operating in high-radiation environments. The transistor provided in this application improves the reliability and lifespan of the device by reducing the impact of single-event irradiation effects.

[0004] A first aspect of this application is to provide a transistor comprising: a semiconductor substrate including a first side and a second side disposed opposite to each other; The first electrode is located on the first surface of the aforementioned semiconductor substrate; The first epitaxial layer and the second epitaxial layer are located on the second surface of the semiconductor substrate, and the first epitaxial layer and the second epitaxial layer are stacked sequentially along the first direction; The second epitaxial layer includes a main body region and an edge region distributed along a second direction. The edge region is disposed at both ends of the main body region. The second direction intersects with the first direction. The main body region of the second epitaxial layer abuts against the first epitaxial layer. The edge region of the second epitaxial layer is connected to the first epitaxial layer through an insulating dielectric layer. The second epitaxial layer has a second electrode and a plurality of gates on the side surface away from the semiconductor substrate. The second electrode is connected to the second epitaxial layer through a Schottky contact and an electrode ohmic contact, and the Schottky contact is located between adjacent gates.

[0005] In some embodiments, the second electrode covers the gate, and an interlayer dielectric layer is provided between the second electrode and the gate.

[0006] In some embodiments, there are multiple second electrodes, each separated by an insulating dielectric layer, and each second electrode is independently connected to the ohmic contact and Schottky contact of each electrode.

[0007] In some embodiments, the edge region of the second epitaxial layer includes a first P-type doped region, a second P-type doped region, and an N-type doped region; Preferably, the first P-type doped region abuts against the insulating dielectric layer, and the second P-type doped region and the N-type doped region are disposed within the first P-type doped region; Preferably, the first P-type doped region, the second P-type doped region, and the N-type doped region are distributed along the second direction, and the first P-type doped region, the second P-type doped region, and the N-type doped region respectively abut against the insulating dielectric layer.

[0008] In some embodiments, the orthographic projection of the first P-type doped region onto the semiconductor substrate completely overlaps with the orthographic projection of the insulating dielectric layer onto the semiconductor substrate. The orthographic projection of the second P-type doped region onto the semiconductor substrate completely overlaps with the orthographic projection of the insulating dielectric layer onto the semiconductor substrate. The orthographic projection of the N-type doped region onto the semiconductor substrate completely overlaps with the orthographic projection of the insulating dielectric layer onto the semiconductor substrate.

[0009] In some embodiments, the orthographic projection of the first P-type doped region onto the semiconductor substrate partially overlaps with the orthographic projection of the gate onto the semiconductor substrate. and / or; The orthogonal projection of the N-type doped region onto the semiconductor substrate partially overlaps with the orthogonal projection of the gate onto the semiconductor substrate.

[0010] In some embodiments, the feature depth of the edge region of the second epitaxial layer is greater than the feature depth of the main region of the second epitaxial layer.

[0011] A second aspect of this application is to provide a field-effect transistor, which includes the transistor described in the first aspect, and the gate is a polysilicon gate. and / or; The aforementioned semiconductor substrate is any one or more of silicon carbide substrate, silicon substrate, and gallium nitride substrate.

[0012] and / or; The aforementioned epitaxial layer is an N-type epitaxial layer.

[0013] A third aspect of this application is to provide a method for fabricating a transistor, comprising: Provide a semiconductor substrate: including a first surface and a second surface disposed opposite to each other; Along a first direction, a first epitaxial layer and a plurality of insulating dielectric layers are sequentially grown on the second surface of a semiconductor substrate; the insulating dielectric layers are arranged at intervals along a second direction, and the second direction intersects with the first direction; A second epitaxial layer is grown on the surface of an insulating dielectric layer. The second epitaxial layer includes a main region and an edge region distributed along a second direction. The edge regions are disposed at both ends of the main region. The main region of the second epitaxial layer abuts against the first epitaxial layer. The edge regions of the second epitaxial layer are connected to the first epitaxial layer through the insulating dielectric layer. A plurality of gates and a second electrode are formed on the surface of the second epitaxial layer away from the semiconductor substrate. The second electrode is connected to the second epitaxial layer through a Schottky contact and an electrode ohmic contact.

[0014] In some embodiments, the step of forming a plurality of gates on the surface of the second epitaxial layer away from the semiconductor substrate includes: An insulating dielectric layer is grown on the surface of the second epitaxial layer away from the semiconductor substrate; A gate layer is deposited on the side of the insulating dielectric layer away from the semiconductor substrate, and each gate layer is etched to form a plurality of gates.

[0015] The beneficial effects of this application are: 1. The transistor provided in this application reduces the impact of high-energy particles (such as protons, heavy ions, neutrons, etc.) on the insulating dielectric layer, such as the gate oxide layer, in the active region by adjusting the gate to be multiple and partitioned. Furthermore, a Schottky contact is provided between the gates, which facilitates the formation of carrier leakage paths, rapidly expelling electron-hole pairs generated by the incident high-energy particles. Simultaneously, the multiple electrodes also assist in the expulsion of carriers generated by high-energy particles. In addition, an insulating dielectric layer is provided between the epitaxial layers, which conveniently blocks the transport path of high-energy particles. Therefore, the transistor provided in this application reduces the impact of single-event irradiation, thereby improving the reliability and lifespan of the device.

[0016] 2. The transistor provided in this application, by adjusting the gate to be multiple and partitioned, helps to reduce the gate capacitance and improve the dynamic response capability of the device. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A schematic diagram of one structure of the transistor of this application is shown. Figure 2 A schematic diagram of another structure of the transistor of this application is shown; Figure 3 A schematic diagram of another structure of the transistor of this application is shown; Figure 4 A schematic diagram of another structure of the transistor of this application is shown; Figure 5 A flowchart illustrating the transistor fabrication method of this application is shown schematically; Figures 6A to 6J This application is illustrated schematically. Figure 1 A schematic diagram of the transistor fabrication process; Figure 7 for Figure 3 Top view of a transistor; The labels in the attached diagram are as follows: 1000, Transistor; 100. First electrode; 110. Semiconductor substrate; 120, Epitaxial layer; 1201, First epitaxial layer; 1202, Second epitaxial layer; 1202A, Main region; 1202B, Edge region; 1202a, First P-type doped region; 1202b, N-type doped region; 1202c, Second P-type doped region; 130. First insulating dielectric layer; 140. Second insulating dielectric layer; 150. Interlayer dielectric layer; 200, gate; 200a, first gate; 200b, second gate; 300, Second electrode; 300a, First sub-electrode; 300b, Second sub-electrode; 300A, Schottky contact; 300B, Ohmic electrode contact; First direction: Figure 1 The X-direction of the transistor's coordinate axis is shown in the diagram. Second direction: Figure 1 The Y-axis of the transistor coordinate axis is shown in the diagram. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0020] In the context of this application, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0021] This application may use the term “coupled with” along with its derivatives. “Coupled” can mean one or more of the following: “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements are coupled or connected between the elements said to be coupled to each other. The term “direct coupling” can mean two or more elements in direct contact.

[0022] Transistors, with their low power consumption, high switching speed, and excellent integration characteristics, are widely used in various electronic systems, such as spacecraft, satellites, and nuclear reactor monitoring systems. However, these electronic systems need to operate in high-radiation environments. For example, high-energy particles (such as protons, heavy ions, and neutrons) in such environments can easily cause single-event effects (SEE) in transistors. SEE refers to the phenomenon where high-energy particles (such as protons and heavy ions in cosmic rays) collide with atoms inside a semiconductor device, generating a large number of electron-hole pairs, thus triggering a series of electrical effects. These effects can lead to performance degradation or even permanent damage to the device. Common SEE include: single-event burn-out (SEB: high-energy particles hitting a high-electric-field region of the device, causing localized overheating and burn-out), single-event gate breakdown (high-energy particles hitting the gate oxide layer, causing the gate insulating layer to break down), and single-event flip (high-energy particles changing the state of memory cells, leading to data errors).

[0023] In recent years, researchers have proposed various solutions for the radiation-hardened design of SiC devices, including optimizing device structure, improving material processing, and introducing radiation hardening techniques. However, these methods still face many challenges in practical applications, such as increased process complexity, rising costs, and performance trade-offs.

[0024] This application provides a transistor that improves device reliability and lifespan by reducing the effects of single-event irradiation.

[0025] A first aspect of this application is to provide a transistor comprising a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other; a first electrode is provided on the first surface of the semiconductor substrate, and a first epitaxial layer and a second epitaxial layer are provided on the second surface of the semiconductor substrate, the first epitaxial layer and the second epitaxial layer being stacked sequentially along a first direction; the second epitaxial layer includes a main region and an edge region distributed along a second direction, the edge region of the second epitaxial layer being disposed at both ends of the main region, the second direction intersecting the first direction; the main region of the second epitaxial layer abutting against the first epitaxial layer, the edge region of the second epitaxial layer being connected to the first epitaxial layer through an insulating dielectric layer; a second electrode and a plurality of gates are provided on the side surface of the second epitaxial layer away from the semiconductor substrate, the second electrode being connected to the second epitaxial layer through a Schottky contact and an electrode ohmic contact, the Schottky contact being located between adjacent gates.

[0026] The transistor provided in this application reduces the impact of high-energy particles (such as protons, heavy ions, neutrons, etc.) on the insulating dielectric layer in the active region, such as the gate oxide layer, by adjusting the number of gates to multiple and partitioned. This results in a smaller leakage current in the device during high-energy particle processes. Furthermore, with multiple gates, the gate capacitance is also reduced, thereby mitigating the Miller effect caused by the gate capacitance (in amplifier circuits, the presence of feedback capacitance (usually parasitic capacitance) causes additional phase delay and amplitude attenuation between the input and output signals), and enhancing the dynamic characteristics of the device.

[0027] The transistor provided in this application has a Schottky contact between its gate and the gate. This Schottky contact facilitates the formation of a carrier leakage path, which allows for the rapid discharge of electron-hole pairs generated by the incident high-energy particles, thereby reducing the impact of high-energy particles on the device.

[0028] The transistor provided in this application can also assist in the discharge of charge carriers generated by high-energy particles by setting multiple electrodes. For example, a bias voltage can be set separately on the second electrode to assist in the discharge of charge carriers generated by high-energy particles and reduce the impact of high-energy particles on the device.

[0029] The transistor provided in this application has an insulating dielectric layer between the epitaxial layers. This insulating dielectric layer can conveniently block the transport path of high-energy particles. Specifically, on the one hand, it reduces the amount of charge deposition on the surface region caused by high-energy particles, and reduces the instantaneous impact of high-energy particles on the injection region structure on the device surface. On the other hand, it reduces the transport of electron-hole pairs deposited inside the material to the device surface, thereby reducing the probability of single-particle leakage damage and single-particle burn-out.

[0030] Therefore, the transistor provided in this application reduces the impact of single-event irradiation, thereby improving the reliability and lifespan of the device.

[0031] like Figure 1 This application illustrates a transistor 1000, which includes a semiconductor substrate 110. The semiconductor substrate 110 is made of one or more materials selected from silicon carbide, silicon, and gallium nitride. Silicon carbide (SiC), as a typical representative of third-generation semiconductor materials, has attracted much attention due to its excellent characteristics such as wide bandgap (~3.2 eV), high thermal conductivity (~4.9 W / cm·K), and high breakdown field strength (~3 MV / cm). Taking 4H-SiC as an example, its bandgap is approximately three times that of silicon, meaning that higher energy is required to achieve intrinsic excitation, thus significantly improving the radiation resistance of SiC devices. Furthermore, the high thermal conductivity of SiC allows it to operate stably in high-temperature environments, while its high breakdown field strength makes it suitable for high-voltage applications.

[0032] The semiconductor substrate 110 includes a first surface and a second surface disposed opposite to each other along a first direction (coordinate axis X direction). A first electrode, which is a drain electrode, is disposed on the first surface. A first epitaxial layer 1201 and a second epitaxial layer 1202 are disposed on the second surface, and the first epitaxial layer 1201 and the second epitaxial layer 1202 are stacked sequentially along the first direction. The second epitaxial layer 1202 includes a main region 1202A and an edge region 1202B distributed along a second direction (coordinate axis Y direction). The edge region 1202B of the second epitaxial layer is disposed at both ends of the main region 1202A. The second direction intersects with the first direction. In these embodiments, this application illustrates that the second direction and the first direction are perpendicular to each other. The main region 1202A of the second epitaxial layer 1202 abuts against the first epitaxial layer 1201, and the edge region 1202B of the second epitaxial layer 1202 is connected to the first epitaxial layer 1201 through a first insulating dielectric layer 130. The epitaxial layer of this application refers to one or more thin film materials grown on a semiconductor substrate using epitaxial growth technology. This thin film material has a matching lattice and a high-quality interface with the semiconductor, and simultaneously facilitates the formation of channel regions within the epitaxial layer. The material of the epitaxial layer includes any material conventional in the art, such as silicon carbide. The epitaxial growth technology of this application includes any method conventional in the art. The first insulating dielectric layer of this application refers to a material layer used to isolate adjacent epitaxial layers. The material of the first insulating dielectric layer includes any material conventional in the art, such as silicon nitride, aluminum nitride, etc.

[0033] like Figure 1The diagram illustrates that the edge region 1202B of the second epitaxial layer 1202 includes a first P-type doped region 1202a, a second P-type doped region 1202c, and an N-type doped region 1202b. The first P-type doped region 1202a abuts against the first insulating dielectric layer 130, and the second P-type doped region 1202c and the N-type doped region 1202b are disposed within the first P-type doped region 1202a. The first P-type doped region 1202a is a P-base region, typically a lightly doped P-type region with a low doping concentration to ensure good blocking characteristics under high voltage, and is mainly used to form a PN junction to control current flow. The second P-type doped region 1202c is a P+ short-circuit region, a heavily doped P-type region in contact with the source metal. Its main function is to provide a low-resistance path, fixing the potential of the P-base region at the source potential. The N-type doped region 1202b is an N+ source region, a highly doped N-type region in contact with the source metal. Its main function is to provide a low-resistance path for current to be drawn from the source. Meanwhile, the orthographic projection of the first P-type doped region 1202a onto the semiconductor substrate 110 completely overlaps with the orthographic projection of the first insulating dielectric layer 130 onto the semiconductor substrate 110; the orthographic projection of the second P-type doped region 1202c onto the semiconductor substrate 110 completely overlaps with the orthographic projection of the first insulating dielectric layer 130 onto the semiconductor substrate 110; and the orthographic projection of the N-type doped region 1202b onto the semiconductor substrate 110 completely overlaps with the orthographic projection of the first insulating dielectric layer 130 onto the semiconductor substrate 110. This insulating dielectric layer effectively blocks the transport path of high-energy particles. Specifically, it reduces the amount of charge deposition on the surface region caused by high-energy particles, thereby reducing the instantaneous impact of high-energy particles on the injection region structure of the device surface. On the other hand, it reduces the transport of electron-hole pairs deposited inside the material to the device surface, thereby reducing the probability of single-particle leakage damage and single-particle burn-out.

[0034] Combination Figure 1It is understood that a second electrode 300 and a plurality of gates 200 are provided on the surface of the second epitaxial layer 1202 away from the semiconductor substrate 110. Each gate 200 includes a first gate 200a and a second gate 200b. The second electrode 300 covers the first gate 200a and the second gate 200b. An interlayer dielectric layer 150 is provided between the second electrode 300 and the first gate 200a and the second gate 200b. The second electrode is a source electrode. The first gate 200a and the second gate 200b are polysilicon gates. A second insulating dielectric layer 140 is provided between the polysilicon gates and the second epitaxial layer 1202. This second insulating dielectric layer 140 is a gate insulating dielectric layer. The material of this gate insulating dielectric layer includes any material conventional in the art. The transistor provided in this application reduces the impact of high-energy particles (such as protons, heavy ions, neutrons, etc.) on the active region by adjusting the number of gates to multiple and partitioning them, resulting in smaller leakage current in the device during high-energy particle processes. Furthermore, with multiple gates, the gate capacitance is also reduced, thereby mitigating the Miller effect caused by the gate capacitance (in amplifier circuits, the presence of feedback capacitance (usually parasitic capacitance) causes additional phase delay and amplitude attenuation between the input and output signals), and enhancing the dynamic characteristics of the device.

[0035] The interlayer dielectric layer 150 of this application is made of any material conventional in the art, such as a low dielectric constant material. The second electrode 300 is connected to the second epitaxial layer 1202 via a Schottky contact 300A and an ohmic contact 300B. The Schottky contact 300A is located between the first gate 200a and the second gate 200b. Figure 1 It is known that the orthographic projection of the first P-type doped region 1202a onto the semiconductor substrate 110 partially overlaps with the orthographic projection of the first gate 200a or the first gate 200b onto the semiconductor substrate 110; and the orthographic projection of the N-type doped region 1202b onto the semiconductor substrate 110 partially overlaps with the orthographic projection of the first gate 200a or the first gate 200b onto the semiconductor substrate 110. Furthermore, the orthographic projection of the first P-type doped region 1202a onto the semiconductor substrate 110 completely overlaps with the orthographic projection of the source ohmic contact 300B onto the semiconductor substrate 110.

[0036] The transistor provided in this application has a Schottky contact between its gate and the gate. The Schottky contact is designed based on the Schottky barrier principle and is used to realize non-ohmic contact between metal and semiconductor. The Schottky contact facilitates the formation of a carrier leakage path, which can quickly discharge electron-hole pairs generated by the incident high-energy particles, thereby reducing the impact of high-energy particles on the device.

[0037] Meanwhile, the first electrode of this application is located on the first side of the semiconductor substrate, and the second electrode is located on the second side of the semiconductor substrate. Multiple electrodes can also assist in the discharge of charge carriers generated by high-energy particles. For example, a bias voltage can be set separately on the second electrode to assist in the discharge of charge carriers generated by high-energy particles and reduce the impact of high-energy particles on the device.

[0038] Therefore, the field-effect transistor provided in this application improves the reliability and lifespan of the device by reducing the influence of single-event irradiation.

[0039] like Figure 2 This application illustrates that a transistor 1000 is provided, which is a field-effect transistor with... Figure 1 The difference in the schematic transistor is that the first P-type doped region 1202a, the second P-type doped region 1202c, and the N-type doped region 1202b are distributed along the second direction, wherein the N-type doped region 1202b is disposed between the first P-type doped region 1202a and the second P-type doped region 1202c, and the N-type doped region 1202b simultaneously abuts against the first P-type doped region 1202a and the second P-type doped region 1202c.

[0040] like Figure 3 This application illustrates that a transistor 1000 is provided, which is a field-effect transistor with... Figure 1 The difference in the illustrated transistor is that there are multiple second electrodes 300, such as a first sub-electrode 300a and a second sub-electrode 300b, with the second sub-electrode 300b located at both ends of the first sub-electrode 300a along the second direction. The first sub-electrode 300a and the second sub-electrode 300b are separated by the gate 200, and each second electrode 300 is independently connected to the respective electrode ohmic contact portion 300B and Schottky contact portion 300A. Specifically... Figure 3 The diagram illustrates the connection of the first sub-electrode 300a to the Schottky contact 300A, and the second sub-electrode 300b to the ohmic electrode contact 300B. This application, by using multiple electrodes, can also assist in the discharge of charge carriers generated by high-energy particles. Figure 3 The schematic transistor splits the second electrode 300 into two disconnected sub-electrodes, a first sub-electrode 300a and a second sub-electrode 300b, to facilitate individual bias voltage setting and to assist in better outward displacement of charge carriers generated by high-energy particles. Specifically, as shown in the diagram... Figure 7 Indication.

[0041] like Figure 4 This application illustrates that a transistor 1000 is provided, which is a field-effect transistor with... Figure 3 The difference between the illustrated transistors is that the field-effect transistor 1000 and... Figure 3The difference in the illustrated transistor lies in the following: the first P-type doped region 1202a, the second P-type doped region 1202c, and the N-type doped region 1202b are distributed along the second direction. The N-type doped region 1202b is disposed between the first P-type doped region 1202a and the second P-type doped region 1202c, and simultaneously abuts against both the first P-type doped region 1202a and the second P-type doped region 1202c. The design of this transistor is different from... Figure 3 The design approach removes part of the first P-type doped region 1202a below the N-type doped region 1202b, ensuring that the hole movement path does not exceed the left and right widths of the first P-type doped region 1202a. This limits the potential drop height caused by hole movement, suppresses the turn-on of parasitic transistors, and ultimately effectively reduces the probability of single-event burn-out (SEB).

[0042] A second aspect of this application is to provide a field-effect transistor comprising the transistor described above.

[0043] A third aspect of this application is to provide a method for fabricating a transistor, such as... Figure 5 This preparation method, as illustrated, includes the following preparation process: S100, providing a semiconductor substrate: including a first surface and a second surface disposed opposite to each other; S200. Along the first direction, a first epitaxial layer and a plurality of insulating dielectric layers are sequentially grown on the second surface of the semiconductor substrate; the insulating dielectric layers are arranged at intervals along the second direction, and the second direction intersects with the first direction. S300. A second epitaxial layer is grown on the surface of an insulating dielectric layer. The second epitaxial layer includes a main region and an edge region distributed along a second direction. The edge regions are disposed at both ends of the main region. The main region of the second epitaxial layer abuts against the first epitaxial layer. The edge regions of the second epitaxial layer are connected to the first epitaxial layer through the insulating dielectric layer. S400. A plurality of gates and a second electrode are formed on the surface of the second epitaxial layer away from the semiconductor substrate. The second electrode is connected to the second epitaxial layer through a Schottky contact and an electrode ohmic contact.

[0044] In some embodiments, the step of forming a plurality of gates on the surface of the second epitaxial layer away from the semiconductor substrate includes: An insulating dielectric layer is grown on the surface of the second epitaxial layer away from the semiconductor substrate; A gate layer is deposited on the side of the insulating dielectric layer away from the semiconductor substrate, and each gate layer is etched to form a plurality of gates.

[0045] This application is combined with Figures 6A to 6J right Figure 1The fabrication method of the schematic field-effect transistor is described in detail.

[0046] like Figure 6A The illustration shows a semiconductor substrate 110, which is a silicon carbide semiconductor substrate used to fabricate silicon carbide devices, facilitating stable operation of the devices under high temperature and high voltage conditions. In some embodiments, this application discloses that the silicon carbide semiconductor substrate is an N-type silicon carbide semiconductor substrate, with a resistivity of 0.01 Ω·cm to 0.03 Ω·cm and a thickness of 100 μm to 500 μm. The methods for measuring resistivity and thickness include any methods conventional in the art, which will not be elaborated upon in this application.

[0047] like Figure 6B The diagram illustrates that an epitaxial layer 1201 is formed on the aforementioned N-type silicon carbide semiconductor substrate using an epitaxial process. This first epitaxial layer 1201 is an N-type epitaxial layer, and the doping concentration of the N-type epitaxial layer is 5e⁻¹. 14 cm -3 ~5e 16 cm -3 The thickness ranges from 3μm to 50μm.

[0048] like Figure 6C The diagram illustrates that an insulating dielectric layer, such as an aluminum nitride insulating dielectric layer, is deposited on one side surface of the first epitaxial layer 1201 using atomic layer deposition (ALD) or vapor deposition processes. The thickness of the aluminum nitride insulating dielectric layer is 0.05 μm to 5 μm. Then, two first insulating dielectric layers 130 are formed by photolithography and chlorine-based gas etching processes, and the two first insulating dielectric layers 130 are spaced apart along the first direction. The distance between them can be flexibly adjusted according to actual needs. In these embodiments, this application discloses that the thickness of the first insulating dielectric layer 130 is any one of 0.05μm, 0.06μm, 0.07μm, 0.08μm, 0.09μm, 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, 2.0μm, 3.0μm, 4.0μm, and 5.0μm, or any one of the above ranges.

[0049] like Figure 6D The diagram illustrates that a second epitaxial layer 1202 is grown on the surface of the first insulating dielectric layer 130 away from the semiconductor substrate 110 using a chemical vapor deposition process. This second epitaxial layer 1202 is an N-type epitaxial layer, and its thickness is greater than that of the first insulating dielectric layer 130, so that the N-type epitaxial layer covers the first insulating dielectric layer 130. The doping concentration of the N-type epitaxial layer is 5e14 cm⁻¹. -3 ~5e16cm-3 After deposition, a chemical mechanical polishing process is used to obtain a smooth surface (surface roughness of 0.5 nm to 5 nm), ultimately forming the second epitaxial layer 1202. Figure 6D It is understood that the second epitaxial layer 1202 includes a main region 1202A and an edge region 1202B. The main region 1202A is in direct contact with the first epitaxial layer 1201, and the edge region 1202B is connected to the first epitaxial layer 1201 through the aforementioned first insulating dielectric layer 130. The feature depth of the edge region 1202B of the second epitaxial layer is greater than the feature depth of the main region 1202A of the second epitaxial layer. For example... Figure 6D The characteristic depth of the edge region 1202B of the second epitaxial layer is the distance h2 between the two end faces of the edge region 1202B that are relatively distributed in the first direction, and the characteristic depth of the edge region 1202A of the first epitaxial layer is the distance h1 between the two end faces of the main region 1202A that are relatively distributed in the first direction, where h1 is greater than h2.

[0050] like Figure 6E The diagram illustrates that two first P-type doped regions 1202a are formed within the second epitaxial layer 1202 using photolithography and ion implantation processes. These first P-type doped regions 1202a are P-based regions, and the peak doping concentration of these P-based regions is 1e17cm⁻¹. -3 ~5e19cm -3 The junction depth is 0.2 μm to 2.5 μm, and the first P-type doped region 1202a is located on one side surface of the first insulating dielectric layer 130 and abuts against the first insulating dielectric layer 130. The orthographic projection of the first P-type doped region 1202a onto the semiconductor substrate 110 completely overlaps with the orthographic projection of the first insulating dielectric layer 130 onto the semiconductor substrate 110.

[0051] An N-type doped region 1202b and a second P-type doped region 1202c are formed within the first P-type doped region 1202a. The junction depths of the N-type doped region 1202b and the second P-type doped region 1202c are both smaller than the junction depth of the first P-type doped region 1202a. The orthographic projection of the second P-type doped region 1202c onto the semiconductor substrate 110 completely overlaps with the orthographic projection of the first insulating dielectric layer 130 onto the semiconductor substrate 110, and the orthographic projection of the N-type doped region 1202b onto the semiconductor substrate 110 completely overlaps with the orthographic projection of the first insulating dielectric layer 130 onto the semiconductor substrate 110. In these embodiments, it is disclosed that the N-type doped region 1202b is an N+ source region and the second P-type doped region 1202c is a P+ short-circuit region. The junction depth of the N+ source region is smaller than that of the first P-type doped region 1202a. The junction depth of the N+ source region is 0.1 μm to 0.5 μm, and the peak doping concentration of the N+ source region is 5e18 cm⁻¹. -3 ~5e20cm -3The junction depth of the P+ short-circuit region is smaller than that of the first P-type doped region 1202a. The junction depth of the P+ short-circuit region is 0.2 μm to 2.5 μm, and the peak doping concentration of the P+ short-circuit region is 5e18cm. -3 ~5e21cm -3 .

[0052] like Figure 6F As illustrated, a second insulating dielectric layer 140 is grown on the surface of the second epitaxial layer 1202 away from the semiconductor substrate 110 using a thermal oxidation or deposition process. The thickness of the second insulating dielectric layer 140 is 10 nm to 200 nm.

[0053] like Figure 6G To illustrate, a polysilicon layer is deposited above the second insulating dielectric layer 140 as a gate layer using deposition, photolithography, and etching processes. This gate layer is then etched to form multiple gates 200. Figure 6G The diagram illustrates two gates 200, and the orthographic projection of the gates 200 onto the semiconductor substrate 110 overlaps with the orthographic projection of the first P-type doped region 1202a onto the semiconductor substrate 110. Specifically, Figure 6G The diagram illustrates that the orthogonal projection of the gate 200 onto the semiconductor substrate 110 extends beyond the orthogonal projection of the first P-type doped region 1202a onto the semiconductor substrate 110, and the extended portion is NN, with a length of 0 μm to 0.3 μm. Simultaneously, the orthogonal projection of the gate 200 onto the semiconductor substrate 110 overlaps with the orthogonal projection of the N-type doped region 1202b onto the semiconductor substrate 110, and this overlapping portion is MM, with a length of 0.05 μm to 0.5 μm.

[0054] like Figure 6H Indicates, to Figure 6G The second insulating dielectric layer 140 is etched to remove excess portions of the second insulating dielectric layer 140, and the orthogonal projection of the gate 200 onto the semiconductor substrate 110 completely overlaps with the orthogonal projection of the etched second insulating dielectric layer 140 onto the semiconductor substrate 110. This etched second insulating dielectric layer 140 serves as the gate insulating dielectric layer of the gate 200. Simultaneously, an interlayer dielectric layer 150 is grown on the surface of the gate 200 so that the interlayer dielectric layer 150 covers the gate 200 and the etched second insulating dielectric layer 140.

[0055] like Figure 6IThe diagram illustrates that a second electrode 300 is formed on the surface of the interlayer dielectric layer 150 using deposition, photolithography, and etching processes. The second electrode 300 is the source electrode and covers the gate 200 and the second epitaxial layer 1202. The second electrode 300 is connected to the second epitaxial layer 1202 through a Schottky contact 300A and an electrode ohmic contact 300B. The Schottky contact 300A is located between adjacent gates 200.

[0056] like Figure 6J The diagram illustrates how a first electrode 100, serving as the drain electrode, is formed on the first side (back side) of a semiconductor substrate 110 using laser annealing, metal thickening, and deposition processes. This process ultimately produces a field-effect transistor.

[0057] This application is in Figures 6A to 6J China is only for Figure 1 An illustration of the transistor fabrication process, others. Figures 2 to 4 Transistor fabrication methods and Figure 1 Similarities exist, and will not be elaborated upon in this application.

[0058] Therefore, the design method provided in this application is beneficial to improving the reliability of the device.

[0059] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a specific order described or illustrated unless explicitly stated otherwise. It should also be understood that additional or alternative steps may be used. The above descriptions are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transistor, characterized in that: include: Semiconductor substrate: including a first surface and a second surface disposed opposite to each other; The first electrode is located on the first surface of the semiconductor substrate; A first epitaxial layer and a second epitaxial layer are located on the second surface of the semiconductor substrate, and the first epitaxial layer and the second epitaxial layer are stacked sequentially along a first direction; The second epitaxial layer includes a main body region and an edge region distributed along a second direction. The edge regions are disposed at both ends of the main body region. The second direction intersects with the first direction. The main body region of the second epitaxial layer abuts against the first epitaxial layer. The edge region of the second epitaxial layer is connected to the first epitaxial layer through an insulating dielectric layer. The second epitaxial layer has a second electrode and a plurality of gates on the side surface away from the semiconductor substrate. The second electrode is connected to the second epitaxial layer through a Schottky contact and an electrode ohmic contact. The Schottky contact is located between adjacent gates.

2. The transistor according to claim 1, characterized in that: The second electrode covers the gate, and an interlayer dielectric layer is provided between the second electrode and the gate.

3. The field-effect transistor according to claim 1, characterized in that: There are multiple second electrodes, each separated by an insulating dielectric layer, and each second electrode is independently connected to the ohmic contact and Schottky contact of each electrode.

4. The transistor according to any one of claims 1 to 3, characterized in that: The edge region of the second epitaxial layer includes a first P-type doped region, a second P-type doped region, and an N-type doped region; Preferably, the first P-type doped region abuts against the insulating dielectric layer, and the second P-type doped region and the N-type doped region are disposed within the first P-type doped region; Preferably, the first P-type doped region, the second P-type doped region, and the N-type doped region are distributed along the second direction, and the first P-type doped region, the second P-type doped region, and the N-type doped region respectively abut against the insulating dielectric layer.

5. The transistor according to claim 4, characterized in that: The orthographic projection of the first P-type doped region onto the semiconductor substrate completely overlaps with the orthographic projection of the insulating dielectric layer onto the semiconductor substrate; The orthographic projection of the second P-type doped region onto the semiconductor substrate completely overlaps with the orthographic projection of the insulating dielectric layer onto the semiconductor substrate; The orthographic projection of the N-type doped region onto the semiconductor substrate completely overlaps with the orthographic projection of the insulating dielectric layer onto the semiconductor substrate.

6. The transistor according to claim 4, characterized in that: The orthographic projection of the first P-type doped region onto the semiconductor substrate partially overlaps with the orthographic projection of the gate onto the semiconductor substrate; and / or; The orthographic projection of the N-type doped region onto the semiconductor substrate partially overlaps with the orthographic projection of the gate onto the semiconductor substrate.

7. The transistor according to any one of claims 1 to 3, characterized in that: The feature depth of the edge region of the second epitaxial layer is greater than the feature depth of the main region of the second epitaxial layer.

8. A field-effect transistor, characterized in that: The transistor comprising any one of claims 1 to 7, wherein the gate is a polysilicon gate; and / or; The semiconductor substrate is any one or more of silicon carbide substrate, silicon substrate, and gallium nitride substrate. and / or; The epitaxial layer is an N-type epitaxial layer.

9. A method for fabricating a transistor, characterized in that: include: Provide a semiconductor substrate: including a first surface and a second surface disposed opposite to each other; Along a first direction, a first epitaxial layer and a plurality of insulating dielectric layers are sequentially grown on the second surface of a semiconductor substrate; Each of the insulating dielectric layers is arranged at intervals along a second direction, and the second direction intersects with the first direction; A second epitaxial layer is grown on the surface of the insulating dielectric layer. The second epitaxial layer includes a main region and an edge region distributed along a second direction. The edge regions are disposed at both ends of the main region. The main region of the second epitaxial layer abuts against the first epitaxial layer. The edge regions of the second epitaxial layer are connected to the first epitaxial layer through the insulating dielectric layer. A plurality of gates and a second electrode are formed on the side of the second epitaxial layer away from the semiconductor substrate. The second electrode is connected to the second epitaxial layer through a Schottky contact and an electrode ohmic contact.

10. The preparation method according to claim 9, characterized in that: The step of forming a plurality of gates on the side of the second epitaxial layer away from the semiconductor substrate includes: An insulating dielectric layer is grown on the surface of the second epitaxial layer on the side away from the semiconductor substrate; A gate layer is deposited on the surface of the insulating dielectric layer away from the semiconductor substrate, and the gate layer is etched to form a plurality of gates.

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