A method of manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises the following steps: providing a plurality of pseudo gate structures, the pseudo gate structures being arranged on a substrate; forming a first nitride layer on the top surface of the pseudo gate structures, and forming an oxide layer on the first nitride layer, wherein the greater the width of the pseudo gate structure is, the smaller the thickness of the oxide layer on the pseudo gate structure is; forming a second nitride layer on the exposed surface of the oxide layer, the first nitride layer and the pseudo gate structure; forming a dielectric layer on the first nitride layer and the substrate; removing the dielectric layer, the second nitride layer and the oxide layer on the pseudo gate structure until the surface of the first nitride layer and the second nitride layer is flush; and removing the first nitride layer and part of the second nitride layer so that the surface of the second nitride layer and the pseudo gate structure is flush. The application provides a semiconductor structure manufacturing method and a semiconductor structure, and the surface flatness of the semiconductor structure manufacturing can be improved, so that the manufacturing yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, as transistor sizes continue to shrink, sufficient gate capacitance needs to be maintained to ensure gate control capability, thus requiring a continuous reduction in gate oxide thickness. However, when the gate oxide thickness becomes too thin, the direct tunneling effect increases exponentially, leading to a significant increase in device leakage current and rendering the device inoperable.

[0003] Introducing high-k materials into integrated circuit manufacturing processes can result in a relatively large gate oxide thickness while ensuring a continuous reduction in the equivalent gate oxide thickness, thereby suppressing gate leakage current. However, when multiple semiconductor structures of different sizes and structures coexist on a wafer, introducing high-k gate dielectric materials into the metal gate forming process makes it difficult to control the gate height and surface flatness, which can easily lead to defects. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure that can improve the surface flatness of the semiconductor structure and thus improve the manufacturing yield.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] This invention provides a method for manufacturing a semiconductor structure, comprising:

[0007] Multiple pseudo-gate structures are provided, and the pseudo-gate structures are disposed on a substrate;

[0008] A first nitride layer is formed on the top surface of the pseudo-gate structure, and an oxide layer is formed on the first nitride layer, wherein the wider the pseudo-gate structure, the smaller the thickness of the oxide layer on the pseudo-gate structure;

[0009] A second nitride layer is formed on the exposed surfaces of the oxide layer, the first nitride layer, and the pseudo-gate structure;

[0010] A dielectric layer is formed on the first nitride layer and on the substrate;

[0011] Remove the dielectric layer, the second nitride layer, and the oxide layer from the dummy gate structure until the surfaces of the first nitride layer and the second nitride layer are flush; and

[0012] Remove the first nitrided layer and part of the second nitrided layer so that the surface of the second nitrided layer and the pseudo-gate structure are flush.

[0013] In one embodiment of the present invention, when removing the second nitride layer and the oxide layer on the pseudo-gate structure, the second nitride layer located on the oxide layer is first removed by wet etching until the surface of the oxide layer is exposed.

[0014] In one embodiment of the present invention, after exposing the surface of the oxide layer, the oxide layer, a portion of the second nitride layer, and a portion of the dielectric layer are polished away, using the first nitride layer as a stop layer.

[0015] In one embodiment of the present invention, before removing the first nitride layer, a dielectric deposition layer is formed on the first nitride layer, the second nitride layer, and the dielectric layer until the dielectric deposition layer located between adjacent pseudo-gate structures is higher than the surface of the first nitride layer.

[0016] In one embodiment of the present invention, in the step of removing the first nitride layer and a portion of the second nitride layer, the first nitride layer is used as a stop layer to polish and remove a portion of the dielectric deposition layer, and the surface of the dummy gate structure is used as a stop layer to remove the first nitride layer, a portion of the second nitride layer and a portion of the dielectric deposition layer. In the obtained semiconductor structure, the surfaces of the second nitride layer, the dielectric deposition layer and the dummy gate structure are flush.

[0017] In one embodiment of the present invention, after the dielectric layer is formed, the dielectric layer located on top of the pseudo-gate structure is removed, and a portion of the second nitride layer and a portion of the dielectric layer located at the corners of the pseudo-gate structure are removed.

[0018] In one embodiment of the present invention, after removing the dielectric layer located on the pseudo-gate structure and before removing the second nitride layer located on the pseudo-gate structure, a dielectric deposition layer is formed on the dielectric layer and the second nitride layer, wherein the surface of the dielectric deposition layer located between adjacent pseudo-gate structures is higher than the surface of the second nitride layer.

[0019] In one embodiment of the present invention, after the dielectric deposition layer is formed, a portion of the dielectric deposition layer and a portion of the second nitride layer located on the pseudo-gate structure are polished away until the surface of the oxide layer is exposed.

[0020] In one embodiment of the present invention, after exposing the oxide layer, the oxide layer, a portion of the second nitride layer, and a portion of the dielectric deposition layer are polished away using the first nitride layer as a stop layer. The first nitride layer, a portion of the second nitride layer, and a portion of the dielectric deposition layer are then polished away using the surface of the dummy gate structure as a stop layer, thereby obtaining the semiconductor structure. In the obtained semiconductor structure, the surfaces of the second nitride layer, the dielectric deposition layer, and the dummy gate structure are flush.

[0021] This invention provides a semiconductor structure, and a method for manufacturing a semiconductor structure based on the above-described method, comprising:

[0022] substrate;

[0023] Multiple pseudo-gate structures are disposed on the substrate;

[0024] A second nitride layer covers the side portion of the pseudo-gate structure; and

[0025] A dielectric deposition layer is disposed on the substrate, and the dielectric layer fills the space between adjacent pseudo-gate structures, wherein the top surface of the pseudo-gate structure, the top surface of the second nitride layer, and the top surface of the dielectric deposition layer are flush.

[0026] As described above, the present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. Its unexpected technical effect is that the manufacturing method for forming a high-K metal gate provided by the present invention can overcome the loading effect, form a metal gate with high surface flatness, and at the same time help reduce the possibility of defects such as voids and bubbles in the metal gate forming process, thereby improving the effectiveness of the semiconductor structure and the forming yield of the semiconductor process.

[0027] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the semiconductor stacking structure in this invention.

[0030] Figure 2 This is a schematic diagram of the structure in which the dielectric layer is formed in this invention.

[0031] Figure 3 This is a schematic diagram of the structure in this invention that exposes the second nitride layer.

[0032] Figure 4 This is a schematic diagram of the structure in one embodiment of the present invention, showing the etching removal of a portion of the second nitride layer.

[0033] Figure 5 This is a schematic diagram of the structure in one embodiment of the present invention, showing the polishing removal of part of the second nitride layer and oxide layer.

[0034] Figure 6This is a schematic diagram of the structure for forming the first medium deposition layer in one embodiment of the present invention.

[0035] Figure 7 This is a schematic diagram of the structure for polishing and removing part of the first dielectric deposit layer in one embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of a semiconductor structure obtained by polishing to remove the first nitride layer in one embodiment of the present invention.

[0037] Figure 9 This is a schematic diagram of a structure in another embodiment of the present invention with part of the second nitriding layer and part of the dielectric layer removed.

[0038] Figure 10 This is a schematic diagram of the structure for forming a second medium deposition layer in another embodiment of the present invention.

[0039] Figure 11 This is a schematic diagram of the structure in another embodiment of the present invention, showing the polishing removal of part of the second nitrided layer and part of the second dielectric deposition layer.

[0040] Figure 12 This is a schematic diagram of the structure for polishing to remove the oxide layer, part of the second nitride layer, and part of the second dielectric deposition layer in another embodiment of the present invention.

[0041] Figure 13 This is a schematic diagram of the structure obtained by polishing to remove the first nitride layer and obtaining a semiconductor structure in another embodiment of the present invention.

[0042] In the figure: 100, substrate; 200, pseudo-gate structure; 300, first nitride layer; 400, oxide layer; 500, second nitride layer; D1, first spacing; D2, second spacing; H1, first thickness; H2, second thickness; H3, third thickness; W1, first width; W2, second width; W3, third width; 600, dielectric layer; 601a, first dielectric film; 602a, first dielectric deposition layer; 601b, second dielectric film; 602b, second dielectric deposition layer. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] The semiconductor structure manufacturing method provided by this invention can be used to form a metal gate structure with a high-k gate dielectric. See also... Figure 2As shown, the high-k material is a material with a dielectric constant higher than silicon dioxide (SiO2), and can replace silicon dioxide in forming the gate dielectric layer 600 to improve transistor performance and reduce size. The high-k material has a higher dielectric constant, which can effectively reduce gate leakage current and improve transistor efficiency. In this invention, the high-k material includes, but is not limited to, hafnium-based oxides, aluminum-based oxides, and zirconium-based oxides, etc. Hafnium-based oxides include, for example, hafnium dioxide (HfO2), hafnium oxide silicate (HfSiO), and hafnium oxynitride (HfSiON). Aluminum-based oxides include, for example, aluminum oxide (Al2O3). Zirconium-based oxides include, for example, zirconium oxide (ZrO2).

[0045] Please see Figure 1 As shown, in the semiconductor structure manufacturing method provided by the present invention, a dummy gate structure 200 is first provided. The dummy gate structure 200 is disposed on a substrate 100. The substrate 100 includes a substrate and a working region formed in the substrate. The substrate is, for example, a wafer silicon substrate for forming the semiconductor structure. The substrate may include a substrate and a silicon layer disposed above the substrate. The substrate is, for example, a semiconductor substrate 100 material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), or lithium aluminate (LiAlO2), and the silicon layer is formed above the substrate. Phosphorus ions or arsenic ions can be implanted in the silicon layer to form doped regions, thereby forming functional doped regions of the semiconductor structure, such as source or drain regions, thus forming the working region. The present invention does not limit the material and thickness of the substrate. In this embodiment, the substrate can be an intrinsic semiconductor, or ions can be implanted into the substrate to form an N-type semiconductor or a P-type semiconductor. In this embodiment, the dummy gate structure 200 includes a gate oxide layer, an isolation layer, and a polysilicon layer. The gate oxide layer is disposed on the substrate 100 and is a high-k material. The isolation layer is disposed on the gate oxide layer, and the isolation layer is, for example, titanium nitride (TiN). The polycrystalline silicon layer is disposed on the isolation layer.

[0046] It should be noted that there are various pseudo-gate structures of different sizes on the wafer 200. For example... Figure 1 A pseudo-gate structure 200 with a first width W1, a second width W2, and a third width W3 is shown. In this embodiment, the first width W1 is smaller than the second width W2, and the second width W2 is smaller than the third width W3. Furthermore, the spacing between different pseudo-gate structures 200 on the wafer is also different. In densely patterned regions, the spacing between adjacent pseudo-gate structures 200 is smaller. In sparsely patterned regions, the spacing between adjacent pseudo-gate structures 200 is larger. Figure 1 A schematic diagram of the pseudo-gate structure 200 with a first spacing D1 and a second spacing D2 is shown, wherein the first spacing D1 is smaller than the second spacing D2.

[0047] Please see Figure 1As shown, in this invention, a stacked structure is formed on the dummy gate structure 200. First, a first nitride layer 300 is formed on the dummy gate structure 200, covering the top surface of the dummy gate structure 200. Specifically, silicon nitride is deposited on the dummy gate structure 200 and the substrate 100 using methods such as Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). Then, a portion of the deposited silicon nitride is etched away, leaving only the silicon nitride on the top surface of the dummy gate structure 200, thereby forming the first nitride layer 300. In this embodiment, the first nitride layers 300 formed on multiple dummy gate structures 200 have the same thickness. Next, an oxide layer 400 is formed on the first nitride layer 300. The oxide layer 400 can be formed by depositing silicon oxide using methods such as Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). In the step of forming oxide layer 400, during the deposition process, a portion of oxide layer 400 is deposited on the substrate 100 and the surface of dummy gate structure 200. Therefore, after the deposition process, the deposited material outside the surface of the first nitride layer 300 can be removed by dry etching. In this invention, the thickness of oxide layer 400 is inversely proportional to the width of dummy gate structure 200. In this embodiment, the thickness of oxide layer 400 above dummy gate structure 200 with a first width W1 is a third thickness H3, the thickness of oxide layer 400 above dummy gate structure 200 with a second width W2 is a second thickness H2, and the thickness of oxide layer 400 above dummy gate structure 200 with a first width W1 is a first thickness H1. The first thickness H1 is less than the second thickness H2, and the second thickness H2 is less than the third thickness H3. Then, a second nitride layer 500 is formed on the exposed surfaces of dummy gate structure 200, the first nitride layer 300, and the oxide layer 400. The second nitride layer 500 can be formed by depositing silicon nitride through chemical vapor deposition or plasma-enhanced chemical vapor deposition. It should be noted that in the step of forming the second nitride layer 500, the deposited material is partially deposited on the substrate 100, and after deposition, part of the deposited material on the substrate 100 is removed by dry etching.

[0048] Please see Figure 2 and Figure 3As shown, in this invention, after forming the second nitride layer 500, a dielectric layer 600 is then formed on the substrate 100 and the second nitride layer 500. The dielectric layer 600 located on the surface of the second nitride layer 500 is then removed, and the remaining dielectric layer 600 is defined as the first dielectric film 601a. ​​Specifically, silicon oxide is deposited on the substrate 100 and the surface of the second nitride layer 500 by chemical vapor deposition or plasma-enhanced chemical vapor deposition. Then, the dielectric layer 600 on the top surface of the second nitride layer 500 is removed by chemical mechanical polishing (CMP). In the step of removing the dielectric layer 600 on the top surface of the second nitride layer 500, a portion of the second nitride layer 500 can be removed, thereby ensuring that the top surface of the second nitride layer 500 above each dummy gate structure 200 is exposed.

[0049] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, after removing the dielectric layer 600 on the top surface of the second nitride layer 500, the entire second nitride layer 500 above the oxide layer 400 is etched away. In this embodiment, the entire second nitride layer 500 on the oxide layer 400 can be removed by wet etching. The etchant used in the wet etching can be a high-selectivity etchant, where the etching ratio of silicon nitride to silicon oxide is much higher than that of silicon oxide, thereby ensuring that the oxide layer 400 is not overly damaged when removing the second silicon nitride layer. In this step, the surface of the oxide layer 400 is exposed.

[0050] Please see Figure 4 and Figure 5As shown, in one embodiment of the present invention, after removing the second nitride layer 500 from the top surface of the oxide layer 400, the oxide layer 400, the second nitride layer 500, and the first dielectric film 601a are polished, using the first nitride layer 300 as a stop layer, until the top surface of the first nitride layer 300 above all the pseudo-gate structures 200 is exposed. After polishing, the top surfaces of the first nitride layer 300, the second nitride layer 500, and the first dielectric film 601a are flush. During the polishing step, the thicker oxide layer 400 will contact the polishing surface first, followed by the thinner oxide layer 400. For example, in this embodiment, the oxide layer 400 with a third thickness H3 will contact the polishing surface first, followed by the oxide layer 400 with a second thickness H2, and then the oxide layer 400 with a first thickness H1. During the polishing step, the polishing speed of the first dielectric film 601a is higher than that of the nitride layer. In this embodiment, after the etching step, due to the etching selectivity, the top height of the first dielectric film 601a is higher than the surface height of the second nitride layer 500, while the height of the second nitride layer 500 is lower than or equal to the height of the oxide layer 400. Furthermore, the top height of the second nitride layer 500 is higher than the surface of the first nitride layer 300. During the polishing step, during the etching process, the first dielectric film 601a and the oxide layer 400 first come into contact with the polishing surface and are removed, followed by the second nitride layer 500. This continues until all of the oxide layer 400 is removed, exposing the first nitride layer 300. Then, the second nitride layer 500 is polished until its surface is flush with the surface of the first nitride layer 300. After the polishing step, the dielectric material covering the surface of the substrate 100 remains unaffected.

[0051] Please see Figures 5 to 7As shown, in one embodiment of the present invention, after removing the oxide layer 400, a first dielectric deposition layer 602a is then formed on the first nitride layer 300, the first dielectric film 601a, and the second nitride layer 500, until the first dielectric deposition layer 602a located between adjacent pseudo-gate structures 200 is higher than the surface of the first nitride layer 300. Silicon oxide can be deposited on the first nitride layer 300, the first dielectric film 601a, and the second nitride layer 500 by chemical vapor deposition or plasma-enhanced chemical vapor deposition. The first dielectric deposition layer 602a and the first dielectric film 601a are made of the same material, and after deposition, the first dielectric deposition layer 602a and the first dielectric film 601a are connected and form a single unit. During deposition, the dielectric material covers the first nitride layer 300 and the second nitride layer 500. Then, polishing removes a portion of the first dielectric deposition layer 602a until the surfaces of the first dielectric deposition layer 602a, the second nitride layer 500, and the first nitride layer 300 are flush. In the polishing step, only the dielectric material is removed, so the grinding rate is balanced, which ensures that the surfaces of the first dielectric deposition layer 602a, the first nitride layer 300, and the second nitride layer 500 are flush.

[0052] Please see Figure 7 and Figure 8 As shown, in one embodiment of the present invention, after obtaining the first dielectric deposition layer 602a, the surface of the dummy gate structure 200 is used as a stop layer to polish and remove the first nitride layer 300, a portion of the second nitride layer 500, and a portion of the first dielectric deposition layer 602a. The second nitride layer 500 has a smaller thickness. The first nitride layer 300 and the second nitride layer 500 are made of the same material, so polishing can obtain dummy gate structure 200, second nitride layer 500, and first dielectric deposition layer 602a of equal height. Based on the semiconductor structure obtained in this embodiment, a high-k metal gate structure can be formed by subsequently etching to remove the polysilicon layer in the dummy gate structure 200, replacing the polysilicon layer, and depositing metal material.

[0053] Please see Figure 3 and Figure 9As shown, in another embodiment of the present invention, after forming the dielectric layer 600, a portion of the dielectric layer 600 located on the second nitride layer 500 is etched away, and a portion of the second nitride layer 500 and a portion of the dielectric layer 600 located at the top corner of the dummy gate structure 200 are also removed, thereby increasing the deposition window size between adjacent dummy gate structures 200 and forming a second dielectric film 601b. In this embodiment, the etching of the portion of the dielectric layer 600 and the second nitride layer 500 can be done using dry etching, and different plasma gases can be used to first remove the dielectric layer 600 located on top of the dummy gate structure 200, and then remove a portion of the second nitride layer 500 and a portion of the dielectric layer 600 located at the top corner of the dummy gate structure 200, forming a chamfer structure at the corner of the dummy gate structure 200. During subsequent deposition of dielectric materials, the chamfer structure facilitates the formation of a dielectric deposition layer without internal bubbles or voids.

[0054] Please see Figures 9 to 11 As shown, in another embodiment of the present invention, after forming the chamfered structure, a second dielectric deposition layer 602b is then formed on the second dielectric film 601b and the second nitride layer 500. Using the second nitride layer 500 as a stop layer, a portion of the second dielectric deposition layer 602b is polished away. Then, using the oxide layer 400 as a stop layer, a portion of the second nitride layer 500 is polished away. In this embodiment, in the step of forming the second dielectric deposition layer 602b, silicon oxide is deposited by chemical vapor deposition until the deposition height of the silicon oxide material is greater than the maximum height of the dummy gate structure 200. After two polishing operations, due to the loading effect, the surfaces of the dummy gate structures 200 with different widths, and the dummy gate structures 200 located in the dense region and the gate region, are not flush. Furthermore, in the dense region, the larger the width of the dummy gate structure 200, the higher the surface height of the oxide layer 400 after polishing.

[0055] Please see Figures 11 to 13 As shown, in another embodiment of the present invention, the first nitride layer 300 is used as a stop layer, and the oxide layer 400, a portion of the second dielectric deposition layer 602b, and a portion of the second nitride layer 500 are removed by polishing. After polishing, the surfaces of the second nitride layer 500, the first nitride layer 300, and the second dielectric deposition layer 602b are flush. Next, the second nitride layer 500 is removed by polishing. After removing the second nitride layer 500, the surfaces of the dummy gate structure 200, the second nitride layer 500, and the second dielectric deposition layer 602b are flush, resulting in a semiconductor structure. Based on the semiconductor structure obtained in this embodiment, a high-k metal gate structure can be formed by subsequently etching away the polysilicon layer in the dummy gate structure 200, replacing the polysilicon layer, and depositing metal material.

[0056] This invention provides a method for manufacturing a semiconductor structure and the semiconductor structure itself. The manufacturing method includes: providing a plurality of dummy gate structures disposed on a substrate; forming a first nitride layer on the top surface of the dummy gate structures; forming an oxide layer on the first nitride layer, wherein the wider the dummy gate structure, the thinner the oxide layer on the dummy gate structure; forming a second nitride layer on the exposed surfaces of the oxide layer, the first nitride layer, and the dummy gate structures; forming a dielectric layer on the first nitride layer and the substrate; sequentially removing the dielectric layer, the second nitride layer, and the oxide layer on the dummy gate structures until the surfaces of the first nitride layer and the second nitride layer are flush; and removing the first nitride layer and a portion of the second nitride layer to make the surfaces of the first nitride layer and the dummy gate structures flush. The unexpected technical effect of this invention is that the manufacturing method for forming a high-K metal gate provided by this invention can overcome the loading effect, form a metal gate with high surface flatness, and simultaneously reduce the possibility of defects such as voids and bubbles in the metal gate forming process, thereby improving the effectiveness of the semiconductor structure and the forming yield of the semiconductor process.

[0057] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Multiple pseudo-gate structures are provided, and the pseudo-gate structures are disposed on a substrate; A first nitride layer is formed on the top surface of the pseudo-gate structure, and an oxide layer is formed on the first nitride layer, wherein the wider the pseudo-gate structure, the smaller the thickness of the oxide layer on the pseudo-gate structure; A second nitride layer is formed on the exposed surfaces of the oxide layer, the first nitride layer, and the pseudo-gate structure; A dielectric layer is formed on the first nitride layer and on the substrate; Remove a portion of the dielectric layer and a portion of the second nitride layer on the pseudo-gate structure to expose the oxide layer, and then use a polishing process to remove the remaining portion of the dielectric layer, a portion of the second nitride layer, and the oxide layer until the surfaces of the first nitride layer and the second nitride layer are flush; as well as Remove the first nitrided layer and part of the second nitrided layer so that the surface of the second nitrided layer and the pseudo-gate structure are flush.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, When removing part of the dielectric layer and part of the second nitride layer on the dummy gate structure, the dielectric layer on the top surface of the second nitride layer is first removed by a polishing process to expose the top surface of the second nitride layer above the dummy gate structure. Then, the second nitride layer located on the oxide layer is removed by wet etching until the surface of the oxide layer is exposed.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, After exposing the surface of the oxide layer, the oxide layer, part of the second nitride layer, and part of the dielectric layer are removed by polishing, using the first nitride layer as the stop layer.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, Before removing the first nitride layer, a dielectric deposition layer is formed on the first nitride layer, the second nitride layer, and the dielectric layer until the dielectric deposition layer located between adjacent pseudo-gate structures is above the surface of the first nitride layer.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, In the step of removing the first nitride layer and a portion of the second nitride layer, the first nitride layer is used as a stop layer to polish and remove a portion of the dielectric deposition layer. The surface of the dummy gate structure is used as a stop layer to remove the first nitride layer, a portion of the second nitride layer, and a portion of the dielectric deposition layer. In the obtained semiconductor structure, the surfaces of the second nitride layer, the dielectric deposition layer, and the dummy gate structure are flush.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After the dielectric layer is formed, the dielectric layer located on top of the pseudo-gate structure is removed, and a portion of the second nitride layer and a portion of the dielectric layer located at the corners of the pseudo-gate structure are removed.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, After removing a portion of the dielectric layer located on the dummy gate structure, and before polishing to remove the remaining second nitride layer located on the dummy gate structure, a dielectric deposition layer is formed on the dielectric layer and the second nitride layer, wherein the surface of the dielectric deposition layer located between adjacent dummy gate structures is higher than the surface of the second nitride layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, After the dielectric deposition layer is formed, a portion of the dielectric deposition layer, a portion of the second nitride layer located on the pseudo-gate structure, and a portion of the dielectric layer are polished away until the surface of the oxide layer is exposed.

9. A method for manufacturing a semiconductor structure according to claim 8, characterized in that, After exposing the oxide layer, the oxide layer, a portion of the second nitride layer, a portion of the dielectric deposition layer, and a portion of the dielectric layer are polished away using the first nitride layer as a stop layer. Then, the first nitride layer, a portion of the second nitride layer, a portion of the dielectric deposition layer, and a portion of the dielectric layer are polished away using the surface of the dummy gate structure as a stop layer, to obtain the semiconductor structure. In the obtained semiconductor structure, the surfaces of the second nitride layer, the dielectric deposition layer, the dummy gate structure, and the dielectric layer are flush.

10. A semiconductor structure, based on a method for manufacturing a semiconductor structure according to any one of claims 1-9, characterized in that, include: substrate; Multiple pseudo-gate structures are disposed on the substrate; A second nitriding layer covers the side of the pseudo-gate structure; as well as A dielectric deposition layer is disposed on the substrate and fills the space between adjacent pseudo-gate structures, wherein the top surface of the pseudo-gate structure, the top surface of the second nitride layer, and the top surface of the dielectric deposition layer are flush.

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