Semiconductor package with two or more drivers

Abstract

A semiconductor package includes a lead frame, two or more low side field effect transistors (FETs), two or more high side FETs, two or more metal clips, a metal block, an integrated circuit (IC) controller, and a molded package. The method has the advantages that the DrMOS is jointly packaged in a single package, the packaging size is reduced, and the impedance is reduced.

Description

Technical Field

[0001] This invention generally relates to a semiconductor package. More specifically, this invention relates to a semiconductor package having two or more drivers. Background Technology

[0002] Traditional circuits that power a central processing unit (CPU) or graphics processing unit (GPU) consist of multiple driver metal-oxide-semiconductor (DrMOS) circuits. These DrMOS circuits take up space and add impedance.

[0003] U.S. Patent No. 11,094,617 (Xue et al.) discloses a size-reduced (from 5 mm × 6 mm to 5 mm × 5 mm) buck-boost power controller comprising at least four field-effect transistors (FETs) packaged in a single package. This invention further reduces the size to 5 mm × 4 mm by using a common Vcc pin, TMON pin, AGND pin, and PVcc pin. Summary of the Invention

[0004] This invention discloses a semiconductor package, comprising:

[0005] A lead frame includes: a first chip pad; and a second chip pad;

[0006] Two or more low-side field-effect transistors (FETs), wherein each of the two or more low-side FETs is flipped and connected to the first chip pad, each of the two or more low-side FETs includes a source electrode and a gate electrode located on the top surface of each of the two or more low-side FETs, and each of the two or more low-side FETs includes a drain electrode located on the bottom surface of each of the two or more low-side FETs;

[0007] Two or more high-side FETs, wherein each of the two or more high-side FETs is connected to the second chip pad, and each of the two or more high-side FETs includes a source electrode and a gate electrode located on the top surface of each of the two or more high-side FETs;

[0008] Two or more metal clips, wherein each of the two or more metal clips connects the drain electrode of a corresponding low-side FET of the two or more low-side FETs to the source electrode of a corresponding high-side FET of the two or more high-side FETs;

[0009] A metal block is located above the two or more metal clips, wherein each of the two or more metal clips is connected to the metal block;

[0010] An integrated circuit (IC) controller is located above the two or more metal clips; and

[0011] A molded package encapsulates the two or more low-side FETs, the two or more high-side FETs, the two or more metal clips, most of the metal block, the IC controller, and most of the lead frame.

[0012] Specifically, a first significant portion of the bottom surface of the first chip pad is exposed from the molded package; a second significant portion of the bottom surface of the second chip pad is exposed from the molded package; and the top surface of the metal block is exposed from the molded package.

[0013] The semiconductor package also includes multiple bonding wires;

[0014] The lead frame also includes multiple pins;

[0015] The plurality of bonding wires connect the IC controller to the plurality of pins; and

[0016] The molded package further encapsulates the plurality of bonding wires.

[0017] The first chip pad includes two or more chip pad portions and one or more connection portions;

[0018] Each of the one or more connection portions is located between a first corresponding chip pad portion and a second corresponding chip pad portion of the two or more chip pad portions; and

[0019] Each of the one or more connection portions is top-etched such that the thickness of each of the one or more connection portions is less than the thickness of the first corresponding chip pad portion of the two or more chip pad portions.

[0020] The thickness of each of the one or more connection portions is 50% of the thickness of the first corresponding chip pad portion.

[0021] Each of the one or more connecting portions includes one or more slots; and

[0022] Each of the one or more connecting portions has one or more slots filled with a molded encapsulation.

[0023] The second chip pad includes two or more chip pad portions and one or more connection portions:

[0024] Each of the one or more connection portions is located between a first corresponding chip pad portion and a second corresponding chip pad portion of the two or more chip pad portions; and

[0025] Each of the one or more connecting portions has a groove etched into its bottom;

[0026] The groove is filled with a molded package; and

[0027] The thickness of each of the one or more connection portions is less than the thickness of the first corresponding chip pad portion of the two or more chip pad portions.

[0028] The semiconductor package also includes two or more drivers;

[0029] Each of the two or more drives mentioned herein includes:

[0030] The corresponding low-side FETs of the two or more low-side FETs;

[0031] The corresponding high-side FETs of the two or more high-side FETs; and

[0032] The corresponding metal clips of the two or more metal clips.

[0033] Each of the two or more drivers is connected to the same Vcc pin, the same TMON pin, the same AGND pin, and the same PVcc pin.

[0034] The metal block and the IC controller are connected to the two or more metal clips via non-conductive epoxy resin.

[0035] The present invention also discloses a method for manufacturing a semiconductor package. The method includes the following steps: providing a lead frame including chip pads; connecting transistors to the chip pads respectively; mounting metal clips; mounting a metal block and a controller; applying bonding wires; forming a molded package; and applying a dicing process.

[0036] This invention encapsulates DrMOS within a single package to reduce package size and lower impedance. Furthermore, by using common Vcc, TMON, AGND, and PVcc pins, the size is further reduced to 5 mm × 4 mm. Attached Figure Description

[0037] Figure 1 A schematic diagram showing a traditional circuit that provides power to a CPU or GPU.

[0038] Figure 2A This is a top perspective view of a semiconductor package, as shown in the example of the present invention. Figure 2B This indicates its bottom perspective view.

[0039] Figure 3 This represents a top perspective view of another semiconductor package in an example of the present invention.

[0040] Figure 4 This illustrates a process flow diagram for developing semiconductor packaging, as shown in the example of this invention.

[0041] Figure 5A , 5B 5C, 5D, 5E, 5F, 5G, 5H, 5I, and 5J represent perspective views of various steps in manufacturing a semiconductor package in the examples of the present invention. Detailed Implementation

[0042] Figure 1 This is a schematic diagram of a circuit 100 that provides power to a CPU or GPU 110. Circuit 100 includes a first DrMOS 122, a second DrMOS 124, and a controller 130. An advantage of this invention is that the DrMOS components are co-packaged in a single package, reducing package size and impedance.

[0043] Figure 2A This is a top perspective view of the semiconductor package 200 in the example of this invention. Figure 2B This is a bottom perspective view. The semiconductor package 200 includes a lead frame 220, such as... Figure 5C The two or more low-side field-effect transistors (FETs) 540 shown, such as Figure 5C The two or more high-side FETs 550 shown, such as Figure 5E The two or more metal clips 560 and metal blocks 280 shown are as follows: Figure 5G The integrated circuit (IC) controller 582 and the molded package 290 are shown.

[0044] The lead frame 220 includes, for example, Figure 5A The first chip pad 522 shown and as follows Figure 5A The second chip pad 524 is shown. In one example, the top of the first chip pad 522 is etched to form one or more cavities 523, which are filled with the molded package 290. In another example, the bottom of the second chip pad 524 is etched to form one or more recesses, including... Figure 5AThe recess 525 shown is filled with the molded package 290. In an example of the invention, the lead frame 220 includes one or more slots 529 filled with the molded package 290 to facilitate a locking mechanism, thereby improving the integration of the lead frame 220 and the molded package 290.

[0045] like Figure 5C As shown, each of the two or more low-side FETs 540 is flipped and connected to the first chip pad 522. Each of the two or more low-side FETs 540 includes a source electrode 541 and a gate electrode 543 located on the top surface of each of the two or more low-side FETs 540. Each of the two or more low-side FETs 540 includes a drain electrode 547 located on the bottom surface of each of the two or more low-side FETs 540.

[0046] Each of the two or more high-side FETs 550 is connected to a second chip pad 524. Each of the two or more high-side FETs 550 includes a source electrode 551 and a gate electrode 553 located on the top surface of each of the two or more high-side FETs 550.

[0047] Each of the two or more metal clips 560 connects the drain electrode 547 of the corresponding low-side FET of the two or more low-side FETs 540 to the source electrode 551 of the corresponding high-side FET of the two or more high-side FETs 550.

[0048] Metal block 280 is mounted above two or more metal clips 560, optionally above two or more low-side FETs 540. Each of the two or more metal clips 560 is connected to metal block 280.

[0049] IC controller 582 is mounted above two or more metal clips 560, optionally above two or more high-side FETs 550.

[0050] The molded package 290 encapsulates two or more low-side FETs 540, two or more high-side FETs 550, two or more metal clips 560, a first majority portion of a metal block 280, an IC controller 582, and a second majority portion of a lead frame 220. In this example of the invention, the first majority portion refers to a percentage greater than 50%. The second majority portion refers to a percentage greater than 50%.

[0051] A first significant portion of the bottom surface of the first chip pad 522 is exposed from the molded package 290. A second significant portion of the bottom surface of the second chip pad 524 is exposed from the molded package 290. In this example of the invention, the first significant portion refers to a portion greater than 90%. The second significant portion refers to a portion greater than 90%. The top surface of the metal block 280 is exposed from the molded package 290.

[0052] In an example of the present invention, the semiconductor package 200 further includes, for example, Figure 5H Multiple bonding wires 589 are shown. The lead frame 220 also includes, as shown... Figure 5G Multiple pins 287 are shown. Multiple bonding wires 589 connect the IC controller 582 to the multiple pins 287. The molded package 290 also encapsulates the multiple bonding wires 589.

[0053] The first chip pad includes, for example: Figure 5A The diagram shows two or more chip pad portions 531 and one or more connection portions 533. Although Figure 5A Only the first corresponding chip pad portion 532 and the second corresponding chip pad portion 534 are shown; the number of two or more chip pad portions 531 may vary. Each of one or more connection portions 533 is located between the first corresponding chip pad portion 532 and the second corresponding chip pad portion 534 of the two or more chip pad portions 531. Each of one or more connection portions 533 is top-etched such that the thickness of each of the one or more connection portions 533 is less than the thickness of the first corresponding chip pad portion 532 of the two or more chip pad portions 531. In the example of the invention, the thickness of each of the one or more connection portions 533 is 50% of the thickness of the first corresponding chip pad portion 532.

[0054] Each of the one or more connection portions 533 includes one or more slots 529. The one or more slots 529 of each of the one or more connection portions 533 are filled with a molded package 290.

[0055] The second chip pad 524 includes two or more chip pad portions 537 and one or more connection portions 539. One or more connection portions 539 of each connection portion are located between a first corresponding chip pad portion 536 and a second corresponding chip pad portion 538 of the two or more chip pad portions 537. A groove 525 is etched into the bottom of the one or more connection portions 539 of each connection portion. The groove 525 is filled with a molded package 290. The thickness of the one or more connection portions 539 of each connection portion is less than the thickness of the first corresponding chip pad portion 536 of the two or more chip pad portions 537.

[0056] A semiconductor package includes two or more drivers. In one example, Figure 2A The semiconductor package 200 includes, for example, Figure 5G The first driver 597 shown and as Figure 5G The second driver 599 is shown. In another example, Figure 3 The semiconductor package 300 includes a first driver 391, a second driver 393, a third driver 395, and a fourth driver 397. Each of the two or more drivers in the semiconductor package 200 includes two or more low-side FETs 540 of a corresponding low-side FET, two or more high-side FETs 550 of a corresponding high-side FET, and corresponding metal clips of two or more metal clips 560. Each of the two or more drivers is connected to, for example, Figure 5G The same Vcc pin 501, the same TMON pin 503, the same AGND pin 505, and the same PVcc pin 507 are shown to reduce the width of the semiconductor package 200 (from 5 mm × 5 mm to 5 mm × 4 mm).

[0057] Figure 4 This is a flowchart illustrating a semiconductor packaging process 400 in an example of the present invention. Process 400 can begin at step 402.

[0058] In step 402, refer to Figure 5A A leadframe 220 is provided. The leadframe 220 includes a first chip pad 522 and a second chip pad 524. In one example, the top of the first chip pad 522 is etched to form one or more cavities 523, which are filled with a molded package 290. In another example, the bottom of the second chip pad 524 is etched to form one or more recesses, including recesses 525, which are filled with the molded package 290. In examples of this disclosure, the leadframe 220 includes one or more slots 529, which are filled with the molded package 290 to facilitate a locking mechanism, thereby improving the integration of the leadframe 220 and the molded package 290.

[0059] The first chip pad includes two or more chip pad portions 531 and one or more connection portions 533. Although Figure 5AOnly the first corresponding chip pad portion 532 and the second corresponding chip pad portion 534 are shown; the number of two or more chip pad portions 531 may vary. Each of the one or more connection portions 533 is located between the first corresponding chip pad portion 532 and the second corresponding chip pad portion 534 of the two or more chip pad portions 531. Each of the one or more connection portions 533 is top-etched such that the thickness of each of the one or more connection portions 533 is less than the thickness of the first corresponding chip pad portion 532 of the two or more chip pad portions 531. In the example of the invention, the thickness of each of the one or more connection portions 533 is 50% of the thickness of the first corresponding chip pad portion 532.

[0060] Each of the one or more connection portions 533 includes one or more slots 529. The one or more slots 529 of each of the one or more connection portions 533 are filled with a molded package 290.

[0061] The second chip pad 524 includes two or more chip pad portions 537 and one or more connection portions 539. Each of the one or more connection portions 539 is located between a first corresponding chip pad portion 536 and a second corresponding chip pad portion 538 of the two or more chip pad portions 537. Each of the one or more connection portions 539 has a bottom-etched recess 525. The recess 525 is filled with a molded package 290. The thickness of each of the one or more connection portions 539 is less than the thickness of the first corresponding chip pad portion 536 of the two or more chip pad portions 537. Step 402 may be followed by step 404.

[0062] In step 404, refer to Figure 5B and 5C Two or more low-side FETs 540 are connected to a first chip pad 522 via a printed solder material layer 549, and two or more high-side FETs 550 are connected to a second chip pad 524. For example... Figure 5C Each of the two or more low-side FETs 540 shown is flipped and connected to the first chip pad 522. Each of the two or more low-side FETs 540 includes a source electrode 541 and a gate electrode 543 located on the top surface of each of the two or more low-side FETs 540. Each of the two or more low-side FETs 540 includes a drain electrode 547 located on the bottom surface of each of the two or more low-side FETs 540.

[0063] Each of the two or more high-side FETs 550 is connected to a second chip pad 524. Each of the two or more high-side FETs 550 includes a source electrode 551 and a gate electrode 553 located on the top surface of each of the two or more high-side FETs 550. Step 404 may be followed by step 406.

[0064] In step 406, refer to Figure 5D and 5E Two or more metal clips are mounted by distributing solder material layer 559. Each of the two or more metal clips 560 connects the drain electrode 547 of the corresponding low-side FET of the two or more low-side FETs 540 to the source electrode 551 of the corresponding high-side FET of the two or more high-side FETs 550. Step 406 may be followed by step 408.

[0065] In step 408, refer to Figure 5F and 5G A metal block 280 and an IC controller 582 are mounted on two or more metal clips 560 via a non-conductive epoxy resin layer 579. Optionally, the metal block 280 can be mounted above two or more low-side FETs 540. Each of the two or more metal clips 560 is connected to the metal block 280. The IC controller 582 is located above two or more high-side FETs 550. Optionally, the IC controller 582 can be connected to each of the two or more metal clips 560. Step 408 can be followed by step 410.

[0066] In step 410, refer to Figure 5H Install and connect multiple bonding wires 589. The multiple bonding wires 589 connect the IC controller 582 to multiple pins 287 of the lead frame 220. Step 410 can be followed by step 412.

[0067] In step 412, refer to Figure 5I This forms a molded package 290. The molded package 290 encapsulates two or more low-side FETs 540, two or more high-side FETs 550, two or more metal clips 560, a majority portion of a metal block 280, an IC controller 582, and a majority portion of a lead frame 220. In one example, the molded package 290 also encapsulates a plurality of bonding wires 589. In examples of the invention, "majority" refers to a portion greater than 50%.

[0068] A first significant portion of the bottom surface of the first chip pad 522 is exposed from the molded package 290. A second significant portion of the bottom surface of the second chip pad 524 is exposed from the molded package 290. In this example of the invention, the first significant portion refers to a portion greater than 90%. The second significant portion refers to a portion greater than 90%. The top surface of the metal block 280 is exposed from the molded package 290. Step 412 may be followed by step 414.

[0069] In step 414, refer to Figure 5J The semiconductor package 200 is separated from the adjacent semiconductor packages 201 and 203 by applying the cutting process 209.

[0070] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the number of leads may vary. Other modifications can be made by those skilled in the art, and all such modifications are considered to be within the scope of the invention as defined in the claims.

Claims

1. A semiconductor package, characterized in that, include: A lead frame comprising: A first chip pad; and A second chip pad; Two or more low-side FETs, wherein each of the two or more low-side FETs is flipped and connected to the first chip pad, each of the two or more low-side FETs includes a source electrode and a gate electrode located on the top surface of each of the two or more low-side FETs, and each of the two or more low-side FETs includes a drain electrode located on the bottom surface of each of the two or more low-side FETs; Two or more high-side FETs, wherein each of the two or more high-side FETs is connected to the second chip pad, and each of the two or more high-side FETs includes a source electrode and a gate electrode located on the top surface of each of the two or more high-side FETs; Two or more metal clips, wherein each of the two or more metal clips connects the drain electrode of a corresponding low-side FET of the two or more low-side FETs to the source electrode of a corresponding high-side FET of the two or more high-side FETs; A metal block is located above the two or more metal clips, wherein each of the two or more metal clips is connected to the metal block; An IC controller is located above the two or more metal clips; and A molded package encapsulates the two or more low-side FETs, the two or more high-side FETs, the two or more metal clips, most of the metal block, the IC controller, and most of the lead frame.

2. The semiconductor package according to claim 1, characterized in that, A first significant portion of the bottom surface of the first chip pad is exposed from the molded package; a second significant portion of the bottom surface of the second chip pad is exposed from the molded package; and the top surface of the metal block is exposed from the molded package.

3. The semiconductor package according to claim 1, characterized in that, It also includes multiple bond wires; The lead frame also includes multiple pins; The plurality of bonding wires connect the IC controller to the plurality of pins; and The molded package further encapsulates the plurality of bonding wires.

4. The semiconductor package according to claim 1, characterized in that, The first chip pad includes two or more chip pad portions and one or more connection portions; Each of the one or more connection portions is located between a first corresponding chip pad portion and a second corresponding chip pad portion of the two or more chip pad portions; and Each of the one or more connection portions is top-etched such that the thickness of each of the one or more connection portions is less than the thickness of the first corresponding chip pad portion of the two or more chip pad portions.

5. The semiconductor package according to claim 4, characterized in that, The thickness of each of the one or more connection portions is 50% of the thickness of the first corresponding chip pad portion.

6. The semiconductor package of claim 4, characterized in that, Each of the one or more connecting portions includes one or more slots; and Each of the one or more connecting portions has one or more slots filled with a molded encapsulation.

7. The semiconductor package of claim 1, characterized in that, The second chip pad includes two or more chip pad portions and one or more connection portions: Each of the one or more connection portions is located between a first corresponding chip pad portion and a second corresponding chip pad portion of the two or more chip pad portions; and Each of the one or more connecting portions has a groove etched into its bottom; The groove is filled with a molded package; and The thickness of each of the one or more connection portions is less than the thickness of the first corresponding chip pad portion of the two or more chip pad portions.

8. The semiconductor package of claim 1, characterized in that, It also includes two or more drives; Each of the two or more drives mentioned herein includes: The corresponding low-side FETs of the two or more low-side FETs; The corresponding high-side FETs of the two or more high-side FETs; and The corresponding metal clips of the two or more metal clips.

9. The semiconductor package of claim 8, characterized in that, Each of the two or more drivers is connected to the same Vcc pin, the same TMON pin, the same AGND pin, and the same PVcc pin.

10. The semiconductor package of claim 1, characterized in that, The metal block and the IC controller are connected to the two or more metal clips via non-conductive epoxy resin.

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