Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate body and a circuit function layer located on one side of the substrate body. The circuit function layer comprises a plurality of transistors, and the plurality of transistors comprise driving transistors; a channel region of the driving transistor comprises at least two active layers; in the first direction, the at least two active layers are stacked and connected in sequence; the first direction is the direction from the substrate to the circuit function layer; the channel region comprises a first channel region and a second channel region which are connected along a second direction, and the length of the first channel region is smaller than that of the second channel region along a third direction; the second direction and the third direction intersect and are parallel to the plane where the substrate is located. According to the technical scheme, the area of the pixel circuit can be effectively compressed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] In an LED display panel, a pixel circuit is usually used to drive an LED to emit light. The area occupied by the pixel circuit is much larger than the area occupied by the LED. By compressing the area of the pixel circuit, the space utilization can be further improved, and the display resolution can be improved.

[0003] In the prior art, a pixel circuit usually includes a driving transistor and a switching transistor. The switching transistor is used to quickly switch the working state of the circuit, and the driving transistor is used to provide a stable current to drive the LED to emit light. In order to ensure the performance stability and reliability of the driving transistor and ensure the display effect, the driving transistor is usually provided with a long channel length, which results in that the driving transistor occupies a large area in the horizontal plane, which is the main factor affecting the area of the pixel circuit, and it is difficult to further compress the area of the pixel circuit. SUMMARY

[0004] The present application provides an array substrate and a display panel to further compress the area of the pixel circuit and improve the space utilization.

[0005] According to an aspect of the present application, an array substrate is provided, comprising:

[0006] a substrate and a circuit functional layer located on one side of the substrate; the circuit functional layer includes a plurality of transistors, and the plurality of transistors includes a driving transistor;

[0007] The channel region of the driving transistor includes at least two layers of active layers;

[0008] In the first direction, the at least two layers of active layers are stacked and connected in sequence; the first direction is the direction in which the substrate points to the circuit functional layer;

[0009] The channel region includes a first channel region and a second channel region connected in the second direction, and in the third direction, the length of the first channel region is less than the length of the second channel region; the second direction and the third direction intersect and are both parallel to the plane in which the substrate is located.

[0010] According to another aspect of the present application, a display panel is provided, comprising the array substrate provided by any one of the embodiments of the present application;

[0011] The display panel further includes a light-emitting layer located on the side of the circuit functional layer away from the substrate; the light-emitting layer includes a plurality of light-emitting elements, and the light-emitting elements are coupled to the driving transistor.

[0012] The technical scheme of the embodiment of the present application is characterized in that the channel region of the driving transistor in the pixel circuit comprises at least two layers of active layers, the at least two layers of active layers are stacked and connected in sequence along the direction in which the substrate points to the circuit functional layer, thus, the channel of the driving transistor can extend in the direction parallel to the substrate and in the direction intersecting the plane in which the substrate lies, forming a three-dimensional channel, so that the projected area of the channel region of the driving transistor on the substrate can be reduced, the area occupied by the driving transistor can be reduced, and the area of the pixel circuit can be effectively compressed. In addition, by setting the channel region of the driving transistor to comprise a first channel region and a second channel region connected along the second direction, and setting the length of the first channel region along the third direction to be smaller than the length of the second channel region along the third direction, the channel region of the driving transistor can have a notch at the connected corner of the first channel region and the second channel region, so that the electrical connection between different structures can be realized as needed at the notch, for example, the electrical connection between the gate of the driving transistor and other circuit structures can be realized, and the design of the multi-layer active layer of the driving transistor can avoid increasing the difficulty of circuit connection.

[0013] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0015] Figure 1 is a schematic diagram of a film layer structure of an active layer in an existing array substrate;

[0016] Figure 2 is a schematic diagram of a 2T1C pixel circuit;

[0017] Figure 3 is a schematic diagram of a partial film layer structure of an array substrate provided by the embodiment of the present application;

[0018] Figure 4 is Figure 3 is a schematic diagram of an enlarged structure of the channel region of the driving transistor in

[0019] Figure 5 is a schematic diagram of the cross-sectional structure of the array substrate along BB' in Figure 3

[0020] Figure 6 Figure 3 ​​A cross-sectional structure diagram of an array substrate intercepted along CC';

[0021] Figure 7 A three-dimensional structure diagram of a channel of a driving transistor in an array substrate provided by an embodiment of the present application;

[0022] Figure 8 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along BB';

[0023] Figure 9 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along CC';

[0024] Figure 10 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along CC';

[0025] Figure 11 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along CC';

[0026] Figure 12 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along BB';

[0027] Figure 13 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along CC';

[0028] Figure 14 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along CC';

[0029] Figure 15 A partial film layer structure diagram of another array substrate provided by an embodiment of the present application;

[0030] Figure 16 is along Figure 15 A cross-sectional structure diagram of an array substrate intercepted along DD';

[0031] Figure 17 is along Figure 15 A cross-sectional structure diagram of an array substrate intercepted along EE';

[0032] Figure 18 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along BB';

[0033] Figure 19 is along Figure 3 A cross-sectional structure diagram of another array substrate intercepted along CC';

[0034] Figure 20 is a schematic diagram of a 7T1C pixel circuit;

[0035] Figure 21 is a schematic diagram of another film layer structure of an array substrate provided by an embodiment of the present application;

[0036] Figure 22 is Figure 21 is a schematic diagram of a stack structure of a film layer where a first active layer, a second active layer and a third active layer are located;

[0037] Figure 23 is Figure 21 is a schematic diagram of a stack structure of a film layer where a first active layer is located and a first metal layer;

[0038] Figure 24 is Figure 21 is a schematic diagram of a stack structure of a film layer where a first active layer is located, a film layer where a second active layer is located and a second metal layer;

[0039] Figure 25 is Figure 21 is a schematic diagram of a stack structure of a film layer where a first active layer is located, a film layer where a third active layer is located and a third metal layer;

[0040] Figure 26 is a schematic diagram of a cross-sectional structure of an array substrate taken along JJ’ in Figure 21

[0041] Figures 27-44 is a manufacturing flow chart corresponding to the array substrate shown in Figure 26

[0042] Figure 45 is a schematic diagram of a structure of a display panel provided by an embodiment of the present application;

[0043] Figure 46 is a schematic diagram of another structure of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the personnel in the technical field better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should belong to the scope of protection of the present application.

[0045] ​​Various modifications and changes can be made to the present application without departing from the spirit and scope thereof. Accordingly, it is intended that the present application cover all modifications and changes as fall within the scope of the claims (technical solutions claimed) and their equivalents. It should be noted that the embodiments provided in the present application can be combined with each other if not contrary.

[0046] First of all, it should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present application should be understood as the usual meaning understood by a person with ordinary skills in the art to which the present application belongs. In the present application, the terms "first", "second" and the like do not represent any order, number or importance, but are only used to distinguish different components. "Include" and the like mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect. "Up", "down", "left" and "right" and the like are only used to represent relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, the shape and size of the components in the drawings do not reflect the true proportion, but only aim to illustrate the content of the present application.

[0047] Exemplary, Figure 1 is a schematic diagram of a film layer structure of an active layer in a prior art array substrate, as Figure 1 In the prior art, the channel of all transistors in a pixel circuit is formed in the same layer of active layer, Figure 1 The dashed box position in the figure represents the channel region of the driving transistor. As Figure 1 It can be seen that in the prior art, the channel length of the driving transistor is relatively long, resulting in a large area occupied by the driving transistor. Therefore, it is difficult to further compress the area of the pixel circuit.

[0048] To solve the above problems, the present application provides an array substrate and a display panel. The array substrate comprises a substrate and a circuit functional layer located on one side of the substrate; the circuit functional layer comprises a plurality of transistors, and the plurality of transistors comprises a driving transistor; the channel region of the driving transistor comprises at least two layers of active layers; the at least two layers of active layers are stacked and connected in sequence along a first direction; the first direction is the direction in which the substrate points to the circuit functional layer; the channel region comprises a first channel region and a second channel region connected along a second direction, and the length of the first channel region is smaller than the length of the second channel region along a third direction; the second direction and the third direction intersect and are both parallel to the plane in which the substrate is located.

[0049] By adopting the above scheme, the channel of the driving transistor extends in both the direction parallel to the substrate and the direction intersecting the plane where the substrate is located, forming a three-dimensional channel, so that the projection area of the channel region of the driving transistor on the substrate can be reduced, the area occupied by the driving transistor can be reduced, and the area of the pixel circuit can be effectively compressed. In addition, by arranging the channel region of the driving transistor to include the first channel region and the second channel region connected along the second direction, and arranging the length of the first channel region along the third direction to be smaller than the length of the second channel region along the third direction, a notch can be formed at the connected corner of the first channel region and the second channel region, so that the electrical connection between different structures can be realized as needed at the notch, for example, the electrical connection between the gate of the driving transistor and other circuit structures can be realized, and the design of the multi-layer active layer of the driving transistor avoids increasing the difficulty of circuit connection.

[0050] At present, the pixel circuit is mostly connected by a plurality of transistors (T) and a storage capacitor (C), and common circuit types include but are not limited to 2T1C pixel circuit and 7T1C pixel circuit. The following will take the 2T1C pixel circuit as an example, and in combination with the drawings, the design of the driving transistor according to the embodiments of the present application will be described in detail.

[0051] Figure 2 is a schematic diagram of a 2T1C pixel circuit, Figure 3 is a schematic diagram of a partial film layer structure of an array substrate provided by the embodiments of the present application, which specifically shows a layout structure corresponding to the pixel circuit shown in Figure 2 , and Figure 4 is a layout structure of the pixel circuit shown in Figure 3 , and Figure 5 is a schematic diagram of an enlarged structure of the channel region of the driving transistor in Figure 3 , and Figures 2-5 , the array substrate 100 provided by the embodiments of the present application includes a substrate 10 and a circuit functional layer 20 located on one side of the substrate 10; the circuit functional layer 20 includes a plurality of transistors, and the plurality of transistors includes a driving transistor T0; the channel region Q of the driving transistor T0 includes at least two layers of active layers 31; along a first direction D1, the at least two layers of active layers 31 are arranged in layers and are sequentially connected; the first direction Z is the direction in which the substrate 10 points to the circuit functional layer 20; the channel region Q includes a first channel region Q1 and a second channel region Q2 connected along a second direction D2, and along a third direction D3, the length of the first channel region Q1 is smaller than the length of the second channel region Q2; the second direction D2 and the third direction D3 intersect and are both parallel to the plane where the substrate 10 is located.

[0052] It should be noted that, Figure 5The active layers 31 in different layers are distinguished by different filling manners. In the embodiment, the materials of the active layers 31 are the same, including but not limited to monocrystalline silicon, polycrystalline silicon and metal oxide, and can be determined according to the type of the driving transistor required.

[0053] With reference to Figure 5 , in the embodiment, the channel region Q of the driving transistor T0 includes at least two layers of active layers 31 stacked one on another, each layer of the active layers 31 is not formed at one time but is prepared in multiple times (which will be exemplarily described later), and finally each layer of the active layers 31 is connected in sequence from bottom to top along the first direction D1 to form a three-dimensional channel. In this way, a part of the channel of the driving transistor extends in a direction intersecting the plane where the substrate is located, so that the length of the channel which needs to extend in a direction parallel to the plane where the substrate is located can be reduced, and further the projection area of the channel region of the driving transistor on the substrate can be reduced, the area occupied by the driving transistor can be reduced, and further the area of the pixel circuit can be compressed.

[0054] Exemplarily, Figure 5 Taking an example of three layers of active layers 31 connected in sequence from bottom to top to form an “S”-shaped channel, it is assumed that the inclination angle of the two sides of the “S”-shaped channel is 90° in the limit case, and under the condition that the total length of the channel is equal, the projection area of the channel region of the driving transistor on the substrate can be equal to about one third of that of a traditional channel design (such as Figure 1 ) using the technical solution of the embodiment of the present application, the area occupied by the driving transistor can be greatly reduced, and further the area of the pixel circuit can be reduced.

[0055] It should be noted that in other embodiments, the channel region of the driving transistor can include two layers of active layers or four or more layers of active layers, which are not limited in the embodiment of the present application. Too few layers of active layers have limited effect on compressing the area of the pixel circuit, and too many layers of active layers increase the design difficulty and manufacturing cost, and the embodiment of the present application adopts the design that the channel region of the driving transistor includes three layers of active layers, which can effectively compress the area of the pixel circuit while avoiding excessive increase of the design difficulty and manufacturing cost.

[0056] Further, with reference to Figure 4 , in the embodiment, the channel region Q includes a first channel region Q1 and a second channel region Q2 connected along the second direction D2, and along the third direction D3, the length of the first channel region Q1 is less than the length of the second channel region Q2.

[0057] Figure 4The middle dotted line represents the boundary line of the first channel region Q1 and the second channel region Q2, and the channel region Q is divided into the first channel region Q1 and the second channel region Q2 according to the length difference of the channel region Q in the third direction D3, the length of the first channel region Q1 in the third direction D3 is less than the length of the second channel region Q2 in the third direction D3. In this way, the channel region Q has a notch at the connecting corner of the first channel region Q1 and the second channel region Q2, which facilitates the electrical connection between the gate of the driving transistor and other circuit structures in the subsequent area (i.e. the notch region Q0 described below), and other electrical connections between structures can also be made as needed, avoiding the increase in the difficulty of circuit connection caused by the design of the multi-layer active layer of the driving transistor, which will be described in detail later.

[0058] The channel region Q of the driving transistor T0 can be understood as the projection area of the channel of the driving transistor T0 on the substrate. Specifically, in the embodiment, the channel of the driving transistor is arranged in at least two layers of active layers, Figure 3 The mark "310" represents a composite area (or joint area) formed by the projection area of all active layers of the driving transistor on the substrate, which is the area where the channel of the driving transistor is located, and is referred to as the channel region.

[0059] Based on the projection shape of the channel region Q, it can be understood that for any one layer of active layer 31 of the driving transistor, the projection shape is consistent with the projection shape of the channel region Q, and can be divided into two regions connected along the second direction D2, the length of the region corresponding to the first channel region Q1 in the third direction D3 is less than the length of the region corresponding to the second channel region Q2 in the third direction D3, and each layer of active layer 31 has a notch, and the notches of each layer of active layer are projected and overlapped in the first direction D1.

[0060] In summary, the technical scheme of the embodiment of the present application, by arranging the channel region of the driving transistor in the pixel circuit to include at least two layers of active layers, and arranging the at least two layers of active layers to be stacked and connected in sequence along the direction of the substrate to the circuit functional layer, the channel of the driving transistor can extend not only in the direction parallel to the substrate, but also in the direction intersecting the plane of the substrate, forming a three-dimensional channel, thereby reducing the projection area of the channel region of the driving transistor on the substrate, reducing the area occupied by the driving transistor, and effectively compressing the area of the pixel circuit. In addition, by arranging the channel region of the driving transistor to include a first channel region and a second channel region connected along the second direction, and arranging the length of the first channel region along the third direction to be less than the length of the second channel region along the third direction, the channel region of the driving transistor has a notch at the connecting corner of the first channel region and the second channel region, which facilitates the electrical connection between different structures as needed, such as the electrical connection between the gate of the driving transistor and other circuit structures, avoiding the increase in the difficulty of circuit connection caused by the design of the multi-layer active layer of the driving transistor.

[0061] Below, we will take the channel region Q of the driving transistor T0, which includes three active layers 31, as an example to further explain the design of the driving transistor.

[0062] Figure 6 It is along Figure 3 A schematic diagram of the cross-sectional structure of the array substrate taken from CC'. Figure 7 This is a three-dimensional structural diagram of the channel of the driving transistor in the array substrate provided in an embodiment of the present invention, combined with... Figures 5-7 As shown, optionally, at least two active layers 31 include a first active layer 311, a second active layer 312, and a third active layer 313; the second active layer 312 is located on the side of the first active layer 311 away from the substrate 10; the second active layer 312 includes a first active portion 3101 and a second active portion 3102, the second active portion 3102 being connected between the first active portion 3101 and the first active layer 311; the third active layer 313 is located on the side of the second active layer 312 away from the substrate 10; the third active layer 313 includes a third active portion 3103 and a fourth active portion 3104, the fourth active portion 3104 being connected between the first active portion 3101 and the third active portion 3104. Between 103; the plane where the second active portion 3102 is located intersects the plane where the fourth active portion 3104 is located; along the first direction D1 and the third direction D3, the second active portion 3102 and the fourth active portion 3104 are both located on opposite sides of the first active portion 3101; part of the orthographic projection of the second active portion 3102 on the substrate 10 is located in the first channel region Q1, and the other part is located in the second channel region Q2; the orthographic projection of the fourth active portion 3104 on the substrate 10 is located in the second channel region Q2; the planes where the first active layer 311, the first active portion 3101 and the third active portion 3103 are located are all parallel to the plane where the substrate 10 is located, and the three overlap along the first direction D1.

[0063] The overlap of the first active layer 311, the first active portion 3101, and the third active portion 3103 along the first direction D1 means that, along the first direction D1, the first active layer 311, the first active portion 3101, and the third active portion 3103 share a common overlapping area. (Refer to...) Figure 5 and Figure 6 Along the first direction Z, the portion of the first active layer 311 that overlaps with the first active portion 3101, and the portion of the third active portion 3103 that overlaps with the first active portion 3101, are mutually overlapping, and the three have a common overlapping area.

[0064] The plane where the second active sub-part 3102 is located intersects the plane where the substrate 10 is located, the plane where the fourth active sub-part 3104 is located intersects the plane where the substrate is located, and the plane where the second active sub-part 3102 and the fourth active sub-part 3104 are located intersects. In a specific implementation, refer to Figure 5 Optionally, the second active sub-part 3102 has an acute angle with the first active layer 311, the second active sub-part 3102 has an obtuse angle with the first active sub-part 3101, the fourth active sub-part 3104 has an acute angle with the first active sub-part 3101, and the fourth active sub-part 3104 has an obtuse angle with the third active sub-part 3103, so that the preparation difficulty can be reduced.

[0065] Refer to Figures 5-7 The planes where the first active layer 311, the first active sub-part 3101, and the third active sub-part 3103 are located are parallel to the plane where the substrate 10 is located. From bottom to top, the first active layer 311 and the first active sub-part 3101 are connected through the second active sub-part 3102, the first active sub-part 3101 and the second active sub-part 3102 belong to the second active layer 312, the first active sub-part 3101 and the third active sub-part 3103 are connected through the fourth active sub-part 3104, the third active sub-part 3103 and the fourth active sub-part 3104 belong to the third active layer 313, along the first direction D1, the fourth active sub-part 3104 and the second active sub-part 3102 are arranged on the upper and lower sides of the first active sub-part 3101, along the third direction D3, the fourth active sub-part 3104 and the second active sub-part 3102 are arranged on the left and right sides of the first active sub-part 3101, so that the first active layer 311, the second active layer 312, and the third active layer 313 can be sequentially connected, the driving transistor has a three-dimensional channel, and the area occupied by the driving transistor is reduced.

[0066] In addition, refer to Figures 5-7 In the embodiment, the fourth active sub-part 3104 for connecting the first active sub-part 3101 and the third active sub-part 3103 is close to the notch area Q0. In the embodiment, the orthographic projection of the fourth active sub-part 3104 on the substrate 10 is located only in the second channel area Q2, so that the preparation difficulty can be reduced, and the notch area Q0 is not arranged with an active layer, which is convenient for electrical connection between circuit structures. As for the second active sub-part 3102 between the first active sub-part 3101 and the first active layer 311, since the position is far away from the notch area Q0, a part of the second active sub-part 3102 is located in the first channel area Q1, and another part is located in the second channel area Q2.

[0067] In other embodiments, if the second active section 3102 is close to the gap region Q0 and the fourth active section 3104 is away from the gap region, the second active section 3102 can be arranged such that its orthographic projection on the substrate is located in the second channel region Q2, and the fourth active section 3104 can be arranged such that its orthographic projection on the substrate is partially located in the first channel region Q1 and partially located in the second channel region Q2.

[0068] As shown in Figure 5 and Figure 6 , optionally, in the array substrate 100, the circuit functional layer 20 further comprises a first insulating layer 201, a second insulating layer 202, a third insulating layer 203, a fourth insulating layer 204 and a fifth insulating layer 205; the first insulating layer 201 is partially located on the side of the first active layer 311 away from the substrate 10; the second insulating layer 202 is partially located between the second active layer 312 and the first insulating layer 201, and is connected with the first insulating layer 201 within the channel region Q; the third insulating layer 203 is partially located on the side of the second active layer 312 away from the second insulating layer 202; the fourth insulating layer 204 is partially located between the third active layer 313 and the third insulating layer 203, and is connected with the third insulating layer 203 within the channel region Q; and the fifth insulating layer 205 is partially located on the side of the third active layer 313 away from the fourth insulating layer 204, and is connected with the second insulating layer 202 within the channel region Q.

[0069] Specifically, referring to Figure 5 , in the embodiment, the first active layer 311, the second active layer 312 and the third active layer are sequentially connected to form an "S"-shaped channel layer, in other words, the channel layer can be understood as the whole formed by connecting all the active layers of the driving transistor T0. The "S"-shaped channel layer has an inner surface and an outer surface, taking the left profile of the "S" as the outer surface of the channel layer and the right profile of the "S" as the inner surface of the channel layer as examples, the first insulating layer 201, the second insulating layer 202 and the fifth insulating layer 205 are sequentially connected to cover at least part of the outer surface of the channel layer, and the third insulating layer 203 and the fourth insulating layer 204 are sequentially connected to cover the inner surface of the channel layer, so that the inner surface and the outer surface of the channel layer can be protected by the insulating layers, and the insulating layers can also be used as gate insulating layers.

[0070] It should be noted that the above-mentioned first insulating layer 201 is partially located on the side of the first active layer 311 away from the substrate 10, which can be specifically understood as that a part of the first insulating layer 201 is located on the side of the first active layer 311 away from the substrate 10, and another part of the first insulating layer 201 is located in other regions, for example, regions outside the region where the driving transistor is located. The arrangement of other insulating layers is the same as this, and will not be described in detail here.

[0071] Referring to Figure 5 and Figure 6Optionally, the driving transistor T0 further comprises at least one of the first gate 32 and the second gate 33. The second gate 33 comprises a first gate part 331 and a second gate part 332, the first gate part 331 is located between the first insulating layer 201 and the second insulating layer 202 between the first active layer 311 and the first active part 3101, at least part of the second gate part 332 is located on one side of the fifth insulating layer 205 away from the third active part 3103, and the first gate part 331 and the second gate part 332 are electrically connected. The first gate 32 comprises a third gate part 321, at least part of the third gate part 321 is located between the third insulating layer 203 and the fourth insulating layer 204 between the first active part 3101 and the third active part 3103.

[0072] With reference to Figure 5 The first gate 32 specifically refers to a gate located on one side of the inner surface of the channel layer, and at least part of the first gate 32 is insulated from the channel layer by the third insulating layer 203 and the fourth insulating layer 204.

[0073] With reference to Figure 5 The second gate 33 specifically refers to a gate located on one side of the outer surface of the channel layer, and the second gate 33 is insulated from the channel layer by the first insulating layer 201, the second insulating layer 202 and the fifth insulating layer 205.

[0074] The driving transistor T0 comprises at least one of the first gate 32 and the second gate 33, and can adopt any one of the following three setting modes: the first setting mode, the driving transistor T0 only comprises the first gate 32; the second setting mode, the driving transistor T0 only comprises the second gate 33; the third setting mode, the driving transistor T0 comprises both the first gate 32 and the second gate 33. For the first two setting modes, the driving transistor only sets a gate on one side of the channel layer, at this time, the driving transistor is a single-gate transistor, and for the third setting mode, the opposite sides of the channel layer of the driving transistor are both provided with a gate, at this time, the driving transistor is a double-gate transistor, which is beneficial to further improve the performance of the driving transistor. Herein, the driving transistor T0 comprises both the first gate 32 and the second gate 33 is taken as an example for description.

[0075] The third gate portion 321 in the first gate 32 is at least partially located between the third insulating layer 203 and the fourth insulating layer 204 between the first active portion 3101 and the third active portion 3103. Specifically, the planes containing the first active portion 3101 and the third active portion 3103 are both parallel to the plane of the substrate, and at least a portion of the first gate 32 is located between the third insulating layer 203 and the fourth insulating layer 204 between the first active portion 3101 and the third active portion 3103. In other words, the third gate portion 321 has at least a portion parallel to the plane of the substrate, and this portion is located between the third insulating layer 203 and the fourth insulating layer 204. Specifically, the entire third gate portion 321 may be parallel to the plane of the substrate and located between the third insulating layer 203 and the fourth insulating layer 204, or a portion of the third gate portion 321 may be parallel to the plane of the substrate 10 and located between the third insulating layer 203 and the fourth insulating layer 204, while the plane of the other portion intersects with the plane of the substrate 10.

[0076] Reference Figure 5 and Figure 6 As a possible implementation, the third gate portion 321 extends from between the first active portion 3101 and the third active portion 3103 to the side of the third insulating layer 203 away from the second active portion 3102. In this case, a portion of the third gate portion 321 is parallel to the plane of the substrate, and another portion intersects the plane of the substrate. This arrangement ensures that the third gate portion 321 has a relatively large projected area on the channel layer, thereby ensuring the control capability of the first gate 32 over the driving transistor.

[0077] Figure 8 It is along Figure 3 A cross-sectional view of another array substrate taken from BB'. Figure 9 It is along Figure 3 Another cross-sectional view of the array substrate taken from CC' is shown below. Figure 8 and Figure 9 As shown, as another feasible implementation, the third gate portion 321 is optionally parallel to the plane of the substrate 10 and is located between the third insulating layer 203 and the fourth insulating layer 204 between the first active portion 3101 and the third active portion 3103.

[0078] Similarly, since the third active section 3103 is parallel to the substrate plane, for the second gate section 332, at least a part of it is located on the side of the fifth insulating layer 205 away from the third active section 3103, in other words, the second gate section 332 has at least a part parallel to the substrate plane, and the part is located on the side of the fifth insulating layer 205 away from the third active section 3103. Specifically, the entire second gate section 332 can be parallel to the substrate plane, and located on the side of the fifth insulating layer 205 away from the third active section 3103, or a part of the second gate section 332 can be parallel to the substrate plane, and the part is located on the side of the fifth insulating layer 205 away from the third active section 3103, and the other part is perpendicular to the substrate plane.

[0079] With reference to Figure 5 and Figure 6 As a feasible implementation, optionally, the second gate section 332 extends from the side of the fifth insulating layer 205 away from the third active section 3103 to the side of the fifth insulating layer 205 away from the fourth active section 3104, and is connected with the first gate section 331. At this time, a part of the second gate section 332 is parallel to the substrate plane, and the other part is perpendicular to the substrate plane. In this way, the second gate section 332 can have a relatively large projected area on the channel layer, thereby ensuring the control ability of the second gate 33 on the driving transistor, and in addition, the electrical connection between the second gate section 332 and the first gate section 331 is facilitated, so that they can be directly connected in contact, thereby reducing the complexity of the manufacturing process.

[0080] With reference to Figure 8 and Figure 9 As another feasible implementation, optionally, the second gate section 332 is parallel to the substrate plane, and located on the side of the fifth insulating layer 205 away from the third active section 3103. At this time, the first gate section 331 and the second gate section 332 can be arranged to overlap the notch region Q0, so that the second gate section 332 and the first gate section 331 are electrically connected by punching in the notch region Q0.

[0081] With reference to Figure 4 and Figure 6Optionally, the region where the driving transistor T0 is located comprises a notch region Q0; the notch region Q0 is adjacent to the second channel region Q2 in the second direction D2 and adjacent to the first channel region Q1 in the third direction D3; the driving transistor T0 comprises a first gate 32 and a second gate 33, and the first gate subpart 331, the second gate subpart 332 and the third gate subpart 321 of the first gate 32 all overlap the notch region Q0 in the first direction D1; at least the third gate subpart 321 is electrically connected to the data signal transmission structure 4 in the notch region Q0; and the data signal transmission structure 4 is spaced apart from the first active layer 311 of the driving transistor T0 in the same layer.

[0082] According to the above description, by designing the shape of the channel region of the driving transistor, the region where the driving transistor T0 is located has a notch region Q0, which is not provided with the active layer of the driving transistor, and the electrical connection between different structures can be realized as required by using the notch region Q0. In the embodiment, the electrical connection between the gate of the driving transistor and the data signal transmission structure 4 can be realized by using the notch region Q0.

[0083] As the name implies, the data signal transmission structure 4 refers to a structure for transmitting data signals, which extends from the position of other circuit elements to the notch region and is used for electrical connection with the gate of the driving transistor to transmit data signals to the gate of the driving transistor, so as to realize the regulation of the driving current based on the regulation of the data signals, and further control the luminous brightness of the light emitting element.

[0084] For example, referring to Figure 2 and Figure 3 In the 2T1C pixel circuit, in addition to the driving transistor T0, a first switch transistor T1 is further included, the first pole of the first switch transistor T1 is electrically connected to the data signal line Data, the second pole of the first switch transistor T1 is electrically connected to the gate of the driving transistor T0, and the gate of the first switch transistor T1 is electrically connected to the scan signal line Scan; when the first switch transistor T1 is turned on under the control of the scan signal, the data signal on the data signal line Data is written to the gate of the driving transistor T0. At this time, the data signal transmission structure 4 can be specifically understood as an extension pattern of the active layer pattern of the first switch transistor T1.

[0085] For example, referring to Figure 3 and Figure 6 Optionally, the active layer pattern of the first switch transistor T1 and the extension pattern thereof (the data signal transmission structure 4) are spaced apart from the first active layer 311 of the driving transistor T0 in the same layer.

[0086] As described above, the gate of the driving transistor T0 comprises at least one of the first gate 32 and the second gate 33, and according to different arrangement modes of the gate of the driving transistor T0, the structure connected by the data signal transmission structure 4 is different.

[0087] With reference to Figure 6 In this example, the driving transistor T0 includes the first gate 32 and the second gate 33, and the first gate sub-part 331, the second gate sub-part 332, and the third gate sub-part 321 all overlap the notch area Q0. Among the first gate sub-part 331, the second gate sub-part 332, and the third gate sub-part 321, at least the third gate sub-part 321 is electrically connected to the data signal transmission structure 4 in the notch area Q0. In other words, among the first gate 32 and the second gate 33, at least the first gate 32 is electrically connected to the data signal transmission structure 4 for receiving the data signal.

[0088] Similarly, it can be easily understood that in other embodiments, if the driving transistor T0 includes only the first gate 32, the third gate sub-part 321 overlaps the notch area Q0 along the first direction D1, and the third gate sub-part 321 is electrically connected to the data signal transmission structure 4 in the notch area Q0.

[0089] In other embodiments, if the driving transistor T0 includes only the second gate 33, the first gate sub-part 331 and the second gate sub-part 332 both overlap the notch area Q0 along the first direction D1. On the basis of the electrical connection between the first gate sub-part 331 and the second gate sub-part 332, the first gate sub-part 331 is further electrically connected to the data signal transmission structure 4 in the notch area Q0.

[0090] Next, still taking the example of the driving transistor T0 including the first gate 32 and the second gate 33, the setting mode of the gate in the driving transistor is further described.

[0091] With reference to Figure 6 As a feasible implementation, the first gate 32 and the second gate 33 are electrically connected. The first gate sub-part 331 and the third gate sub-part 321 are electrically connected through the first via hole 211. The first gate sub-part 331 and the data signal transmission structure 4 are electrically connected through the second via hole 212. The first via hole 211 and the second via hole 212 are both located in the notch area Q0.

[0092] Specifically, in this embodiment, the first gate 32 and the second gate 33 are electrically connected, and both are electrically connected to the data signal transmission structure 4 for receiving the data signal. In this way, the channel control capability can be improved, the performance of the driving transistor can be improved, the threshold voltage stability can be optimized, the reliability of the driving transistor can be ensured, and thus the display effect can be ensured.

[0093] With reference to Figure 6The third gate portion 321 in the first gate 32 is electrically connected to the first gate portion 331 in the second gate 33 through a first through-hole 211. The first gate portion 331 and the data signal transmission structure 4 are electrically connected through a second through-hole 212. This allows the third gate portion 321 to be indirectly electrically connected to the data signal transmission structure 4 via the first gate portion 331, thus achieving electrical connections between the first gate 32 and the second gate 33 and the data signal transmission structure 4, respectively. This configuration, compared to directly connecting the third gate portion 321 to the data signal transmission structure 4 through a through-hole, reduces the difficulty of through-hole fabrication.

[0094] Figure 6 The diagram illustrates a direct electrical connection between the first gate portion 331 and the second gate portion 332. (Refer to...) Figure 9 In other embodiments, when the second gate portion 332 is parallel to the plane of the substrate 10 and the first gate 32 and the second gate 33 are electrically connected, the second gate portion 332 can be electrically connected to the third gate portion 321 through the fifth through-hole 215, and the third gate portion 321 and the first gate portion 331 are electrically connected through the first through-hole 211, thereby enabling the second gate portion 332 to be indirectly electrically connected to the first gate portion 331 through the third gate portion 321, reducing the processing difficulty of the through-hole.

[0095] As another feasible implementation method Figure 10 It is along Figure 3 Another cross-sectional view of the array substrate taken from CC', with the corresponding direction along... Figure 3 The cross-sectional structure of the array substrate cut from BB' can be referred to Figure 5 .like Figure 10 As shown, optionally, the first gate 32 and the second gate 33 are controlled independently; the third gate portion 321 is electrically connected to the data signal transmission structure 4 through the third via 213, the third via 213 is located in the notch region Q0 and passes through the film layer where the first gate portion 331 is located; the first gate portion 331 is provided with a first opening 3310, and the orthographic projection of the area where the third via 213 is located on the substrate 10 is within the orthographic projection range of the area where the first opening 3310 is located on the substrate 10.

[0096] Specifically, in this embodiment, the first gate 32 and the second gate 33 are controlled independently. At this time, the first gate 32 is electrically connected to the data signal transmission structure 4, and the second gate 33 can be connected separately to a control signal for adjusting the threshold voltage of the driving transistor. In this way, more flexible device control capability can be provided.

[0097] like Figure 10As shown, since the film layer where the third gate portion 321 is located is on the side of the film layer where the first gate portion 331 is located away from the substrate, and the data signal transmission structure 4 and the first active layer 311 of the driving transistor T0 are arranged in the same layer at intervals and are located on the side of the film layer where the first gate portion 331 is located close to the substrate, the connection via (third via 213) between the third gate portion 321 and the data signal transmission structure 4 needs to pass through the film layer where the first gate portion 331 is located. In this embodiment, by providing a first opening 3310 in the first gate portion 331, the orthogonal projection of the setting area of ​​the third via 213 on the substrate 10 is located within the orthogonal projection range of the setting area of ​​the first opening 3310 on the substrate 10, which can ensure that the third gate portion 321 and the first gate portion 331 are mutually insulated.

[0098] Figure 10 The following is an example of a direct electrical connection between the first gate portion 331 and the second gate portion 332. Figure 11 It is along Figure 3 Another cross-sectional view of the array substrate taken from CC', with the corresponding direction along... Figure 3 The cross-sectional structure of the array substrate cut from BB' can be referred to Figure 8 . Reference Figure 11 In other embodiments, when the second gate portion 332 is parallel to the plane of the substrate 10 and the first gate 32 and the second gate 33 are independently controlled, the first gate portion 331 and the second gate portion 332 can be electrically connected through the sixth via 216 of the notch region Q0.

[0099] Based on any of the above embodiments related to the gate of the driving transistor, Figure 12 It is along Figure 3 Another cross-sectional view of the array substrate taken from BB'. Figure 13 It is along Figure 3 Another cross-sectional view of the array substrate taken from CC' ( Figure 13 In the middle, the first gate 32 and the second gate 33 are electrically connected. Figure 14 It is along Figure 3 Another cross-sectional view of the array substrate taken from CC' ( Figure 14 In the process, the first gate 32 and the second gate 33 are independently controlled, such as... Figures 12-14 As shown, optionally, the first gate 32 further includes a fourth gate portion 322, which is located between the first active layer 311 and the substrate 10; the fourth gate portion 322 is electrically connected to the data signal transmission structure 4 through a fourth via 214, which is located in the notch region Q0.

[0100] Specifically, in the embodiment, the first gate 32 includes the third gate sub-portion 321 and the fourth gate sub-portion 322, both of which are located on the same side of the entire channel layer of the driving transistor. Compared with the above embodiment, the projection area of the first gate 32 on the channel layer of the driving transistor can be further increased by additionally providing the fourth gate sub-portion 322, and the control ability of the first gate 32 on the driving transistor can be further improved.

[0101] As described above, among the first gate 32 and the second gate 33, at least the first gate 32 is electrically connected with the data signal transmission structure 4, and therefore, the fourth gate sub-portion 322 is electrically connected with the data signal transmission structure 4. As shown in Figure 13 The fourth gate sub-portion 322 can be electrically connected with the data signal transmission structure 4 through the fourth through hole 214 of the gap region Q0.

[0102] As shown in Figure 12 The array substrate 100 further includes a barrier layer 30 between the substrate 10 and the circuit functional layer 20, and the provision of the barrier layer 30 is beneficial to guarantee the quality of the upper film layer structure. The fourth gate sub-portion 322 can be arranged above the barrier layer 30, and the sixth insulating layer 208 is arranged between the film layer where the fourth gate sub-portion 322 is located and the film layer where the first active layer 311 is located.

[0103] Referring to Figures 5-7 Optionally, along the third direction D3, the third active sub-portion 3103 includes a first region S1, and the first region S1 is located at least in the first channel region Q1; the first active layer 311 includes a second region S2, and the second region S2 is located in the second channel region Q2; the normal projection of the first region S1 and the second region S2 on the substrate 10 is oppositely arranged along the third direction D3, the first region S1 is the first pole lead-out region of the driving transistor T0, and the second region S2 is the second pole lead-out region of the driving transistor T0.

[0104] Specifically, along the third direction D3, the first region S1 and the region of the third active sub-portion 3103 which is connected with the fourth active sub-portion 3104 are oppositely arranged, and the second region S2 and the region of the first active layer 311 which is connected with the second active sub-portion 3102 are oppositely arranged, while the second active sub-portion 3102 and the fourth active sub-portion 3104 are oppositely arranged on the two sides of the first active sub-portion 3101 along the third direction D3, and therefore, the normal projection of the first region S1 and the second region S2 on the substrate 10 is oppositely arranged along the third direction D3. In general, the first region S1 and the second region S2 are located at two end portions of the entire channel layer of the driving transistor.

[0105] Regarding the first region S1, it is located at least in the first channel region Q1, and specifically, the first region S1 can be entirely located in the first channel region Q1, or the first region S1 can be partially located in the first channel region Q1 and partially located in the second channel region Q2,Figure 7 Only the latter is exemplified.

[0106] One of the first region S1 (first pole lead-out region) and the second region S2 (second pole lead-out region) is a source lead-out region, and the other is a drain lead-out region. In other words, one of the first region S1 and the second region S2 is an input end of a channel of a driving transistor (hereinafter referred to as an input end of a driving transistor), and the other is an output end of the channel of the driving transistor (hereinafter referred to as an output end of a driving transistor), for electrical connection with other circuit elements or signal lines.

[0107] Referring to Figure 2 In the 2T1C pixel circuit, the input end of the driving transistor T0 is coupled with the first voltage signal end Elvdd, the output end of the driving transistor T0 is coupled with the anode of the LED light emitting element, the cathode of the LED light emitting element is electrically connected with the second voltage signal end Elvss, the voltage of the second voltage signal end Elvss is less than the voltage of the first voltage signal end Elvdd, and the same is true for other types of pixel circuits, which will be exemplified later.

[0108] In combination Figure 3 , Figure 5 and Figure 7 , taking the 2T1C pixel circuit as an example, the driving transistor T0 further includes a first electrode 34 and a second electrode 35, the first electrode 34 is overlapped with the first region S1 of the third active sub-part 3103 and is electrically connected with the first voltage signal end Elvdd, and the second electrode 35 is overlapped with the second region S2 of the first active layer 311 and is electrically connected with the anode structure 6, at this time, the first region S1 is the input end of the driving transistor, and the second region S2 is the output end of the driving transistor.

[0109] In other embodiments, the first region S1 can also be selected as the output end of the driving transistor, and the second region S2 can also be selected as the input end of the driving transistor, and the embodiments of the present application do not limit this. Hereinafter, the first region S1 is taken as the input end of the driving transistor, and the second region S2 is taken as the output end of the driving transistor as an example for illustration.

[0110] Regarding the above-mentioned anode structure 6, it needs to be explained that the array substrate provided in the present embodiment can be applied to any type of LED display panel, including but not limited to OLED display panel, micro-LED display panel and mini-LED display panel, and in different types of display panels, the specific structure represented by the anode structure 6 is different. For example, in the OLED display panel, the anode structure 6 can be directly used as the anode of the OLED light emitting element; in the micro-LED display panel, the anode structure 6 can be used as an anode pad for bonding with the anode of the micro-LED light emitting element.

[0111] With reference to Figure 5 and Figure 6 Optionally, the array substrate further comprises an interlayer insulating layer 206, at least part of the interlayer insulating layer 206 is located on the side of the third insulating layer 203 away from the second active section 3102, and the fourth insulating layer 204 covers the interlayer insulating layer 206; along the first direction D1, the thickness of the interlayer insulating layer 206 is greater than the thickness of the third insulating layer 203.

[0112] The interlayer insulating layer 206 can play a role of support and insulation, and its material can be an organic material or an inorganic material, which is not limited in the embodiments of the present application. By arranging the relatively thick interlayer insulating layer 206 on the side of the third insulating layer 203 away from the second active section 3102 and making the fourth insulating layer 204 cover the interlayer insulating layer 206, the area of the part of the fourth insulating layer 204 parallel to the plane where the substrate 10 is located is increased, the platform for manufacturing the third active section 3103 is increased, and the third active section 3103 is ensured to be manufactured on a relatively leveled plane, thereby ensuring the reliability of the product.

[0113] With reference to Figure 5 Optionally, the driving transistor T0 comprises a first gate 32, the first gate 32 comprises a third gate section 321, part of the third gate section 321 is located between the third insulating layer 203 and the fourth insulating layer 204 between the first active section 3101 and the third active section 3103, and the other part is located between the interlayer insulating layer 206 and the third insulating layer 203; along the first direction D1, the interlayer insulating layer 206 comprises opposite first and second surfaces F1 and F2, the first part of the third gate section 321 comprises opposite third and fourth surfaces F3 and F4, the second surface F2 is located on the side of the first surface F1 away from the substrate 10, the fourth surface F4 is located on the side of the third surface F3 away from the substrate 10, and the second surface F2 is flush with the fourth surface F4; wherein the first part of the third gate section 321 is the part of the third gate section 321 located between the first active section 3101 and the third active section 3103.

[0114] Specifically, the first part of the third gate section 321 can be understood as the part of the third gate section 321 parallel to the plane where the substrate 10 is located.

[0115] It should be noted that the design of the interlayer insulating layer 206 in the present embodiment is applicable to the case where the driving transistor T0 comprises the first gate 32, which can be the case where the driving transistor T0 only comprises the first gate 32, or the case where the driving transistor T0 comprises both the first gate 32 and the second gate 33, Figure 5The latter will be used as an example for illustration only. The case where the driving transistor T0 only includes the first gate 32 is similar, the only difference being the absence of the second gate 33, which will not be illustrated here.

[0116] When the driving transistor T0 includes a first gate 32, the third gate portion 321 in the first gate 32 may extend from the region between the first active portion 3101 and the third active portion 3103 to the side of the third insulating layer 203 away from the second active portion 3102. Figure 5 It can be seen that, limited by the length of the first active portion 3101 in the third direction D3, the length of the horizontal portion of the third gate portion 321 in the third direction D3 is limited. In this embodiment, an interlayer insulating layer 206 is provided on the side of the third gate portion 321 away from the second active portion 3102, so that the top surface (second surface F2) of the interlayer insulating layer 206 is flush with the top surface (fourth surface F4) of the third gate portion 321, and the fourth insulating layer 204 covers the top surface of the interlayer insulating layer 206 and the top surface of the third gate portion 321. This increases the length of the horizontal portion of the fourth insulating layer 204 in the third direction D3, and increases the area of ​​the portion of the fourth insulating layer 204 parallel to the plane of the substrate 10, thereby increasing the fabrication platform of the third active portion 3103 and ensuring that the third active portion 3103 is fabricated on a relatively flat plane, thus ensuring product reliability.

[0117] Figure 15 This is a schematic diagram of a partial film layer structure of another array substrate provided in an embodiment of the present invention, specifically illustrating another type of... Figure 2 The layout structure corresponding to the pixel circuit shown is as follows: Figure 16 It is along Figure 15 A schematic diagram of the cross-sectional structure of the array substrate taken from DD'. Figure 17 It is along Figure 15 A schematic diagram of the cross-sectional structure of the array substrate taken from EE', as shown below. Figures 15-17 As shown, optionally, the interlayer insulation layer 206 is located between the third insulation layer 203 and the fourth insulation layer 204, and is in contact with the third insulation layer 203 and the fourth insulation layer 204; along the first direction D1, the interlayer insulation layer 206 includes a first insulation portion 2061 and a second insulation portion 2062; the first insulation portion 2061 is located on the side of the third insulation layer 203 away from the second active portion 3102; the second insulation portion 2062 is located on the side of the fourth insulation layer 204 away from the third active layer 313, and a portion of the second insulation portion 2062 is located between the first active portion 3101 and the third active portion 3103.

[0118] This embodiment applies to the case where the driving transistor T0 only includes the second gate 33, such as Figure 16As shown, at this time, the first gate sub-portion 331 can be electrically connected with the data signal transmission structure 4 through the second via hole 212 located in the gap region Q0.

[0119] When the driving transistor T0 only includes the second gate 33, the interlayer insulating layer 206 is surrounded by the third insulating layer 203 and the fourth insulating layer 204, and in this embodiment, the thickness of the interlayer insulating layer 206 is further increased, specifically, a part (the first insulating sub-portion 2061) of the interlayer insulating layer 206 is located on the side of the third insulating layer 203 away from the second active sub-portion 3102, and another part (the second insulating sub-portion 2062) is located on the side of the fourth insulating layer 204 away from the third active layer 313, and moreover, a part of the second insulating sub-portion 2062 is located between the first active sub-portion 3101 and the third active sub-portion 3103 (the three overlap along the first direction D1), and another part overlaps the first insulating sub-portion 2061 along the first direction D1, in this way, the length of the fourth active sub-portion 3104 between the first active sub-portion 3101 and the third active sub-portion 3103 can be increased, and further, the projection area of the channel region of the driving transistor on the substrate can be further compressed under the condition that the total length of the channel is constant, and the area of the pixel circuit can be reduced.

[0120] In summary, the above embodiments have made a detailed description of the design of the region where the driving transistor of the pixel circuit is located, and the above design can be applied to any type of pixel circuit.

[0121] Next, still taking the 2T1C pixel circuit as an example, the connection mode between other structures in the pixel circuit and the driving transistor is further described.

[0122] In combination Figures 3-6 Optionally, the circuit functional layer 20 further includes a storage capacitor Cst, the storage capacitor Cst includes a first capacitor plate 51 and a second capacitor plate 52 which are oppositely and insulatively arranged; along the first direction D1, the region where the storage capacitor Cst is located does not overlap the channel region Q; at least part of the orthographic projection of the storage capacitor Cst on the substrate 10 is located on the side of the orthographic projection of the second active sub-portion 3102 on the substrate 10 away from the orthographic projection of the fourth active sub-portion 3104 on the substrate 10.

[0123] Referring to Figure 2 In the pixel circuit, the storage capacitor Cst is usually connected between the gate of the driving transistor T0 and the first voltage signal end Elvdd, for maintaining the stability of the gate voltage of the driving transistor T0, and ensuring the continuity and consistency of the pixel light emission.

[0124] Among them, the first capacitor plate 51 is electrically connected with the gate of the driving transistor T0, and the gate specifically refers to the gate receiving the data signal.

[0125] Specifically, when the driving transistor T0 only includes one gate, the first capacitor plate 51 is electrically connected with the gate. For example, Figures 15-17 In the embodiment, the driving transistor T0 only includes the second gate 33, and the first capacitor plate 51 is electrically connected with the second gate 33.

[0126] In addition, when the driving transistor T0 includes the first gate 32 and the second gate 33, at least the first gate 32 is used to receive the data signal, and therefore, the first capacitor plate 51 is electrically connected with at least the first gate 32. Specifically, in combination with the above explanation, if the first gate 32 and the second gate 33 are electrically connected, the first capacitor plate 51 is electrically connected with both the first gate 32 and the second gate 33; if the first gate 32 and the second gate 33 are independently controlled, the first capacitor plate 51 is only electrically connected with the first gate 32.

[0127] In the embodiment, the second capacitor plate 52 is electrically connected with the first voltage signal terminal Elvdd, and the input terminal of the driving transistor T0 is coupled with the first voltage signal terminal Elvdd, and therefore, the second capacitor plate 52 and the input terminal of the driving transistor T0 are coupled.

[0128] Referring to Figure 7 , according to the above description, the first region S1 of the third active part 3103 can be used as the input terminal of the driving transistor, the second region S2 of the first active layer 311 can be used as the output terminal of the driving transistor, and the projection region of the first region S1 of the third active part 3103 and the fourth active part 3104 on the substrate is arranged in the third direction D3. In the embodiment, at least part of the projection of the storage capacitor Cst on the substrate 10 is located on the side away from the projection of the fourth active part 3104 on the substrate 10, which facilitates the electrical connection between the second capacitor plate 52 of the storage capacitor Cst and the input terminal of the driving transistor, and reduces the design difficulty.

[0129] In addition, since the channel region Q of the driving transistor has a plurality of active layers 31 arranged in a stack, and a gate metal or the like structure is arranged between adjacent active layers, the region where the storage capacitor Cst is located is arranged not to overlap with the channel region Q in the first direction D1, which can avoid interference between the storage capacitor Cst and the driving transistor T0, and facilitate the on-demand setting of the capacitance value by controlling the size of the storage capacitor, thereby reducing the design and process difficulty.

[0130] Referring to Figure 3 , the region where the storage capacitor is located can be half-encircling the channel region, and such arrangement can increase the area of the storage capacitor.

[0131] Referring to Figure 5 and Figure 6Optionally, the third insulating layer 203 extends to a region where the storage capacitor Cst is located, and serves as a capacitor insulating layer between the first capacitor plate 51 and the second capacitor plate 52.

[0132] With reference to Figures 5-7 For the 2T1C pixel circuit, when the driving transistor T0 includes the first gate 32, the driving transistor also includes the first electrode 34, the first electrode 34 is overlapped with the first region S1 of the third active part 3103; the first capacitor plate 51 is electrically connected with the third gate part 321; and the second capacitor plate 52 is electrically connected with the first electrode 34.

[0133] Specifically, with reference to Figure 6 The first electrode 34 is overlapped with the first region S1, and is electrically connected with the first connecting part 221 and the second capacitor plate 52, so that the input end of the driving transistor is electrically connected with the second capacitor plate 52 of the storage capacitor. In combination with Figure 3 The first electrode 34, the second capacitor plate 52 and the first connecting part 221 are integrally formed.

[0134] With reference to Figure 6 When the driving transistor T0 includes the first gate 32, the first capacitor plate 51 can be electrically connected with the third gate part 321 through the second connecting part 222. Optionally, the first capacitor plate 51, the second connecting part 222 and the third gate part 321 are integrally formed.

[0135] It should be noted that the design of the first capacitor plate 51 in the storage capacitor Cst in the embodiment is applicable to the case that the driving transistor T0 includes the first gate 32, and specifically can be the case that the driving transistor T0 only includes the first gate 32, or the case that the driving transistor T0 includes both the first gate 32 and the second gate 33, Figure 5 and Figure 6 Only the latter is taken as an example for illustration. The case that the driving transistor T0 only includes the first gate 32 is similar to this, and the difference is only that there is no design of the second gate 33, which will not be illustrated one by one here.

[0136] With reference to Figure 6 For the case that the driving transistor T0 includes the first gate 32, in the 2T1C pixel circuit, by setting a relatively thick interlayer insulating layer 206, the coupling capacitor between the side surface part of the third gate part 321 and the first connecting part 221 can also be avoided, and the controllability of the setting region and the capacitance value of the storage capacitor Cst is further ensured.

[0137] In other embodiments, with reference to Figures 15-17The driving transistor T0 can also only include the second gate 33. At this time, the first gate sub-portion 331 can be disposed in the first metal layer M1, the first capacitor plate 51 can be disposed in the second metal layer M2, the first electrode 34 and the second capacitor plate 52 can be disposed in the third metal layer M3, the first gate sub-portion 331 and the first capacitor plate 51 can optionally overlap in projection in the first direction D1, and the first gate sub-portion 331 and the first capacitor plate 51 are electrically connected through the seventh through hole 217, which can be disposed outside the region where the driving transistor T0 is located.

[0138] With reference to Figure 16 and Figure 17 Optionally, the planes where the first capacitor plate 51 and the second capacitor plate 52 are located are both parallel to the plane where the substrate 10 is located. In this way, the manufacturing process is relatively simple.

[0139] Figure 18 is another schematic view of the cross-sectional structure of the array substrate taken along the BB' in Figure 3 Figure 19 is another schematic view of the cross-sectional structure of the array substrate taken along the CC' in Figure 3 Figure 18 and Figure 19 Optionally, the storage capacitor Cst includes a first capacitor sub-portion 501 and a second capacitor sub-portion 502, the plane where the first capacitor sub-portion 501 is located is parallel to the plane where the substrate 10 is located, and the plane where the second capacitor sub-portion 502 is located intersects the plane where the substrate 10 is located; and a support column 230 is disposed between the first capacitor sub-portion 501 and the substrate 10.

[0140] Specifically, the plane where the first capacitor sub-portion 501 is located can be understood as the planes where the first capacitor plate 51 and the second capacitor plate 52 in the first capacitor sub-portion 501 are located. In the first capacitor sub-portion 501, the planes where the first capacitor plate 51 and the second capacitor plate 52 are located are parallel to the plane where the substrate is located. Similarly, the plane where the second capacitor sub-portion 502 is located can be understood as the planes where the first capacitor plate 51 and the second capacitor plate 52 in the second capacitor sub-portion 502 are located. In the second capacitor sub-portion 502, the planes where the first capacitor plate 51 and the second capacitor plate 52 are located intersect the plane where the substrate is located.

[0141] The support column 230 is used to support the first capacitor sub-portion 501, and the material of the support column 230 can be an organic material or an inorganic material, which is not limited in the embodiments of the present application. In a specific embodiment, the support column 230 can be stacked by multiple insulating layers.

[0142] ​​In the case that the facing area and the interval of the first capacitor plate 51 and the second capacitor plate 52 are unchanged, compared with the case that the plane where the whole first capacitor plate 51 and the whole second capacitor plate 52 are located is parallel to the plane where the substrate 10 is located, the embodiment sets the storage capacitor Cst to include a first capacitor subpart 501 parallel to the substrate and a second capacitor subpart 502 intersecting the substrate, and sets a support column 230 between the first capacitor subpart 501 and the substrate 10, so that the projection area of the storage capacitor on the substrate can be further compressed, and the area of the pixel circuit can be further reduced.

[0143] In summary, the above embodiment takes the 2T1C pixel circuit as an example, and the design of the driving transistor and the connection relationship between the driving transistor and the storage capacitor are described in detail. It should be noted that, in the above embodiment, in addition to the connection mode of the storage capacitor and the driving transistor, the design of the storage capacitor itself, such as the setting area, the film layer position of the first capacitor plate and the second capacitor plate, and the parallel / intersecting relationship with the plane where the substrate is located, is also applicable to other pixel circuits, and will not be described in detail hereinafter.

[0144] Next, taking the 7T1C pixel circuit as an example, the technical solutions of the embodiments of the present application are further briefly described, and the same parts will not be described hereinafter.

[0145] Exemplarily, Figure 20 is a schematic diagram of a 7T1C pixel circuit, Figure 21 is a schematic diagram of a film layer structure of another array substrate provided by the embodiment of the present application, which specifically shows a layout structure corresponding to the pixel circuit shown in Figure 20 , as shown in Figure 20 and Figure 21 , in the circuit functional layer 20, one pixel circuit includes a driving transistor T0, an initialization transistor T2, a data writing transistor T3, a threshold compensation transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a reset transistor T7 and a storage capacitor Cst, which form a 7T1C pixel circuit according to the connection mode shown in the figure, and the specific working principle will not be explained here.

[0146] As shown in Figure 21 , the circuit functional layer 20 includes a first active layer 311, a first metal layer M1, a second active layer 312, a second metal layer M2, a third active layer 313, a third metal layer M3 and a fourth metal layer M4, and the transistors and the storage capacitor in the above pixel circuit are formed in these film layers.

[0147] Figure 22 is a schematic diagram of the stacking structure of the film layers where the first active layer, the second active layer and the third active layer are located in Figure 21 , combined with Figure 21 andFigure 22 As shown, in the film layer where the first active layer 311 is located, in addition to the first active layer 311 of the driving transistor T0, the active layer patterns of the initialization transistor T2, the data writing transistor T3, the threshold compensation transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6 and the reset transistor T7 are also formed, and the data signal transmission structure 4 is also provided. The second region S2 (output end) of the first active layer 311 of the driving transistor T0, the input end of the active layer pattern of the threshold compensation transistor T4 and the input end of the active layer pattern of the second light emitting control transistor T6 are connected to the first node N1. The output end of the active layer pattern of the threshold compensation transistor T4 and the output end of the active layer pattern of the initialization transistor T2 are connected to the second node N2, and the second node N2 is also electrically connected to the data signal transmission structure 4 through the first cross-bridge structure 91 located in the third metal layer M3. The data signal transmission structure 4 extends into the notch area of the region where the driving transistor T0 is located, so as to be electrically connected with the gate of the driving transistor. The active layer pattern of the data writing transistor T3 is arranged in the same layer as the first active layer 311 of the driving transistor T0. The output end of the active layer pattern of the data writing transistor T3 and the output end of the first light emitting control transistor T5 are connected to the third node N3, and the third node N3 is electrically connected to the first electrode 34 (located in the third metal layer M3) of the driving transistor T0 through a via hole. The film layer where the second active layer 312 and the third active layer 313 are located only includes the active layer of the driving transistor, and for the convenience of display, Figure 22 Only the first active sub-part 3101 in the second active layer 312 and the third active sub-part in the third active layer 313 are shown. The design of the active layer in the driving transistor is explained above and will not be repeated here.

[0148] Figure 23 is Figure 21 The stack structure of the film layer where the first active layer is located and the first metal layer is shown in combination with Figure 21 and Figure 23 As shown, the first metal layer M1 includes the first scan line Scan1, the second scan line Scan2, the light emitting control signal line Emit and the first gate sub-part 331 of the driving transistor T0. The first gate sub-part 331 overlaps the first active layer 311 and overlaps the notch area. As explained above, whether the first gate sub-part 331 is electrically connected with the data signal transmission structure 4 or not can be determined as needed. Figure 23 Only the example of the punch connection between the first gate sub-part 331 and the data signal transmission structure 4 is shown.

[0149] In addition, the region where the pixel circuit is located can include two first scan lines Scan1. One of the two first scan lines Scan1 overlaps with the active layer pattern of the initialization transistor T2, and is used to control the on-off of the initialization transistor T2. The other first scan line Scan1 overlaps with the active layer pattern of the reset transistor T7, and is used to control the on-off of the reset transistor T7. The second scan line Scan2 overlaps with the active layer patterns of the data writing transistor T3 and the threshold compensation transistor T4, and is used to control the on-off of the data writing transistor T3 and the threshold compensation transistor T4. The emission control signal line Emit overlaps with the active layer patterns of the first emission control transistor T5 and the second emission control transistor T6, and is used to control the on-off of the first emission control transistor T5 and the second emission control transistor T6. The first scan line Scan1, the second scan line Scan2, and the emission control signal line Emit all extend along the third direction D3, and are arranged side by side along the second direction D2 and spaced apart from the first gate sub-part 331, so that the gate of each switch transistor is spaced apart from the first gate sub-part 331, for example, the gate of the data writing transistor T3 is spaced apart from the first gate sub-part 331.

[0150] Figure 24 is Figure 21 the first active layer, the second active layer, and the second metal layer in FIG. 8, in combination with Figure 21 and Figure 24 As shown in FIG. 8, the second metal layer M2 includes the initialization signal line Vref1, the reset signal line Vref2, the third gate sub-part 321, and the first capacitor plate 51 of the storage capacitor. The third gate sub-part 321 overlaps with the channel region of the driving transistor, overlaps with the notch region, and is electrically connected to the data signal transmission structure 4. The specific connection manner can be referred to the description above. The third gate sub-part 321 and the first capacitor plate 51 are electrically connected and can be integrally formed.

[0151] In addition, the initialization signal line Vref1 is used to transmit an initialization signal to the initialization transistor T2, so as to initialize the gate potential of the driving transistor. Optionally, the initialization signal line Vref1 and the initialization transistor T2 can be electrically connected through the second cross-bridge structure 92 located in the third metal layer M3. The reset signal line Vref2 is used to transmit a reset signal to the reset transistor T7, so as to reset the anode voltage of the light emitting element. Optionally, the reset signal line Vref2 and the reset transistor T7 can be electrically connected through the third cross-bridge structure 93 located in the third metal layer M3.

[0152] Figure 25 is Figure 21 the first active layer, the third active layer, and the third metal layer in FIG. 9, in combination with Figure 21 ,Figure 22 and Figure 25 As shown in FIG. 4, the third metal layer M3 includes, in addition to the first bridge-crossing structure 91, the second bridge-crossing structure 92 and the third bridge-crossing structure 93, a second gate sub-portion 332 and the first electrode 34 of the driving transistor, a second capacitor plate 52 and a capacitor extension 520 of the storage capacitor. The second gate sub-portion 332 is electrically connected with the first gate sub-portion 331 of the first metal layer M1; the first electrode 34 is overlapped with the first region S1 of the third active sub-portion 3103, and the second capacitor plate 52 is arranged in the same layer and spaced apart from the first electrode 34; the capacitor extension 520 is located on the opposite sides of the second capacitor plate 52 along the third direction D3 and connected with the second capacitor plate 52. By arranging the capacitor extension 520, the second capacitor plates 52 in the pixel circuits in the same row along the third direction D3 can be connected, which is conducive to the voltage uniformity of the first voltage signal (Elvdd).

[0153] It should be noted that, Figure 25 Only the first region S1 of the third active sub-portion 3103 is located in the first channel region Q1 is taken as an example for illustration. In other embodiments, the first region S1 can also be partially located in the first channel region Q1 and partially located in the second channel region Q2. In this way, the overlapping area of the first electrode 34 and the third active sub-portion 3103 can be increased, as long as there is a spacing between the second capacitor plate 52 and the first electrode 34 and other structures in the same layer.

[0154] In addition, with reference to Figure 21 , the fourth metal layer M4 includes a first voltage signal line (Elvdd) and a data signal line Data, both of which extend along the second direction D2 and are spaced apart along the third direction D3. The first end (input end) of the active layer pattern of the data writing transistor T2 is electrically connected with the data signal line Data through a via, and the second end (output end) of the active layer pattern of the data writing transistor is electrically connected with the first electrode 34 of the driving transistor T0 through a via. In addition, the first voltage signal line (Elvdd) and the second capacitor plate 52 of the storage capacitor are electrically connected through a via.

[0155] Exemplarily, Figure 26 is a cross-sectional structure diagram of the array substrate taken along JJ' in Figure 21 , combined with Figure 21 , Figure 25 and Figure 26As shown, optionally, the circuit functional layer 20 further includes a first planarization layer 207, a second planarization layer 209, and a fifth metal layer M5. The first planarization layer 207 is located on the side of the third metal layer M3 away from the substrate 10, the fourth metal layer M4 is located on the side of the first planarization layer 207 away from the substrate 10, and the fifth metal layer M5 is located on the side of the second planarization layer 209 away from the substrate 10. The anode structure 6 is located on the fifth metal layer M5. The third metal layer M3 further includes a first transition structure 81 and a second transition structure 82, and the fourth metal layer M4 further includes a third transition structure 83. Data writing... The first end of the input transistor T2 is electrically connected to the first adapter structure 81 through the eighth through hole K1. The first adapter structure 81 is electrically connected to the data signal line Data through the eleventh through hole K4. The second end of the data writing transistor T2 is electrically connected to the first electrode 34 of the driving transistor T0 through the ninth through hole K2. The output end of the second light-emitting control transistor T6 is electrically connected to the second adapter structure 82 through the tenth through hole K3. The second adapter structure 82 is electrically connected to the third adapter structure 83 through the twelfth through hole K5. The third adapter structure 83 is electrically connected to the anode structure 6 through the thirteenth through hole K6.

[0156] In this embodiment, a first transition structure 81 and a second transition structure 82 are provided in the third metal layer M3, and two planarization layers are provided on the side of the third metal layer M3 away from the substrate 10. The first voltage signal line (Elvdd), the data signal line Data, and the third transition structure 83 are arranged between the two planarization layers. The first voltage signal line (Elvdd) and the data signal line Data can be protected by the second planarization layer 209, ensuring the flatness of the film layer below the anode structure 6. This also reduces the processing difficulty of vias and ensures product reliability. For example, the first planarization layer 207 and the second planarization layer 209 can be formed using organic materials.

[0157] In summary, the above embodiments, based on 2T1C pixel circuits and 7T1C pixel circuits respectively, have provided a detailed description of the technical solutions of the embodiments of the present invention. For example, Figures 27-44 Is with Figure 26 The fabrication flowchart corresponding to the array substrate shown is as follows: Figure 26 Taking the structure shown as an example, the fabrication method of the array substrate will be briefly explained.

[0158] like Figure 27As shown, in the first step, a barrier layer 30 is fabricated on the substrate 10 using a CVD (Chemical Vapor Deposition) process. Optionally, the barrier layer 30 includes a SiNx layer and a SiOx layer stacked from bottom to top. The SiNx layer can be used to block impurity ions in the substrate. The SiOx layer can match the lattice of the active layer (e.g., P-Si) and can also be used for heat preservation during the subsequent ELA (excimer laser annealing) process.

[0159] like Figure 28 As shown, the second step involves fabricating a monocrystalline silicon layer on the barrier layer using a CVD process, then converting the monocrystalline silicon into polycrystalline silicon using an ELA process. Finally, the polycrystalline silicon is etched to form the desired pattern, such as... Figure 22 The first active layer 311 shown includes an active layer pattern of the channels for each transistor in the film layer. For example, polysilicon can be patterned using dry etching, and the etching gases can be Cl2 and SF6. The etching amount can be controlled by the etching time.

[0160] like Figure 29 As shown, in the third step, a first insulating layer is first prepared on the side of the film layer containing the first active layer 311 away from the substrate 10 using a CVD process. Then, this insulating layer is etched to form a first insulating layer 201 with a specific pattern. In this embodiment, the first insulating layer 201 exposes the third region S3 of the first active layer 311 of the driving transistor T0, so that the connection between the first active layer 311 and the second active layer 312 can be achieved subsequently through the third region S3. For example, the material of the first insulating layer 201 can be SiOx, and it can be patterned using dry etching. The etching gas can be gases such as CF4, CHF3, SF6, and Ar, and the etching amount can be controlled by the etching time. Other insulating layers of the same material can also be etched using this method, which will not be elaborated further.

[0161] like Figure 30As shown, in the fourth step, a first metal layer is prepared on the first insulating layer 201 using a PVD (Physical Vapor Deposition) process. This metal layer is then etched to form a first metal layer M1 with a specific pattern. As described above, the first metal layer M1 includes a first scan line Scan1, a second scan line Scan2, a light-emitting control signal line Emit, and a first gate portion 331 of the driving transistor T0, among other patterns. For example, the material of the first metal layer M1 can be at least one of Al, Cu, and Mo. The first metal layer can be patterned using dry etching. Different etching gases can be used depending on the metal; for example, etching gases such as Cl2 and SF6 can be used for Mo. Other metal layers of the same material can also be etched using this method, which will not be elaborated further.

[0162] like Figure 31 As shown, in the fifth step, a second insulating layer is first prepared on the side of the first metal layer M1 away from the substrate 10 using a CVD process. The material can be SiOx. Then, the insulating layer is etched to form a second insulating layer 202 with a certain pattern. In this embodiment, the second insulating layer 202 exposes the fourth region S4 of the first gate portion 331 of the driving transistor T0 so that the first gate portion 331 and the second gate portion 332 can be directly contacted and electrically connected through the fourth region S4.

[0163] like Figure 32 As shown, in the sixth step, a layer of monocrystalline silicon is prepared on the second insulating layer 202 using a CVD process. Then, the monocrystalline silicon is converted into polycrystalline silicon using an ELA process. Finally, the polycrystalline silicon is etched to form the second active layer 312 of the driving transistor T0. The second active layer 312 includes a first active portion 3101 and a second active portion 3102. The second active portion 3102 contacts the third region S3 of the first active layer, thus connecting the first active layer 311 and the second active layer 312. Furthermore, as... Figure 32 As shown, in this embodiment, the first active portion 3101 exposes not only the fourth region S4 of the first gate portion 331, but also the fifth region S5 of the second insulating layer 202, so that the connection between the second insulating layer 202 and the fifth insulating layer 205 can be realized through the fifth region S5.

[0164] like Figure 33As shown, in the seventh step, a third insulating layer is first prepared on the side of the film layer containing the second active layer 312 away from the substrate 10 using a CVD process. The material can be SiOx. Then, the insulating layer is etched to form a third insulating layer 203 with a certain pattern. In this embodiment, in addition to exposing the fourth region S4 of the first gate portion 331 and the fifth region S5 of the second insulating layer 202, the third insulating layer 203 also exposes the sixth region S6 of the first active portion 3101 so that the connection between the second active layer 312 and the third active layer 313 can be realized through the sixth region S6.

[0165] like Figure 34 As shown, in step eight, a second metal layer is prepared on the third insulating layer 203 using a PVD process. The material can be at least one of Al, Cu, and Mo. Then, the metal layer is etched to form a second metal layer M2 with a specific pattern. As described above, the second metal layer M2 includes an initialization signal line Vref1, a reset signal line Vref2, a first gate 32 (third gate portion 321) of the driving transistor T0, and a first capacitor plate 51 of the storage capacitor. The third gate portion 321 and the first capacitor plate 51 are electrically connected and can be integrally formed. In this embodiment, in addition to exposing the fourth region S4 of the first gate portion 331, the fifth region S5 of the second insulating layer 202, and the sixth region S6 of the first active portion 3101, the third gate portion 321 also exposes the seventh region S7 of the third insulating layer 203, so that the connection between the third insulating layer 203 and the fourth insulating layer 204 can be achieved subsequently through the seventh region S7.

[0166] like Figure 35 As shown, in the ninth step, an interlayer insulating layer 206 is prepared on the side of the third gate portion 321 away from the second active portion 3102 using a photolithography process. Specifically, an organic adhesive layer is first coated on the side of the second metal layer M2 away from the substrate, and then the desired pattern is formed by exposure and development to obtain the interlayer insulating layer 206. Optionally, the upper surface of the interlayer insulating layer 206 is flush with the upper surface of the third gate portion 321.

[0167] like Figure 36 As shown, in step ten, a fourth insulating layer is first prepared on the side of the film layer containing the second metal layer M2 and the interlayer insulating layer 206 away from the substrate 10 using a CVD process. The material can be SiOx. Then, the insulating layer is etched to form a fourth insulating layer 204 with a certain pattern. In this embodiment, the fourth insulating layer 204 is connected to the third insulating layer 203, and the fourth region S4 of the first gate portion 331, the fifth region S5 of the second insulating layer 202, and the sixth region S6 of the first active portion 3101 are still exposed.

[0168] like Figure 37As shown, in step eleven, a layer of monocrystalline silicon is prepared on the fourth insulating layer 204 using a CVD process. Then, the monocrystalline silicon is converted into polycrystalline silicon using an ELA process. Finally, the polycrystalline silicon is etched to form the third active layer 313 of the driving transistor T0. The third active layer 313 includes a third active portion 3103 and a fourth active portion 3104. The fourth active portion 3104 contacts the sixth region S6 of the first active portion 3101, thus connecting the second active layer 312 and the third active layer 313. The fourth region S4 of the first gate portion 331 and the fifth region S5 of the second insulating layer 202 remain exposed.

[0169] like Figure 38 As shown, in the twelfth step, a fifth insulating layer is first prepared on the side of the film layer containing the third active layer 313 away from the substrate 10 using a CVD process. The material can be SiOx. Then, the insulating layer is etched to form a fifth insulating layer 205 with a certain pattern. In this embodiment, the fifth insulating layer 205 is connected to the second insulating layer 202, and the fourth region S4 of the first gate portion 331 is still exposed. In addition, the fifth insulating layer 205 also exposes the first region S1 of the third active portion 3103.

[0170] like Figure 39 As shown, in step thirteen, a plurality of through-holes penetrating the first insulating layer 201, the second insulating layer 202, the third insulating layer 203, and the fourth insulating layer 204 are formed in the array substrate using photolithography. For example... Figure 39 The eighth via K1, the ninth via K2, and the tenth via K3 are shown. The eighth via K1 exposes the first end of the active layer pattern of the data writing transistor T2, the tenth via K2 exposes the second end of the active layer pattern of the data writing transistor T2, and the tenth via K3 exposes the second end of the active layer pattern of the second light-emitting control transistor T6. Other vias can be configured as needed and will not be described in detail here.

[0171] like Figure 40 As shown, in step fourteen, a third metal layer is prepared on the side of the fifth insulating layer 205 away from the substrate 10 using a PVD process. The material can be at least one of Al, Cu, and Mo. This metal layer is then etched to form a third metal layer M3 with a specific pattern. As described above, the third metal layer M3 includes a second gate portion 332 and a first electrode 34 of a driving transistor, a second capacitor plate 52 of a storage capacitor and a capacitor extension 520 connected thereto, a first transition structure 81, a second transition structure 82, a first bridge structure 91, a second bridge structure 92, and a third bridge structure 93, etc. Except for the second capacitor plate 52 and the capacitor extension 520 being electrically connected (integrated), the different structures are spaced apart from each other.

[0172] likeFigure 41 As shown, in step fifteen, a first planarization layer is prepared on the side of the third insulating layer M3 away from the substrate 10 using a coating process. The material can be, for example, an organic photoresist. Then, several through-holes penetrating the planarization layer are formed by exposure and development. Figure 41 The eleventh through-hole K4 and the twelfth through-hole K5 shown form a first planarization layer 207. Among them, the eleventh through-hole K4 exposes the first transition structure 81, and the twelfth through-hole K5 exposes the second transition structure 82.

[0173] like Figure 42 As shown, in step sixteen, a fourth metal layer is prepared on the side of the first planarization layer 207 away from the substrate 10 using a PVD process. The material can be at least one of Al, Cu, and Mo. This metal layer is then etched to form a fourth metal layer M4 with a specific pattern. As described above, the fourth metal layer M4 includes patterns such as a first voltage signal line (Elvdd), a data signal line (Data), and a third adapter structure 83, with different patterns spaced apart. The data signal line (Data) is electrically connected to the first adapter structure 81 through an eleventh via K4, and the third adapter structure 83 is electrically connected to the second adapter structure 82 through a twelfth via K5.

[0174] In addition, refer to Figure 21 The first voltage signal line (Elvdd) is electrically connected to the second capacitor plate 52 through the fourteen-hole K7, and is also electrically connected to the first end of the active layer pattern of the first light-emitting control transistor T5 through the fifteenth-hole K8.

[0175] like Figure 43 As shown, in step seventeen, a second planarization layer is prepared on the side of the fourth metal layer M4 away from the substrate 10 using a coating process. The material can be, for example, organic photoresist. Then, several vias penetrating the planarization layer are formed by exposure and development, for example... Figure 43 The thirteenth via K6 shown forms a second planarization layer 209. The thirteenth via K6 exposes a third transition structure 83.

[0176] like Figure 44 As shown, in step eighteen, a fifth metal layer is fabricated on the side of the second planarization layer 209 away from the substrate 10 using a PVD process. The material can be, for example, an ITO / Ag / ITO stacked structure. Then, a fifth metal layer M5 with a certain pattern is formed by an etching process. The fifth metal layer M5 includes at least a plurality of anode structures 6 for subsequent electrical connection with the light-emitting element.

[0177] Based on the same inventive concept, embodiments of the present invention also provide a display panel. For example, Figure 45 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, such as... Figure 45As shown, the display panel 1000 includes the light emitting layer 400 and the array substrate 100 provided by any of the above embodiments, the light emitting layer 400 is located on the side of the circuit functional layer 20 away from the substrate 10; the light emitting layer 400 includes a plurality of light emitting elements 41, and the light emitting element 41 is coupled with the driving transistor T0. Since the display panel 1000 provided by the embodiment of the present application includes the array substrate 100 provided by any of the above embodiments, it has the same beneficial effects as the above array substrate embodiments, and specific descriptions can be referred to the above embodiments, which will not be repeated here.

[0178] It should be noted that the display panel provided by the embodiment of the present application can be any type of LED display panel, including but not limited to OLED display panel, micro-LED display panel and mini-LED display panel.

[0179] Exemplarily, Figure 45 Taking the OLED display panel as an example, the light emitting element 41 includes an anode structure 6, a light emitting functional layer 412 and a cathode 413, the light emitting layer 400 further includes a pixel defining layer 42, the pixel defining layer 42 has a pixel opening 420, the pixel opening 420 exposes part of the anode structure 6, the light emitting functional layer 412 is located in the pixel opening 420 and contacts with the anode structure 6, and the cathode 413 covers the light emitting functional layer 413. At this time, the anode structure 6 is directly used as the anode of the OLED light emitting element.

[0180] Exemplarily, Figure 46 is another structural schematic diagram of a display panel provided by the embodiment of the present application, as Figure 46 As shown, in the micro-LED display panel, the light emitting element 41 can be transferred to the array substrate by a large amount of transfer, at this time, the anode structure 6 can be used as an anode pad, the film layer where the anode structure 6 is located further includes a cathode pad 7, the anode structure 6 is used for bonding with the anode of the light emitting element 41, and the cathode pad 7 is used for bonding with the cathode of the light emitting element. It can be understood that in the array substrate, the cathode pad 7 is electrically connected with the second voltage signal line (Elvss, not shown).

[0181] Based on the same inventive concept, the present application also provides a display device comprising the display panel provided by any of the embodiments of the present application. The display device can be any electronic product with display function, including but not limited to the following categories: mobile phone, television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal, etc., and the present application does not make special limitation to this.

[0182] The above detailed description does not limit the scope of the application. Various modifications, combinations, sub-combinations and alternatives can be made to the detailed description. Any modification, equivalent replacement and improvement etc. made within the spirit and principle of the application shall be included in the scope of the application.

Claims

1. An array substrate, comprising: A substrate and a circuit functional layer located on one side of the substrate; the circuit functional layer includes a plurality of transistors, the plurality of transistors including a driving transistor; The characteristic feature is that the channel region of the driving transistor includes at least two active layers; Along a first direction, the at least two active layers are stacked and connected in sequence; the first direction is the direction from the substrate to the circuit functional layer; The channel region includes a first channel region and a second channel region connected along a second direction. Along a third direction, the length of the first channel region is less than the length of the second channel region. The second direction and the third direction intersect and are both parallel to the plane of the substrate.

2. The array substrate according to claim 1, characterized in that, The at least two active layers include: First active layer; The second active layer is located on the side of the first active layer away from the substrate; the second active layer includes a first active portion and a second active portion, and the second active portion is connected between the first active portion and the first active layer. The third active layer is located on the side of the second active layer away from the substrate; the third active layer includes a third active portion and a fourth active portion, the fourth active portion being connected between the first active portion and the third active portion; The plane containing the second active portion intersects the plane containing the fourth active portion; along the first direction and the third direction, the second active portion and the fourth active portion are located on opposite sides of the first active portion; a portion of the orthographic projection of the second active portion on the substrate is located in the first channel region, and another portion is located in the second channel region; the orthographic projection of the fourth active portion on the substrate is located in the second channel region; The planes containing the first active layer, the first active portion, and the third active portion are all parallel to the plane containing the substrate, and the three overlap along the first direction.

3. The array substrate according to claim 2, characterized in that, The array substrate further includes: The first insulating layer is partially located on the side of the first active layer away from the substrate; The second insulating layer is partially located between the second active layer and the first insulating layer, and is connected to the first insulating layer within the channel region; The third insulating layer is partially located on the side of the second active layer away from the second insulating layer; The fourth insulating layer is partially located between the third active layer and the third insulating layer, and is connected to the third insulating layer within the channel region; The fifth insulating layer is partially located on the side of the third active layer away from the fourth insulating layer, and is connected to the second insulating layer within the channel region.

4. The array substrate according to claim 3, characterized in that, The driving transistor further includes at least one of a first gate and a second gate; wherein... The second gate includes a first gate portion and a second gate portion. The first gate portion is located between the first insulating layer and the second insulating layer between the first active layer and the first active portion. At least a portion of the second gate portion is located on the side of the fifth insulating layer away from the third active portion. The first gate portion and the second gate portion are electrically connected. The first gate includes a third gate portion, at least a portion of which is located between the third insulating layer and the fourth insulating layer between the first active portion and the third active portion.

5. The array substrate according to claim 4, characterized in that, The third gate portion extends from between the first active portion and the third active portion to the side of the third insulating layer away from the second active portion; The second gate portion extends from the side of the fifth insulating layer away from the third active portion to the side of the fifth insulating layer away from the fourth active portion, and is connected to the first gate portion.

6. The array substrate according to claim 4, characterized in that, The region where the driving transistor is located includes a notch region; the notch region is adjacent to the second channel region in the second direction and to the first channel region in the third direction; The driving transistor includes a first gate and a second gate; along the first direction, the first gate portion, the second gate portion, and the third gate portion all overlap with the notch region; At least the third gate portion is electrically connected to the data signal transmission structure in the notch region; the data signal transmission structure is disposed at a distance from the first active layer of the driving transistor.

7. The array substrate according to claim 6, characterized in that, The first gate and the second gate are electrically connected; The first gate portion and the third gate portion are electrically connected through a first via, and the first gate portion and the data signal transmission structure are electrically connected through a second via. Both the first via and the second via are located in the notch region.

8. The array substrate according to claim 6, characterized in that, The first gate and the second gate are controlled independently; The third gate portion is electrically connected to the data signal transmission structure through a third via. The third via is located in the notch region and passes through the film layer where the first gate portion is located. The first gate portion is provided with a first opening. The orthographic projection of the area where the third via is located on the substrate is within the orthographic projection range of the area where the first opening is located on the substrate.

9. The array substrate according to claim 6, characterized in that, The first gate further includes a fourth gate portion, the fourth gate portion being located between the first active layer and the substrate; The fourth gate portion is electrically connected to the data signal transmission structure through a fourth via, and the fourth via is located in the notch region.

10. The array substrate according to claim 5, characterized in that, Along the third direction, the third active portion includes a first region, the first region being at least located in the first channel region; The first active layer includes a second region, which is located in the second channel region; The first region and the second region are positioned opposite each other on the substrate by their orthogonal projections along the third direction. The first region is the first electrode lead-out region of the driving transistor, and the second region is the second electrode lead-out region of the driving transistor.

11. The array substrate according to claim 10, characterized in that, The circuit functional layer also includes a storage capacitor, which includes a first capacitor plate and a second capacitor plate that are opposite to and insulated from each other. Along the first direction, the region where the storage capacitor is located does not overlap with the channel region; At least a portion of the orthographic projection of the storage capacitor onto the substrate is located on the side of the orthographic projection of the second active portion onto the substrate that is away from the orthographic projection of the fourth active portion onto the substrate.

12. The array substrate according to claim 11, characterized in that, The driving transistor includes the first gate; the driving transistor also includes a first electrode, which overlaps with the first region of the third active portion; The first capacitor plate is electrically connected to the third gate section; The second capacitor plate is electrically connected to the first electrode, or the second capacitor plate is disposed in the same layer as the first electrode at a distance.

13. The array substrate according to claim 11, characterized in that, The planes containing the first capacitor plate and the second capacitor plate are both parallel to the plane containing the substrate.

14. The array substrate according to claim 11, characterized in that, The storage capacitor includes a first capacitor portion and a second capacitor portion. The plane where the first capacitor portion is located is parallel to the plane where the substrate is located, and the plane where the second capacitor portion is located intersects with the plane where the substrate is located. A support pillar is provided between the first capacitor section and the substrate.

15. The array substrate according to claim 3, characterized in that, The array substrate further includes an interlayer insulating layer, at least a portion of which is located on the side of the third insulating layer away from the second active portion, and the fourth insulating layer covers the interlayer insulating layer. Along the first direction, the thickness of the interlayer insulation layer is greater than the thickness of the third insulation layer.

16. The array substrate according to claim 15, characterized in that, The driving transistor includes a first gate, the first gate includes a third gate portion, a portion of the third gate portion is located between the third insulating layer and the fourth insulating layer between the first active portion and the third active portion, and another portion is located between the interlayer insulating layer and the third insulating layer; Along the first direction, the interlayer insulating layer includes opposing first and second surfaces, the first portion of the third gate portion includes opposing third and fourth surfaces, the second surface is located on the side of the first surface away from the substrate, the fourth surface is located on the side of the third surface away from the substrate, and the second surface is flush with the fourth surface. The first part of the third gate portion is the portion of the third gate portion located between the first active portion and the third active portion.

17. The array substrate according to claim 15, characterized in that, The interlayer insulation layer is located between the third insulation layer and the fourth insulation layer, and is in contact with the third insulation layer and the fourth insulation layer; Along the first direction, the interlayer insulation layer includes a first insulation portion and a second insulation portion; the first insulation portion is located on the side of the third insulation layer away from the second active portion; the second insulation portion is located on the side of the fourth insulation layer away from the third active layer, and a portion of the second insulation portion is located between the first active portion and the third active portion.

18. The array substrate according to claim 10, characterized in that, The driving transistor further includes a first electrode, which overlaps with the first region of the third active portion; The circuit functional layer further includes a data writing transistor. The active layer pattern of the data writing transistor is disposed on the same layer as the first active layer at a distance. The gate of the data writing transistor is disposed on the same layer as the first gate portion at a distance. The first end of the active layer pattern of the data writing transistor is electrically connected to the data signal line through a via. The second end of the active layer pattern of the data writing transistor is electrically connected to the first electrode through a via.

19. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-18; The display panel further includes a light-emitting layer located on the side of the circuit functional layer away from the substrate; the light-emitting layer includes a plurality of light-emitting elements, which are coupled to the driving transistor.

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