Method for producing a photonic or optoelectronic device

Abstract

The present disclosure relates to a method for manufacturing a photonic or optoelectronic device. A method of manufacturing a photonic or optical device includes the steps of: a) providing a semiconductor substrate having a first region and a second region and covered by a stack wherein an upper portion of the stack covering the first region includes a dielectric layer having interconnect elements formed therein covered by metal pads; b) forming a protective layer at least on the metal pad; c) forming a passivation element on the first region and the second region; d) forming a first opening at the first region extending down to the protective layer in front of the metal pad; e) forming a second opening extending downward to the substrate at the second region; and f) making the metal pad accessible by removing the protective layer in the first opening.

Description

[0001] Priority Claim

[0002] This application claims the benefit of priority of French Patent Application No. FR 24 05 065, filed on May 17, 2024, the content of which is incorporated herein by reference in its entirety to the maximum extent allowable by law. TECHNICAL FIELD

[0003] The present disclosure relates generally to photonic or optoelectronic devices, such as image acquisition devices or image sensors, and to methods of manufacturing thereof. BACKGROUND

[0004] The method of manufacturing a photonic or optoelectronic device comprises a plurality of stages.

[0005] In a first stage, called a front-end-of-line (FEOL) stage, components such as, notably, transistors, diodes, resistors and / or capacitors are formed inside and / or on top of a semiconductor substrate.

[0006] In a second stage, called a back-end-of-line (BEOL) stage, the components are interconnected by an electrical interconnection structure. The interconnection structure typically comprises electrically conductive metal tracks (or lines), generally a plurality of metal tracks stacked on a plurality of levels and electrically insulated from each other by insulating layers. Via holes cross one or more insulating layers of the interconnection structure to electrically couple the metal tracks to each other.

[0007] An end of the interconnection structure is the level farthest from the substrate. It can comprise at least one additional metal track and / or at least one metal pad to couple the components of the integrated circuit to other locations of said integrated circuit or to couple the integrated circuit to another electronic circuit, for example a printed circuit.

[0008] The via holes, the metal tracks and the additional metal track can be made of copper.

[0009] In the case of optical and / or photonic devices, the metal pads are often made of aluminum so as to be able to perform wire bonding.

[0010] Such devices are also generally provided with a trench extending from the upper surface of the device to the substrate. The depth of the trench can reach ranges of tens of micrometers, notably in the case of photonic devices.

[0011] Given the depth of the trench, it must be formed at the end of the method.

[0012] The trench is formed, for example, according to the following steps: forming a resin mask, wherein the openings of the mask are arranged in front of the location of the trench, the resin mask covering the pad; etching the trench; and removing the resin.

[0013] However, these steps can cause contamination or damage of the aluminum pads, since on the one hand the long contact between the polymeric material of the resin and the aluminum pads causes contamination of the surface of the aluminum pads, and on the other hand the removal of the resin can damage the surface of the pads.

[0014] There is a need to obtain a method of manufacturing a photonic or optoelectronic device that makes it possible to form deep trenches while preserving the metal pads of the device. SUMMARY

[0015] In an embodiment, the method of manufacturing a photonic or optical device comprises the steps of: a) providing a semiconductor substrate having a first region and a second region, the semiconductor substrate being covered by a stack, an upper part of the stack covering the first region being a dielectric layer, the dielectric layer having formed therein an interconnection element, a metal pad being formed on the interconnection element; b) forming a protective layer on at least the first region to cover at least the metal pad; c) forming a passivation element on the first region and the second region, the passivation element comprising a bottom layer made of a material different from the material of the protective layer; d) forming a first opening in the passivation element above the metal pad, the first opening extending from an upper surface of the passivation element to the protective layer; e) forming a second opening at the level of the second region, the second opening extending from the upper surface of the passivation element to the semiconductor substrate; and f) removing the protective layer positioned in the first opening to make the metal pad accessible.

[0016] According to a particular embodiment, the metal pad is made of aluminum.

[0017] According to a particular embodiment, the protective layer is an alumina layer.

[0018] According to a particular embodiment, the protective layer is removed by wet etching.

[0019] According to a particular embodiment, the protective layer is a nitride layer.

[0020] According to a particular embodiment, an additional oxide layer is formed on at least the metal pad between step a) and step b).

[0021] According to a particular embodiment, the protective layer is removed by dry etching.

[0022] According to a particular embodiment, the bottom layer of the passivation element is made of an oxide.

[0023] According to a particular embodiment, the passivation element further comprises an additional oxide layer and / or a nitride layer.

[0024] According to a particular embodiment, the passivation element comprises in order a bottom layer of undoped silicate glass, an intermediate layer of phosphorus-doped silicon oxide and a top layer of nitride.

[0025] According to a specific embodiment, step d) is performed by etching through a first resin layer exhibiting a through hole in front of the first opening to be formed.

[0026] According to a specific embodiment, step e) is performed by etching through a second resin layer exhibiting a corresponding through hole in front of the second opening to be formed, the second resin layer filling the first opening, and the method comprises removing the resin filling the first opening before step f).

[0027] In an embodiment, a photonic or optical device comprises: a support substrate having a first region and a second region, a semiconductor substrate being stackedly covered, an upper portion of the stack covering the first region being a dielectric layer in which an interconnection element is formed, a metal pad being formed on the interconnection element; a passivation element covering the stack over the first region and the second region, the passivation element comprising a bottom layer; a protection layer being arranged between the stack and the passivation element, the bottom layer being made of a material different from the material of the protection layer; a first opening extending from an upper surface of the passivation element to an upper surface of the metal pad; and a second opening extending from an upper surface of the passivation element to the semiconductor substrate at a level of the second region.

[0028] According to a specific embodiment, the second opening penetrates down into the semiconductor substrate at least 10 pm in depth.

[0029] According to a specific embodiment, the protection layer is made of aluminum earth.

[0030] According to a specific embodiment, the protection layer is made of nitride, and wherein an additional oxide layer is arranged below the protection layer.

[0031] According to a specific embodiment, a portion of the stack covering the second region is a waveguide. BRIEF DESCRIPTION OF DRAWINGS

[0032] The foregoing features and advantages, as well as others, will be described in detail in the remaining portion of the specification as illustrated in the drawings, in which:

[0033] Figures 1 to 10 Different steps of a method of manufacturing a photonic or optoelectronic device are schematically illustrated;

[0034] Figure 11 Side and cross-sectional views of a photonic or optoelectronic device are schematically illustrated; and

[0035] Figure 12 Side and cross-sectional views of a photonic device are schematically illustrated. DETAILED DESCRIPTION

[0036] In the different drawings, different elements are not shown to the same scale so that the drawings are more readable.

[0037] In the various figures, like features are indicated by like reference numbers. In particular, structural and / or functional features common to the various embodiments can have the same reference numbers and can be deployed with the same structure, dimensions, and material properties.

[0038] For the sake of clarity, only those steps and elements of the method and apparatus that are necessary for understanding the described embodiments are shown and described. In particular, Figures 1 to 11 The upper level (or end) of the semiconductor substrate and the interconnect structure is shown, i.e. the level farthest from the substrate. In addition, these figures only show the insulating layers in this upper level in which the interconnect elements covered by conductive pads are formed. However, this upper level can comprise a plurality of interconnect elements (vias and / or pads), a plurality of conductive tracks and / or further insulating layers. The interconnect structure generally also comprises at least one further level below the upper level in which further interconnect elements are particularly arranged. Between the upper level and the substrate, the device comprises an intermediate level. This intermediate level (labeled "Zi") is shown in Figure 12 In Figures 1 to 11 For the sake of legibility of the figures, only the upper part of the interconnect structure and the substrate are shown, without the intermediate level.

[0039] The vias and pads of the interconnect structure can generally be referred to as "interconnect elements", which can also comprise conductive tracks.

[0040] Furthermore, for the sake of clarity, no electronic components formed in the interior or on top of the substrate are shown.

[0041] Unless otherwise indicated, when two elements are mentioned as being connected together, this means that they are directly connected, without any intermediate element other than a conductor, whereas when two elements are mentioned as being coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0042] For the sake of clarity, the expressions "different materials", "chemically different materials", etc. when referring to two materials mean that the two materials differ in terms of their elemental composition, the proportions thereof and / or the manner in which the atomic structure is arranged. For example, they can have different chemical properties (for example, one oxide and one nitride), or they belong to the same class of materials (for example, both are oxide materials) but they comprise at least one structural element (i.e. an element in a stoichiometric percentage of at least 20%) that is different from one another. For example, aluminum oxide (AI2O3) and silicon oxide (SiO2) are considered to be two different materials.

[0043] In the following description, when referring to absolute position qualifiers such as "front", "back", "top", "bottom", "left", "right" or relative position qualifiers such as "top", "bottom", "upper", "lower" or orientation qualifiers such as "horizontal", "vertical", these refer to the orientation of the figures, unless otherwise stated.

[0044] When referring to an upper layer, level or surface, this means the layer, level or surface that is furthest from the substrate compared to another layer, level or surface that is closer to the substrate.

[0045] The expressions "about", "approximately", "substantially" and "… around” mean plus or minus 10%, preferably plus or minus 5%, unless otherwise stated.

[0046] Unless otherwise stated, a range of values from X to Y means that both the terminal values X and Y are included in the range.

[0047] In the remainder of the disclosure, a layer or film is said to be transparent to radiation when the transmission of radiation through the layer or film is greater than 50% and preferably greater than 70%.

[0048] The device can be a photonic device. It can also be an optoelectronic device.

[0049] The method of manufacturing a photonic or optoelectronic device will be described in more detail in connection with Figures 1 to 11 The method of manufacturing a photonic or optoelectronic device will be described in more detail in connection with

[0050] The method comprises the following steps:

[0051] a) providing a base structure comprising a semiconductor substrate 100 having a first region Z1 and a second region Z2, the substrate being covered by a stack, the upper part of the stack covering the first region Z1 being a dielectric layer 210 in which interconnection elements 220 are formed, metal pads 230 being formed on the interconnection elements 220; Figure 1 ) ;

[0052] b) forming a protective layer 300 on at least the metal pads 230; Figure 2 ) ;

[0053] c) forming a passivation element 400 covering the first region Z1 and the second region Z2; Figure 3 ) ;

[0054] d) forming a first opening 601 in the passivation element 400 above the metal pads 230, the first opening 601 extending from an upper surface of the passivation element 400 to the protective layer 300; Figures 4 to 6 ) ;

[0055] e) forming a second opening 602 in the passivation element 400 at the level of the second zone Z2, the second opening 602 extending from the upper surface of the passivation element 400 to penetrate into the substrate 100 Figures 7 to 9 ) ; and

[0056] f) removing the protective layer 300 positioned in the first opening 601 to make the metal pad 230 accessible Figure 10 ).

[0057] The base structure provided at step a) (only a portion of which is shown in the figures) comprises a stack of semiconductor substrate 100 covered. Figures 1 to 11

[0058] The substrate 100 is made of a semiconductor material. Preferably, it is made of silicon. The substrate has a thickness, for example in the range from 775 pm to 850 pm.

[0059] The substrate 100 is covered by a stack comprising different layers and different elements.

[0060] The stack can have a thickness in the range from 10 to 20 pm.

[0061] A first portion of the stack is positioned over the first zone Z1 and a second portion of the stack is positioned over the second zone Z2.

[0062] The first portion of the stack and the second portion of the stack are adjacent. Each portion can have a specific function.

[0063] For example, in the case of a photonic device, the first portion can comprise components covered with an interconnection structure and the second portion of the stack can be, for example, a waveguide.

[0064] The components are, for example, transistors, diodes, resistors and / or capacitors formed inside and / or on top of the substrate 100.

[0065] The interconnection structure comprises an insulating layer crossed by lines and / or vias and / or metal pads. The lines, vias and pads extend in the insulating layer along a depth direction.

[0066] The lines, vias and pads are, for example, made of copper. The insulating layer is, for example, made of silicon dioxide (Si02). The copper elements can be formed by a method known to those skilled in the art called "damascene" process.

[0067] More particularly, the upper interconnection layer 200 comprises an insulating layer 210 in which interconnection elements 220 are formed. The interconnection elements 220 are electrically conductive elements. They are preferably made of copper. They can be pads.

[0068] In the figures, the interconnection elements 220 are exemplarily shown as recessed with respect to the upper surface of the insulating layer 210 of the interconnection structure.​

[0069] The interconnection element 220 is covered with a metallic pad 230. The conductive pad 230 is preferably made of aluminum. It is formed, for example, by plasma vapor deposition (PVD).

[0070] During step b), a protective layer 300 is formed. Figure 2 This protective layer 300 is a layer intended to protect the pad 230, especially during the formation of the second opening 602. The conductive pad 230 is not in contact with the resin, nor with the products necessary to remove the resin.

[0071] The protective layer 300 is deposited at least on the upper surface of the metallic pad 230. Preferably, it can be deposited at least on the first zone Z1. It can be deposited on the first zone Z1 and on the second zone Z2. It can be deposited over the entire board.

[0072] The protective layer 300 can be formed by atomic layer deposition (ALD) techniques or by chemical vapor deposition (CVD) techniques, for example by plasma-enhanced chemical vapor deposition (PECVD) techniques.

[0073] The protective layer 300 can be made of a material chosen from nitrides, carbides, carbonitrides and oxides (or combinations thereof). In particular, the material is chosen from silicon nitride, silicon carbide, silicon carbonitride and aluminum oxide (also called alumina).

[0074] In one embodiment not explicitly shown, the protective layer 300 can be integrated in a protective multilayer (for example, a bilayer). The material forming each sublayer can be chosen from the materials mentioned previously. This protective multilayer is, for example, a silicon nitride / alumina bilayer.

[0075] According to a first embodiment ( Figures 1 to 10 ), the protective layer 300 is preferably made of silicon nitride.

[0076] The protective layer 300 has a thickness in the range from 10 to 80 nm, preferably from 30 to 80 nm, more preferably from 40 to 60 nm.

[0077] An additional oxide layer 310 can be arranged below the protective layer 300. In other words, the additional layer 310 is positioned between the protective layer 300 on the one hand and the pad 230 and the upper interconnection layer 200 on the other hand. The additional layer 310 can have the purpose of simplifying the deposition of the protective layer 300.

[0078] The additional layer 310 is made of, for example, silicon oxide.

[0079] The additional layer 310 has a thickness, for example, in the range from 10 to 30 nm, for example 20 nm.

[0080] This additional layer 310 is for example shown in Figures 1 to 10 .

[0081] According to a second alternative embodiment, as shown in Figure 11 and Figure 12 , the protective layer 300 can be in direct contact with the pads 230 and the upper interconnection layer 200. In this second embodiment, there is no intermediate layer (such as layer 310) between these elements and the protective layer 300. The protective layer 300 can be a layer of oxide, in particular of alumina.

[0082] The alumina protective layer 300 has a thickness in the range from 20 to 40 nm, for example 30 nm.

[0083] The alumina protective layer 300 can be formed by an atomic layer deposition (ALD) process.

[0084] During step c), a passivation element 400 is formed. Figure 3 .

[0085] The passivation element 400 can be a single layer or a stack of multiple layers (multilayer), in particular a bilayer or a trilayer. The passivation element 400 comprises at least one substantially moisture- resistant layer, making it possible to protect the elements below it from moisture. This layer is in particular a nitride layer. More preferably, it comprises a nitride layer 430 arranged on one or more (preferably two) oxide layers 410, 420.

[0086] In particular, the oxide layers 410, 420 are preferably made of a material chosen from undoped silicate glass (USG) or phosphosilicate glass (PSG).

[0087] The passivation element 400 comprises, for example, in order from the protective layer 300: a first oxide layer 410 (bottom layer), preferably made of USG; a second oxide layer 420 (middle layer), preferably made of PSG; a nitride layer 430 (top layer), preferably made of silicon nitride.

[0088] The thickness of the oxide layers 410, 420 can be in the range from 500 to 2000 nm, preferably in the range from 1000 to 1800 nm, for example equal to 1500 nm.

[0089] The first oxide layer 410 and the second oxide layer 420 form a bilayer, the thickness of which is in the range from 500 nm to 2 pm.

[0090] The thickness of the nitride layer 430 can be in the range from approximately 300 to 700 nm, for example equal to approximately 500 nm.

[0091] The passivation element 400 is configured to protect certain elements of the device, in particular the interconnection structure.

[0092] The different layers of the passivation element 400 can be formed by chemical vapor deposition (CVD), in particular by a plasma-enhanced CVD (PECVD) process.

[0093] During step d), a first opening 601 is formed in the first region Z1 above the pads 230. The opening 601 extends from the upper surface of the passivation element 400 to the protective layer 300. The opening can extend to the upper surface of the protective layer 300, or can stop within the thickness of the protective layer 300. In particular, the first opening 601 can be formed by photolithography.

[0094] In order to perform the selective etching, the material of the protective layer 300 is (chemically) different from the material of the bottom layer 410 of the passivation element 400, i.e. of the layer of the passivation element which is more proximate to the protective layer 300 along the vertical direction. Preferably, the bottom layer 410 is in contact with the protective layer 300.

[0095] In case of a protective multilayer, at least the material of the protective layer 300 is (chemically) different from the material of the bottom layer 410, while the other sub-layers of the protective multilayer can be made of any material within the above mentioned materials.

[0096] The first opening 601 is formed, for example, according to the following steps: forming a resin layer 500 on the passivation element 400, the resin layer comprising at least one through hole 501 (501a, 501b) arranged in front of the pads 230; Figure 4 ) etching the passivation element 400 through the pattern; Figure 5 ) removing the resin 500. Figure 6

[0097] The structure obtained at the end of the photolithography step performed on the upper surface of the passivation element 400 is illustrated. Figure 6 The pattern can be obtained through a conventional photolithography step, i.e. depositing a resist layer 500; exposing the resist layer 500 to radiation through a mask defined by opaque and transparent areas to obtain the desired pattern in the resist; and dissolving a portion of the resist layer in a specific aqueous or organic solution called developing solution to develop the pattern and form the through opening 501 above the pads 230.

[0098] For example, the illustrated pattern is obtained by using a positive resist. The portion of the resist exposed to radiation (through the transparent areas of the mask) becomes soluble in the developing solution, and the unexposed portion of the resist (through the opaque areas of the mask) remains insoluble in the developing solution. Alternatively, the resist can also be negative. The portion of the resist exposed to radiation then becomes insoluble in the developing solution, and the unexposed portion of the resist remains soluble in the developing solution.

[0099] ​

[0100] The etching of the passivation element 400 is performed through an etch mask formed by the resist pattern, so that the etching occurs in the openings 501 of the pattern and in the areas not covered by the pattern.

[0101] An etching forms a cavity 601 (first opening) above the pad 230 in the passivation element 400. The protective layer 300 can not be etched or can be substantially not etched when opening the cavity 601. In this case, the bottom of the cavity 601 is located (substantially) at the upper surface of the protective layer 300. Alternatively, the protective layer 300 can be partially etched, for example due to a partial over-etching during the etching step. In this case, the bottom of the cavity 601 is located in the thickness of the protective layer 300.

[0102] The etching can be a dry etching, for example implementing a fluorine-based plasma, or a wet etching, in particular with the help of a solution of a fluorinated acid, for example hydrofluoric acid.

[0103] The acid concentration in the solution and / or the etching time can be adjusted to etch down to a given depth.

[0104] Then, a step of removing the resist layer 500 is performed, for example by dry etching, in particular by implementing an oxygen-based plasma.

[0105] The first opening 601 forms a cavity. The width of the cavity made by the opening 601 is defined by the width of the opening 501 in the resist pattern. The height of the cavity made by the opening 601 is defined by the etching depth.

[0106] For example, the first opening 601 has a circular cross-section. The diameter of the cross-section can be in the range from 40 to 50 pm. The height of the cavity depends on the thickness of the passivation element 400.

[0107] At the end of step d), the protective layer 300 is still present. It acts as an etch stop layer.

[0108] During step e), a second opening 602 is formed at the level of the second region Z2.

[0109] The second opening 602 is a deep trench. By "deep" it is meant a depth of at least 10 pm. The second opening has a depth, for example, in the range from 10 to 100 pm. The second opening 602 extends at least down to the upper surface of the substrate 100 and preferably into the substrate 100. A portion of the substrate 100 is etched. The substrate 100 can be etched down to a depth of from 5 to 60 pm.

[0110] The second opening 602 has a cross-sectional area, for example, greater than 1 mm 2 .

[0111] The second opening 602 is formed, for example, according to the following steps: forming a resin layer 510 on the passivation element 400, the resin layer 510 having a through hole 511 positioned over the second zone Z2, the resin layer 510 filling the first opening 601 Figure 7 ); forming the second opening 602 in the device, the second opening 602 being formed by etching from the upper surface of the passivation element 400, the second opening 602 extending into the substrate 100 Figure 8 ); and removing the resin layer 510 Figure 9 .

[0112] The etching can be a dry etching, for example implementing a fluorine-based plasma, or a wet etching, in particular with the aid of a solution of fluorinated acid, for example hydrofluoric acid.

[0113] The acid concentration in the solution and / or the etching time can be adjusted to etch down to a given depth.

[0114] The protective layer 300 not only forms an intermediate layer between the conductive pads 230 and the resin 510, but also between the pads 230 and the product required to remove the resin. The protective layer 300 forms a diffusion barrier.

[0115] During step f), the protective layer 300 (and, if present, any additional sublayer of the protective multilayer) and possibly the additional layer 310 are removed to make the pads 230 accessible.

[0116] When the protective layer 300 comprises a nitride layer, the etching is, for example, a plasma etching.

[0117] When the protective layer 300 is an alumina layer, the etching is, for example, a wet etching.

[0118] At the end of the method, a device is obtained which has, in the first zone, an additional cavity 601' the bottom of which has access to the metal pads 230, and, in the second zone, a deep trench 602 Figures 10 to 12 . The surface of the pads 230 is neither contaminated nor damaged. The volume of the cavity 601' corresponds to the total volume comprising the volume of the cavity 601 and the volume previously occupied by the protective layer 300 (and, if present, any additional sublayer of the protective multilayer) and possibly by the additional oxide layer 310.

[0119] Figure 12 A photonic device obtained with this method is illustrated, by way of illustration but not limitation.

[0120] In the first zone, there is at least one cavity 601'. The pads 230 are arranged in the cavity 601'. The pads 230 can be used to connect the device to external elements.

[0121] In the second zone Z2, a deep trench 602 is formed. It extends from the upper surface of the passivation element 400 into the substrate 100. It crosses the entire thickness of the first portion of the stack. The deep trench 602 can be used for example for a laser.

[0122] The nitride layer 430 forming the upper layer of the passivation element 400 can be structured to let light pass.

[0123] The use of a protective layer 300 formed from an aluminum earth monolayer is particularly advantageous because it is transparent. It can even be used for a nitride-based waveguide.

[0124] The optical device can be used as an image acquisition device operating in the near infrared (NIR), i.e. for electromagnetic radiation in the wavelength range from 800 nm to 2500 nm, and more particularly in the short-wave infrared (SWIR), i.e. for electromagnetic radiation in the wavelength range from 800 nm to 2000 nm, preferably from 900 nm to 1700 nm, typically 1.4 pm.

[0125] The device can also be used in the implementation of 5G networks, data centers and servers.

[0126] For example, the device is intended to be used in communication equipment or in computers and their peripherals.

[0127] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants can be combined and that other variants will occur to the person skilled in the art.

[0128] Finally, the practical implementation of the described embodiments and variants is within the capabilities of the person skilled in the art, based on the functional indications given above.

Claims

1. A method for manufacturing a photonic or optical device, comprising the following steps: a) Provides a semiconductor substrate having a first region and a second region, wherein the semiconductor substrate is stacked and covered, the upper portion of the stack covering the first region being a dielectric layer, wherein interconnect elements are formed in the dielectric layer, and including metal pads formed on the interconnect elements; b) A protective layer is formed at least in the first region to at least cover the metal pads; c) Forming passivation elements on the first region and the second region, the passivation elements comprising an underlayer made of a material different from the material of the protective layer; d) A first opening is formed in the passivation element above the metal pad at the first region, the first opening extending from the upper surface of the passivation element to the protective layer; e) A second opening is formed in the second region, the second opening extending from the upper surface of the passivation element to the semiconductor substrate; as well as f) Remove the protective layer positioned in the first opening to allow access to the metal pad.

2. The method according to claim 1, wherein, The metal pads are made of aluminum.

3. The method according to claim 1, wherein, The protective layer is a bauxite layer.

4. The method according to claim 2, wherein, Step f) Removing the protective layer includes performing a wet etching.

5. The method according to claim 1, wherein, The protective layer is a nitride layer.

6. The method of claim 5, further comprising forming an additional oxide layer on at least the metal pads between step a) and step b).

7. The method according to claim 5, wherein, Step f) Removing the protective layer includes performing dry etching.

8. The method according to claim 1, wherein, The bottom layer of the passivation element is made of oxide, and the passivation element further includes an additional oxide layer and / or a nitride layer.

9. The method according to claim 1, wherein, The passivation element is a stack of layers comprising, in sequence: a bottom layer made of undoped silicate glass, an intermediate layer made of phosphorus-doped silicon oxide, and a top layer made of nitride.

10. The method according to claim 1, wherein, Step d) forming the first opening includes etching through a first resin layer, which exhibits a through-hole in front of the location where the first opening is to be formed.

11. The method according to claim 10, wherein, Step e) forming the second opening includes etching through a second resin layer, which exhibits a corresponding through-hole in front of the location where the second opening is to be formed.

12. The method according to claim 10, wherein, The second resin layer fills the first opening, and the method further includes removing the resin filling the first opening before step f).

13. A photonic or optical device, comprising: A semiconductor substrate having a first region and a second region; A stack covering the semiconductor substrate, wherein the upper portion of the stack covers the first region and includes a dielectric layer in which interconnect elements are formed and metal pads are formed on the interconnect elements; The stacked passivation elements are covered over the first region and the second region, wherein the passivation elements include a bottom layer; A protective layer is disposed between the stack and the passivation element; The bottom layer is made of a material different from that of the protective layer; The first opening at the first region extends from the upper surface of the passivation element to the upper surface of the metal pad; and The second opening in the second region extends from the upper surface of the passivation element to the semiconductor substrate.

14. The device according to claim 13, wherein, The second opening extends downwards into the semiconductor substrate to a depth of at least 10 μm.

15. The device according to claim 13, wherein, The protective layer is made of bauxite.

16. The device according to claim 13, wherein, The protective layer is made of nitride and also includes an additional oxide layer disposed beneath the protective layer.

17. The device according to claim 13, wherein, The portion of the stack covering the second region is a waveguide.

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