Manufacturing method of sigma groove

Abstract

The invention provides a manufacturing method of a sigma trench, which comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer which are sequentially formed on the gate oxide layer; etching for the first time by taking the second mask layer as a mask until the second mask layer is removed, forming a first groove in the substrate on two sides of the gate structure, and gathering polymers generated by etching the second mask layer in the etching process on the gate oxide layer on the side wall of the first groove and a junction area of the gate oxide layer, the gate and the substrate as an etching protection layer; and performing second etching by taking the first mask layer as a mask, protecting the substrate covered by the etching protection layer from lateral etching by the etching protection layer, and forming a sigma-like groove in the first groove. According to the method, the etching protection layer is formed on the side wall of the first groove through the polymer generated by the second mask layer in the first etching process, the area is prevented from being excessively etched, serious lateral pushing of the area is avoided, and therefore the shape of the groove can be adjusted and controlled more easily.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating sigma trenches. Background Technology

[0002] With the increasing integration density and shrinking critical dimensions of CMOS technology, strained silicon technology is needed to improve the carrier mobility of devices to compensate for Coulomb scattering caused by high doping and interface scattering caused by strong electric fields, thereby improving device speed.

[0003] Strained silicon technology refers to inducing stress in the material and directing that stress towards the device channel. This alters the energy band structure of the conduction or valence band of the silicon material within the channel. Through proper device design, a suitable stress direction can be achieved, thereby reducing the probability of intra- and inter-valley scattering and the effective mass of carriers along the channel direction, ultimately enhancing carrier mobility and increasing device speed. Currently, there are four commonly used strained silicon technologies in the industry: SiGe (silicon-germanium) / CESL (contact hole etch stop layer) for PMOS, and SiC (silicon-carbon) / SMT (stress memory technology) for NMOS.

[0004] SiGe straining technology refers to embedding SiGe into the source and drain regions of a PMOS transistor. This embedding of SiGe strain material can improve the speed of the PMOS transistor. It is achieved through epitaxial growth technology, embedding SiGe material into the source and drain regions to generate uniaxial compressive stress in the channel, altering the band structure of the silicon valence band and reducing the effective mass of hole conductance. Silicon has a lattice constant of 5.431 Å, while germanium has a lattice constant of 5.653 Å, resulting in a higher lattice constant for SiGe than for pure silicon. <110> The compressive stress generated in the direction causes the valence band to split, heavy holes leave the top of the valence band, and light holes occupy the top of the valence band, reducing the effective mass of holes, increasing mobility, and improving the response speed of PMOS.

[0005] SiGe strain technology is widely used to improve the response speed of PMOS in 90nm and below process technology. In this technology, sigma trench etching is one of the key process steps affecting SiGe strain technology. Summary of the Invention

[0006] The purpose of this invention is to provide a method for fabricating sigma trenches, which avoids excessive etching of the substrate near the gate oxide layer, avoids severe side-push, and improves the control of trench shape.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing sigma trenches, comprising the following steps:

[0008] A substrate is provided, on which a gate oxide layer and a gate structure are formed, the gate structure including a gate, a first mask layer and a second mask layer sequentially formed on the gate oxide layer;

[0009] Using the second mask layer as a mask, a first etching process is performed until the second mask layer is removed, forming a first trench within the substrate on both sides of the gate structure. During the etching process, polymer generated by the etching of the second mask layer accumulates on the gate oxide layer on the sidewalls of the first trench and at its interface with the gate and the substrate, serving as an etching protection layer; and

[0010] A second etching is performed using the first mask layer as a mask. The etching protection layer protects the substrate it covers from being laterally etched, forming a sigma-like trench within the first trench.

[0011] Optionally, the first mask layer is a silicon nitride layer, and the second mask layer is a TEOS layer.

[0012] Optionally, the first etching gas used in the first etching includes HBr and O2, and the etching protective layer is a polymer layer.

[0013] Optionally, the method for performing a second etching using the first mask layer as a mask includes the following steps:

[0014] Anisotropic etching is performed using a second etching gas, wherein the lateral etching rate of the substrate is greater than the longitudinal etching rate of the substrate; and

[0015] Anisotropic etching is performed using a third etching gas, and the longitudinal etching rate of the substrate is greater than the lateral etching rate of the substrate.

[0016] Optionally, the second etching gas includes HBr and Cl2, and the third etching gas includes HBr and NF3.

[0017] Optionally, after forming the sigma-like trenches, the fabrication method further includes: performing wet cleaning to remove the etched protective layer.

[0018] Optionally, after wet cleaning, the fabrication method further includes: wet etching the sigma-like trenches to form sigma trenches.

[0019] Optionally, the substrate includes a first region and a second region, and a gate structure is formed on the substrate in at least the first region.

[0020] Optionally, before performing the first etching, the fabrication method further includes: forming a hard mask layer that covers the second region and exposes the first region;

[0021] After the second etching, the fabrication method further includes removing the hard mask layer.

[0022] Optionally, after forming the gate structure on the gate oxide layer, the method further includes: forming a sidewall material layer, the sidewall material layer covering the top, sidewalls and surface of the gate structure;

[0023] After the hard mask layer is formed and before the first etching is performed, the fabrication method further includes: etching the sidewall material layer in the first region to remove the sidewall material layer on the top of the gate structure and on the gate oxide layer, and retaining the sidewall material layer on the sidewall of the gate structure as a sidewall.

[0024] In summary, the method for fabricating a sigma trench provided by this invention first provides a substrate, on which a gate oxide layer and a gate structure are formed. The gate structure includes a gate, a first mask layer, and a second mask layer sequentially formed on the gate oxide layer. Then, using the second mask layer as a mask, a first etching is performed until the second mask layer is removed, forming a first trench in the substrate on both sides of the gate structure. During the etching process, polymer generated by the etching of the second mask layer accumulates on the gate oxide layer on the sidewall of the first trench and at the interface between it and the gate and the substrate as an etching protection layer. Next, using the first mask layer as a mask, a second etching is performed, and the etching protection layer protects the substrate it covers from lateral etching, forming a sigma trench in the first trench. Compared with existing methods for forming sigma trenches, this invention uses a polymer generated during the first etching process through a second mask layer to form an etching protection layer on the sidewall of the first trench. This etching protection layer covers the gate oxide layer and its interface with the gate and substrate. During the second etching process, since the second mask layer has been removed, there is no polymer accumulation to form the etching protection layer again, or the polymer accumulation decreases rapidly. This accelerates the lateral etching of the substrate below the etching protection layer, while the area of ​​the substrate near the gate oxide layer is not excessively etched due to the protection of the etching protection layer, thus avoiding severe lateral push-out in this area. This makes it easier to control the shape of the trench.

[0025] This invention forms sigma-like trenches through a first and second etching process, which reduces the difficulty of subsequent wet etching using TMAH compared to existing technologies that form U-shaped or bow-shaped trenches. Attached Figure Description

[0026] Figures 1 to 7 This is a schematic diagram of the steps involved in forming an arc-shaped groove according to an embodiment of the present invention.

[0027] Figure 8This is a flowchart of a method for manufacturing sigma trenches according to an embodiment of the present invention.

[0028] Figures 9 to 16 This is a schematic diagram of the steps in a method for manufacturing sigma trenches according to an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures:

[0030] Figures 1 to 7 In the middle: 10-substrate; 11-gate oxide layer; 20-gate structure; 21-gate; 22-gate mask layer; 23-first sidewall material layer; 24-second sidewall material layer; 25-first sidewall; 26-second sidewall; 30-bottom anti-reflective layer; 31-patterned photoresist layer; 41-first trench; 42-second trench; 43-arch trench.

[0031] Figures 9 to 16 100 - Substrate; 110 - Gate oxide layer; 200 - Gate structure; 210 - Gate; 220 - First mask layer; 230 - Second mask layer; 240 - Sidewall material layer; 250 - Sidewall; 300 - Hard mask layer; 310 - Patterned photoresist layer; 320 - Hard mask material layer; 400 - Sigma trench; 410 - First trench; 420 - Second trench; 430 - Quasi-sigma trench; 500 - Etching protection layer. Detailed Implementation

[0032] SiGe strained silicon technology typically employs dry etching to form U-shaped or bow-shaped trenches in the PMOS source and drain regions. Then, wet etching (PET) is performed using DHF (diluted hydrofluoric acid) + SPM (H2SO4 / H2O2, sulfuric acid / hydrogen peroxide) + SC1 (standard cleaning solution No. 1, a mixture of ammonia, hydrogen peroxide, and water). Finally, TMAH (tetramethylammonium hydroxide solution) is used for wet etching to form sigma trenches. A key feature of TMAH is its ability to... <100> Face to face <111> The etching selectivity for silicon on the surface can reach 40:1 to 70:1, so the wet etching of silicon can be stopped at... <111> The surface then forms sigma trenches.

[0033] For U-shaped trenches, dry etching is a simple process with stable in-line etching; however, the TMAH process is relatively difficult to control. For bow-shaped trenches, dry etching is more complex, and while various in-line parameters are adjustable at each etching stage, its in-line etching stability is poor due to the influence of film thickness.

[0034] Figures 1 to 7 This is a schematic diagram illustrating the steps involved in forming an arc-shaped groove according to an embodiment of the present invention. Please refer to... Figure 1As shown, a substrate 10 is provided, which includes a first region I and a second region II. For example, the first region I is a PMOS region, and the second region II is an NMOS region. A gate oxide layer 11 and a gate structure 20 formed on the gate oxide layer 11 are formed on the substrate 10. The gate structure 20 includes a gate 21 and a gate mask layer 22. A first sidewall material layer 23 and a second sidewall material layer 24 are formed on the sidewalls and top of the gate structure 20 and on the top of the gate oxide layer 11. The first sidewall material layer 23 covers the sidewalls and top of the gate structure 20 and the surface of the gate oxide layer 11, and the second sidewall material layer 24 covers the first sidewall material layer 23. In this embodiment, the first sidewall material layer 23 is a silicon oxide layer, the second sidewall material layer 24 is a silicon nitride layer, and the gate material layer 22 is a silicon nitride layer.

[0035] In one embodiment, the method for forming the gate structure 20 includes: sequentially forming a gate material layer, a gate mask material layer, and a TEOS (tetraethoxysilane) material layer on the gate oxide layer 110; then sequentially etching the TEOS material layer, the gate mask material layer, and the gate material layer until a portion of the gate oxide layer 11 is exposed, forming a gate 21, a gate mask layer 22, and a TEOS layer located on a portion of the gate oxide layer 11; subsequently removing the TEOS layer by wet etching, wherein the gate structure 20 includes only the gate 21 and the gate mask layer 22.

[0036] A bottom anti-reflective layer 30 is also formed on the substrate 10. The bottom anti-reflective layer 30 covers the second sidewall material layer 34 and fills the groove between adjacent gate structures 20. The bottom anti-reflective layer 30 has a flat upper surface. A patterned photoresist layer 31 is formed on the bottom anti-reflective layer 30 above the second region II.

[0037] Please refer to Figure 2 As shown, using the patterned photoresist layer 31 as a mask, the bottom anti-reflective layer 30 in the first region I is etched away, exposing the second sidewall material layer 24.

[0038] Please refer to Figure 3 As shown, the second sidewall material layer 24 on the top of the gate structure 20 and on the gate oxide layer 11 between the gate structures 20 within the first region I is removed, and a second sidewall 26 is formed on the sidewall of the gate structure 20. Then, please refer to... Figure 4As shown, the first sidewall material layer 23 on the top of the gate structure 20 and the gate oxide layer 11 between the gate structures 20 in the first region I is removed, and a first sidewall 25 is formed on the sidewall of the gate structure 20, and a second sidewall 26 covers the sidewall of the first sidewall 25.

[0039] Please continue to refer to this. Figure 4 As shown, using the gate mask layer 22 as a mask, the substrate 10 between adjacent gate structures 20 is etched to form a first trench 41 in the substrate 10 (i.e. the PMOS source and drain regions) on both sides of the gate structure 20.

[0040] Please refer to Figure 5 As shown, the substrate 10 is further etched to form a second trench 42 within the first trench 41. In this embodiment, the first trench 41 is a relatively regular inverted T-shaped trench with a wider top and narrower bottom, while the second trench 42 has a U-shaped cross-section.

[0041] Please refer to Figure 6 As shown, etching continues on the substrate 10 to form an arc-shaped trench 43 within the second trench 42. Please refer to... Figure 7 As shown, the patterned photoresist layer 31 and the bottom anti-reflective layer 30 are removed from the second region II.

[0042] Please refer to Figure 6 and Figure 7 As shown, the bow-shaped trench formed by the above method has more lateral etching in the region of the substrate 10 near the gate oxide layer 11, resulting in severe lateral pushing, making it difficult to control the subsequent wet etching process of the bow-shaped trench.

[0043] To address the aforementioned technical problems, this invention provides a method for fabricating sigma trenches. The trenches formed by dry etching are sigma trenches, which can improve side thrust and reduce the difficulty of subsequent wet etching processes.

[0044] Specifically, the present invention provides a method for fabricating a sigma trench, comprising the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer sequentially formed on the gate oxide layer; performing a first etching using the second mask layer as a mask until the second mask layer is removed, forming a first trench in the substrate on both sides of the gate structure, wherein polymer generated during the etching process due to the etching of the second mask layer accumulates on the gate oxide layer on the sidewall of the first trench and at the interface between it and the gate and the substrate as an etching protection layer; and performing a second etching using the first mask layer as a mask, the etching protection layer protecting the substrate it covers from lateral etching, forming a sigma trench in the first trench.

[0045] Compared with existing methods for forming sigma trenches, this invention uses a polymer generated during the first etching process via a second mask layer to form an etching protection layer on the sidewall of the first trench. This etching protection layer covers the gate oxide layer and its interface with the gate and substrate. During the second etching process, since the second mask layer has been removed, there is no polymer accumulation to form the etching protection layer again, or the polymer accumulation decreases rapidly. This accelerates the lateral etching of the substrate below the etching protection layer, while the area of ​​the substrate near the gate oxide layer is not excessively etched due to the protection of the etching protection layer, thus avoiding severe lateral push-out in this area. This makes it easier to control the trench shape.

[0046] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0047] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0048] Figure 8 This is a flowchart of a method for fabricating sigma trenches according to an embodiment of the present invention. Figure 8 As shown, the method for manufacturing sigma trenches provided in this embodiment of the invention includes the following steps:

[0049] S1: Provide a substrate, and form a gate oxide layer and a gate structure on the substrate, wherein the gate structure includes a gate, a first mask layer and a second mask layer sequentially formed on the gate oxide layer;

[0050] S2: Using the second mask layer as a mask, a first etching is performed until the second mask layer is removed, forming a first trench in the substrate on both sides of the gate structure. During the etching process, polymer generated by the etching of the second mask layer accumulates on the gate oxide layer on the sidewall of the first trench and at its interface with the gate and the substrate as an etching protection layer; and

[0051] S3: A second etching is performed using the first mask layer as a mask. The etching protection layer protects the substrate it covers from being laterally etched, forming a sigma-like trench in the first trench.

[0052] Figures 9 to 16 This is a schematic diagram illustrating the steps of a method for fabricating sigma trenches according to an embodiment of the present invention. Next, we will combine... Figure 8 and Figures 9 to 16 The method for manufacturing sigma trenches provided in the embodiments of the present invention will be described in detail.

[0053] In step S1, please refer to Figure 9As shown, a substrate 100 is provided, on which a gate oxide layer 110 and a gate structure 200 are formed. The gate structure 200 includes a gate 210, a first mask layer 220 and a second mask layer 230 sequentially formed on the gate oxide layer 110.

[0054] In this embodiment, the substrate 100 can be made of silicon, germanium, germanium-silicon, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 100 is preferably made of silicon.

[0055] In one embodiment of the present invention, the substrate 100 includes a first region I and a second region II. The first region I is, for example, a PMOS region, and the second region II is, for example, an NMOS region, but is not limited thereto. At least a gate structure 200 is formed on the substrate 100 within the first region I. In this embodiment, the gate structure 200 is formed on the substrate 100 within both the first region I and the second region II. An isolation structure (not shown) is formed in the substrate 100 between adjacent gate structures 200. Source / drain regions (not shown) are also formed in the substrate 100 on both sides of the gate structure 200, and subsequently, sigma trenches are formed in the source / drain regions.

[0056] In one embodiment of the present invention, the gate oxide layer 110 is formed on the entire substrate 100, that is, the gate oxide layer 110 covers the substrate 100. The material of the gate oxide layer 110 is, for example, silicon dioxide, and the methods for forming the gate oxide layer 110 include, but are not limited to, wet oxidation, dry oxidation, and in-situ steam generation (ISSG). Wet oxidation involves introducing water vapor into a reaction chamber at high temperature to react with the surface of the semiconductor substrate 100 to form a silicon oxide layer; wet oxidation has a relatively fast growth rate. Dry oxidation involves introducing dry oxygen into a reaction chamber at high temperature to react with the surface of the semiconductor substrate 100 to form a silicon oxide layer; dry oxidation can form an oxide film with high uniformity and density. ISSG involves introducing hydrogen and oxygen into a reaction chamber at high temperature in a certain proportion; the hydrogen and oxygen react chemically at high temperature to generate a large number of gaseous active free radicals, the main component of which is oxygen atom free radicals. Due to the strong oxidizing effect of the oxygen atom free radicals, they react with the silicon on the surface of the semiconductor substrate 100 to obtain a silicon oxide layer. The gate oxide layer 110 obtained by the ISSG process has fewer bulk defects and a relatively small interface state density.

[0057] The gate structure 200 includes a gate 210 formed on a portion of the gate oxide layer 110, and a first mask layer 220 and a second mask layer 230 sequentially formed on the gate 210. For example, the gate 210 is made of polysilicon, the first mask layer 220 is made of silicon nitride, and the second mask layer 230 is made of TEOS.

[0058] In one embodiment of the present invention, the method for forming the gate structure 200 includes: sequentially forming a gate material layer, a first mask material layer, and a second mask material layer on the gate oxide layer 110, wherein the gate material layer is made of polysilicon, the first mask material layer is made of silicon nitride, and the second mask material layer is made of TEOS. The formation method includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Then, the second mask material layer, the first mask material layer, and the gate material layer are sequentially etched until a portion of the gate oxide layer 110 is exposed, forming a gate 210, a first mask layer 220, and a second mask layer 230 located on a portion of the gate oxide layer 110, thereby forming the gate structure 200. The etching method described above may employ, for example, dry etching, wet etching, or a combination of dry and wet etching processes. In other embodiments, the gate 210 may also be a metal gate, such as a metal material with a low coefficient of thermal expansion, such as nickel, molybdenum or tungsten.

[0059] In the prior art, after the gate structure 200 is formed, the second mask layer 230 is removed during wet etching. In this embodiment of the invention, after the gate structure 200 is formed, the second mask layer 230 is not removed, that is, the TEOS layer is not removed, and the second mask layer 230 is used as the etching mask layer during subsequent etching.

[0060] In one embodiment of the present invention, after forming the gate structure 200, the method further includes forming a sidewall material layer 240, which covers the top, sidewalls, and surface of the gate oxide layer 110 of the gate structure 200. The sidewalls located on the sidewalls of the gate structure 200 are subsequently formed by etching. The sidewall material layer 240 is made of silicon nitride. Alternatively, the sidewall material layer 240 can be one or more stacked structures composed of silicon oxide and silicon nitride or other materials, and can be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods known to those skilled in the art.

[0061] In one embodiment of the present invention, the substrate 100 includes a first region I and a second region II. Before the first etching, a hard mask layer 300 needs to be formed. The hard mask layer 300 covers the region that does not need to be etched. In this embodiment, the hard mask layer 300 covers the second region II. Exemplarily, the hard mask layer 300 is made of BARC (Bottom Anti-Reflective Coatings) or silicon nitride, and can be formed by spin coating or chemical vapor deposition processes.

[0062] For example, firstly, a hard mask material layer 320 is formed, which covers the gate structure 200 and the groove between the gate structure 200, i.e., the hard mask material layer 320 covers the sidewall material layer 240 and has a flat upper surface. Then, a photoresist layer is formed on the hard mask material layer 320, and the photoresist layer is patterned to form a patterned photoresist layer 310. The patterned photoresist layer 310 exposes the first region I, forming a shape as shown in the image. Figure 9 The structure is shown. Next, using the patterned photoresist layer 310 as a mask, the hard mask material layer 320 is etched until the sidewall material layer 240 within the first region I is exposed. The remaining hard mask material layer 320 covers the second region II as a hard mask layer 300, forming the structure shown. Figure 10 The structure shown.

[0063] In step S2, please refer to Figure 13 As shown, the second mask layer 230 is used as a mask for the first etching until the second mask layer 230 is removed, forming a first trench 410 in the substrate 100 on both sides of the gate structure 200. During the etching process, the polymer generated by the etching of the second mask layer 230 accumulates on the gate oxide layer 110 on the sidewall of the first trench 410 and at its interface with the gate 210 and the substrate 100 to serve as an etching protection layer 500.

[0064] In one embodiment of the present invention, before the first etching, the method further includes: etching the sidewall material layer 240 within the first region I to remove the sidewall material layer 240 on the top of the gate structure 200 and on the gate oxide layer 110, retaining the sidewall material layer 240 on the sidewalls of the gate structure 200 as sidewalls 250, forming as shown in the figure. Figure 11 The structure shown. The sidewalls 250 can be formed using a maskless etching method, such as plasma etching.

[0065] In one embodiment of the present invention, after forming the sidewall 250, the method further includes: etching the gate oxide layer 110 exposed on both sides of the gate structure 200 to expose the substrate 100, forming a structure as shown in the figure. Figure 12 The structure shown. Etching methods include, but are not limited to, dry etching, wet etching, or a combination of dry and wet etching processes.

[0066] In one embodiment of the present invention, the first etching is anisotropic dry etching. The first etching gas used in the first etching includes HBr and O2, with HBr as the main gas. HBr has good anisotropy. Due to the presence of the second mask layer 230, a polymer protective layer is easily generated during the etching process and accumulates at the interface of the gate oxide layer 110. Increasing O2 can further passivate the surface, reduce side cuts, and accelerate the nucleation and accumulation of polymers at the interface of the gate oxide layer 110. The second mask layer 230 is a TEOS layer. The TEOS layer and the polymer generated by the first etching gas accumulate on the sidewall of the first trench 410 to form an etching protective layer 500, which is, for example, a polymer layer.

[0067] In step S3, please refer to Figure 15 As shown, the first mask layer 220 is used as a mask for the second etching. The etching protection layer 500 protects the substrate 100 it covers from being laterally etched, and a sigma-like trench 430 is formed in the first trench 410.

[0068] During the first etching, the second mask layer 230 is removed. As the second etching begins after the first etching, since the second mask layer 230 has been removed, there is no polymer accumulation to form an etch protection layer, or the polymer accumulation decreases rapidly. This accelerates the lateral etching of the substrate 100 below the etch protection layer 500, ultimately forming a sigma-like trench 430 within the substrate 100. The region of the substrate 100 near the gate oxide 110 layer is not excessively etched due to the protection of the etch protection layer 500, thus avoiding severe lateral pushing in this region and making it easier to control the shape of the sigma-like trench 430.

[0069] In one embodiment of the present invention, the method for performing a second etching using the first mask layer 220 as a mask includes the following steps: performing anisotropic etching using a second etching gas, wherein the lateral etching rate of the substrate 100 is greater than the longitudinal etching rate of the substrate 100; and performing anisotropic etching using a third etching gas, wherein the longitudinal etching rate of the substrate 100 is greater than the lateral etching rate of the substrate 100. The second etching is also anisotropic dry etching.

[0070] In one embodiment of the present invention, the second etching gas includes HBr and Cl2, with HBr as the main gas. HBr has good anisotropy, and the removal of the second mask layer 230 causes a rapid decrease in polymer aggregation, while the addition of Cl2 is beneficial for lateral etching. During this etching process, the lateral etching rate of the substrate 100 is greater than the longitudinal etching rate of the substrate 100. Lateral etching refers to the direction parallel to the substrate 100, and longitudinal etching refers to the direction perpendicular to the substrate 100. Ultimately, a second trench 420 is formed within the substrate 100. Figure 14 As shown. Due to the protection of the etching protection layer 500, during this etching process, the substrate 100 that is not protected by the etching protection layer 500 is mainly etched laterally, while the substrate 100 protected by the etching protection layer 500 is not etched excessively, thus avoiding severe side cuts in this area and making it easier to control the trench shape.

[0071] In one embodiment of the present invention, the third etching gas includes HBr and NF3, with HBr as the main gas. HBr has good anisotropy, while NF3 has a higher etching rate, resulting in a longitudinal etching rate greater than a lateral etching rate on the substrate 100 during the etching process. This ultimately forms a sigma-like trench 430 within the substrate 100. Figure 15 As shown.

[0072] In the method for fabricating sigma trenches provided by this invention, a substrate 100 is first provided, and a gate oxide layer 110 and a gate structure 200 are formed on the substrate 100. The gate structure 200 includes a gate 210, a first mask layer 220, and a second mask layer 230 sequentially formed on the gate oxide layer 110. Then, using the second mask layer 230 as a mask, a first etching is performed until the second mask layer 230 is removed, forming a second sigma trench in the substrate 100 on both sides of the gate structure 200. In the first trench 410, during the etching process, the polymer generated by the etching of the second mask layer 230 accumulates on the gate oxide layer 110 on the sidewall of the first trench 410 and at the interface between it and the gate 210 and the substrate 100 to serve as an etching protection layer 500; then, a second etching is performed using the first mask layer 220 as a mask, and the etching protection layer 500 protects the substrate 100 it covers from being laterally etched, thus forming a sigma-like trench 430 in the first trench 410.

[0073] Compared with existing methods for forming sigma trenches, the present invention uses polymer generated during the first etching process through the second mask layer 230 to form an etching protection layer 500 on the sidewall of the first trench 410. The etching protection layer 500 covers the gate oxide layer 110 and its interface region with the gate 210 and the substrate 100. During the second etching process, since the second mask layer 230 has been removed, there is no polymer accumulation to form the etching protection layer 500, or the polymer accumulation decreases rapidly. This accelerates the lateral etching of the substrate 100 below the etching protection layer 500. The area of ​​the substrate 100 near the gate oxide layer 110 is not excessively etched due to the protection of the etching protection layer 500, thus avoiding severe lateral push in this area and making it easier to control the trench shape.

[0074] In one embodiment of the present invention, after forming the sigma-like trench 430, the fabrication method further includes: performing wet cleaning to remove the etch protective layer 500. For example, DHF+SPM+SC1 can be used for wet cleaning to remove the etch protective layer 500.

[0075] In one embodiment of the present invention, after wet cleaning, the method further includes: wet etching the sigma-like trench 430 to form a sigma trench 400, such as... Figure 16 As shown. The etching solution used in the wet etching process includes TMAH (tetramethylammonium hydroxide) or ammonia, and may also include NH4OH, NH3OH, KOH, NaOH, BTMH (benzyltrimethylammonium hydroxide) or combinations thereof.

[0076] The wet etching is directional etching, and the etching rate varies depending on the crystal orientation of the substrate 100. For example, for <100> and <110> It has a very high etching rate, for <111> It has a very low etching rate, thus etching out sigma-shaped trenches.

[0077] In one embodiment of the present invention, after forming the sigma-like trench 430 and before performing wet cleaning, or after forming the sigma trench 400, the method further includes: removing the patterned photoresist layer 310 and the hard mask layer 300.

[0078] The present invention forms sigma-like trenches 430 through a first and second etching process, which reduces the difficulty of subsequent wet etching using TMAH compared to the existing technology that forms U-shaped or bow-shaped trenches.

[0079] In summary, the method for fabricating a sigma trench provided by this invention first provides a substrate, on which a gate oxide layer and a gate structure are formed. The gate structure includes a gate, a first mask layer, and a second mask layer sequentially formed on the gate oxide layer. Then, using the second mask layer as a mask, a first etching is performed until the second mask layer is removed, forming a first trench in the substrate on both sides of the gate structure. During the etching process, polymer generated by the etching of the second mask layer accumulates on the gate oxide layer on the sidewall of the first trench and at the interface between it and the gate and the substrate as an etching protection layer. Next, using the first mask layer as a mask, a second etching is performed, and the etching protection layer protects the substrate it covers from lateral etching, forming a sigma trench in the first trench. Compared with existing methods for forming sigma trenches, this invention uses a polymer generated during the first etching process via a second mask layer to form an etching protection layer on the sidewall of the first trench. This etching protection layer covers the gate oxide layer and its interface with the gate and substrate. During the second etching process, since the second mask layer has been removed, there is no polymer accumulation to form the etching protection layer again, or the polymer accumulation decreases rapidly. This accelerates the lateral etching of the substrate below the etching protection layer, while the area of ​​the substrate near the gate oxide layer is not excessively etched due to the protection of the etching protection layer, thus avoiding severe lateral push-out in this area. This makes it easier to control the trench shape.

[0080] This invention forms sigma-like trenches through a first and second etching process, which reduces the difficulty of subsequent wet etching using TMAH compared to existing technologies that form U-shaped or bow-shaped trenches.

[0081] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing sigma trenches, characterized in that, The method comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer formed on the gate oxide layer in sequence; performing a first etching with the second mask layer as a mask until the second mask layer is removed, forming a first trench in the substrate on both sides of the gate structure, and the polymer generated by etching the second mask layer is accumulated on the gate oxide layer of the sidewall of the first trench and the junction area of the gate and the substrate to serve as an etching protection layer; and performing a second etching with the first mask layer as a mask, the etching protection layer protecting the substrate covered thereby from lateral etching, and forming a sigma-like trench in the first trench.

2. The method for manufacturing sigma trenches according to claim 1, characterized in that, The first mask layer is a silicon nitride layer, and the second mask layer is a TEOS layer.

3. The method for manufacturing sigma trenches according to claim 2, characterized in that, The first etching gas used in the first etching comprises HBr and O2, and the etching protection layer is a polymer layer.

4. The method of claim 1, wherein the sigma trench is formed by a process selected from the group consisting of: reactive ion etching, dry etching, wet etching, and combinations thereof. The method for performing the second etching with the first mask layer as a mask comprises the following steps: performing anisotropic etching with a second etching gas, the lateral etching rate of the substrate being greater than the longitudinal etching rate of the substrate; and performing anisotropic etching with a third etching gas, the longitudinal etching rate of the substrate being greater than the lateral etching rate of the substrate.

5. The method of claim 4, wherein the sigma trench is formed by a process selected from the group consisting of: reactive ion etching, dry etching, wet etching, and combinations thereof. The second etching gas comprises HBr and Cl2, and the third etching gas comprises HBr and NF3.

6. The method of claim 1, wherein the sigma trench is formed by a process selected from the group consisting of: reactive ion etching, dry etching, wet etching, and combinations thereof. After forming the sigma-like trench, the manufacturing method further comprises performing wet cleaning to remove the etching protection layer.

7. The method of claim 6, wherein the sigma trench is formed by a process comprising: After performing the wet cleaning, the manufacturing method further comprises performing wet etching on the sigma-like trench to form a sigma trench.

8. The method of claim 1 to 7, wherein The substrate comprises a first region and a second region, and the gate structure is formed on the substrate in at least the first region.

9. The method of claim 8, wherein the sigma trench is formed by a process selected from the group consisting of: reactive ion etching, dry etching, wet etching, and combinations thereof. Before performing the first etching, the manufacturing method further comprises forming a hard mask layer, the hard mask layer covering the second region and exposing the first region; After performing the second etching, the manufacturing method further comprises removing the hard mask layer.

10. The method of claim 8, wherein the sigma trench is formed by a process selected from the group consisting of: reactive ion etching, dry etching, wet etching, and combinations thereof. After forming the gate structure on the gate oxide layer, the manufacturing method further comprises forming a sidewall material layer, the sidewall material layer covering the top of the gate structure, the sidewall of the gate structure and the surface of the gate oxide layer; After forming the hard mask layer and before performing the first etching, the manufacturing method further comprises etching the sidewall material layer on the first region, removing the sidewall material layer on the top of the gate structure and the gate oxide layer, and retaining the sidewall material layer on the sidewall of the gate structure as a sidewall.

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