Image sensor

Abstract

An image sensor includes: a first region disposed in a first direction and a second direction parallel to an upper surface of a substrate, where the first direction and the second direction intersect each other; a second region provided in the first direction and the second direction; a first photodiode in the first region; a second photodiode in the second region; an image sensing pixel circuit configured to generate a first electrical signal based on a charge generated by the first photodiode; an event sensing pixel circuit configured to generate a second electrical signal based on a change in an amount of charge generated by the second photodiode; and a logic circuit electrically connected to the image sensing pixel circuit, in which the first region is disposed diagonally to the second region in a third direction, and in which the third direction is different from the first direction and the second direction.

Description

TECHNICAL FIELD

[0001] The disclosure relates to an image sensor. BACKGROUND

[0002] An image sensor is a semiconductor-based sensor configured to receive light and generate an electrical signal. The image sensor can include a pixel array having a plurality of pixels and a circuit for driving the pixel array and generating an image. The plurality of pixels can include a photodiode configured to generate an electric charge in response to external light and a pixel circuit configured to convert the electric charge generated by the photodiode into an electrical signal.

[0003] Depending on the signal output by the image sensor, there are several types of image sensors, for example, a CMOS image sensor (CIS) configured to output a grayscale image signal, and a dynamic vision sensor (DVS) configured to sense a change in brightness and output an event signal. A conventional method for mixing CIS pixels and DVS pixels can introduce noise due to varying parasitic capacitance and require color reconstruction. SUMMARY

[0004] The disclosure provides a hybrid image sensor having heterogeneous pixels such as CIS pixels and DVS pixels.

[0005] The disclosure provides an image sensor for preventing occurrence of fixed pattern noise in image data, efficiently performing motion deblurring of the image data, and minimizing a computation amount required for color reconstruction.

[0006] According to an aspect of the disclosure, an image sensor includes a first region disposed along a first direction and a second direction parallel to an upper surface of a substrate, wherein the first direction and the second direction intersect each other, a second region disposed along the first direction and the second direction, a first photodiode located in the first region, a second photodiode located in the second region, an image sensing pixel circuit configured to generate a first electrical signal based on an electric charge generated by the first photodiode, an event sensing pixel circuit configured to generate a second electrical signal based on a change in an amount of electric charge generated by the second photodiode, and a logic circuit electrically connected to the image sensing pixel circuit, wherein the first region is diagonally disposed with the second region in a third direction, and wherein the third direction is different from the first direction and the second direction.

[0007] According to an aspect of the disclosure, an image sensor includes a substrate, a first photodiode located in a first region in the substrate, a second photodiode located in a second region in the substrate, a third photodiode located in a third region in the substrate, a fourth photodiode located in a fourth region in the substrate, a transfer transistor, a reset transistor, and an event sensing pixel circuit configured to generate an electrical signal based on a change in an amount of charge generated by the second photodiode, wherein the third region is disposed directly adjacent to the first region in a first direction in a plan view, wherein the fourth region is disposed directly adjacent to the first region in a second direction perpendicular to the first direction in the plan view, wherein the second region is disposed directly diagonally to the first region in a third direction different from the first direction and the second direction in the plan view, wherein a light-receiving area of each of the first photodiode, the third photodiode, and the fourth photodiode is greater than a light-receiving area of the second photodiode, and wherein the transfer transistor and the reset transistor are shared by the first photodiode.

[0008] According to an aspect of the disclosure, an image sensor includes a substrate including a first surface and a second surface opposite the first surface, a first photodiode located in a first region in the substrate, a second photodiode located in a second region in the substrate, a first microlens located on the first photodiode, a second microlens located on the second photodiode, an image sensing pixel circuit configured to generate a first electrical signal based on charge generated in the first photodiode, an event sensing pixel circuit configured to generate a second electrical signal based on a change in an amount of charge generated by the second photodiode, a deep trench isolation located between the first region and the second region, and a logic circuit electrically connected to the image sensing pixel circuit, wherein the first region is directly adjacent to the second region, wherein the deep trench isolation is in contact with the first surface of the substrate and the second surface of the substrate, and wherein a width of the first microlens in a first direction is greater than a width of the second microlens in the first direction in a plan view.

[0009] Aspects of the disclosure to be addressed are not limited to the above-mentioned aspects, and other aspects not mentioned herein will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of an image sensor according to an example embodiment of the present disclosure; FIG. 2 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; FIGS. 3A-3C is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; FIGS. 4-7 is a plan view of a pixel array included in an image sensor according to an example embodiment of the present disclosure; FIG. 8A and FIG. 8B is a circuit diagram illustrating a pixel circuit of an image sensor according to an example embodiment of the present disclosure; FIG. 9 is a view illustrating a layout of an image sensor according to an example embodiment of the present disclosure; FIGS. 10-14 is a view illustrating a pixel included in an image sensor according to an example embodiment of the present disclosure; FIG. 15 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; FIG. 16 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; FIGS. 17-19 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; FIG. 20 is a circuit diagram illustrating a pixel circuit of an image sensor according to an example embodiment of the present disclosure; FIGS. 21-23 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; FIGS. 24-26 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; FIGS. 27-29 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure; and FIG. 30 is a view illustrating a layout of an image sensor according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] This specification merely illustrates the principles of this disclosure. Those skilled in the art will be able to design one or more arrangements that, while not explicitly described herein, embody the principles of this disclosure. Furthermore, the explicit primary intent of all examples described herein is for illustrative purposes only, to aid the reader in understanding the principles of this disclosure and the concepts contributed by the inventors to advance the art, and is to be construed as not being limited to such specific examples and conditions. Moreover, all statements and specific examples of the various principles, aspects, and embodiments of this disclosure herein are intended to encompass equivalent forms of the embodiments.

[0012] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of another embodiment. Singular expressions may include plural expressions unless a different meaning is clearly understood in the context. The terms used herein (including technical or scientific terms) may have the same meaning as commonly understood by one of ordinary skill in the art described in this disclosure. Among the terms used in this disclosure, those defined in a common dictionary may be interpreted in the same or similar sense as in the context of the related art, and are not to be interpreted in an ideal or overly formal sense unless explicitly defined in this disclosure. In some cases, even terms defined in this disclosure should not be construed as excluding embodiments of this disclosure.

[0013] In one or more embodiments of this disclosure below, hardware methods are described by way of example. However, since one or more embodiments of this disclosure include techniques using both hardware and software, various embodiments of this disclosure do not exclude software-based methods.

[0014] Furthermore, in this disclosure, expressions greater than or less than may be used to determine whether a specific condition is met or achieved. However, this is merely a description for illustrative purposes and does not exclude descriptions of being greater than or equal to, or less than or equal to. A condition described as "greater than or equal to" may be replaced with "greater than," a condition described as "less than or equal to" may be replaced with "less than," and a condition described as "greater than or equal to and less than" may be replaced with "greater than and less than or equal to."

[0015] When the phrase “at least one of’ is used with a list of items, it means different combinations of one or more of the listed items can be used and only one item from the list can be needed. For example, “at least one of A, B, and C” includes any of the following combinations: A; B; C; A and B; A and C; B and C; A, B, and C; and any variation of A, B, and C. As an additional example, the expression “at least one of a, b, or c” can indicate: a only; b only; c only; both a and b; a and c; b and c; all of a, b, and c; or a variation of a, b, and c. Similarly, the term “set” means one or more. Thus, a set of items can be a single item or a collection of two or more items.

[0016] FIG. 1 is a block diagram of an image sensor according to example embodiments of the present disclosure.

[0017] Referring to FIG. 1 , an image sensor 1 according to example embodiments of the present disclosure can include a pixel array 10, a first logic circuit 20, and a second logic circuit 30.

[0018] The pixel array 10 can include an array of unit pixel arrays UPA arranged in an array shape along a plurality of rows and a plurality of columns. Each unit pixel array UPA can include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. For example, FIG. 1 The illustrated UPA includes four image sensing pixels (black dots) and one event sensing pixel (white dot).

[0019] The image sensing pixels PX1 can include at least one “photoelectric conversion element” and a first pixel circuit including a transfer transistor, a drive transistor, a selection transistor, and a reset transistor. In example embodiments, the plurality of image sensing pixels in each UPA can share at least a portion of the first pixel circuit. In FIG. 8B In the illustrated example, the event sensing pixel PX2 can include at least one “photoelectric conversion element” and a second pixel circuit including CKT1, CKT2, and CKT3.

[0020] According to example embodiments of the present disclosure, the image sensing pixels PX1 and the event sensing pixels PX2 can be heterogeneous pixels that output different types of electrical signals. For example, the image sensing pixels can be CMOS image sensor (CIS) pixels that output an image signal having a gray scale that indicates a brightness of light within a predetermined wavelength range. In some embodiments, the event sensing pixels PX2 can be dynamic vision sensors (DVS) that sense a change in light brightness and output an event signal that indicates whether the light has become brighter or dimmer.

[0021] The CIS pixel outputs an image signal including grayscale information corresponding to a plurality of data bits. In some embodiments, since each CIS pixel included in the pixel array 10 is capable of generating and outputting an image signal within one frame period, the frame period of the CIS pixel can be relatively long.

[0022] On the other hand, the event signal output by the DVS pixel can include information on whether there is a change in light brightness and information on the direction of the change in light brightness, and can include relatively few data bits, such as one or two bits. In some embodiments, among the DVS pixels included in the pixel array 10, only the pixels in which a change in light brightness is sensed can generate and output an event signal, and thus the frame period of the DVS pixel can be relatively short.

[0023] When an object moves between frame cycles of the CIS pixel, a residual image called "motion blur" can occur in an image generated from the image signal obtained from the CIS pixel. Since the frame period of the DVS pixel is shorter than that of the CIS pixel, the DVS pixel can generate an event signal corresponding to a position where a change in light brightness occurs between frame periods of the CIS pixel. When the CIS pixel and the DVS pixel are mixed in the pixel array 10, and the image signal obtained from the CIS pixel can be corrected using the event signal obtained from the DVS pixel, motion deblurring, i.e., an operation for removing motion blur, can be easily performed.

[0024] In the related art, when a pixel array in which CIS pixels and DVS pixels are mixed is configured by replacing some of a plurality of CIS pixels connected to a row line and a column line with a DVS pixel, the quality of an image signal obtained from the pixel array can be degraded.

[0025] In the related art, depending on whether a DVS pixel is connected to a row line and a column line, a parasitic capacitance can vary between the row line and the column line. When the parasitic capacitance varies between the row line and the column line, a difference can occur in the settling time of the CIS pixel. An image signal generated by pixels having different settling times can cause noise on a fixed position in an image. This noise can be referred to as fixed pattern noise.

[0026] In the related art, grayscale information, i.e., color information depending on a wavelength range, is not generated at a position replaced with a DVS pixel. Therefore, in order to generate an image, a color reconstruction operation can be required to estimate the color of a position where color information is lost.

[0027] According to an example embodiment of the present disclosure, the pixel array 10 can include a plurality of image sensing pixels PX1 connected to a first row line R1 and a first column line C1, and a plurality of event sensing pixels PX2 connected to a second row line R2 and a second column line C2.

[0028] The plurality of image sensing pixels PX1 can be arranged at uniform intervals (or at substantially uniform intervals) with the first row line R1 and the first column line C1 as a reference. In some embodiments, the plurality of event sensing pixels PX2 can be arranged at uniform intervals (or at substantially uniform intervals) between the plurality of image sensing pixels PX1 with the second row line R2 and the second column line C2 as a reference. For example, each of the plurality of event sensing pixels PX2 can be adjacent to at least one image sensing pixel PX1.

[0029] According to example embodiments of the present disclosure, since the event sensing pixels PX2 can be located between the image sensing pixels PX1, motion deblurring of an image obtained from the image sensing pixels PX1 can be effectively performed using an event signal obtained from the event sensing pixels PX2.

[0030] In some embodiments, although the pixel array 10 includes the image sensing pixels PX1 and the event sensing pixels PX2, the image sensing pixels PX1 can be uniformly (or substantially uniformly) distributed in the pixel array 10. Thus, color loss in image data obtained from the image sensing pixels PX1 can be minimized, and the amount of calculation required for color reconstruction can be minimized.

[0031] In some embodiments, the same type of pixels can be connected to the first row line R1 and the first column line C1. Since the parasitic capacitance of the first row line R1 and the parasitic capacitance of the first column line C1 can become uniform (or substantially uniform) respectively, the settling time of the image sensing pixels PX1 can become uniform (or substantially uniform). Thus, fixed pattern noise in an image obtained from the image sensing pixels PX1 can be mitigated.

[0032] The first logic circuit 20 can include a circuit for controlling the image sensing pixels PX1 of the pixel array 10. For example, the first logic circuit 20 can include a row driver 21, a readout circuit 22, a column driver 23, and a first control logic 24.

[0033] The row driver 21 can drive the image sensing pixels PX1 in units of rows. For example, the row driver 21 can generate a transfer control signal for controlling a transfer transistor of the first pixel circuit, a reset control signal for controlling a reset transistor, and a selection control signal for controlling a selection transistor, and can input the generated signals to the pixel array 10 in units of rows. For example, the control signal generated by the row driver 21 can be input to one of the first row lines R1.

[0034] The readout circuit 22 can include a correlated double sampler (CDS) and an analog-to-digital converter (ADC). The correlated double sampler can be connected to the image sensing pixel PX1 through the column line C1. The correlated double sampler can perform correlated double sampling by receiving an image signal from the image sensing pixel PX1 connected to the row line selected by the row selection signal of the row driver 21. The image signal can be received through the column line C1. The analog-to-digital converter can convert the image signal detected by the correlated double sampler into a digital image signal and transmit the digital image signal to the column driver 23.

[0035] The column driver 23 can include a latch or a buffer circuit capable of temporarily storing the digital image signal and an amplification circuit, and can process the digital image signal received from the readout circuit 22. The row driver 21, the readout circuit 22, and the column driver 23 can be controlled by the first control logic 24. The first control logic 24 can include a timing controller for controlling the operation timing of the row driver 21, the readout circuit 22, and the column driver 23.

[0036] The image sensing pixels PX1 located at the same position in the vertical direction can share the same first column line C1. For example, the image sensing pixels PX1 located at the same position in the vertical direction can be sequentially selected by the row driver 21, and an image signal can be output through the first column line C1.

[0037] The second logic circuit 30 can include a circuit for controlling the event sensing pixels PX2 of the pixel array 10. For example, the second logic circuit 30 can include a row address event processor 31, a column address event processor 32, and a second control logic 33.

[0038] The second control logic 33 can transmit a first selection signal for selecting one of the plurality of second column lines C2 to the column address event processor 32. In response to (or based on) the first selection signal, the event sensing pixels PX2 connected to the selected second column line C2 can be turned on at the same time.

[0039] The second control logic 33 can transmit a second selection signal to the row address event processor 31. In response to the second selection signal, the row address event processor 31 can be connected to at least one of the plurality of second row lines R2. For example, the row address event processor 31 can obtain an event signal from at least a portion of the plurality of event sensing pixels PX2 connected to the selected second row line R2 in response to the second selection signal.

[0040] At least some of the event sensing pixels PX2 that are turned on simultaneously (or substantially simultaneously) in response to the first selection signal can output an on-event signal or an off-event signal to the row address event handler 31. For example, the event sensing pixels PX2 in which the change in luminance of the pixel is higher than a reference value in the positive direction can output an on-event signal, and the event sensing pixels PX2 in which the change in luminance of the pixel is higher than a reference value in the negative direction can output an off-event signal. The event sensing pixels PX2 in which the change in luminance of the pixel is lower than a reference value can not output an on-event signal and an off-event signal.

[0041] The row address event handler 31 can include handshake logic corresponding to the plurality of second row lines R2. The handshake logic can obtain event signals from the event sensing pixels PX2 connected to the selected second column line C2, and can transmit a reset signal to the event sensing pixels PX2 in response to the event signals.

[0042] The second control logic 33 can receive event signals from the row address event handler 31, and can provide a reset signal for resetting the row address event handler 31 to the row address event handler 31.

[0043] In the example of FIG. 1, FIG. 1 In the example in which it has been described as an example that the image sensing pixels PX1 are CIS pixels and the event sensing pixels PX2 are DVS pixels, the disclosure is not limited thereto. The event sensing pixels can be included in a time-of-flight (ToF) sensor.

[0044] Hereinafter, a description will be given of an image sensor according to an example embodiment of the disclosure. FIGS. 2-30 An image sensor according to an example embodiment of the disclosure will be described in detail.

[0045] FIG. 2 is a plan view of a pixel included in an image sensor according to an example embodiment of the disclosure.

[0046] According to an example embodiment of the disclosure, the unit pixel array UPA1 can include a plurality of first regions A1 and a plurality of second regions A2. The plurality of first regions A1 can be in a first direction (X direction) and a second direction (Y direction) that are parallel to the upper surface of the substrate and that intersect each other. In some embodiments, the plurality of second regions A2 can also be in the first direction (X direction) and the second direction (Y direction).

[0047] In example embodiments, each of the plurality of first regions A1 can have an octagonal shape including two first edges extending in a first direction (X direction), two second edges extending in a second direction (Y direction), and four third edges. Each of the plurality of first regions A1 can have at least one first edge and at least one second edge adjacent to the at least one first region A1.

[0048] Each of the plurality of second regions A2 can have a rectangular shape. The plurality of second regions A2 can be disposed between the plurality of first regions A1. For example, the plurality of second regions A1 can be adjacent to at least one second region A2 on at least one of the four third edges.

[0049] In some embodiments, a deep trench isolation (DTI) can be formed in a boundary between the plurality of first regions A1 and the plurality of second regions A2. The DTI can prevent crosstalk between regions. The DTI can include an insulating material such as an oxide, and sidewalls of the DTI can be formed of a material having high reflectivity.

[0050] Referring to FIG. 1 At least one photodiode of the described image sensing pixel can be located in each of the plurality of first regions A1, and referring to FIG. 1 At least one photodiode of the described event sensing pixel can be located in each of the plurality of second regions A2. In example embodiments, a size of the first region A1 can be greater than a size of the second region A2. In some embodiments, a sum of light receiving areas of the photodiodes in the first region A1 can be greater than a sum of light receiving areas of the photodiodes in the second region A2.

[0051] FIGS. 3A-3C is a plan view of a pixel included in an image sensor according to example embodiments of the present disclosure.

[0052] Referring to FIGS. 3A-3C The unit pixel arrays UPA1a, UPA1b, and UPA1c can each include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2, respectively. The unit pixel arrays UPA1a, UPA1b, and UPA1c can correspond to the unit pixel arrays UPA1a, UPA1b, and UPA1c described with reference to FIG. 2 The described unit pixel array UPA1.

[0053] Each first region A1 can include one or more photodiodes. In FIGS. 3A-3CIn the example of FIG. 10, each first region A1 can include four photodiodes PD11 to PD14 arranged in a 2x2 shape in the first direction (X direction) and the second direction (Y direction). Each of the four photodiodes PD11 to PD14 belongs to a respective one of four image sensing pixels PX11 to PX14, and the four image sensing pixels can share one floating diffusion node FD.

[0054] Each second region A2 can include one or more photodiodes. In FIGS. 3A-3C In the example of FIG. 10, each second region A2 can include one of photodiodes PD2a, PD2b, PD2c, and PD2d. In an example embodiment, PD2a, PD2b, PD2c, and PD2d in unit pixel arrays UPA1a, UPA1b, and UPA1c can each be included in one event sensing pixel PX2.

[0055] Each of the photodiodes PD2a, PD2b, PD2c, and PD2d can convert light incident through the upper microlens into an electric charge. A current of a size corresponding to an amount of electric charge generated in each of the photodiodes PD2a, PD2b, PD2c, and PD2d can flow through a contact CT connected to each of the photodiodes PD2a, PD2b, PD2c, and PD2d to a second pixel circuit of the event sensing pixel PX2. The event sensing pixel PX2 can generate an event signal based on an amount of current flowing through the contact CT.

[0056] In the unit pixel array UPA1, the microlenses on the first regions A1 upper portion and the microlenses on the second regions A2 upper portion can have various sizes and shapes.

[0057] In FIG. 3A In the example of FIG. 10, each first region A1 can include one first microlens ML1a on an upper portion of the four photodiodes PD11 to PD14. For example, a center point of the first microlens ML1a can overlap the floating diffusion node FD in a vertical direction (Z direction) perpendicular to an upper surface of the substrate. In some embodiments, each second region A2 can include one second microlens ML2 on an upper portion of a respective one of the photodiodes PD2a, PD2b, PD2c, and PD2d. In some embodiments, a width of the first microlens ML1a in the second direction (Y direction) can be greater than a width of the second microlens ML2 in the second direction (Y direction).

[0058] However, the present disclosure is not limited thereto. As another example, each of the image sensing pixels PX11 to PX14 in the first regions A1 has one microlens.

[0059] In FIG. 3BIn the example of FIG. 10A, each first region A1 can include two first microlenses ML1b. The two first microlenses ML1b can be disposed at upper portions of the two photodiodes PD11 and PD12 and upper portions of the two photodiodes PD13 and PD14, respectively. In some embodiments, each second region A2 can include one second microlens ML2 disposed at an upper portion of a corresponding one of the photodiodes PD2a, PD2b, PD2c, and PD2d.

[0060] In FIG. 3C the example of FIG. 10B, each first region A1 can include four first microlenses ML1a located at upper portions of the four photodiodes PD11 to PD14, respectively. In some embodiments, each second region A2 can include one second microlens ML2 at an upper portion of a corresponding one of the photodiodes PD2a, PD2b, PD2c, and PD2d.

[0061] Referring to FIG. 2 , FIG. 3A , FIG. 3B and FIG. 3C described such as the unit pixel array UPA1 can be included in the pixel array 10 as described with reference to FIG. 1 .

[0062] FIGS. 4-7 is a plan view of a pixel array included in an image sensor according to an example embodiment of the present disclosure.

[0063] Referring to FIG. 4 , a plurality of unit pixel arrays UPA can be in a first direction (X direction) and a second direction (Y direction), and thus, can be included in the pixel array 10a. In FIG. 4 the example of FIG. 10A, the unit pixel array UPA is illustrated in the same shape as the unit pixel array UPA1a described with reference to FIG. 3A , but the shape of the unit pixel array UPA is not limited to the shape of the unit pixel array UPA1a.

[0064] The unit pixel array UPA can include a plurality of first regions A1 and a plurality of second regions A2. In FIG. 4 , image sensing pixels PX1 in the first regions A1 and event sensing pixels PX2 including four second regions A2 are shown as examples.

[0065] The unit pixel array UPA can include a color filter that can receive light passing through the microlens and can transmit light corresponding to a certain range of wavelengths among the received light. For example, each color filter can transmit light corresponding to a wavelength of a single color, for example, one of red (R), green (G), and blue (B), among the received light.

[0066] In FIG. 4 In an example of the first region A1, the color filter can be included in the first region A1 of the unit pixel array UPA, and the color filter can not be included in the second region A2. For example, the second region A2 can transmit light of all wavelengths in at least a visible light band, and the photodiode PD2 in the second region A2 can generate charges based on light of all wavelengths in at least the visible light band.

[0067] In the first region A1, the color filter can adopt a tetra pattern. The tetra pattern can refer to a color pattern in which a pixel group including four pixels arranged in a 2x2 shape includes color filters that transmit light of the same wavelength.

[0068] For example, in the first region A1 arranged in a 2x2 shape in the unit pixel array UPA, a red color filter, a green color filter, and a blue color filter can be arranged in a Bayer pattern. In some embodiments, each color filter can be shared by four image sensing pixels PX1 included in the first region A1.

[0069] However, the present disclosure is not limited thereto. As a first example, the first region A1 can include only one single color filter among a red color filter, a green color filter, and a blue color filter. As a second example, the first region A1 can include different color filters that transmit light of different colors such as cyan, magenta, or yellow. As a third example, at least a portion of the first region A1 can not include a color filter.

[0070] The first region A1 located in the middle portion except for the first region A1 located at the edge in the pixel array 10a can be adjacent to four first regions A1 in the first direction (X direction) and the second direction (Y direction). In some embodiments, the first region A1 located in the middle portion can be adjacent to four second regions A2 in a third direction and a fourth direction parallel to the upper surface of the substrate and intersecting the first direction (X direction) and the second direction (Y direction). The second region A2 located in the middle portion except for the second region A2 located at the edge can be adjacent to four first regions A1.

[0071] Referring to FIG. 5The plurality of unit pixel arrays UPA can be in a first direction (X direction) and a second direction (Y direction), and thus can be included in the pixel array 10b. FIG. 5 The pixel array 10b can have a similar structure to the pixel array 10a. FIG. 4 However, in the pixel array 10b, FIG. 5 of the pixel array 10b, part of the image sensing pixels among the plurality of image sensing pixels PX1 can be phase detection pixels PX1b.

[0072] In the example of FIG. 5 Each phase detection pixel PX1b can include two photodiodes having a first relative position in the first direction (X direction), and two photodiodes having a second relative position different from the first relative position in the first direction (X direction). Each phase detection pixel PX1b can detect a phase difference in the first direction (X direction) based on an amount of charge accumulated in the photodiodes having the first relative position and an amount of charge accumulated in the photodiodes having the second relative position, and can provide an auto focus function. However, the present disclosure is not limited thereto, and the phase detection pixel PX1b can be a pixel that detects a phase difference in the second direction (Y direction).

[0073] Referring to FIG. 6 The plurality of large unit pixel arrays LUPA can be in a first direction (X direction) and a second direction (Y direction), and thus can be included in the pixel array 10c. FIG. 6 The pixel array 10c can have a similar structure to the pixel array 10a. FIG. 4 However, a pattern of color filters in the pixel array 10c FIG. 6 may be different from a pattern of color filters in the pixel array 10a in FIG. 4

[0074] For example, FIG. 6 The large unit pixel array LUPA illustrated in FIG. 10A can have a structure in which the unit pixel array UPA illustrated in FIG. 9A is arranged in a 2x2 shape in the first direction (X direction) and the second direction (Y direction). FIG. 4 In the large unit pixel array LUPA of FIG. 6 The color filters can be arranged in a sixteen pattern. For example, in a plurality of first regions A1 included in the large unit pixel array LUPA and arranged in a 4x4 shape, green color filters, red color filters, and blue color filters can be arranged in a Bayer pattern in units of four first regions A1 arranged in a 2x2 shape.

[0075] Referring to FIG. 7 The plurality of large unit pixel arrays LUPA can be in a first direction (X direction) and a second direction (Y direction), and thus can be included in the pixel array 10d.​FIG. 7 The pixel array 10d can have the same as FIG. 6 The structure is similar to that of the pixel array 10c. However, FIG. 7 The pattern of the color filters arranged in the pixel array 10d can be different FIG. 6 The pattern of color filters arranged in the pixel array 10c.

[0076] For example, some image sensing pixels PX1 of the pixel array 10d may provide autofocus (AF) functionality. The image sensing pixels PX1 providing AF functionality may include color filters for transmitting the same color. For example, eight image sensing pixels PX1 included in two first regions A1 adjacent to each other in the first direction (X direction) and including color filters for transmitting the same color can detect phase differences in the first direction (X direction) and provide autofocus functionality in the first direction (X direction). However, this disclosure is not limited thereto. For example, the pixel array 10d may also include image sensing pixels PX1 adjacent to each other in the second direction (Y direction) and providing autofocus functionality in the second direction (Y direction).

[0077] For reference FIG. 1 As described, the image sensing pixel PX1, which includes a photodiode in the first region A1 of the pixel arrays 10a, 10b, 10c, and 10d, can be a CIS pixel, and the event sensing pixel PX2, which includes a second photodiode in the second region A2, can be a DVS pixel.

[0078] FIG. 8A and FIG. 8B These are circuit diagrams illustrating the first pixel circuit and the second pixel circuit of an image sensor according to an exemplary embodiment of the present disclosure.

[0079] FIG. 8A The diagram shows the circuit diagram of the first pixel circuit PXC1.

[0080] refer to FIG. 8A The first pixel circuit PXC1 (also referred to herein as the image sensing pixel circuit) of the image sensing pixels PX11, PX12, PX13, and PX14 can output an electrical signal using the charge generated by multiple photodiodes PD11, PD12, PD13, and PD14 (PD1). The operation of the active elements included in the image sensing pixel circuit can be determined by a reference... FIG. 1 The image sensor 1 described includes a first logic circuit 20 for control.

[0081] The first pixel circuit PXC1 can include a reset transistor RX, a plurality of first transfer transistors TX11, TX12, TX13, and TX14 (TX1), a drive transistor DX, and a selection transistor SX. The plurality of image sensing pixels PX11, PX12, PX13, and PX14 can include dedicated photodiodes PD1 and dedicated first transfer transistors TX1. In some embodiments, the plurality of image sensing pixels PX1 can share the reset transistor RX, the drive transistor DX, and the selection transistor SX.

[0082] The plurality of photodiodes PD1 can be connected to a first floating diffusion node FD1 through the plurality of first transfer transistors TX1, respectively. The plurality of photodiodes PD1 can share the first floating diffusion node FD1.

[0083] The plurality of first transfer transistors TX1 can transfer the charge accumulated in a respective photodiode of the plurality of photodiodes PD1 to the first floating diffusion node FD1 based on a plurality of first transfer control signals TG11, TG12, TG13, and TG14 (TG1) transferred from a row driver, respectively. The plurality of photodiodes PD1 can generate electrons as primary charge carriers. The drive transistor DX can operate as a source follower buffer amplifier with the charge accumulated in the first floating diffusion node FD1. The drive transistor DX can amplify the charge accumulated in the first floating diffusion node FD1 and transfer the charge to the selection transistor SX.

[0084] The reset transistor RX can reset the voltage of the first floating diffusion node FD1 to a reset voltage based on a reset control signal RG transferred from a row driver.

[0085] The selection transistor SX can operate in accordance with a selection control signal SEL input by a row driver and can perform a switching and addressing operation. When the selection control signal SEL is applied from the row driver, a voltage can be output to a column line Col connected to the selection transistor SX. The voltage can be detected by a column driver and a readout circuit connected to the column line Col. The column driver and the readout circuit can detect a reset voltage in a state in which no charge is accumulated in the first floating diffusion node FD1 and can detect a pixel voltage in a state in which charge is accumulated in the first floating diffusion node FD1. In an example embodiment, the image sensor can generate an image signal by calculating a difference between the reset voltage and the pixel voltage.

[0086] FIG. 8B A circuit diagram of a second pixel circuit PXC2 is illustrated.

[0087] Reference FIG. 8BThe second pixel circuit PXC2 (which can also be referred to herein as an event sensing pixel circuit) of the event sensing pixel PX2 can output an electrical signal using the charges generated by the plurality of photodiodes PD2a to PD2d. The operation of the active elements included in the second pixel circuit PXC2 can be controlled by the second logic circuit 30 included in the image sensor 1 described above. FIG. 1 The second logic circuit 30 included in the image sensor 1 described above controls.

[0088] The second pixel circuit PXC2 includes a conversion circuit CKT1, an amplifier circuit CKT2, a comparison circuit CKT3, a first switch SW1, and a second switch SW2. The plurality of photodiodes PD2a to PD2d (PD2) can generate charges in response to light, and currents la, lb, lc, and Id can flow to the plurality of photodiodes PD2 in accordance with the amount of charges generated.

[0089] The plurality of photodiodes PD2a to PD2d can be connected to a common node. A current I corresponding to the sum of the charges generated by the plurality of photodiodes PD2a to PD2d can be input to the conversion circuit CKT1.

[0090] The conversion circuit CKT1 can sense the current I flowing due to the charges generated by the photodiodes PD2a to PD2d, and can output a first voltage Vin corresponding to the current I. The conversion circuit CKT1 can include a first transistor TR1, a second transistor TR2, a first amplifier AMP1, a first bias circuit BI1, and a second bias circuit BI2. The first amplifier AMP1, the first bias circuit BI1, and the second bias circuit BI2 can be implemented with transistors.

[0091] The first transistor TR1 can be connected in series to the plurality of photodiodes PD2 connected in parallel. The first bias circuit BI1 and the first amplifier AMP1 can be connected in series. In some embodiments, the gate of the first transistor TR1 can be connected between the gate of the second transistor TR2 and the first bias circuit BI1 and the first amplifier AMP1.

[0092] The second transistor TR2 can be connected in series with the second bias circuit BI2. The second transistor TR2 can operate as a source follower. The second transistor TR2 can output the first voltage Vin corresponding to the magnitude of the current I.

[0093] The amplifier circuit CKT2 can include a first capacitor C1, a second capacitor C2, a second amplifier AMP2, and a reset switch SWR. The reset switch SWR can be turned on in response to a reset control signal RESET received from the row address event processor, and can reset the second voltage Vout output by the amplifier circuit CKT2. Through the above reset operation, the second voltage Vout can be reset to a constant voltage.

[0094] The amplifier circuit CKT2 can output a second voltage Vout associated with a change in the first voltage Vin over time based on the first voltage Vin. In other words, the amplifier circuit CKT2 can amplify the first voltage Vin and output the second voltage Vout in order to show a change in the light intensity.

[0095] The comparison circuit CKT3 can include a first comparator COMP1 and a second comparator COMP2. The comparison circuit CKT3 can output the turn-on event signal ON_EVENT or the turn-off event signal OFF_EVENT through a change in the second voltage Vout. For example, the first comparator COMP1 can compare the second voltage Vout with a turn-on threshold voltage and generate the turn-on event signal ON_EVENT according to a comparison result. The second comparator COMP2 can compare the second voltage Vout with a turn-off threshold voltage and can generate the turn-off event signal OFF_EVENT according to a comparison result.

[0096] The comparison circuit CKT3 can generate the turn-on event signal ON_EVENT or the turn-off event signal OFF_EVENT when a change in the intensity of light incident on the photodiode PD2 is greater than a certain standard range. For example, the turn-on event signal ON_EVENT can have a high logic value when the size of an increase in brightness of light incident on the photodiode PD2 is greater than or equal to a standard range. The turn-off event signal OFF_EVENT can have a high logic value when the size of a decrease in brightness of light incident on the photodiode PD2 is greater than or equal to a standard range.

[0097] The second pixel circuit PXC2 can receive the first selection signal SEL1 from the digital address event processor through the column address event processor. The first switch SW1 and the second switch SW2 can be turned on in response to the first selection signal SEL1. When the first switch SW1 and the second switch SW2 are turned on, the generated turn-on event signal ON_EVENT or the generated turn-off event signal OFF_EVENT can be output to the row address event processor.

[0098] For example, when the magnitude of the increase in the brightness of the light incident on the photodiode PD2 is greater than or equal to a standard range, the second pixel circuit PXC2 can output an on event signal ON_EVENT to the row address event processor through the first switch SW1 turned on in response to the first selection signal SEL1. When the magnitude of the decrease in the brightness of the light incident on the photodiode PD2 is greater than or equal to a standard range, the second pixel circuit PXC2 can output an off event signal OFF_EVENT to the row address event processor through the second switch SW2 turned on in response to the first selection signal SEL1. When the magnitude of the change in the brightness of the light incident on the photodiode PD2 is less than the standard range, the second pixel circuit PXC2 can not output the on event signal ON_EVENT and the off event signal OFF_EVENT.

[0099] After the comparison circuit CKT3 outputs the on event signal ON_EVENT or the off event signal OFF_EVENT, the amplifier circuit CKT2 can receive a reset signal RESET from the row address event processor. The second voltage Vout output from the amplifier circuit CKT2 can be reset by the reset signal RESET.

[0100] In an example embodiment, the second pixel circuit PXC2 can occupy a larger area on the substrate than the first pixel circuit PXC1. In FIG. 8A and FIG. 8B In an example, the first pixel circuit PXC1 can include only seven transistor elements, but the second pixel circuit PXC2 can include a relatively complex circuit such as a comparator circuit. According to an example embodiment of the disclosure, the first pixel circuit PXC1 and the second pixel circuit PXC2 can be vertically stacked in an image sensor, and the first pixel circuit PXC1 and the second pixel circuit PXC2 can be effectively arranged.

[0101] FIG. 9 is a view illustrating a layout of an image sensor according to an example embodiment of the disclosure.

[0102] Referring to FIG. 9 , the image sensor 100 can include an upper semiconductor chip 200, an intermediate semiconductor chip 300, and a lower semiconductor chip 400. Each of the upper semiconductor chip 200, the intermediate semiconductor chip 300, and the lower semiconductor chip 400 can include a main region and a peripheral region.

[0103] For example, the photodiode PD1 and the photodiode PD2 can be arranged in the main region of the upper semiconductor chip 200. FIG. 9 A first region A1 in which the photodiode PD1 can be arranged and a second region A2 in which the photodiode PD2 can be arranged are illustrated.

[0104] According to an exemplary embodiment of this disclosure, the upper semiconductor chip 200 may further include an image sensing pixel circuit formed beneath the photodiodes PD1. For example, a first region A1 of the upper semiconductor chip 200 may include four photodiodes PD1 included in the image sensing pixel and a first pixel circuit. The first pixel circuit may correspond to a reference... FIG. 8A The first pixel circuit is described.

[0105] According to an exemplary embodiment of this disclosure, the second pixel circuit PCX2 can be arranged in the main region of the intermediate semiconductor chip 300. The four photodiodes PD1 of the upper semiconductor chip 200 and the second pixel circuit PXC2 of the intermediate semiconductor chip 300 can be electrically connected via signal pads PAD or metal-to-metal connections such as copper-to-copper hybrid bonding.

[0106] exist FIG. 9 In the example, the second pixel circuit PCX2 may occupy the area corresponding to the four first regions A1 and the four second regions A2. In some embodiments, photodiodes PD2 in the four second regions A2 may be connected to a second pixel circuit PCX2 via signal pads PAD or copper-to-copper hybrid bonding. For example, the four second photodiodes PD2 may be electrically connected via interconnect patterns in the upper semiconductor chip 200, and the four photodiodes PD2 may be connected to the second pixel circuit PCX2 via a signal pad PAD.

[0107] According to an example embodiment of this disclosure, since the second pixel circuit PCX2 is disposed on the intermediate semiconductor chip 300, the area of ​​the image sensor 100 on the XY plane will not increase even when the area occupied by a second pixel circuit PCX2 is larger than the area of ​​the second region A2 in which the photodiode PD2 is disposed.

[0108] In some embodiments, by using four photodiodes PD2 to configure an event sensing pixel, the area of ​​the image sensor 100 on the XY plane will not increase even when the area occupied by a second pixel circuit PCX2 is larger than the area of ​​the first region A1 in which the image sensing pixel PX1 is disposed.

[0109] The main area of ​​the lower semiconductor chip 400 may include logic circuitry LOGIC for image sensing pixels PX1 and event sensing pixels PX2. For example, the logic circuitry LOGIC may include a reference... FIG. 1 The first logic circuit 20 and the second logic circuit 30 are described. In an example embodiment, the logic circuit LOGIC may further include an image signal processor (ISP) that generates an image by processing image signals and an event signal processor (ESP) that processes event signals.

[0110] The peripheral circuits connected to the main region can be located in the peripheral regions of each of the upper semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400.

[0111] The image sensor 100 may include a through-path (TSV) that penetrates the peripheral region. For example, FIG. 9 The diagram illustrates a through-path (TSV) connecting the peripheral circuits of the upper semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400 to each other.

[0112] In the following text, reference will be made to FIGS. 10-14 The structure of an image sensor according to an example embodiment of the present disclosure is described in detail.

[0113] FIGS. 10-14 This is a view illustrating pixels included in an image sensor according to an exemplary embodiment of the present disclosure.

[0114] FIG. 10 The diagram illustrates the pixels included in the unit pixel array UPA1a. FIG. 10 The unit pixel array UPA1a can correspond to the reference FIG. 3A The unit pixel array UPA1a is described. However, FIG. 10 The unit pixel array UPA1a further illustrates the DTI formed between the first region A1 and the second region A2, as well as the color filter located in the first region A1.

[0115] FIG. 11 It is along FIG. 10 A cross-sectional view taken from line I-I'. FIG. 12 It is along FIG. 10 The cross-sectional view taken from line II-II', and FIG. 13 It is along FIG. 10 The cross-sectional view taken from line III-III'.

[0116] refer to FIGS. 11-13 The image sensor 100 may include, as in the reference... FIG. 9 The described semiconductor chip 200, intermediate semiconductor chip 300, and lower semiconductor chip 400. However, in FIGS. 11-13 The semiconductor chip 400 is omitted in the text.

[0117] In an image sensor 100 according to an exemplary embodiment of the present disclosure, pixel circuits may be located below a plurality of photodiodes PD1 disposed in a first region A1 and below a plurality of photodiodes PD2 disposed in a second region A2.

[0118] For example, the first pixel circuit can be disposed on the first surface of the first substrate 201. The first pixel circuit can include a plurality of first elements 230, a first interconnection pattern 231 connected to the plurality of first elements 230, and a first insulating layer 232 covering the plurality of first elements 230 and the first interconnection pattern 231.

[0119] The first pixel circuit can include a first floating diffusion node FD1. For example, FIG. 10 The image sensing pixels PX1 included in the first region A1 described in the middle can share one first floating diffusion node.

[0120] The first floating diffusion node FD1 can be disposed near the in-pixel partition 212. For example, the first floating diffusion node FD1 can be located at a position where the first floating diffusion node FD1 overlaps the in-pixel partition 212 in a direction perpendicular to the first surface of the first substrate 201. The plurality of first elements 230 adjacent to the first floating diffusion node FD1 can correspond to a plurality of first transfer transistors. The gate of the plurality of first transfer transistors can have a vertical structure in which at least a part of the gate is buried in the substrate 201, and the charge generated in the photodiode PD1 can be moved to the first floating diffusion node FD1 through the transfer transistor.

[0121] Each of the image sensing pixels PX1 can include a color filter 203, a light transmission layer 204, and a micro lens 205 disposed on a second surface opposite to the first surface of the first substrate 201. For example, each of the image sensing pixels PX1 can include a first micro lens 205 disposed on an upper portion of the plurality of photodiodes PD1. Among the light passing through the first micro lens 205, the light of the wavelength component transmitted by the color filter 203 can be incident on the photodiode PD1 of the lower portion of the first micro lens 205.

[0122] Referring to FIG. 11 The pixel partition 211 can have a first width W1 and a first length L1, and the in-pixel partition 212 can have a second width W2 and a second length L2. For example, the second width W2 of the in-pixel partition 212 can be narrower than the first width W1, and thus the pixel partition 211 and the in-pixel partition 212 can be formed simultaneously in one process. However, the disclosure is not limited thereto, and according to an example embodiment, the first width W1 and the second width W2 can be the same.

[0123] In some embodiments, the first length L1 can be longer than the second length L2. However, the disclosure is not limited thereto, and the first length L1 and the second length L2 can each have various values. In an embodiment, the pixel partition 211 can penetrate completely from the first surface of the first substrate 201 to the second surface of the first substrate 201.

[0124] In an example embodiment, the length of the in-pixel partition 212 in the first direction can be less than the length of the plurality of photodiodes PD1 in the first direction. Accordingly, the charge can move between the plurality of photodiodes PD1 with the in-pixel partition 212 interposed therebetween. For example, when the charge is excessively generated in one of the plurality of photodiodes PD1, the photodiode PD1 can be prevented from being saturated by moving the charge.

[0125] The second pixel circuit can be disposed on the first surface of the second substrate 301 of the middle semiconductor chip 300. The second pixel circuit can include a plurality of second elements 330, a second interconnection pattern 331 connected to the plurality of second elements 330, and a second insulating layer 332 covering the plurality of second elements 330 and the second interconnection pattern 331.

[0126] The upper semiconductor chip 200 can include a contact CT for connecting one or more photodiodes PD2 to the event sensing pixel circuit. The charge generated by the photodiode PD2 can move to the second pixel circuit through the contact CT.

[0127] The contact CT can penetrate a region of the first substrate 201 in which the photodiode PD2 is formed. The insulating layer 332 can include a first signal pad 233 for electrically connecting circuit elements located in the main region of the upper semiconductor chip 200 and the main region of the middle semiconductor chip 300. The contact CT can be connected to the first signal pad 233 through the first interconnection pattern 231.

[0128] The event sensing pixel PX2 can include a light transmission layer and a second micro-lens 206 disposed on the second surface of the first substrate 201. For example, the event sensing pixel PX2 can include the second micro-lens 206 disposed on an upper portion of each photodiode PD2. Light passing through the second micro-lens 206 can be incident on the photodiode PD2 of a lower portion of the second micro-lens 206.

[0129] In an example embodiment, the event sensing pixel PX2 can not include a color filter. For example, in the upper portion of the photodiode PD2, a light transmission layer 207 having the same thickness as that of the color filter 203 disposed on the upper portion of the photodiode PD1 can be disposed.

[0130] According to example embodiments of the disclosure, the upper semiconductor chip 200 and the middle semiconductor chip 300 can be bonded by chip-to-chip (C2C) bonding. That is, the insulating layer 232 of the upper semiconductor chip 200 can be in contact with the insulating layer 332 of the middle semiconductor chip 300, and the signal pad 233 of the upper semiconductor chip 200 can be in contact with the signal pad 333 of the middle semiconductor chip 300. The photodiode PD2 can be electrically connected to the event sensing pixel circuit formed on the middle semiconductor chip 300 through the signal pads 233 and 333.

[0131] In FIGS. 11-13 , a case where the upper semiconductor chip 200 and the middle semiconductor chip 300 are bonded by C2C bonding is described as an example, but the disclosure is not limited thereto. For example, the upper semiconductor chip 200 and the middle semiconductor chip 300 can be bonded by direct bonding.

[0132] FIG. 14 FIG. 13 illustrates a cross-sectional view taken along line III-III' of FIG. 12 when the upper semiconductor chip 200 and the middle semiconductor chip 300 are bonded by direct bonding. In FIG. 10 , the lower semiconductor chip 400 described with reference to FIG. 10 is omitted. FIG. 14 FIG. 9

[0133] FIG. 14 The semiconductor device 100a of FIG. 14 may include the upper semiconductor chip 200 and the middle semiconductor chip 300a. FIGS. 11-13 The upper semiconductor chip 200 and the middle semiconductor chip 300a in FIGS. 11-13 may have a structure similar to that of the upper semiconductor chip 200 and the middle semiconductor chip 300 described with reference to FIGS. 1 to 10. For example, the second substrate 301a, the plurality of second elements 330a, the second interconnection pattern 331a, and the second insulating layer 332a of the middle semiconductor chip 300a can have a structure similar to that of the second substrate 301, the second element 330, the second interconnection pattern 331, and the second insulating layer 332 described with reference to FIGS. 1 to 10.

[0134] However, unlike the middle semiconductor chip 300 of FIGS. 11-13 , the middle semiconductor chip 300a of FIG. 14 ​​The intermediate semiconductor chip 300a can be bonded with the upper semiconductor chip 200 by direct bonding. That is, the insulating layer 232 of the upper semiconductor chip 200 and the second substrate 301a of the intermediate semiconductor chip 300a can be bonded with each other. The intermediate semiconductor chip 300a can include a through via 334a that penetrates the second substrate 301a and at least a portion of the insulating layer 332a so as to connect the photodiode PD2 to the event sensing pixel circuit. The through via 334a can be in contact with the pad 233 and the interconnection pattern 331a of the upper semiconductor chip 200.

[0135] In FIGS. 3A-14 In an example of the present disclosure, an example in which four photodiodes PD2 provided in the second region A2 are connected to one event sensing pixel circuit and included in one event sensing pixel PX2 has been described. However, the present disclosure is not limited thereto. For example, when an area occupied by one second pixel is less than or equal to a sum of areas of the first region A1 and the second region A2, one second pixel circuit can be electrically connected to one photodiode PD2, and can be disposed to overlap with one first region A1.

[0136] FIG. 15 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure.

[0137] FIG. 15 An upper surface of the unit pixel array UPA2 in FIG. 3A described above. However, in the unit pixel array UPA2 of FIG. 15 In the unit pixel array UPA2, each of the plurality of photodiodes PD21 to PD24 can be included in one event sensing pixel. For example, the unit pixel array UPA2 can include four event sensing pixels PX21 to PX24.

[0138] According to an example embodiment of the present disclosure, the event sensing pixel circuits (first pixel circuits) of the event sensing pixels PX21 to PX24 can overlap with the image sensing pixel circuits (second pixel circuits) of the image sensing pixels PX11 to PX14 in a vertical direction (Z direction). For example, the photodiodes PD11 to PD14, the photodiodes PD21 to PD24, and the first pixel circuits of the image sensing pixels can be included in the upper semiconductor chip. In some embodiments, each second pixel circuit of the event sensing pixels can be included in the second region A2 and the first region A1 adjacent to the second region A2 in the intermediate semiconductor chip.

[0139] This disclosure is not limited to the case where the image sensing pixel disposed on a first region A1 includes four photodiodes PD1. For example, the image sensing pixel may include one photodiode PD1 in a first region A1, or may include nine photodiodes PD1, or may include various numbers of photodiodes.

[0140] FIG. 16 It is a planar view of pixels included in an image sensor according to an exemplary embodiment of the present disclosure.

[0141] FIG. 16 The upper surface of the unit pixel array UPA3 can have the same shape as the reference. FIG. 3A The structure of the upper surface of the described unit pixel array UPA1a is similar to that of the other structures. However, FIG. 16 The unit pixel array UPA3 can include nine photodiodes PD1 arranged in a 3×3 shape along a first direction (X direction) and a second direction (Y direction) in a first region A1. The photodiodes PD1 included in a first region A1 can be included in an image sensing pixel.

[0142] exist FIG. 16 In one example, the unit pixel array UPA3 may include an event sensing pixel PX2 having four second photodiodes PD2a to PD2d included in four second regions A2. However, the invention is not limited thereto. As a first example, the unit pixel array UPA3 may include four event sensing pixels PX2 consisting of a photodiode PD2 included in one second region A2. As a second example, the unit pixel array UPA3 may include nine first regions A1 and nine second regions A2 arranged in a 3×3 shape, and may include an event sensing pixel PX2 consisting of a photodiode PD2 included in the nine second regions A2.

[0143] According to an example embodiment of this disclosure, an image sensing pixel may have a split photodiode structure. An image sensing pixel with a split photodiode structure may include a small photodiode with a small light-receiving area and a large photodiode with a larger light-receiving area compared to the small photodiode.

[0144] For example, large photodiodes can primarily generate pixel signals in low-light areas. Large photodiodes can operate in high conversion gain (HCG) mode in the lowest light intensity areas and in low conversion gain (LCG) mode in general low-light areas. Small photodiodes can operate in high-light areas by extending the exposure time.

[0145] In the following text, see references FIGS. 17-20FIG. 1 illustrates an example of a structure that an image sensor according to an example embodiment of the present disclosure can have when an image sensing pixel PX1 has a split photodiode structure.

[0146] FIGS. 17-19 is a plan view of a pixel included in an image sensor according to an example embodiment of the present disclosure.

[0147] Referring to FIG. 17 The unit pixel array UPA4 can include a plurality of first regions A1, a plurality of second regions A2, and a plurality of third regions A3. Each of the plurality of first regions A1, the plurality of second regions A2, and the plurality of third regions A3 can be in a first direction (X direction) and a second direction (Y direction) that are parallel to an upper surface of the substrate and that intersect each other.

[0148] Specifically, the unit pixel array UPA4 can include a plurality of octagonal regions and the plurality of third regions A3. Each of the plurality of octagonal regions can have an octagonal shape including two first edges extending in the first direction (X direction), two second edges extending in the second direction (Y direction), and four third edges. In some embodiments, each of the plurality of third regions A3 can have a rectangular shape.

[0149] Each of the plurality of octagonal regions can adjoin at least one octagonal region at at least one first edge and at least one second edge. In some embodiments, each of the plurality of third regions A3 can be disposed between the plurality of octagonal regions. For example, each of the plurality of octagonal regions can adjoin at least one third region A3 at at least one third edge.

[0150] Each of the plurality of octagonal regions can include a first region A1 and a second region A2. In an example embodiment, an area of the first region A1 can be greater than an area of the second region A2. For example, the first region A1 can be in contact with three of the four third edges, and the second region A2 can be in contact with one of the four third edges.

[0151] Deep trench isolation DTI can be formed in a boundary between the plurality of first regions A1, the plurality of second regions A2, and the plurality of third regions A3.

[0152] According to example embodiments of the disclosure, each of the plurality of first regions A1 can include a large photodiode, and each of the plurality of second regions A2 can include a small photodiode. The large photodiode and the small photodiode can each be included in each of the plurality of image sensing pixels. In some embodiments, the plurality of third regions A3 can include a photodiode included in an event sensing pixel.

[0153] Referring to FIG. 18A and FIG. 18B , the unit pixel arrays UPA4a and UPA4b can include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA4a and UPA4b can correspond to the unit pixel arrays UPA4 described with reference to FIG. 17 .

[0154] Each first region A1 can include one or more photodiodes PD11, PD12, and PD13 (PD1). In some embodiments, each second region A2 can include one or more photodiodes PD21 (PD2). The sum of the light-receiving areas of the photodiodes PD1 can be greater than the light-receiving area of the photodiodes PD2. The sum of the photodiodes PD1 can be collectively referred to as a large photodiode, and the photodiodes PD2 can be referred to as a small photodiode. The first regions A1 and the second regions A2 share a first pixel circuit. That is, the image sensing pixels PX1 can have a split photodiode structure.

[0155] Each first region A1 can include one or more first floating diffusion nodes FD1. For example, the photodiodes PD1 included in one first region A1 can share one first floating diffusion node FD1. Each second region A2 can include a second floating diffusion node FD2.

[0156] The first regions A1 and the second regions A2 included in one octagonal region can include a plurality of image sensing pixels PX1 sharing one first pixel circuit. The image sensing pixels PX1 can generate an image signal using at least a portion of the charge accumulated in the first floating diffusion nodes FD1 and the charge accumulated in the second floating diffusion nodes FD2.

[0157] Each third region A3 can include one or more photodiodes. In FIG. 18A and FIG. 18BIn the example, each third region A3 may include one of the third photodiodes PD3a to PD3d. In the example embodiment, the photodiodes PD3 included in the plurality of third regions A3 included in the unit pixel arrays UPA4a and UPA4b may be included in an event sensing pixel PX2. Each third region A3 may include a contact CT for transferring the charge generated in the third photodiodes PD3a to PD3d to the event sensing pixel PX2.

[0158] In the unit pixel array UPA4, the microlenses included in the upper part of the first region A1 to the third region A3 can have various sizes and shapes.

[0159] exist FIG. 18A In the example, the first region A1 may include a first microlens ML1 disposed on the upper part of three photodiodes PD1. In some embodiments, the second region A2 may include a second microlens ML2 on the upper part of a photodiode PD2, and the third region A3 may include a third microlens ML3 on the upper part of a photodiode PD3.

[0160] exist FIG. 18B In the example, the first region A1 may include three first microlenses ML1b disposed on each of the three photodiodes PD1.

[0161] refer to FIG. 19 The unit pixel array UPA4c can have the same as FIG. 18A The structure is similar to that of the unit pixel array UPA4a. However, in FIG. 19 In the unit pixel array UPA4c, a first region A1 may include eight photodiodes PD1. In an octagonal region, the eight photodiodes PD1 and one photodiode PD2 may be arranged in a 3×3 shape.

[0162] Photodiodes PD1 and PD2 in an octagonal region can share a first pixel circuit. The sum of the light-receiving areas of the eight photodiodes PD1 can be greater than the light-receiving area of ​​the photodiodes PD2.

[0163] refer to FIG. 18A , FIG. 18B and FIG. 19 The described event-sensing pixel PX2 may include, as in the reference... FIG. 8B The described second pixel circuit. However, reference... FIG. 18A , FIG. 18B and FIG. 19 The first pixel circuit included in the described image sensing pixel PX1 may be different from the reference one. FIG. 8A The first pixel circuit is described. References will be made below.FIG. 20 A circuit structure of a first pixel circuit included in an image sensing pixel PX1 having a split photodiode structure is described.

[0164] FIG. 20 is a circuit diagram illustrating a pixel circuit of an image sensor according to an example embodiment of the present disclosure.

[0165] Reference FIG. 20 The first pixel circuit PXC1 can output an electrical signal using charges generated by a plurality of photodiodes PD11 to PD13 included in one first region A1 and a photodiode PD2 included in one second region A2. Operations of active elements included in the image sensing pixel circuit (the first pixel circuit PXC1) can be controlled by the first logic circuit 20 included in the image sensor 1 described with reference to FIG. 1

[0166] The first pixel circuit PXC1 can include a reset transistor RX, a plurality of first transfer transistors TX11, TX12, and TX13 (TX1), a second transfer transistor TX2, a storage capacitor SC, a first switch transistor SWX1, a second switch transistor SWX2, a drive transistor DX, and a selection transistor SX.

[0167] Each of the plurality of photodiodes PD11 to PD13 can be connected to a first floating diffusion node FD1 through the plurality of first transfer transistors TX1. The plurality of photodiodes PD11 to PD13 can share the first floating diffusion node FD1. In some embodiments, the photodiode PD2 can be connected to a second floating diffusion node FD2 through the second transfer transistor TX2.

[0168] The storage capacitor SC can be an element for storing charges generated by the photodiode PD2. The storage capacitor SC can be implemented as a metal-insulator-metal (MIM) capacitor or an active capacitor. In embodiments, a second power supply voltage VSC connected to the storage capacitor SC can be less than a first power supply voltage VDD of the entire pixel circuit. However, this is only one example and is not limited thereto, and the first power supply voltage VDD and the second power supply voltage VSC can be the same.

[0169] The storage capacitor SC can store charges in response to an amount of charges generated in the photodiode PD2 and an operation of the second transfer transistor TX2. The first switch transistor SWX1 can be connected between the storage capacitor SC and a third floating diffusion node FD3, and charges of the storage capacitor SC can be moved to the third floating diffusion node FD3 through on / off operations of the first switch transistor SWX1.

[0170] ​In an embodiment, the second switch transistor SWX2 can be connected between the third floating diffusion node FD3 and the first floating diffusion node FD1. That is, the third floating diffusion node FD3 can be connected to the reset transistor RX1, the first switch transistor SWX1, and the second switch transistor SWX2. The charge accumulated in the third floating diffusion node FD3 can move to the first floating diffusion node FD1 in response to the operation of the second switch transistor SWX2.

[0171] In FIG. 20 In the illustrated example embodiment, the plurality of photodiodes PD1 and the plurality of photodiodes PD2 can share the column line Col. Accordingly, the photodiodes PD2 can be isolated from the column line Col when the pixel voltage corresponding to the charge of the plurality of photodiodes PD11 to PD13 is output to the column line Col. For example, the photodiodes PD2 can be isolated from the column line Col when at least one of the first switch transistor SWX1 and the second switch transistor SWX2 is turned off while the first pixel voltage is output to the column line Col. To generate the first pixel voltage using the charge of the plurality of photodiodes PD1 and output the first pixel voltage to the column line Col, the first transfer transistor TX1 can be turned on so that the charge generated in the photodiodes PD1 can be accumulated in the first floating diffusion node FD1.

[0172] Similarly, the plurality of photodiodes PD11 to PD13 can be isolated from the column line Col when the second pixel voltage corresponding to the charge of the photodiodes PD2 is output to the column line Col. For example, the plurality of photodiodes PD11 to PD13 can be isolated from the column line Col when the first transfer transistor TX1 is turned off while the second pixel voltage is output to the column line Col. To generate the second pixel voltage and output the second pixel voltage to the column line Col, the first switch transistor SWX1 and the second switch transistor SWX2 can be turned on so that the third floating diffusion node FD3 and the first floating diffusion node FD1 can be connected to each other. The charge generated in the photodiodes PD2 and stored in the storage capacitor SC can be accumulated in the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3 and can be converted to a voltage by the drive transistor DX.

[0173] The image sensor in which the image sensing pixel PX1 has the split photodiode structure can have various structures in addition to the structures described with reference to FIGS. 1 to 6. FIGS. 17-19 The image sensor in which the image sensing pixel PX1 has the split photodiode structure can have various structures in addition to the structures described with reference to FIGS. 1 to 6.

[0174] FIGS. 21-23 is a plan view of a pixel included in an image sensor according to an example embodiment of the disclosure.

[0175] Reference FIG. 21The unit pixel array UPA5 can include a plurality of first regions A1, a plurality of second regions A2, and a plurality of third regions A3. FIG. 21 The unit pixel array UPA5 in FIG. 5A can correspond to the unit pixel array UPA5 described with reference to FIG. 5B. FIG. 17 The unit pixel array UPA4 described with reference to FIG. 4 has regions having similar shapes. However, the unit pixel array UPA5 can have a structure in which the shapes and positions of the second regions A2 and the third regions A3 in the unit pixel array UPA4 are changed.

[0176] For example, each of the unit pixel arrays UPA5 can include a plurality of octagonal regions that adjoin two first edges extending in a first direction (X direction), two second edges extending in a second direction (Y direction), and four third edges. Each of the plurality of octagonal regions can adjoin at least one of the plurality of octagonal regions on at least one of the first edges and at least one of the second edges. Each of the plurality of octagonal regions can include the first region A1 and the third region A3.

[0177] The plurality of second regions A2 can be disposed between the plurality of octagonal regions. For example, at least one of the third edges of the plurality of octagonal regions can adjoin at least one of the plurality of second regions A2.

[0178] Referring to FIG. 5B, FIG. 22A and FIG. 22B The unit pixel arrays UPA5a and UPA5b can include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA5a and UPA5b can correspond to the unit pixel array UPA5 described with reference to FIG. 5A. FIG. 21 The unit pixel array UPA5 described with reference to FIG. 5A.

[0179] Each of the first regions A1 can include one or more photodiodes PD11 to PD13 (PD1). In some embodiments, each of the second regions A2 can include one or more photodiodes PD21 (PD2). The sum of the light-receiving areas of the photodiodes PD1 can be greater than the light-receiving area of the photodiode PD2.

[0180] In an example implementation, one first region A1 and one second region A2 spaced apart from each other by one third region A3 therebetween can share one first pixel circuit. The color filters transmitting the same color can be located in the first region A1 and the second region A2 sharing one first pixel circuit.

[0181] Each third region A3 can include one of photodiodes PD3a to PD3d. In an example embodiment, the photodiodes PD3 included in the plurality of third regions A3 included in the unit pixel arrays UPA5a and UPA5b can be included in one event sensing pixel PX2.

[0182] In the unit pixel array UPA5, the microlenses included in the upper portions of the first to third regions A1 to A3 can have various sizes and shapes.

[0183] In FIG. 22A an example, the first region A1 can include one first microlens ML1 in the upper portion of the three photodiodes PD1. In some embodiments, the second region A2 can include one second microlens ML2 disposed on the upper portion of one photodiode PD2, and the third region A3 can include one third microlens ML3 disposed on the upper portion of the photodiode PD3.

[0184] In FIG. 22B an example, the first region A1 can include three first microlenses ML1b disposed on the upper portions of the three photodiodes PD1, respectively.

[0185] Referring to FIG. 23 , the unit pixel array UPA5c can have a structure similar to that of the unit pixel array UPA5a of FIG. 22A However, the unit pixel array UPA5c of FIG. 23 may include eight photodiodes PD1. In one octagonal region, the eight photodiodes PD1 and one photodiode PD3 can be arranged in a 3x3 shape.

[0186] A first region A1 and a second region A2 spaced apart from each other by one third region A3 therebetween can share one first pixel circuit. The sum of the light-receiving areas of the eight photodiodes PD1 can be greater than the light-receiving area of the photodiode PD2.

[0187] FIGS. 24-26 is a plan view of a pixel in an image sensor according to an example embodiment of the disclosure.

[0188] Referring to FIG. 24 , the unit pixel array UPA6 can include a plurality of first regions A1, a plurality of second regions A2, and a plurality of third regions A3. The unit pixel array UPA6 can include a plurality of rectangular regions. Each of the plurality of rectangular regions can include one first region A1, one second region A2, and one third region A3.

[0189] In FIG. 24In an example of the unit pixel array UPA6, the first area A1 can be adjacent to the second area A2 and the third area A3 in a first direction (X direction), and the second area A2 and the third area A3 can be adjacent to each other in a second direction (Y direction). The plurality of third areas A3 can be spaced apart from each other in the first direction (X direction) and the second direction (Y direction).

[0190] A deep trench isolation (DTI) can be formed in a boundary between the first area A1, the second area A2, and the third area A3.

[0191] According to example embodiments of the disclosure, the plurality of first areas A1 can each include a large photodiode, and the plurality of second areas A2 can each include a small photodiode. The large photodiode and the small photodiode can share one first pixel circuit. In some embodiments, the plurality of third areas A3 can include a photodiode included in an event sensing pixel.

[0192] Referring to FIG. 25A and FIG. 25B , the unit pixel arrays UPA6a and UPA6b can include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA6a and UPA6b can correspond to the unit pixel array UPA6 described with reference to FIG. 24 .

[0193] In FIG. 25A and FIG. 25B , each first area A1 can include two photodiodes PD1, each second area A2 can include one photodiode PD2, and each third area A3 can include one of photodiodes PD3a to PD3b.

[0194] Similar to what is described with reference to FIG. 18A , FIG. 18B , FIG. 22A and FIG. 22B , the photodiode PD1 and the photodiode PD2 included in one rectangular area can share one first pixel circuit. The image sensing pixels sharing one first pixel circuit can include color filters transmitting the same color. In some embodiments, the photodiode PD3 included in the plurality of third areas A3 included in the unit pixel arrays UPA6a and UPA6b can be included in one event sensing pixel PX2.

[0195] In the unit pixel array UPA6, the microlenses included in the upper portions of the first area A1 to the third area A3 can have various sizes and shapes.

[0196] In FIG. 25AIn the example, the first region A1 may include a first microlens ML1 disposed on the upper part of two photodiodes PD1. In some embodiments, the second region A2 may include a second microlens ML2 disposed on the upper part of a photodiode PD2, and the third region A3 may include a third microlens ML3 disposed on the upper part of a photodiode PD3.

[0197] exist FIG. 25B In the example, the first region A1 may include two first microlenses ML1b respectively disposed on the upper part of the two photodiodes PD1.

[0198] refer to FIG. 26 The unit pixel array UPA6c can have the same as FIG. 25A The structure is similar to that of the unit pixel array UPA6a. However, in FIG. 26 In the unit pixel array UPA6c, a first region A1 may include six photodiodes PD1, and a second region A2 may include two photodiodes PD2. In a rectangular region, photodiodes PD1, PD2, and PD3 may be arranged in a 3×3 shape.

[0199] FIGS. 27-29 It is a planar view of pixels included in an image sensor according to an exemplary embodiment of the present disclosure.

[0200] refer to FIG. 27 The unit pixel array UPA7 may include multiple first regions A1, multiple second regions A2, and multiple third regions A3. The unit pixel array UPA7 may also include multiple rectangular regions. Each of these rectangular regions may include one first region A1, one second region A2, and one third region A3.

[0201] and FIG. 24 Unlike the unit pixel array UPA6 depicted in the image, the first region A1, the second region A2, and the third region A3 are in... FIG. 27 The relative positions of units within a rectangular region of the unit pixel array UPA7 can be different from each other. For example, in adjacent rectangular regions of the unit pixel array UPA6 in the first direction (X direction) and the second direction (Y direction), the third region A3 can be adjacent to each other.

[0202] refer to FIG. 28A and FIG. 28B The unit pixel arrays UPA7a and UPA7b may include multiple image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA7a and UPA7b may correspond to a reference... FIG. 27 The unit pixel array UPA7 is described.

[0203] Similarly to what is described with reference to FIG. 25A and FIG. 25B , the photodiode PD1 and the photodiode PD2 included in one rectangular region can share one first pixel circuit. The image sensing pixels sharing one first pixel circuit can include filters transmitting the same color. In some embodiments, the photodiodes PD3 included in the plurality of third regions A3 included in the unit pixel arrays UPA7a and UPA7b can be included in one event sensing pixel PX2.

[0204] In the unit pixel array UPA7, the microlenses included in the upper portions of the first regions A1 to the third regions A3 can have various sizes and shapes.

[0205] In the example of FIG. 28A , the first region A1 can include one first microlens ML1 disposed on the upper portion of the two photodiodes PD1. In some embodiments, the second region A2 can include one second microlens ML2 disposed on the upper portion of the one photodiode PD2, and the third region A3 can include one third microlens ML3 disposed on the upper portion of one of the photodiodes PD3a to PD3d.

[0206] In the example of FIG. 28B , the first region A1 can include two first microlenses ML1b disposed on the upper portions of the two photodiodes PD1, respectively.

[0207] With reference to FIG. 29 , the unit pixel array UPA7c can have a structure similar to that of the unit pixel array UPA7a of FIG. 28A . However, in the unit pixel array UPA7c of FIG. 29 , one first region A1 can include six photodiodes PD1, and one second region A2 can include two photodiodes PD2. In one rectangular region, the photodiodes PD1, the photodiodes PD2, and the photodiodes PD3 can be arranged in a 3x3 shape.

[0208] Examples of image sensors having various structures according to example embodiments of the present disclosure have been described with reference to FIGS. 17-29 . Hereinafter, an example of a vertical structure that an image sensor can have by including a lower semiconductor layer will be described.

[0209] FIG. 30 is a side cross-sectional view illustrating an image sensor according to an example embodiment of the present disclosure, which illustrates a cutout of a main region and a peripheral region.

[0210] The image sensor 1100 can include a first semiconductor chip 1200, a second semiconductor chip 1300, and a third semiconductor chip 1400. The first semiconductor chip 1200, the second semiconductor chip 1300, and the third semiconductor chip 1400 can correspond to the first semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400 described with reference to FIGS. 1A and 1B. FIG. 9 The upper semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400 are described. In each of the first semiconductor chip 1200, the second semiconductor chip 1300, and the third semiconductor chip 1400, a main area MAIN and a peripheral area PERI can be defined.

[0211] The first semiconductor layer 1200 can include a first semiconductor substrate 1210 and a first interconnection structure 1220 disposed on the first semiconductor substrate 1210.

[0212] The first semiconductor substrate 1210 can be a silicon substrate or a semiconductor substrate such as silicon germanium. A surface in which semiconductor elements are formed in the first semiconductor substrate 1210 can be referred to as an upper surface or a front surface, and a face opposite to the upper surface of the first semiconductor substrate 1210 can be referred to as a lower surface or a back surface.

[0213] The first semiconductor substrate 1210 can include a plurality of photodiodes PD1 and PD2 and a pixel separation structure 1280. In an example embodiment, the plurality of photodiodes PD1 can share one pixel circuit PXC1, and the photodiode PD2 can be connected to a second pixel circuit PXC2. The lower surface of the first semiconductor substrate 1210 can be a light-receiving surface on which light is incident.

[0214] The pixel separation structure 1280 can be disposed between a plurality of pixels arranged in a matrix shape to define the plurality of pixels. In an example embodiment, the pixel separation structure 1280 can physically and electrically separate the first photodiode PD1 and the second photodiode PD2. The pixel separation structure 1280 can have a DTI structure that penetrates the semiconductor substrate 1210 from the upper surface of the semiconductor substrate 1210 to the lower surface of the semiconductor substrate 1210. The DTI structure can be in contact with the lower surface of the semiconductor substrate 1210. A deep trench for the pixel separation structure 1280 can be formed in the semiconductor substrate 1210, and the pixel separation structure 1280 can include an insulating layer 1281 conformally formed on an inner surface of the trench, and a conductive layer 1285 filling the trench on the insulating layer 1281. For example, the insulating layer 1281 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and tantalum oxide. The conductive layer 1285 can include at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing film.

[0215] On the upper surface of the first semiconductor substrate 1210, a first semiconductor layer 1200, a second semiconductor layer 1300, and a third semiconductor layer 1400 can be disposed as described with reference to FIGS. 1A and 1B.FIG. 8A Semiconductor elements included in the described image sensing pixel circuit. A device isolation pattern ISO can be formed in the first semiconductor substrate 1210 to define an active region in which the first semiconductor elements are to be formed. For example, the device isolation pattern ISO can be formed by filling an insulating material in a shallow trench formed by patterning the first semiconductor substrate 1210.

[0216] The first semiconductor elements can include some of the elements included in the first pixel circuit, and can include transistors having a gate electrode, a gate insulating film, and a source / drain region.

[0217] The first semiconductor elements can include transistors such as the following: reference FIG. 8A The described first transfer transistor TX1, reset transistor RX, drive transistor DX, and select transistor SX.

[0218] At least a portion of the gate electrode of the first transfer transistor TX1 can extend in a vertical direction and can be buried in the first semiconductor substrate 1210. The first floating diffusion node FD1 can be connected to one end of the first transfer transistor TX1. When the first transfer transistor TX1 is turned on, the electric charge generated by the photodiode PD1 can be stored in the first floating diffusion node FD1.

[0219] The first interconnect structure 1220 located on the upper surface of the first semiconductor substrate 1210 can include a first insulating layer 1221 and a first interconnect layer 1225 located in the first insulating layer 1221. The first interconnect layer 1225 can be connected to the first semiconductor elements, and thus, can be included in the image sensing pixel circuit. The first interconnect layer 1225 can include a plurality of interconnect lines 1222 located at a plurality of levels in the first insulating layer 1221 and an interconnect via 1223 connected to the plurality of interconnect lines 1222. For example, the first interconnect layer 1225 can include copper or a copper alloy.

[0220] The second semiconductor chip 1300 can include a second interconnect structure 1320 located on the first interconnect structure 1220 and having a capacitor 1380, and a second semiconductor substrate 1310 disposed on the second interconnect structure 1320. According to example embodiments of the present disclosure, an event sensing pixel circuit can be formed in the second semiconductor chip 1300.

[0221] The second semiconductor chip 1300 can be located on the first semiconductor chip 1200. The first semiconductor chip and the second semiconductor chip can be bonded such that the first interconnect structure 1220 and the second interconnect structure 1320 face each other.

[0222] As described with reference to FIG. 8BThe second semiconductor element included in the event sensing pixel circuit described can be disposed on the upper surface of the second semiconductor substrate 1310. The second semiconductor element 1350 can include some of the elements included in the event sensing pixel circuit, and can include a transistor having a gate electrode 1352, a gate insulating film 1351, and source / drain regions 1355a and 1355b.

[0223] Similar to the first interconnection structure 1220, the second interconnection structure 1320 can include a second insulating layer 1321 and a second interconnection layer 1325 located in the second insulating layer 1321. The second interconnection layer 1325 can include a plurality of interconnection lines 1322 and interconnection vias 1323.

[0224] According to example embodiments of the present disclosure, the photodiode PD2 formed in the first semiconductor substrate 1210 can be connected to the second pixel circuit formed in the second semiconductor chip 1300 by the first metal pad 1225P.

[0225] The first interconnection structure 1220 can include a first bonding insulating layer 1221B disposed at the uppermost portion of the first interconnection structure 1220 and a first metal pad 1225P in the first bonding insulating layer 1221B connected to the first interconnection layer 1225. Similarly, the second interconnection structure 1320 can include a second bonding insulating layer 1321B located at the lowermost portion of the second interconnection structure 1320 and a second metal pad 1325P located in the second bonding insulating layer 1321B. The first metal pad 1225P can have an upper surface that is substantially flush with the upper surface of the first bonding insulating layer 1221B, and the second metal pad 1325P can have an upper surface that is substantially flush with the upper surface of the second bonding insulating layer 1321B.

[0226] The first metal pad 1225P and the second metal pad 1325P can be directly bonded to form a metal-to-metal bond, and the first bonding insulating layer 1221B and the second bonding insulating layer 1321B can be directly bonded to form a dielectric-to-dielectric bond. Such bonding can also be referred to as a hybrid bond.

[0227] The first interconnection layer 1225 and the second interconnection layer 1325 can be electrically connected by the bonding between the first metal pad 1225P and the second metal pad 1325P. The bonding between the first metal pad 1225P and the second metal pad 1325P can be electrically connected not only in the peripheral region PERI but also in the main region MAIN. FIG. 30 A first path P1a and P1b (P1) for electrically connecting the second pixel circuit and the photodiode PD2 is illustrated.

[0228] In an embodiment, in the peripheral region PERI, a first through via 1510 can be further included to electrically connect the first semiconductor chip 1200 and the second semiconductor chip 1300.

[0229] The third semiconductor chip 1400 can include a third interconnection structure 1420 disposed on the second semiconductor substrate 1310, and a third semiconductor substrate 1410 disposed on the third interconnection structure 1420 and in which logic elements are implemented. The third semiconductor chip 1400 can include a logic circuit.

[0230] Similar to the first interconnection structure 1220 and the second interconnection structure 1320, the third interconnection structure 1420 can include a third insulating layer 1421 and a third interconnection layer 1425 located in the third insulating layer 1421. The third interconnection layer 1425 can include a plurality of interconnection lines 1422 and an interconnection via 1423.

[0231] The third semiconductor elements 1450 formed in the active region defined by the device isolation pattern ISO can be formed on a lower surface of the third semiconductor substrate 1410. The third semiconductor elements 1450 can include a logic circuit, for example, the first logic circuit 20 and the second logic circuit 30 as described with reference to FIG. 1

[0232] In an example embodiment, the third semiconductor chip 1400 is illustrated as being electrically connected to the first semiconductor chip 1200 and the second semiconductor chip 1300 through the second through via 420, but similar to the connection between the first semiconductor chip 1200 and the second semiconductor chip 1300, the connection between the second semiconductor chip 1300 and the third semiconductor chip 1400 can be implemented by metal pad bonding, instead of through the second through via 420, or in parallel with the second through via 420.

[0233] The present disclosure is not limited to the above-described embodiments and drawings, but is defined by the appended claims. Therefore, those of ordinary skill in the art can make various substitutions, modifications, or changes without departing from the scope of the present disclosure defined by the appended claims, and such substitutions, modifications, or changes should be interpreted as being included in the scope of the present disclosure.​

Claims

1. An image sensor, the image sensor comprising: A first region is provided along a first direction and a second direction parallel to the upper surface of the substrate, wherein the first direction and the second direction intersect each other; A second region is provided along the first direction and the second direction; A first photodiode, the first photodiode being located in the first region; A second photodiode, located in the second region; An image sensing pixel circuit, the image sensing pixel circuit being configured to generate a first electrical signal based on the charge generated by the first photodiode; An event sensing pixel circuit, configured to generate a second electrical signal based on a change in the amount of charge generated by the second photodiode; and Logic circuit, which is electrically connected to the image sensing pixel circuit; The first region is diagonally positioned opposite the second region on a third-order upward direction, and The third direction is different from the first direction and the second direction.

2. The image sensor according to claim 1, wherein, The light-receiving area of ​​the first photodiode is larger than that of the second photodiode.

3. The image sensor according to claim 1, wherein, The first region is octagonal in shape, the octagonal shape including two first edges extending in the first direction, two second edges extending in the second direction, and four third edges, and The second region is rectangular in shape.

4. The image sensor according to claim 1, wherein, The first photodiode and the second photodiode are disposed in the first chip, and The event sensing pixel circuit is disposed in a second chip that is stacked on the first chip.

5. The image sensor according to claim 4, wherein, The logic circuit is disposed in a third chip stacked on the second chip, and The second chip is disposed between the first chip and the third chip.

6. The image sensor according to claim 5, further comprising: A third photodiode, wherein the third photodiode is located in the first region; as well as Floating diffusion nodes, The first photodiode and the third photodiode are configured to share the floating diffusion node.

7. The image sensor according to claim 5, further comprising: Floating diffusion nodes; A reset transistor configured to reset the voltage of the floating diffusion node; as well as A transfer transistor configured to transfer the charge generated by the first photodiode to the floating diffusion node. The floating diffusion node, the reset transistor, and the transmission transistor are disposed in the first chip.

8. The image sensor according to claim 7, wherein, The first chip is connected to the second chip via copper-to-copper bonding.

9. The image sensor according to claim 8, further comprising: A third photodiode, wherein the third photodiode is located in the first region; as well as A microlens is disposed on the first photodiode and the third photodiode.

10. The image sensor according to claim 8, wherein, The first chip is connected to the third chip via a through-path.

11. The image sensor of claim 10, further comprising: A third region is disposed directly adjacent to the first region in the first direction; as well as A third photodiode, located in the third region. The light-receiving area of ​​the third photodiode is larger than that of the second photodiode.

12. The image sensor of claim 11, further comprising: A first microlens, the first microlens being located on the first photodiode; as well as The second microlens is located on the second photodiode. Wherein, the width of the first microlens in the second direction is greater than the width of the second microlens in the second direction.

13. The image sensor according to claim 9, further comprising: A fourth photodiode, wherein the fourth photodiode is located in the first region; as well as The fifth photodiode, located in the first region, The microlens is disposed on the first photodiode, the third photodiode, the fourth photodiode, and the fifth photodiode.

14. The image sensor of claim 11, further comprising: Deep trench isolation, wherein the deep trench isolation is located between the first region and the second region, and The deep trench isolation is in contact with the upper surface of the substrate.

15. The image sensor according to claim 14, wherein, The deep trench isolates contact with the lower surface of the substrate, and Wherein, the lower surface of the substrate is opposite to the upper surface of the substrate.

16. The image sensor according to claim 8, wherein, The transmission transistor extends into the substrate.

17. An image sensor, the image sensor comprising: substrate; A first photodiode, the first photodiode being located in a first region of the substrate; A second photodiode, wherein the second photodiode is located in a second region of the substrate; A third photodiode, wherein the third photodiode is located in a third region of the substrate; A fourth photodiode, wherein the fourth photodiode is located in a fourth region of the substrate; Transmission transistor; Reset transistor; as well as An event-sensing pixel circuit is configured to generate an electrical signal based on changes in the amount of charge generated by the second photodiode. In the plan view, the third region is directly adjacent to the first region along the first direction. In the plan view, the fourth region is directly adjacent to the first region along a second direction perpendicular to the first direction. In the plan view, the second region is diagonally opposite to the first region along a third direction different from both the first and second directions. Wherein, the light-receiving area of ​​each of the first photodiode, the third photodiode, and the fourth photodiode is greater than the light-receiving area of ​​the second photodiode, and The transmission transistor and the reset transistor are shared by the first photodiode.

18. The image sensor according to claim 17, wherein, The first photodiode, the second photodiode, the third photodiode, the fourth photodiode, the transmission transistor, and the reset transistor are disposed in the first chip. The event sensing pixel circuit is located in the second chip. The first chip is stacked on top of the second chip, and The first chip is connected to the second chip via copper-to-copper bonding.

19. The image sensor of claim 17, further comprising: The first microlens, located on the first photodiode, and The second microlens is located on the second photodiode. Wherein, the width of the first microlens in the first direction is greater than the width of the second microlens in the first direction.

20. An image sensor, the image sensor comprising: A substrate, the substrate including a first surface and a second surface opposite to the first surface; A first photodiode, the first photodiode being located in a first region of the substrate; A second photodiode, wherein the second photodiode is located in a second region of the substrate; A first microlens, the first microlens being located on the first photodiode; The second microlens is located on the second photodiode; An image sensing pixel circuit, the image sensing pixel circuit being configured to generate a first electrical signal based on the charge generated in the first photodiode; An event sensing pixel circuit, the event sensing pixel circuit being configured to generate a second electrical signal based on a change in the amount of charge generated by the second photodiode; Deep trench isolation, wherein the deep trench isolation is located between the first region and the second region; as well as The logic circuit is electrically connected to the image sensing pixel circuit. The first region and the second region are directly adjacent. The deep trench isolation contacts the first surface and the second surface of the substrate, and In the planar view, the width of the first microlens in the first direction is greater than the width of the second microlens in the first direction.

Images