Light-emitting diode capable of improving welding voidage and preparation method thereof

Abstract

The invention provides a light-emitting diode capable of improving welding voidage and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises an epitaxial layer, a first insulating layer, an electrode and a bonding pad, the surface of the epitaxial layer is provided with a first groove, the first insulating layer is located on the surface of the epitaxial layer and in the first groove, the first insulating layer is provided with a first through hole and a second through hole, the first through hole is located in the first groove, the second through hole is located outside the first groove, and the electrode is located on the surface of the first insulating layer. The substrate is connected with the epitaxial layer through the first through hole and the second through hole; the orthographic projection of the first through hole and the orthographic projection of the second through hole on the surface, away from the bonding pad, of the epitaxial layer are both located outside the orthographic projection of the bonding pad on the surface, away from the bonding pad, of the epitaxial layer. The problem that a welding cavity is easily formed below the bonding pad can be solved, and the heat dissipation effect of the light-emitting diode is improved.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved welding void ratio and its preparation method. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. They are characterized by their small size, long lifespan, rich and colorful colors, and low energy consumption. They are widely used in lighting, displays, signal lights, backlights, toys, and other fields.

[0003] In related technologies, light-emitting diodes typically include an epitaxial layer, an insulating layer, and pads. The surface of the epitaxial layer has grooves, the insulating layer covers the surface of the epitaxial layer and the grooves, the surface of the insulating layer also has vias, and the pads are located on the surface of the insulating layer and are electrically connected to the epitaxial layer through the vias.

[0004] Vias and grooves on the epitaxial layer surface result in an uneven surface for the insulating layer used to form solder pads, containing numerous micron-sized pores. Since solder pads are typically made of AuSn, which has a high melting point, fast solidification rate, and poor fluidity in its molten state, the AuSn solder tends to solidify rapidly during pad fabrication, making it difficult to fill the micron-sized pores on the uneven insulating layer surface. This results in some gaps in the areas containing the pores not being completely filled by the molten AuSn, forming solder voids. The air within these voids has extremely low thermal conductivity, hindering heat conduction and affecting the heat dissipation performance of the LED. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) with improved solder void ratio and its fabrication method, which can improve the problem of solder voids easily forming under the solder pads and enhance the heat dissipation effect of the LED. The technical solution is as follows:

[0006] On one hand, this disclosure provides a light-emitting diode (LED) comprising an epitaxial layer, a first insulating layer, an electrode, and a pad; the surface of the epitaxial layer has a first groove, the first insulating layer is located on the surface of the epitaxial layer and within the first groove, the first insulating layer has a first through-hole and a second through-hole, the first through-hole is located within the first groove, the second through-hole is located outside the first groove, the electrode is located on the surface of the first insulating layer and is connected to the epitaxial layer through the first through-hole and the second through-hole; the pad is located on the surface of the electrode, and the orthographic projections of the first through-hole and the second through-hole on the surface of the epitaxial layer away from the pad are both located outside the orthographic projection of the pad on the surface of the epitaxial layer away from the pad.

[0007] Optionally, the first via includes a plurality of first sub-vias, which are spaced apart and arranged at intervals along the peripheral edge of the epitaxial layer.

[0008] Optionally, the solder pad includes a first solder joint block and a second solder joint block, the first solder joint block and the second solder joint block are arranged at intervals, and there is a strip-shaped gap between the opposite sides of the first solder joint block and the second solder joint block; the first through hole also includes a plurality of second sub-holes, the second sub-holes and the second through holes are both located in the gap, and the plurality of second sub-holes and the plurality of second through holes are arranged alternately along the length direction of the gap.

[0009] Optionally, the electrode includes a first electrode block and a second electrode block; the first electrode block and the second electrode block are located on the surface of the first insulating layer, the first electrode block has a second groove exposing the first insulating layer, the second electrode block is located in the second groove and is spaced apart from the sidewall of the second groove; the orthographic projection of the first through-hole on the surface of the epitaxial layer away from the pad is located within the orthographic projection of the first electrode block on the surface of the epitaxial layer away from the pad, the first electrode block is connected to the epitaxial layer through the first through-hole, and the first solder joint is located on the surface of the first electrode block; the orthographic projection of the second through-hole on the surface of the epitaxial layer away from the pad is located within the orthographic projection of the second electrode block on the surface of the epitaxial layer away from the pad, the second electrode block is connected to the epitaxial layer through the second through-hole, and the second solder joint is located on the surface of the second electrode block.

[0010] Optionally, one sidewall of the second groove is a first concave-convex sidewall, which has grooves and protrusions arranged alternately in sequence; the sidewall of the second electrode block opposite to the first concave-convex sidewall is a second concave-convex sidewall, which has grooves and protrusions arranged alternately in sequence, and the first concave-convex sidewall engages with the second concave-convex sidewall; the second sub-hole is located below the protrusion of the first concave-convex sidewall, and the second through hole is located below the protrusion of the second concave-convex sidewall (521).

[0011] Optionally, the first sub-hole is elongated, the second sub-hole is circular, and the second through hole is elongated.

[0012] Optionally, the light-emitting diode further includes a transparent conductive layer and a silver mirror reflective layer, wherein the transparent conductive layer is located on the surface of the epitaxial layer, the silver mirror reflective layer is located on the surface of the epitaxial layer and covers the silver mirror reflective layer, and the second via exposes the silver mirror reflective layer.

[0013] Optionally, the light-emitting diode further includes a second insulating layer located on the surface of the first insulating layer and covering the electrode; the second insulating layer has a via exposing the electrode, the pad being located within the via, and the orthographic projection of the pad onto the surface of the epitaxial layer away from the pad being located within the orthographic projection of the via onto the surface of the epitaxial layer away from the pad.

[0014] On the other hand, embodiments of this disclosure also provide a method for fabricating a light-emitting diode, the method comprising: forming an epitaxial layer on a substrate, the surface of the epitaxial layer having a first groove; forming a first insulating layer on the surface of the epitaxial layer and within the first groove, the first insulating layer having a first through-hole and a second through-hole, the first through-hole being located within the first groove and the second through-hole being located outside the first groove; forming an electrode on the surface of the first insulating layer, the electrode being connected to the epitaxial layer through the first through-hole and the second through-hole; forming a pad on the surface of the electrode, wherein the orthographic projections of the first through-hole and the second through-hole on the surface of the epitaxial layer away from the pad are both located outside the orthographic projection of the pad on the surface of the epitaxial layer away from the pad.

[0015] Optionally, forming a pad on the surface of the electrode includes: forming a second insulating layer covering the electrode on the surface of the first insulating layer; forming a mask layer on the surface of the second insulating layer, the mask layer having etched holes exposing the second insulating layer; etching the second insulating layer through the etched holes to form a via exposing the electrode; and depositing a pad through the etched holes in the via, wherein the orthographic projection of the pad on the surface of the epitaxial layer away from the pad is located within the orthographic projection of the via on the surface of the epitaxial layer away from the pad.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] The epitaxial layer of the light-emitting diode provided in this embodiment has a first groove, a first insulating layer is located on the surface of the epitaxial layer and in the first groove, the first insulating layer has a first through hole located in the first groove and a second through hole located outside the first groove, an electrode is disposed on the surface of the first insulating layer, and the electrode can be connected to the epitaxial layer through the first through hole and the second through hole, and the pad is disposed on the electrode, so that current can be injected into the epitaxial layer to achieve the purpose of powering by energizing the pad.

[0018] Furthermore, the orthographic projections of the first and second vias onto the surface of the epitaxial layer furthest from the pad are both outside the orthographic projections of the pads onto the surface of the epitaxial layer furthest from the pad. That is, the pads are not opposite the first and second vias, and the first and second vias are not located below the pads. This makes the surface of the first insulating layer used to form the pads smoother and less prone to the formation of numerous micron-sized voids. Therefore, pads without solder voids can be fabricated on the surface of the first insulating layer, improving the heat dissipation performance of the light-emitting diode. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0021] Figure 2 This is a cross-sectional view of a light-emitting diode provided in an embodiment of this disclosure;

[0022] Figure 3 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure;

[0023] Figure 4 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0024] Figure 5 yes Figure 4 A cross-sectional view is provided;

[0025] Figure 6 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0026] Figure 7 yes Figure 6 A cross-sectional view is provided;

[0027] Figure 8 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0028] Figure 9 yes Figure 8 A cross-sectional view is provided;

[0029] Figure 10 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0030] Figure 11 yes Figure 10 A cross-sectional view is provided;

[0031] Figure 12 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0032] Figure 13 yes Figure 12 A cross-sectional view is provided.

[0033] The markings in the diagram are explained as follows:

[0034] 10. Substrate;

[0035] 20. Epitaxial layer; 21. n-type layer; 22. Multiple quantum well layer; 23. p-type layer; 24. First groove;

[0036] 31. First insulating layer;

[0037] 311, First through hole; 3111, First sub-hole; 3112, Second sub-hole;

[0038] 312. Second through hole;

[0039] 32. Second insulating layer; 320. Via;

[0040] 41. First solder joint block; 42. Second solder joint block;

[0041] 51. First electrode block; 510. Second groove; 511. First concave-convex sidewall;

[0042] 52. Second electrode block; 521. Second concave-convex sidewall;

[0043] 61. Transparent conductive layer; 62. Silver mirror reflective layer. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0045] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0046] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 This is a cross-sectional view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken from section AA.

[0047] like Figure 1 , 2 As shown, the light-emitting diode includes an epitaxial layer 20, a first insulating layer 31, electrodes, and pads.

[0048] like Figure 1 , 2 As shown, the surface of the epitaxial layer 20 has a first groove 24, and the first insulating layer 31 is located on the surface of the epitaxial layer 20 and in the first groove 24. The first insulating layer 31 has a first through hole 311 and a second through hole 312. The first through hole 311 is located in the first groove 24, and the second through hole 312 is located outside the first groove 24. The electrode is located on the surface of the first insulating layer 31 and is connected to the epitaxial layer 20 through the first through hole 311 and the second through hole 312.

[0049] like Figure 1 , 2 As shown, the pads are located on the surface of the electrode, and the orthographic projections of the first via 311 and the second via 312 on the surface of the epitaxial layer 20 away from the pads are both outside the orthographic projections of the pads on the surface of the epitaxial layer 20 away from the pads.

[0050] The epitaxial layer 20 of the light-emitting diode provided in this embodiment has a first groove 24. A first insulating layer 31 is located on the surface of the epitaxial layer 20 and inside the first groove 24. The first insulating layer 31 has a first through hole 311 located inside the first groove 24 and a second through hole 312 located outside the first groove 24. An electrode is disposed on the surface of the first insulating layer 31, and the electrode can be connected to the epitaxial layer 20 through the first through hole 311 and the second through hole 312. The pad is disposed on the electrode. Therefore, by energizing the pad, current can be injected into the epitaxial layer 20 to achieve the purpose of energizing.

[0051] Furthermore, the orthographic projections of the first via 311 and the second via 312 onto the surface of the epitaxial layer 20 away from the pad are both located outside the orthographic projections of the pad onto the surface of the epitaxial layer 20 away from the pad. That is, the pad is not opposite to the first via 311 and the second via 312, and the first via 311 and the second via 312 are not located below the pad. This makes the surface of the first insulating layer 31 used to form the pad smoother and less prone to the formation of numerous micron-sized voids. Therefore, a pad without solder voids can be fabricated on the surface of the first insulating layer 31, improving the heat dissipation performance of the light-emitting diode.

[0052] Optionally, such as Figure 1 As shown, the first through hole 311 includes a plurality of first sub-holes 3111, which are spaced apart on the peripheral edge of the epitaxial layer 20.

[0053] By dispersing the first through-hole 311 into multiple first sub-holes 3111, the first through-hole 311 is prevented from occupying a large area of ​​the epitaxial layer 20, thus avoiding large areas of brightness loss in local areas of the epitaxial layer 20; and the first sub-holes 3111 are arranged in the edge area of ​​the epitaxial layer 20, which can effectively avoid the location of the pads and provide more fabrication area for the pads.

[0054] Furthermore, arranging the first sub-via 3111 at the periphery of the epitaxial layer 20 allows current to diffuse from the edge to the center, significantly improving the uniformity of current distribution. Moreover, the first sub-via 3111 also serves as a heat dissipation channel; arranging it at the periphery prevents heat from accumulating in the center of the LED.

[0055] Optionally, such as Figure 1 As shown, the solder pad includes a first solder joint block 41 and a second solder joint block 42, which are arranged at intervals, and there is a strip-shaped gap between the opposite sides of the first solder joint block 41 and the second solder joint block 42.

[0056] like Figure 1 , 2As shown, the first through hole 311 also includes a plurality of second sub-holes 3112. The second sub-holes 3112 and the second through holes 312 are both located in the gap, and the plurality of second sub-holes 3112 and the plurality of second through holes 312 are arranged alternately along the length of the gap.

[0057] By arranging the second sub-hole 3112 and the second through-hole 312 in the gap between the two solder blocks, the location of the solder blocks is avoided, thus providing more fabrication area for the solder blocks. Since the gap area of ​​the solder blocks is often underutilized, placing the second sub-hole 3112 and the second through-hole 312 in this position reduces the occupied area of ​​the light-emitting area and improves the brightness of the light-emitting diode.

[0058] Meanwhile, by densely arranging the second sub-hole 3112 and the second through hole 312 in the gap between the two solder blocks, an efficient heat dissipation channel can be formed to avoid local overheating.

[0059] Optionally, such as Figure 2 As shown, the electrode includes a first electrode block 51 and a second electrode block 52. The first electrode block 51 and the second electrode block 52 are located on the surface of the first insulating layer 31. The first electrode block 51 has a second groove 510 that exposes the first insulating layer 31. The second electrode block 52 is located in the second groove 510 and is arranged at intervals from the sidewall of the second groove 510.

[0060] like Figure 1 As shown, the first electrode block 51 is frame-shaped, and the central region of the first electrode block 51 has a second groove 510. The second electrode block 52 is arranged in the second groove 510 so that the first electrode block 51 and the second electrode block 52 can be insulated.

[0061] The frame-shaped first electrode block 51 allows current to be injected evenly from the edge of the chip, avoiding the current concentration problem caused by the first electrode block 51 being arranged in the center. The second electrode block 52 is located in the central inner hole, and the current diffusion path from the first electrode block 51 at the edge to the second electrode block 52 at the center is shorter and symmetrical, significantly reducing resistance loss.

[0062] like Figure 2 As shown, the orthographic projection of the first through-hole 311 on the surface of the epitaxial layer 20 away from the pad is located within the orthographic projection of the first electrode block 51 on the surface of the epitaxial layer 20 away from the pad. The first electrode block 51 is connected to the epitaxial layer 20 through the first through-hole 311, and the first solder joint block 41 is located on the surface of the first electrode block 51.

[0063] The first through hole 311 is located below the first electrode block 51 so that the first electrode block 51 can be electrically connected to the epitaxial layer 20 through the first through hole 311, so that current can be transmitted to the epitaxial layer 20 through the first electrode block 51.

[0064] like Figure 2As shown, the orthographic projection of the second via 312 on the surface of the epitaxial layer 20 away from the pad is located within the orthographic projection of the second electrode block 52 on the surface of the epitaxial layer 20 away from the pad. The second electrode block 52 is connected to the epitaxial layer 20 through the second via 312, and the second solder block 42 is located on the surface of the second electrode block 52.

[0065] The second through hole 312 is disposed below the second electrode block 52 so that the second electrode block 52 can be electrically connected to the epitaxial layer 20 through the second through hole 312, so that current can be transmitted to the epitaxial layer 20 through the second electrode block 52.

[0066] Optionally, such as Figure 1 As shown, one sidewall of the second groove 510 is a first concave-convex sidewall 511, which has alternating grooves and protrusions. That is, the sidewall of the first electrode block 51 facing the second electrode block 52 has an uneven, serrated shape. The serrated structure significantly extends the contact perimeter of the electrode edge, making the current more evenly distributed when injected from the electrode. Furthermore, the serrated structure increases the contact area between the electrode block and the semiconductor material, accelerating heat dissipation.

[0067] like Figure 1 As shown, the sidewall of the second electrode block 52 opposite to the first concave-convex sidewall 511 is a second concave-convex sidewall 521. The second concave-convex sidewall 521 has alternating grooves and protrusions, and the first concave-convex sidewall 511 engages with the second concave-convex sidewall 521. That is, the sidewall of the second electrode block 52 facing the first electrode block 51 is uneven and serrated. The serrated structure significantly extends the contact perimeter of the electrode edge, making the current more evenly distributed when injected from the electrode. The serrated structure increases the contact area between the electrode block and the semiconductor material, accelerating heat dissipation.

[0068] like Figure 1 As shown, the second sub-hole 3112 is located below the protrusion of the first concave-convex sidewall 511, and the second through hole 312 is located below the protrusion of the second concave-convex sidewall 521.

[0069] By setting the first concave-convex sidewall 511 and the second concave-convex sidewall 521 into a mutually cooperating serrated shape, the second sub-hole 3112 and the second through hole 312 can be arranged alternately on the same straight line. This allows more second sub-holes 3112 and second through holes 312 to be arranged simultaneously in the gap between the two solder blocks, reducing the occupation of the light-emitting area and improving the brightness of the light-emitting diode. Furthermore, the dense arrangement of the second sub-holes 3112 and the second through holes 312 in the gap between the two solder blocks forms an efficient heat dissipation channel.

[0070] Optionally, the first sub-hole 3111 is elongated, the second sub-hole 3112 is round, and the second through hole 312 is elongated.

[0071] The first sub-hole 3111, which is elongated, has strong lateral expansion, which is beneficial to the lateral expansion of current. Furthermore, the first sub-hole 3111 is arranged on the periphery of the epitaxial layer 20, which can significantly improve the current density in the corner area and enhance the uniformity of light emission.

[0072] The second sub-hole 3112 is round to dissipate heat evenly and prevent local overheating of the light-emitting diode.

[0073] The second through hole 312 is elongated, which facilitates the lateral spread of current in the gap between the two solder blocks.

[0074] Optionally, such as Figure 2 As shown, the light-emitting diode also includes a transparent conductive layer 61 and a silver mirror reflective layer 62. The transparent conductive layer 61 is located on the surface of the epitaxial layer 20, and the silver mirror reflective layer 62 is located on the surface of the epitaxial layer 20 and covers the silver mirror reflective layer 62. The second through hole 312 exposes the silver mirror reflective layer 62.

[0075] Since silver has a reflectivity of over 95%, the silver mirror reflective layer 62 can efficiently reflect the light emitted by the epitaxial layer 20 to the light-emitting surface, reducing light absorption loss from the substrate or electrode.

[0076] For example, the transparent conductive layer can be an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer. ITO and IZO have good transmittance and low resistivity, and using ITO and IZO as transparent conductive layers facilitates carrier conduction and improves injection efficiency.

[0077] As an example, the thickness of the transparent conductive layer can range from 100 angstroms to 5000 angstroms. For instance, the thickness of the transparent conductive layer is 1000 angstroms.

[0078] Optionally, such as Figure 1 , 2 As shown, the light-emitting diode also includes a second insulating layer 32, which is located on the surface of the first insulating layer 31 and covers the electrode.

[0079] like Figure 1 , 2 As shown, the second insulating layer 32 has a via 320 that exposes the electrode, and the pad is located inside the via 320. The orthographic projection of the pad on the surface of the epitaxial layer 20 away from the pad is located within the orthographic projection of the via 320 on the surface of the epitaxial layer 20 away from the pad.

[0080] The second insulating layer 32 serves to protect the electrodes. Furthermore, the via 320 on the second insulating layer 32 is larger than the pad, so that the pad is completely located within the via 320. This prevents the pad from forming on the sidewalls and openings of the via 320, allowing the pad to be fabricated on a completely flat surface without creating numerous micron-sized holes, thus improving the heat dissipation performance of the LED.

[0081] For example, the first insulating layer 31 and the second insulating layer 32 may be a silicon oxide layer or a titanium oxide layer.

[0082] Optionally, the thickness of the first insulating layer 31 and the second insulating layer 32 is from 1000 Å to 3 μm. For example, the thickness of the first insulating layer 31 and the second insulating layer 32 is 1 μm.

[0083] The thickness of the first insulating layer 31 and the second insulating layer 32 is set within the above-mentioned range so that the first insulating layer 31 and the second insulating layer 32 have sufficient thickness to ensure that the first insulating layer 31 and the second insulating layer 32 can provide good strength, and also avoid the first insulating layer 31 and the second insulating layer 32 being too thick, which would increase production costs.

[0084] Optionally, such as Figure 2 As shown, the light-emitting diode also includes a substrate, and the epitaxial layer 20 is located on the substrate.

[0085] For example, the substrate is a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode (LED) good luminous efficacy and stability.

[0086] Optionally, the epitaxial layer 20 includes an n-type layer 21, a multiple quantum well layer 22 and a p-type layer 23 sequentially stacked on the substrate, wherein the p-type layer 23 has a groove exposing the n-type layer 21.

[0087] For example, the first electrode block 51 is an n-electrode, which is located in the groove and connected to the n-type layer 21. The second electrode block 52 is a p-electrode, which is connected to the silver mirror reflective layer 62 through a through hole and can be transmitted to the p-type layer 23 in sequence through the silver mirror reflective layer 62 and the transparent conductive layer 61.

[0088] Optionally, the n-type layer 21 is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0089] Optionally, the multi-quantum-well layer 22 includes alternating InGaN quantum-well layers and GaN quantum-barrier layers. Specifically, the multi-quantum-well layer 22 may include 3 to 8 alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0090] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 22 includes five alternating periods of InGaN quantum-well layers and GaN quantum-barrier layers.

[0091] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0092] Optionally, the p-type layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0093] Figure 3 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. This method is used to fabricate... Figure 1 and Figure 2 The light-emitting diode shown. For example... Figure 3 As shown, the preparation method includes:

[0094] S11: An epitaxial layer 20 is formed on the substrate.

[0095] The surface of the epitaxial layer 20 has a first groove 24.

[0096] S12: A first insulating layer 31 is formed on the surface of the epitaxial layer 20 and in the first groove 24.

[0097] The first insulating layer 31 has a first through hole 311 and a second through hole 312. The first through hole 311 is located inside the first groove 24, and the second through hole 312 is located outside the first groove 24.

[0098] S13: An electrode is formed on the surface of the first insulating layer 31.

[0099] The electrode is connected to the epitaxial layer 20 through the first through-hole 311 and the second through-hole 312.

[0100] S14: Forming pads on the surface of the electrode.

[0101] The orthographic projections of the first through-hole 311 and the second through-hole 312 on the surface of the epitaxial layer 20 away from the pad are both located outside the orthographic projection of the pad on the surface of the epitaxial layer 20 away from the pad.

[0102] The epitaxial layer 20 of the light-emitting diode prepared by this method has a first groove 24. A first insulating layer 31 is located on the surface of the epitaxial layer 20 and inside the first groove 24. The first insulating layer 31 has a first through hole 311 located inside the first groove 24 and a second through hole 312 located outside the first groove 24. An electrode is disposed on the surface of the first insulating layer 31, and the electrode can be connected to the epitaxial layer 20 through the first through hole 311 and the second through hole 312. The pad is disposed on the electrode. Therefore, by applying current to the pad, current can be injected into the epitaxial layer 20 to achieve the purpose of powering.

[0103] Furthermore, the orthographic projections of the first via 311 and the second via 312 onto the surface of the epitaxial layer 20 away from the pad are both located outside the orthographic projections of the pad onto the surface of the epitaxial layer 20 away from the pad. That is, the pad is not opposite to the first via 311 and the second via 312, and the first via 311 and the second via 312 are not located below the pad. This makes the surface of the first insulating layer 31 used to form the pad smoother and less prone to the formation of numerous micron-sized voids. Therefore, a pad without solder voids can be fabricated on the surface of the first insulating layer 31, improving the heat dissipation performance of the light-emitting diode.

[0104] In step S11, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0105] As an example, in this embodiment of the disclosure, the substrate is a sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.

[0106] The sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment, the sapphire substrate is baked for 15 minutes.

[0107] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.

[0108] Step S11, growing the epitaxial layer 20 on the substrate, may include:

[0109] First, such as Figure 5 As shown, an n-type layer 21, a multi-quantum-well layer 22, and a p-type layer 23 are sequentially formed on a sapphire substrate using MOCVD technology.

[0110] Then, as Figure 5 As shown, the p-type layer 23 is etched to form a first groove 24 that exposes the n-type layer 21.

[0111] Specifically, this includes: after photolithography and development on the p-type layer 23, using ICP dry etching technology to create a first groove 24 extending from the p-type layer 23 to the n-type layer 21 on the p-type layer 23.

[0112] Next, an isolation trench extending from the n-type layer 21 to the substrate is formed on the n-type layer 21 using ICP dry etching technology.

[0113] Then, as Figure 7 As shown, an ITO film is deposited on the entire surface as a current spreading layer. Then, a pattern is formed on the surface using photolithography. Finally, the unpatterned ITO film is removed using an ITO etching solution to form an ITO layer.

[0114] Next, as Figure 9 As shown, after patterning is formed on the surface using photolithography, a silver mirror reflective layer 62 is fabricated by sputtering a silver mirror and then peeling off the resist.

[0115] like Figure 11 As shown, step S12 may include: depositing a silicon oxide layer over the entire surface to obtain a first insulating layer 31.

[0116] The thickness of the first insulating layer 31 is 1000 angstroms to 3 μm. After patterning is formed on the surface using photolithography, the target pattern is etched using BOE etching process.

[0117] like Figure 13 As shown, step S13 may include: after forming a pattern on the surface using photolithography, forming the first electrode block 51 and the second electrode block 52 by electron beam evaporation and metal deposition followed by a stripping and resist removal process.

[0118] Step S14 may include the following steps:

[0119] First, a second insulating layer 32 covering the electrode is formed on the surface of the first insulating layer 31.

[0120] Next, a mask layer is formed on the surface of the second insulating layer 32, the mask layer having etched holes that expose the second insulating layer 32.

[0121] Specifically, this includes: depositing a silicon oxide layer over the entire surface, wherein the thickness of the silicon oxide layer is 1000 angstroms to 3 μm, forming a pattern on the surface using photolithography, and then etching the target pattern using a BOE etching process.

[0122] Then, the second insulating layer 32 is etched through the etching holes to form vias 320 that expose the electrodes.

[0123] Next, pads are deposited by vapor deposition within the via 320 through etched holes.

[0124] The orthographic projection of the pad on the surface of the epitaxial layer 20 away from the pad is located within the orthographic projection of the via 320 on the surface of the epitaxial layer 20 away from the pad.

[0125] Specifically, the process includes: fabricating the first solder joint block 41 and the second solder joint block 42 using an electron beam evaporation metal deposition followed by a stripping and resist removal process; using the same photolithography step for etching the second insulating layer 32 and the electrodes, reducing the complexity of the fabrication process and improving fabrication efficiency. The first solder joint block 41 and the second solder joint block 42 are then fabricated again using an electron beam evaporation metal deposition followed by a stripping and resist removal process.

[0126] For example, the first insulating layer 31 and the second insulating layer 32 may be silicon oxide or silicon nitride, and the thickness of the first insulating layer 31 and the second insulating layer 32 may be from 1000 angstroms to 3 μm.

[0127] Finally, the sapphire substrate can be stealth-cut and scratched, which can effectively reduce brightness loss. Then, the light-emitting diode is obtained through testing.

[0128] The above are merely optional embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light emitting diode, characterized by, The light emitting diode comprises an epitaxial layer (20), a first insulating layer (31), an electrode and a pad; The surface of the epitaxial layer (20) has a first groove (24), the first insulating layer (31) is located on the surface of the epitaxial layer (20) and in the first groove (24), the first insulating layer (31) has a first through hole (311) and a second through hole (312), the first through hole (311) is located in the first groove (24), the second through hole (312) is located outside the first groove (24), the electrode is located on the surface of the first insulating layer (31) and connected with the epitaxial layer (20) through the first through hole (311) and the second through hole (312); The pad is located on the surface of the electrode, and the first through hole (311) and the second through hole (312) are both located outside the projection of the pad on the surface of the epitaxial layer (20) away from the pad.

2. A light emitting diode according to claim 1, characterised in that The first through hole (311) comprises a plurality of first sub-holes (3111), and the plurality of first sub-holes (3111) are arranged at intervals on the peripheral edge of the epitaxial layer (20).

3. A light emitting diode according to claim 2, characterised in that the first and second layers of gallium nitride are doped with silicon. The pad comprises a first pad block (41) and a second pad block (42), the first pad block (41) and the second pad block (42) are arranged at intervals, and the first pad block (41) and the second pad block (42) have a gap in the form of a strip between the opposite sides thereof; The first through hole (311) further comprises a plurality of second sub-holes (3112), the second sub-holes (3112) and the second through holes (312) are both located in the gap, and the plurality of second sub-holes (3112) and the plurality of second through holes (312) are alternately arranged along the length direction of the gap.

4. A light emitting diode according to claim 3, characterised in that the n-type layer is a layer of n-type GaN. The electrode comprises a first electrode block (51) and a second electrode block (52); The first electrode block (51) and the second electrode block (52) are located on the surface of the first insulating layer (31), the first electrode block (51) has a second groove (510) exposing the first insulating layer (31), and the second electrode block (52) is located in the second groove (510) and arranged at intervals with the side wall of the second groove (510); The projection of the first through hole (311) on the surface of the epitaxial layer (20) away from the pad is located within the projection of the first electrode block (51) on the surface of the epitaxial layer (20) away from the pad, the first electrode block (51) is connected with the epitaxial layer (20) through the first through hole (311), and the first pad block (41) is located on the surface of the first electrode block (51). The second via hole (312) is located in the second electrode block (52) in the orthographic projection of the surface of the epitaxial layer (20) away from the pad, the second electrode block (52) is connected with the epitaxial layer (20) through the second via hole (312), and the second pad block (42) is located on the surface of the second electrode block (52).

5. A light emitting diode according to claim 4, characterised in that the n-type layer is a layer of n-type GaN. The side wall of the second groove (510) is a first concave-convex side wall (511), and the first concave-convex side wall (511) has concaves and convexs arranged alternately. The side wall of the second electrode block (52) opposite to the first concave-convex side wall (511) is a second concave-convex side wall (521), the second concave-convex side wall (521) has concaves and convexs arranged alternately, and the first concave-convex side wall (511) is engaged with the second concave-convex side wall (521). The second sub-hole (3112) is located below the convex of the first concave-convex side wall (511), and the second via hole (312) is located below the convex of the second concave-convex side wall (521).

6. A light emitting diode according to claim 3, characterised in that the n-type layer is a layer of n-type GaN. The first sub-hole (3111) is in a strip shape, the second sub-hole (3112) is in a round hole shape, and the second via hole (312) is in a strip shape.

7. A light emitting diode according to any one of claims 1 to 6, characterised in that, The light emitting diode further comprises a transparent conductive layer (61) and a silver mirror reflection layer (62), the transparent conductive layer (61) is located on the surface of the epitaxial layer (20), the silver mirror reflection layer (62) is located on the surface of the epitaxial layer (20), and covers the silver mirror reflection layer (62), and the second via hole (312) exposes the silver mirror reflection layer (62).

8. A light emitting diode according to any one of claims 1 to 6, characterised in that, The light emitting diode further comprises a second insulating layer (32), the second insulating layer (32) is located on the surface of the first insulating layer (31) and covers the electrode; The second insulating layer (32) has a via hole (320) exposing the electrode, the pad is located in the via hole (320), and the orthographic projection of the pad on the surface of the epitaxial layer (20) away from the pad is located in the orthographic projection of the via hole (320) on the surface of the epitaxial layer (20) away from the pad.

9. A method for fabricating a light-emitting diode, characterized in that, The preparation method comprises: forming an epitaxial layer (20) on a substrate, and the surface of the epitaxial layer (20) has a first groove (24); forming a first insulating layer (31) on the surface of the epitaxial layer (20) and in the first groove (24), the first insulating layer (31) has a first via hole (311) and a second via hole (312), the first via hole (311) is located in the first groove (24), and the second via hole (312) is located outside the first groove (24); forming an electrode on the surface of the first insulating layer (31), and the electrode is connected with the epitaxial layer (20) through the first via hole (311) and the second via hole (312); A pad is formed on the surface of the electrode, and the first via hole (311) and the second via hole (312) are both located outside the pad in the orthographic projection of the epitaxial layer (20) away from the surface of the pad.

10. The production method according to claim 9, characterized in that, Forming the pad on the surface of the electrode comprises: forming a second insulating layer (32) covering the electrode on the surface of the first insulating layer (31); forming a mask layer on the surface of the second insulating layer (32), the mask layer having etching holes exposing the second insulating layer (32); forming a via hole (320) exposing the electrode by etching the second insulating layer (32) through the etching holes; forming a pad in the via hole (320) by evaporation through the etching holes, the pad being located within the orthographic projection of the via hole (320) in the epitaxial layer (20) away from the surface of the pad.

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