Non-overlap generation techniques for bootstrap switches

Abstract

The system includes a bootstrap circuit having an input terminal and an output terminal. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a second transistor, a third transistor, and a first transistor coupled between the first terminal of the boost capacitor and an output terminal of the bootstrap circuit, wherein the second transistor and the third transistor are coupled in series between the gate of the first transistor and the second terminal of the boost capacitor. The system also includes a switching transistor, where a gate of the switching transistor is coupled to an output of the bootstrap circuit, and a terminal of the switching transistor is coupled to an input of the bootstrap circuit.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of non-provisional patent application serial number 18 / 307,441 filed in the United States Patent Office on April 26, 2023, the contents of which are hereby fully relied upon and incorporated herein in their entirety and for all applicable purposes. BACKGROUND TECHNICAL FIELD

[0003] Aspects of the present disclosure relate generally to switches, and more particularly to bootstrap switches. BACKGROUND

[0004] A system can include a bootstrap switch for selectively blocking or passing signals in two or more channels of the system. To reduce crosstalk between the channels, a timing circuit (e.g., a clock path) can be used to generate non-overlapping clock signals for timing switching operations of the bootstrap switch. A challenge in implementing the timing circuit is that the timing circuit includes a delay circuit and a clock driver that introduce jitter / skew into the non-overlapping clock signals, thereby degrading performance. SUMMARY

[0005] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0006] A first aspect is directed to a system. The system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a second transistor, a third transistor, and a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor. The system further includes a switching transistor, wherein a gate of the switching transistor is coupled to the output of the bootstrap circuit and a terminal of the switching transistor is coupled to the input of the bootstrap circuit.

[0007] The second aspect relates to a system. The system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, a second transistor coupled between the gate of the first transistor and the second terminal of the boost capacitor, a first switch coupled between the output of the bootstrap circuit and ground, and a timing circuit. The timing circuit includes a logic gate having a first input, a second input, and an output, wherein the first input of the logic gate is coupled to the input of the timing circuit, and the output of the logic gate is coupled to the gate of the second transistor. The timing circuit also includes a clock path coupled between the input of the timing circuit and the second input of the logic gate, wherein a control input of the first switch is coupled to the clock path. The system also includes a switching transistor, wherein the gate of the switching transistor is coupled to the output of the bootstrap circuit, and the terminal of the switching transistor is coupled to the input of the bootstrap circuit. Attached Figure Description

[0008] Figure 1 Examples of bootstrap circuits and switching transistors according to certain aspects of this disclosure are shown.

[0009] Figure 2 Examples of systems including switching transistors and bootstrap circuits according to certain aspects of this disclosure are shown.

[0010] Figure 3 This illustrates certain aspects of this disclosure. Figure 2 A timing diagram of an example of the output clock signal of a bootstrap circuit.

[0011] Figure 4 This disclosure illustrates, according to certain aspects, an analog-to-digital converter. Figure 2 An example of a system.

[0012] Figure 5A An exemplary embodiment of a bootstrap circuit according to certain aspects of this disclosure is shown.

[0013] Figure 5B An example of a timing circuit according to certain aspects of this disclosure is shown.

[0014] Figure 6 This is an example illustrating certain aspects of this disclosure. Figure 5B Timing diagram of signals in a timing circuit.

[0015] Figure 7A Another exemplary embodiment of a bootstrap circuit according to certain aspects of this disclosure is shown.

[0016] Figure 7BAnother example of a bootstrap circuit is shown in accordance with certain aspects of the present disclosure.

[0017] Figure 7C Another example of a timing circuit is shown in accordance with certain aspects of the present disclosure.

[0018] Figure 8 An example implementation of a switch and voltage boosting circuit is shown in accordance with certain aspects of the present disclosure.

[0019] Figure 9A Another example implementation of a bootstrap circuit is shown in accordance with certain aspects of the present disclosure.

[0020] Figure 9B Another example of a timing circuit is shown in accordance with certain aspects of the present disclosure.

[0021] Figure 10 An example of a system including a switch transistor, a bootstrap circuit, and a receiver is shown in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0022] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0023] A switch transistor can be used in a signal path to selectively block or pass a signal in the signal path. As used herein, a “switch transistor” is a transistor used as a switch. A switch transistor can be implemented with an n-type field effect transistor (NFET) or another type of transistor. By controlling the voltage of the gate of the switch transistor, the on / off state of the switch transistor can be controlled. For the example of a switch transistor implemented with an NFET, the switch transistor can be turned on by applying a high voltage to the gate of the switch transistor, and the switch transistor can be turned off by applying a low voltage to the gate of the switch transistor. A switch transistor has an on-resistance, which is the resistance across the switch transistor when the switch transistor is turned on (i.e., turned on).

[0024] A challenge with using a switch transistor to selectively pass or block a signal in a signal path is that the on-resistance of the switch transistor depends on the gate-source voltage of the switch transistor. This dependency causes the on-resistance of the switch transistor to vary when the voltage of the signal in the signal path varies. The variation in the on-resistance of the switch transistor causes distortion of the signal in the signal path.

[0025] To address the voltage-dependent on-resistance of the switch transistor, a bootstrap circuit can be used. In this regard, Figure 1 An example of a switch transistor 110 and a bootstrap circuit 120 according to certain aspects is shown. In Figure 1 In the example of FIG. 1, the switch transistor 110 is implemented with an NFET. However, it should be appreciated that the switch transistor 110 can be implemented with another type of transistor, such as a p-type field effect transistor (PFET).

[0026] The switch transistor 110 is used to selectively pass or block a signal in a signal path 112. In Figure 1 In the example of FIG. 1, the signal path 112 is between an output of a buffer 130 and a sampling capacitor 140. The sampling capacitor 140 can be used in an analog-to-digital converter (ADC), a capacitive digital-to-analog converter (DAC), or another type of circuit to sample a signal. However, it should be appreciated that the present disclosure is not limited to these examples. It should also be appreciated that, in some implementations, the sampling capacitor 140 can be implemented with multiple capacitors (e.g., coupled in parallel).

[0027] The bootstrap circuit 120 is configured to turn on and turn off the switch transistor 110 based on a clock signal CLK. The bootstrap circuit 120 has an input 122 coupled to a terminal (e.g., source) of the switch transistor 110, a clock input 124 configured to receive the clock signal CLK, and an output 126 coupled to a gate of the switch transistor 110. The clock signal CLK can have an amplitude equal to the supply voltage Vdd, as shown in the example of FIG. 1. Figure 1

[0028] ​The bootstrap circuit 120 is configured to receive a voltage Vin of a signal at a terminal (e.g., source) of the switch transistor 110, generate an output clock signal ckout based on the clock signal CLK and the voltage Vin, and output the output clock signal ckout to a gate of the switch transistor 110 to turn on and turn off the switch transistor 110. The output clock signal ckout can have a period approximately equal to a period of the clock signal CLK. The output clock signal ckout has an amplitude equal to Vb + Vin, where Vb is a boost voltage (also referred to as an offset voltage). Thus, when the output clock signal ckout is high, the output clock signal ckout boosts the voltage Vin by the boost voltage Vb. The boost voltage Vb can be greater than a threshold voltage of the switch transistor 110 to turn on the switch transistor 110 when the output clock signal ckout is high. In one example, the boost voltage Vb is approximately equal to the supply voltage Vdd. In this example, the amplitude of the output clock signal ckout is approximately equal to Vdd + Vin. When the output clock signal ckout is low, the output clock signal ckout can have a voltage approximately equal to a ground potential.

[0029] Thus, when the output clock signal ckout is high, the voltage at the gate of the switch transistor 110 is equal to Vb + Vin, and the voltage at a terminal (e.g., source) of the switch transistor 110 is equal to Vin. This makes the gate-source voltage VGS of the switch transistor 110 approximately constant at Vb (i.e., VGS = Vb + Vin - Vin, which simplifies to Vb). The constant gate-source voltage VGS makes the on-resistance of the switch transistor 110 approximately constant for good linearity. In this example, the switch transistor 110 is turned on during a high phase of the output clock signal ckout (i.e., when the output clock signal ckout is high) and turned off during a low phase of the output clock signal ckout (i.e., when the output clock signal ckout is low).

[0030] Two or more switch transistors and two or more bootstrap circuits can be used to implement time-interleaved channels. In this regard, Figure 2 An example of a system 205 with two time-interleaved channels according to certain aspects of the disclosure is shown. The system 205 includes the switch transistor 110, the bootstrap circuit 120, the buffer 130, and the sampling capacitor 140 discussed above. The system 205 also includes a second switch transistor 210, a second bootstrap circuit 220, and a second sampling capacitor 240. In the following discussion, the switch transistor 110 is referred to as a first switch transistor, the bootstrap circuit 120 is referred to as a first bootstrap circuit, the sampling capacitor 140 is referred to as a first sampling capacitor 140, and the signal path 112 is referred to as a first signal path.

[0031] In this example, the second switch transistor 210 is used to selectively pass or block signals in the second signal path 212. The second signal path 212 is between the output of the buffer 130 and a second sampling capacitor 240. The second sampling capacitor 240 can be used in an ADC, a capacitive DAC, or another type of circuit to sample signals in the second signal path 212. It should also be understood that, in some implementations, the second sampling capacitor 240 can be implemented with multiple capacitors (e.g., coupled in parallel). The second bootstrap circuit 220 has an input 222 coupled to a terminal (e.g., source) of the second switch transistor 210, a clock input 224, and an output 226 coupled to a gate of the second switch transistor 210. In some implementations, the second bootstrap circuit 220 can be a second instance (i.e., a copy) of the first bootstrap circuit 120.

[0032] In this example, the first switch transistor 110 and the first bootstrap circuit 120 are used to sample signals in the first signal path 112 (also referred to as the first channel), and the second switch transistor 210 and the second bootstrap circuit 220 are used to sample signals in the second signal path 212 (also referred to as the second channel). In Figure 2 In this example, the first switch transistor 110 and the first bootstrap circuit 120 are used to sample signals in the first signal path 112 (also referred to as the first channel), and the second switch transistor 210 and the second bootstrap circuit 220 are used to sample signals in the second signal path 212 (also referred to as the second channel). In

[0033] During operation, the first bootstrap circuit 120 receives a first clock signal CLK0 at the respective clock input 124, and the second bootstrap circuit 220 receives a second clock signal CLK1 at the respective clock input 224. In certain aspects, the second clock signal CLK1 can be complementary to the first clock signal CLK0 to provide time interleaving of the two channels, as discussed further below.

[0034] The first bootstrap circuit 120 receives the first clock signal CLK0 and a voltage Vin0 of the signal at a terminal (e.g., source) of the first switch transistor 110. The first bootstrap circuit 120 generates an output clock signal ckout0 based on the first clock signal CLK0 and the voltage Vin0, and outputs the output clock signal ckout0 to a gate of the first switch transistor 110 to turn on and off the first switch transistor 110. When the output clock signal ckout0 is high, the output clock signal ckout0 has a voltage of approximately Vb + Vin0.

[0035] The second bootstrap circuit 220 receives the second clock signal CLK1 and a voltage Vin1 of the signal at a terminal (e.g., source) of the second switch transistor 210. The second bootstrap circuit 220 generates an output clock signal ckout1 based on the second clock signal CLK1 and the voltage Vin1, and outputs the output clock signal ckout1 to the gate of the second switch transistor 210 to turn on and turn off the second switch transistor 210. When the output clock signal ckout1 is high, the output signal ckout1 has a voltage of approximately Vb + Vin1.

[0036] Because the first clock signal CLK0 and the second clock signal CLK1 are complementary, the output clock signals ckout0 and ckout1 are alternately high. As a result, the first switch transistor 110 and the second switch transistor 210 are alternately turned on by the output clock signals ckout0 and ckout1 (i.e., the first switch transistor 110 and the second switch transistor 210 are time-interleaved).

[0037] Figure 3 is a timing diagram illustrating an example of the output clock signals ckout0 and ckout1 according to certain aspects. In this example, the rising edge 310 of the output clock signal ckout0 is delayed by a time delay to with respect to the falling edge 320 of the output clock signal ckout1, and the rising edge 330 of the output clock signal ckout1 is delayed by a time delay ti with respect to the falling edge 340 of the output clock signal ckout0, as shown. Figure 3 The time delays help to ensure that there is no overlap between the high phase of the output clock signal ckout0 and the high phase of the output clock signal ckout1. This avoids the first switch transistor 110 and the second switch transistor 210 being turned on at the same time, thereby reducing cross-talk between the first channel and the second channel. In some implementations, the time delays to and ti can be programmable.

[0038] As discussed above, the sampling capacitors 140 and 240 can be used in an ADC. In this regard, Figure 4 An example is shown in which the system includes a first ADC 410 and a second ADC 420. In this example, the first ADC 410 includes a first sampling capacitor 140 and a first digitizer 415, and the second ADC 420 includes a second sampling capacitor 240 and a second digitizer 425.

[0039] In this example, the first sampling capacitor 140 samples the voltage of the signal in the first signal path 112 when the first switch transistor 110 is turned on by the output clock signal ckoutO. When the first switch transistor 110 is turned off by the output clock signal ckoutO, the first sampling capacitor 140 holds the voltage of the sampled signal, and the first digitizer 415 converts the held voltage to a first digital signal (e.g., a first digital code). In this example, the falling edge of the output clock signal ckoutO determines the sampling instance of the first sampling capacitor 140. This is because the first switch transistor 110 is turned off at the falling edge of the output clock signal ckoutO. As a result, the first sampling capacitor 140 holds the voltage of the signal in the first signal path 112 at the time of the falling edge of the output clock signal ckoutO, and the first digitizer 415 converts the voltage to the first digital signal.

[0040] The second sampling capacitor 240 samples the voltage of the signal in the second signal path 212 when the second switch transistor 210 is turned on by the output clock signal ckoutl. When the second switch transistor 210 is turned off by the output clock signal ckoutl, the second sampling capacitor 240 holds the voltage of the sampled signal, and the digitizer 425 converts the held voltage to a second digital signal (e.g., a second digital code). In this example, the falling edge of the output clock signal ckoutl determines the sampling instance of the second sampling capacitor 240. This is because the second switch transistor 210 is turned off at the falling edge of the output clock signal ckoutl. As a result, the second sampling capacitor 240 holds the voltage of the signal in the second signal path 212 at the time of the falling edge of the output clock signal ckoutl, and the second digitizer 425 converts the voltage to the second digital signal.

[0041] Figure 5A An example implementation of the first bootstrap circuit 120 is shown, in accordance with certain aspects. Figure 5A The example implementation shown can also be used to implement the second bootstrap circuit 220.

[0042] In this example, the first bootstrap circuit 120 includes a boost capacitor 525, a first switch 520, a second switch 530, a third switch 535, and a fourth switch 540. Each of the switches 520, 530, 535, and 540 has a respective control input 522, 532, 538, and 542 for controlling the on / off state of the switch. Each of the switches 520, 530, 535, and 540 can be implemented with one or more respective transistors. As discussed further below, the on / off state of the switches 520, 530, 535, and 540 can be controlled by control signals (e.g., clock signals) generated from a clock signal CLK0.

[0043] In this example, the first switch 520 is coupled between a first terminal 524 of the boost capacitor 525 and a supply rail that provides a supply voltage Vdd. The second switch 530 is coupled between a second terminal 527 of the boost capacitor 525 and ground (also referred to as Vss). The third switch 535 is coupled between the second terminal 527 of the boost capacitor 525 and the input 122 of the first bootstrap circuit 120. A control input 538 of the third switch 535 is coupled to the output 126 of the first bootstrap circuit 120. It should be understood that the terminals of a capacitor can also be referred to as plates, electrodes, or another term.

[0044] The first bootstrap circuit 120 further includes a transistor 510 coupled between the first terminal 524 of the boost capacitor 525 and the output 126 of the first bootstrap circuit 120. In this example, a source of the transistor 510 is coupled to the first terminal 524 of the boost capacitor 525, and a drain of the transistor 510 is coupled to the output 126 of the first bootstrap circuit 120. In this example, a gate of the transistor 510 is coupled to the second terminal 527 of the boost capacitor 525. Figure 5A In the illustrated example, the transistor 510 is implemented with a p-type field effect transistor (PFET). However, it should be understood that the transistor 510 can be implemented with another type of transistor.

[0045] The first bootstrap circuit 120 further includes a transistor 515 coupled between the gate of the transistor 510 and the second terminal 527 of the boost capacitor 525. In this example, a drain of the transistor 515 is coupled to the gate of the transistor 510, and a source of the transistor 515 is coupled to the second terminal 527 of the boost capacitor 525.

[0046] The first bootstrap circuit 120 further includes a transistor 518 coupled between the gate of the transistor 510 and the supply rail. In this example, a source of the transistor 518 is coupled to the supply rail, a drain of the transistor 518 is coupled to the gate of the transistor 510, and a gate of the transistor 518 is coupled to the gate of the transistor 515.

[0047] In this example, the transistor 515 is implemented with an n-type field effect transistor (NFET), and the transistor 518 is implemented with a PFET. However, it should be understood that the present disclosure is not limited to this example. Figure 5A The first bootstrap circuit 120 further includes a voltage boost circuit 545 coupled to the control input 522 of the first switch 520. As discussed further below, the voltage boost circuit 545 is configured to generate a control signal ckboost for controlling the first switch 520.

[0048]

[0049] Figure 5B ​An example of a timing circuit 550 (e.g., a clock path) configured to receive a clock signal CLK0 and generate control signals phi and phib (e.g., clock signals) based on the clock signal CLK0 is shown. The control signals phi and phib are used to control the on / off states of switches 520, 530, 535, and 540, and the on / off states of transistors 515 and 518, as discussed further below. The timing circuit 550 includes a rising edge delay circuit 555, a first driver 562, and a second driver 565. Figure 5B In the example shown, each of drivers 562 and 565 is implemented using a corresponding inverter. However, it should be understood that this disclosure is not limited to this example.

[0050] As used herein, a “driver” is a circuit that receives a signal (e.g., a clock signal) and drives a load (e.g., another driver, one or more switches, or any combination thereof) based on that signal. A driver can be either inverting or non-inverting. For the example of a clock signal, a driver may also be referred to as a clock driver, a clock buffer, or another term.

[0051] The rising edge delay circuit 555 has an input 558 configured to receive a clock signal CLK0, and an output 560. The rising edge delay circuit 555 is configured to delay the rising edge of the clock signal CLK0 by a time delay (e.g., a programmable time delay). This is done to create a time delay t0 between the rising edge 310 of the output clock signal ckout0 discussed above and the falling edge 320 of the output clock signal ckout1, to prevent overlap between the high phase of the output clock signal ckout0 and the high phase of the output clock signal ckout1.

[0052] exist Figure 5B In the example shown, the rising edge delay circuit 555 includes a delay circuit 570, a NAND gate 575, and a driver 580 (e.g., an inverter). A first input of the NAND gate 575 is coupled to an input 558 of the rising edge delay circuit 555, and the delay circuit 570 is coupled between the input 558 of the rising edge delay circuit 555 and the second input of the NAND gate 575. An input of the driver 580 is coupled to the output of the NAND gate 575, and the output of the driver 580 is coupled to the output 560 of the rising edge delay circuit 555. The rising edge delay circuit 555 outputs a clock signal clkin based on a clock signal CLK0, wherein the rising edge of the clock signal clkin is delayed relative to the rising edge of the clock signal CLK0 by the delay circuit 570.

[0053] Figure 6 This is a timing diagram showing an example of clock signals CLK0 and clkin based on certain aspects. (e.g.)Figure 6 As shown, the rising edge delay circuit 555 delays the rising edge 610 of the clock signal CLK0 by a time delay t0, which is controlled by the delay of the delay circuit 570. This is because, when the rising edge 610 of the clock signal CLK0 is received at the input 558, the output 560 of the rising edge delay circuit 555 does not transition from low to high until both inputs of the NAND gate 575 are high. This occurs when the rising edge of the clock signal CLK0 delayed by the delay circuit 570 reaches the second input of the NAND gate 575.

[0054] In the example shown in Figure 6 , the falling edge 620 of the clock signal CLK0 is not delayed (for simplicity, assume that the delay in the NAND gate 575 and driver 580 is negligible compared to the delay of the delay circuit 570). This is because, when the falling edge 620 of the clock signal CLK0 is received at the input 558, the output 560 of the rising edge delay circuit 555 transitions from high to low when the falling edge 620 of the clock signal CLK0 reaches the first input of the NAND gate 575, regardless of the logic state at the second input of the NAND gate 575. Although for simplicity, the delay in the NAND gate 575 and driver 580 is assumed to be negligible in the example shown in Figure 6 , it should be understood that this is not necessarily the case.

[0055] Returning to Figure 5B , the input of the first driver 562 is coupled to the output 560 of the rising edge delay circuit 555, and the input of the second driver 565 is coupled to the output of the first driver 562. In this example, the control signals phi and phib are provided at the outputs of the first driver 562 and the second driver 565, respectively. The control signals phi and phib are complementary in that, in this example, the second driver 565 inverts the control signal phi to generate the control signal phib. As Figure 5A shown, the control signal phi is input to the control inputs 532 and 542 of the second switch 530 and the fourth switch 540, and the control signal phib is input to the gates of the transistors 515 and 518. In this example, the second switch 530 and the fourth switch 540 are configured to turn on when the control signal phi is high (e.g., Vdd) and turn off when the control signal phi is low (e.g., zero volts).

[0056] In certain aspects, the voltage boosting circuit 545 is configured to boost the voltage of the control signal phi to generate a control signal ckboost that is input to the control input 522 of the first switch 520. For example, the voltage boosting circuit 545 can boost the voltage of the control signal phi by the supply voltage Vdd to generate the control signal ckboost. In this example, the control signal phi can have a high voltage of approximately Vdd and a low voltage of approximately zero volts, and the control signal ckboost can have a high voltage of approximately 2Vdd and a low voltage of approximately Vdd. However, it should be understood that the present disclosure is not limited to this example, and the voltage boosting circuit 545 can boost the voltage of the control signal phi by a different voltage to generate the control signal ckboost. In this example, the first switch 520 is configured to turn on when the control signal ckboost is high (e.g., 2Vdd) and to turn off when the control signal ckboost is low (e.g., Vdd).

[0057] An example operation of the first bootstrap circuit 120 will now be discussed in accordance with certain aspects. During a first phase of the clock signal CLK0, the control signal phi is high (e.g., approximately Vdd), the control signal ckboost is high (e.g., approximately 2Vdd), and the control signal phib is low. This causes the first switch 520, the second switch 530, and the fourth switch 540 to turn on. As a result, the first terminal 524 of the boost capacitor 525 is coupled to the supply rail through the first switch 520, and the second terminal 527 of the boost capacitor 525 is coupled to ground through the second switch 530. This causes the first terminal 524 of the boost capacitor 525 to charge to the supply voltage Vdd. In addition, the gate of the switch transistor 110 is coupled to ground through the fourth switch 540, which causes the switch transistor 110 to turn off. The control input 538 of the third switch 535 is also coupled to ground through the fourth switch 540, which causes the third switch 535 to turn off.

[0058] As discussed above, the control signal phib is low during the first phase. This causes the transistor 515 to turn off and the transistor 518 to turn on. As a result, the gate of the transistor 510 is coupled to the supply rail through the transistor 518. This turns off the transistor 510, which is implemented with a PFET in this example.

[0059] Thus, during the first phase, the boost capacitor 525 is charged to the supply voltage Vdd and the switch transistor 110 is turned off. In addition, because the output 126 of the first bootstrap circuit 120 is coupled to ground through the fourth switch 540, the output clock signal ckout0 is approximately equal to zero volts during the first phase.

[0060] During the second phase of the clock signal CLK0 (which is after the first phase), the control signal phi transitions from high to low, the control signal ckboost transitions from high to low, and the control signal phib transitions from low to high. This causes the first switch 520, the second switch 530, and the fourth switch 540 to turn off. As a result, the first terminal 524 of the boost capacitor 525 is decoupled from the supply rail, and the second terminal 527 of the boost capacitor 525 is decoupled from ground. In addition, the output terminal 126 of the first bootstrap circuit 120 is decoupled from ground.

[0061] As discussed above, the control signal phib transitions from low to high during the second phase. This causes the transistor 515 to turn on, and the transistor 518 to turn off. As a result, the gate of the transistor 510 is coupled to the second terminal 527 of the boost capacitor 525 through the transistor 515. The source of the transistor 510 is coupled to the first terminal 524 of the boost capacitor 525. Thus, the source-to-gate voltage of the transistor 510 is approximately equal to the voltage across the boost capacitor 525. Since the boost capacitor 525 was charged to Vdd during the first phase, the source-to-gate voltage of the transistor 510 is approximately equal to Vdd. This turns on the transistor 510, assuming Vdd is greater than the threshold voltage of the transistor 510. As a result, the first terminal 524 of the boost capacitor 525 is coupled to the output terminal 126 through the transistor 510.

[0062] The first terminal 524 of the boost capacitor 525 is also coupled to the control input 538 of the third switch 535 through the transistor 510, which turns on the third switch 535. As a result, the second terminal 527 of the boost capacitor 525 is coupled to the input terminal 122 of the first bootstrap circuit 120 through the third switch 535. As a result, the input voltage Vin0 at the input terminal 122 is applied to the second terminal 527 of the boost capacitor 525 through the third switch 535. This raises the voltage at the first terminal 524 of the boost capacitor 525 to Vdd + Vin0. Since the first terminal 524 of the boost capacitor 525 is coupled to the output terminal 126 of the first bootstrap circuit 120, the voltage of the output clock signal ckout0 at the output terminal 126 during the second phase is approximately equal to Vdd + Vin0, which turns on the switch transistor 115.

[0063] In this example, the rising edge of the output clock ckout0 is delayed by the delay circuit 570 in the timing circuit 550. This is because the delay circuit 570 delays the rising edge of the clock signal clkin by the delay of the delay circuit 570. This delays the transition of the control signal phi from high to low, since the control signal phi is the inverse of the clock signal clkin, and delays the transition of the control signal phib from low to high, which delays the rising edge of the output clock signal ckout0.

[0064] In this example, the falling edge of the output clock signal ckout0 is determined at least in part by the timing when the fourth switch 540 is turned on by the control signal phi. This is because turning on the fourth switch 540 couples the output 126 of the first bootstrap circuit 120 to ground, causing the output clock signal ckout0 to transition from high to low (e.g., ground). As discussed above, the sampling instance of the sampling capacitor 140 is determined by the falling edge of the output clock signal ckout0. Therefore, the timing of the falling edge of the output clock signal ckout0 (which is controlled by the control signal phi) affects the sampling instance of the sampling capacitor 140.

[0065] Figure 5B A drawback of the timing circuit 550 shown is that the input clock signal CLK0 needs to be propagated through three gates in the timing circuit 550 (i.e., NAND gate 575 and drivers 580 and 562) to provide the control signal phi, which controls the falling edge of the output clock signal ckout0. These three gates introduce jitter / skew into the control signal phi, and therefore into the falling edge of the output clock signal ckout0, which degrades performance. Therefore, the quality of the control signal phi needs to be improved to enhance the timing of the falling edge of the output clock signal ckout0.

[0066] and Figure 5B Compared to the timing circuit 550 in the present disclosure, aspects thereof reduce jitter / skew in the falling edge of the output clock signal ckout0 by reducing the number of gates in the clock path of the control signal phi, as discussed further below. As used herein, a clock path is the path through which a clock signal propagates. A clock path may include one or more drivers, one or more delay circuits, or any combination thereof.

[0067] Figure 7A An example of a first bootstrap circuit 120 according to various aspects of this disclosure is shown. In this example, the first bootstrap circuit 120 includes a transistor 710, wherein transistor 710 and transistor 515 are coupled in series between the gate of transistor 510 and the second terminal 527 of boost capacitor 525. As used herein, transistors are series coupled when their channels are in series. The channel of the transistor is between the source and drain of the transistor, wherein the conductance of the channel is controlled by a voltage applied to the gate of the transistor.

[0068] Transistor 710 is used to delay the rising edge of the output clock signal ckout0, as discussed further below. Figure 7A In the example shown, transistor 710 is implemented using an NFET. However, it should be understood that in other specific implementations, transistor 710 may be implemented using another type of transistor.

[0069] althoughFigure 7A An example is shown in which transistor 710 is on top of transistor 515, but it should be understood that in other implementations, the positions of transistors 710 and 515 can be swapped, such that transistor 515 is on top of transistor 710. In this regard, Figure 7B An example is shown in which transistor 515 is on top of transistor 710. In Figure 7A In Figure 7B transistors 710 and 515 are coupled in series between the gate of transistor 510 and the second terminal 527 of boost capacitor 525.

[0070] Figure 7C An example of a timing circuit 720 (e.g., a clock path) for generating control signals phi and phib is shown. Timing circuit 720 includes a first driver 725, a second driver 730, a delay circuit 735, and a third driver 740. An input of first driver 725 is coupled to an input 722 of timing circuit 720 and is configured to receive a clock signal CLK0. An input of second driver 730 is coupled to an output of first driver 725, an input of delay circuit 735 is coupled to an output of second driver 730, and an input of third driver 740 is coupled to an output of delay circuit 735. In Figure 7C In the example shown, each of drivers 725, 730, and 740 is implemented with a respective inverter. However, it should be understood that the present disclosure is not limited to this example.

[0071] In this example, control signal phi (which controls the falling edge of output clock signal ckout0) is taken from a node 727 at an output of first driver 725, and control signal phib is taken from a node 732 at an output of second driver 730. In this example, node 727 is coupled to Figure 7A and Figure 7B control inputs 532 and 542 of second and fourth switches 530 and 540 to provide control signals phi to control inputs 532 and 542, and node 732 is coupled to gates of transistors 515 and 518 to provide control signal phib to gates of transistors 515 and 518.

[0072] In this example, clock signal CLK0 propagates through one gate (i.e., first driver 725) to generate control signal phi, rather than Figure 5B three gates as shown in timing circuit 550 in This significantly reduces jitter / skew introduced into control signal phi, and thus significantly reduces jitter / skew in the falling edge of output clock signal ckout0 (which is controlled by the turning on of fourth switch 540 by control signal phi). This significantly reduces jitter / skew introduced into control signal phi, and thus significantly reduces jitter / skew in the falling edge of output clock signal ckout0 (which is controlled by the turning on of fourth switch 540 by control signal phi).

[0073] In this example, the clock signal CLK0 propagates to the delay circuit 735, where the clock signal CLK0 is delayed by the delay circuit 735 and inverted by the third driver 740 to generate the control signal phib_delay at the node 737. The control signal phib_delay is input to the gate of the transistor 710 (i.e., the gate of the transistor 710 is coupled to the node 737). The transistor 710 delays the rising edge of the output clock signal ckout0 based on the delay in the control signal phib_delay, which is controlled by the delay circuit 735. This is because the transistor 710 is coupled in series with the transistor 515. Thus, the transistor 710 does not allow the transistor 515 to couple the gate of the transistor 510 to the second terminal 527 of the boost capacitor 525 until the transistor 710 is turned on by the control signal phib_delay, which is delayed by the delay circuit 735. Thus, in this example, the delay circuit 735 and the transistor 710 perform the function of delaying the rising edge of the output clock signal ckout, which is performed by the delay circuit 570 and the NAND gate 575 in Figure 5B .

[0074] As shown in Figure 7C , the delay circuit 735, as well as the drivers 730 and 740, are located after the control signal phi in the timing circuit 720 and thus do not introduce jitter / skew into the control signal phi, which controls the falling edge of the output clock signal ckout0. In contrast, in the timing circuit 550 in Figure 5B , the NAND gate 575, as well as the drivers 580 and 562, are located before the control signal phi and thus introduce jitter / skew into the control signal phi.

[0075] It should be appreciated that the timing circuit 720 is not limited to the example shown in Figure 7C . In general, the timing circuit 720 (e.g., clock path) can include a delay circuit 735 and one or more drivers (e.g., one or more inverters) coupled in series, where the node 727, which provides the control signal phi for the fourth switch 540, is located before the delay circuit 735, and the node 737, which provides the control signal phi_delay for the transistor 710, is located after the delay circuit 735.

[0076] Figure 8Exemplary implementations of switches 520, 530, 535, and 540 are shown, in accordance with certain aspects. In this example, first switch 520 includes a transistor 815 (e.g., NFET), where the drain of transistor 815 is coupled to the supply rail, the gate of transistor 815 is coupled to voltage boost circuit 545, and the source of transistor 815 is coupled to a first terminal 524 of boost capacitor 525. Second switch 530 includes a transistor 820 (e.g., NFET), where the drain of transistor 820 is coupled to a second terminal 527 of boost capacitor 525, the gate of transistor 820 is coupled to a control input 532 of second switch 530 (and thus receives control signal phi), and the source of transistor 820 is coupled to ground. Third switch 535 includes a transistor 825 (e.g., NFET), where the source of transistor 825 is coupled to the second terminal 527 of boost capacitor 525, the gate of transistor 825 is coupled to the output 126 of first bootstrap circuit 120, and the drain of transistor 825 is coupled to the input 122 of first bootstrap circuit 120.

[0077] In this example, fourth switch 540 includes a first transistor 830 (e.g., first NFET), a second transistor 835 (e.g., second NFET), and a third transistor 840 (e.g., PFET). The gate of first transistor 830 is coupled to a control input 542 of fourth switch 540 (and thus receives control signal phi), and the source of first transistor 830 is coupled to ground. The drain of second transistor 835 is coupled to the output 126 of first bootstrap circuit 120, the gate of second transistor 835 is coupled to the supply rail, the source of second transistor 835 is coupled to the drain of first transistor 830. The source of third transistor 840 is coupled to the supply rail, the gate of third transistor 840 is coupled to the control input 542 of fourth switch 540 (and thus receives control signal phi), and the drain of third transistor 840 is coupled to the source of second transistor 835.

[0078] In operation, when control signal phi is high, first transistor 830 is turned on and third transistor 840 is turned off. As a result, first transistor 830 couples the source of second transistor 835 to ground. Because the gate of second transistor 835 is coupled to the supply rail, the gate-source voltage of second transistor 835 is approximately equal to Vdd, which turns on second transistor 835. Thus, both first transistor 830 and second transistor 835 are turned on, and the output 126 of first bootstrap circuit 120 is coupled to ground through first transistor 830 and second transistor 835. Accordingly, when control signal phi is high (e.g., Vdd), fourth switch 540 couples the output 126 of first bootstrap circuit 120 to ground.

[0079] When the control signal phi is low, the first transistor 830 is turned off, and the third transistor 840 is turned on. As a result, the third transistor 840 couples the source of the second transistor 835 to the supply rail. Because the gate of the second transistor 835 is coupled to the supply rail, the gate-source voltage of the second transistor 835 is approximately zero volts, which turns off the second transistor 835. As a result, both the first transistor 830 and the second transistor 835 are turned off, and the output 126 of the first bootstrap circuit 120 is decoupled from ground. Thus, when the control signal phi is low, the fourth switch 540 decouples the output 126 of the first bootstrap circuit 120 from ground.

[0080] It should be appreciated that the fourth switch 540 is not limited to the exemplary implementation shown. For example, the fourth switch 540 can be implemented with other arrangements of transistors, or can be implemented with a single transistor. Figure 8

[0081] Figure 8 An exemplary implementation of a voltage boost circuit 545 according to certain aspects is also shown. In this example, the voltage boost circuit 545 includes a first transistor 850 (e.g., a first NFET), a second transistor 855 (e.g., a second NFET), a first capacitor 860, and a second capacitor 870. In this example, the drain of the first transistor 850 is coupled to the supply rail, the gate of the first transistor 850 is coupled to the source of the second transistor 855, and the source of the first transistor 850 is coupled to a first terminal 862 of the first capacitor 860. A second terminal 864 of the first capacitor 860 receives a control signal phi delay, which is provided at the output of the delay circuit 735. A control signal ckboost is provided at the first terminal 862 of the first capacitor 860, as discussed further below.

[0082] The drain of the second transistor 855 is coupled to the supply rail, the gate of the second transistor 855 is coupled to the source of the first transistor 850, and the source of the second transistor 855 is coupled to a first terminal 872 of the second capacitor 870. A second terminal 874 of the second capacitor 870 receives a control signal phi b.

[0083] Exemplary operation of the voltage boost circuit 545 will now be described according to certain aspects. In the discussion below, it is assumed that the high voltage of the control signal phi b is Vdd, and it is assumed that the high voltage of the control signal phi delay is Vdd. However, it should be appreciated that the present disclosure is not limited to this example.

[0084] ​When the control signal phi delay is low and the control signal phi b is high, the first transistor 850 is turned on and the second transistor 855 is turned off. In this way, the first terminal 862 of the first capacitor 860 is charged to the supply voltage Vdd through the first transistor 850. Since the control signal ckboost is provided at the first terminal 862 of the first capacitor 860, the control signal ckboost is approximately Vdd. During this time, the first terminal 872 of the second capacitor 870 is approximately equal to 2Vdd, assuming that the first terminal 872 of the second capacitor 870 was previously charged to Vdd when the control signal phi b was previously low.

[0085] When the control signal phi delay is high and the control signal phi b is low, the first transistor 850 is turned off and the second transistor 855 is turned on. In this case, the high voltage Vdd of the control signal phi delay is applied to the second terminal 864 of the first capacitor 860. This boosts the voltage at the first terminal 862 of the first capacitor 860 to a boosted voltage of approximately 2Vdd. Since the control signal ckboost is provided at the first terminal 862 of the first capacitor 860, the control signal ckboost is boosted to approximately 2Vdd. During this time, the first terminal 872 of the second capacitor 870 is charged to Vdd through the second transistor 855.

[0086] Thus, in this example, the voltage boosting circuit 545 raises the voltage of the control signal phi delay (e.g., the voltage at node 727) by Vdd to generate the control signal ckboost, which has a voltage of approximately 2Vdd when the control signal ckboost is high. The boosted voltage is needed to keep the transistor 815 (e.g., NFET) on to charge the first terminal 524 of the boost capacitor 525 to Vdd through the transistor 815. This is because the gate-source voltage of the transistor 815 needs to be greater than the threshold voltage of the transistor 815 to keep the transistor 815 on, and the source of the transistor 815 is coupled to the first terminal 524 of the boost capacitor 525. Thus, when the voltage at the first terminal 524 of the boost capacitor 525 approaches Vdd (and thus the voltage at the source of the transistor 815 approaches Vdd), the voltage at the gate of the transistor 815 needs to be greater than Vdd by the threshold voltage or more to keep the transistor 815 on.

[0087] In this example, the control signal ckboost has a low voltage of approximately Vdd. However, after the first terminal 524 of the boost capacitor 525 is charged to approximately Vdd, the low voltage of Vdd does not turn on transistor 510. This is because the gate-source voltage of transistor 510 is approximately zero volts, which keeps transistor 510 off. When the first terminal of the boost capacitor 525 is boosted to Vdd + Vin0, the low voltage of Vdd also does not turn on transistor 510. In this case, the source voltage of transistor 815 is higher than the gate voltage of the transistor, which keeps transistor 815 off.

[0088] exist Figure 8 In the example shown, the bootstrap circuit 120 also includes a transistor 880, wherein the drain of transistor 880 is coupled to the gate of transistor 510, the source of transistor 880 is coupled to the second terminal 527 of boost capacitor 525, and the gate of transistor 880 is coupled to the output terminal 126 of bootstrap circuit 120. Transistor 880 can be an NFET (such as...). Figure 8 (as shown in the example) or another type of transistor can be used to achieve this.

[0089] When the voltage at output terminal 126 is approximately equal to Vdd + Vin0 during the second phase, transistor 880 is turned on, and the gate of transistor 510 is coupled to the second terminal 527 of boost capacitor 525 through transistor 880. When the voltage at output terminal 126 is approximately equal to zero volts during the first phase, transistor 880 is turned off.

[0090] In this example, transistor 880 assists transistors 710 and 515 in coupling the gate of transistor 510 to the second terminal 527 of boost capacitor 525 during the second phase. When the input voltage Vin0 swings high, transistor 880 is able to maintain the gate of transistor 510 coupled to the second terminal 527 of boost capacitor 525 because transistor 880 is turned on by the boost voltage Vdd+Vin0. It should be understood that transistor 880 may be omitted in some specific implementations.

[0091] Figure 9A Another example of a bootstrap circuit 120 according to various aspects of this disclosure is shown. In this example, [details omitted]. Figure 8 The transistor 710 is shown, and the drain of transistor 515 is coupled to the gate of transistor 510. Furthermore, in this example, the gates of transistors 515 and 518 receive the control signal phib_0, and the second terminal 864 of the first capacitor 860 receives the control signal phi.

[0092] Figure 9B It shows the method for generating Figure 9AThe example shown is a timing circuit 910 for control signals phi, phib, and phib_0. In this example, the timing circuit 910 includes a clock path 915 and logic gates 940. Figure 9A As shown in the example, clock path 915 may include a first driver 920, a second driver 925, and a delay circuit 930 coupled in series. Figure 9A In the example shown, the input of the first driver 920 is coupled to the input 912 of the timing circuit 910 to receive the clock signal CLK0, the input of the second driver 925 is coupled to the output of the first driver 920, and the input of the delay circuit 930 is coupled to the output of the second driver 925. Figure 9B In the example shown, each of drivers 920 and 925 is implemented using a corresponding inverter. However, it should be understood that drivers 920 and 925 are not limited to this example.

[0093] Logic gate 940 has a first input terminal 942, a second input terminal 944, and an output terminal 946. Figure 9B In the example shown, logic gate 940 includes a NAND gate. However, it should be understood that logic gate 940 is not limited to this example. In this example, the first input 942 of logic gate 940 is coupled to input 912 of timing circuit 910 and is configured to receive clock signal CLK0. Clock path 915 is coupled between input 912 of timing circuit 910 and the second input 944 of logic gate 940.

[0094] In this example, the control signal phi is provided at node 922 by the output of the first driver 920, and the control signal phib is provided at node 927 by the output of the second driver 925. Therefore, node 922 is coupled to the control input 532 of the second switch 530 and the control input 542 of the fourth switch 540 to provide the control signal phi. Figure 9B In the example shown, nodes 922 and 927 are located before delay circuit 930 in clock path 915, and delay circuit 930 is located between node 927 and the second input 944 of logic gate 940. Furthermore, in this example, a control signal phib_0 is provided at the output 946 of logic gate 940 (e.g., a NAND gate). Therefore, output 946 is coupled to the gates of transistors 515 and 518 to provide control signal phib_0.

[0095] In this example, the control signal phi controls the falling edge of the output clock signal ckoutO. This is because when the control signal phi transitions from low to high, the control signal phi turns on the fourth switch 540 and couples the output 126 of the first bootstrap circuit 120 to ground. As discussed above, the control signal phi is provided by the output of the first driver 920 at node 922 in the timing circuit 910. Thus, in this example, the clock signal CLK0 propagates through one gate (i.e., the first driver 920) to generate the clock signal phi, rather than Figure 5B three gates as shown in FIG. 6. This significantly reduces the jitter / skew introduced into the control signal phi, and thus the falling edge of the output clock signal ckoutO (which is controlled by the control signal phi).

[0096] In this example, the delay circuit 930 and the logic gate 940 (e.g., a NAND gate) are configured to generate the control signal phib_0 as shown in FIG. 7. The control signal phib_0 is input to the gates of the transistors 515 and 518 to control the rising edge of the output clock signal ckoutO. Since the rising edge of the control signal phib_0 is delayed by the delay circuit 930, the rising edge of the output clock signal ckoutO is also delayed by the delay circuit 930. Figure 9A

[0097] As shown in FIGS. 6 and 7, the delay circuit 930, the second driver 925, and the logic gate 940 are located outside of the clock path between the input 912 of the timing circuit 910 and the control input 542 of the fourth switch 540. As a result, the delay circuit 930, the second driver 925, and the logic gate 940 (e.g., a NAND gate) do not affect the falling edge of the output clock signal ckoutO, which reduces the jitter / skew in the falling edge of the clock signal ckoutO. Figure 9A Figure 9B In certain aspects, the system 205 can be used to digitize a signal from a receiver in a wireless device. In this regard,

[0098] In certain aspects, the system 205 can be used to digitize a signal from a receiver in a wireless device. In this regard, Figure 10 ​​An example of a receiver 1010 coupled to an input of a buffer 130 is shown. In this example, the receiver 1010 includes a mixer 1020, an amplifier 1030 (e.g., an impedance-mismatch amplifier), and a filter 1040. The mixer 1020 has an input 1022 and an output 1024. The mixer 1020 is configured to receive, at the input 1022, a radio frequency (RF) or intermediate frequency (IF) signal, to mix the RF signal or the IF signal with a local oscillator (LO) signal to down-convert the RF signal or the IF signal to a baseband signal, and to output the baseband signal at the output 1024. The RF signal can be from an antenna (not shown) and can be processed by one or more front-end components (e.g., a low noise amplifier) before being input to the mixer 1020. For an example of an IF signal, the IF signal can be from a pre-mixer (not shown) that down-converts the RF signal to the IF signal.

[0099] The amplifier 1030 has an input 1032 coupled to the output 1024 of the mixer 1020, and an output 1034. The amplifier 1030 is configured to amplify the baseband signal from the mixer 1020, and to output the amplified baseband signal at the output 1034. The filter 1040 is coupled between the output 1034 of the amplifier 1030 and the input of the buffer 130. For example, the filter 1040 can be a low-pass filter (e.g., a low-pass resistor-capacitor (RC) filter) configured to filter out out-of-band signals, and to output the filtered baseband signal to the buffer 130. The switch transistors 110 and 210, and the ADCs 410 and 420 can then sample and digitize the baseband signal to a digital baseband signal. The digital baseband signal can be processed by a baseband processor (not shown) to recover data and / or control information from the baseband signal.

[0100] Although Figure 2 , Figure 4 and Figure 10 a system 205 with two channels is shown, it should be understood that in some implementations, the system 205 can include more than two channels (i.e., in addition to the channels shown in Figure 2 , Figure 4 and Figure 10 . Generally speaking, aspects of the present disclosure can be used in time-interleaved systems with a number of channels that can equal two or be greater than two.

[0101] Implementation examples are described in the following numbered clauses:

[0102] 1. A system comprising:

[0103] a bootstrap circuit having an input and an output, the bootstrap circuit comprising:

[0104] a boost capacitor having a first terminal and a second terminal;

[0105] a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit;

[0106] a second transistor; and

[0107] a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor; and

[0108] a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

[0109] 2. The system of clause 1, wherein the bootstrap circuit further comprises a switch coupled between the output of the bootstrap circuit and ground.

[0110] 3. The system of clause 2, wherein the bootstrap circuit further comprises a clock path comprising a delay circuit and one or more drivers coupled in series, wherein:

[0111] a control input of the switch is coupled to a first node on the clock path before the delay circuit; and

[0112] a gate of the third transistor is coupled to a second node on the clock path after the delay circuit.

[0113] 4. The system of clause 3, wherein a gate of the second transistor is coupled to a third node on the clock path before the delay circuit.

[0114] 5. The system of clause 4, wherein one of the one or more drivers is between the second node and the third node.

[0115] 6. The system of clause 4 or 5, wherein:

[0116] the bootstrap circuit further comprises a fourth transistor coupled between the gate of the first transistor and a supply rail; and

[0117] a gate of the fourth transistor is coupled to the third node on the clock path.

[0118] 7. The system of any of clauses 3-6, wherein the delay circuit has a programmable delay.

[0119] 8. The system of any of clauses 3-7, wherein each driver of the one or more drivers comprises a respective inverter.

[0120] 9. The system of any of clauses 1-8, wherein:

[0121] the bootstrap circuit further comprises a fourth transistor coupled between the gate of the first transistor and a supply rail;

[0122] the second transistor comprises a first n-type field effect transistor (NFET);

[0123] the third transistor comprises a second NFET; and

[0124] the fourth transistor comprises a p-type field effect transistor (PFET).

[0125] 10. The system of clause 1, wherein the bootstrap circuit further comprises:

[0126] a first switch coupled between the first terminal of the boost capacitor and a supply rail;

[0127] a second switch coupled between the second terminal of the boost capacitor and ground;

[0128] a third switch coupled between the second terminal of the boost capacitor and the input of the bootstrap circuit; and

[0129] a fourth switch coupled between the output of the bootstrap circuit and the ground.

[0130] 11. The system of clause 10, wherein the bootstrap circuit further comprises a clock path comprising a delay circuit and one or more drivers coupled in series,

[0131] wherein:

[0132] a control input of the second switch and a control input of the fourth switch

[0133] are coupled to a first node on the clock path before the delay circuit; and

[0134] the gate of the third transistor is coupled to a second node on the clock path after the delay circuit.

[0135] the gate of the third transistor is coupled to a second node on the clock path after the delay circuit.

[0136] the gate of the third transistor is coupled to a second node on the clock path after the delay circuit.

[0137] 12. The system of clause 11, wherein a gate of the second transistor is coupled to a third node on the clock path before the delay circuit.

[0138] 13. The system of clause 12, wherein:

[0139] the bootstrap circuit further comprises a fourth transistor coupled between the gate of the first transistor and the supply rail; and

[0140] a gate of the fourth transistor is coupled to the third node on the clock path.

[0141] 14. The system of clause 13, further comprising a fifth transistor coupled between the gate of the first transistor and the second terminal of the boost capacitor, wherein a gate of the fifth transistor is coupled to the output of the bootstrap circuit.

[0142] 15. The system of any one of clauses 11-14, wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input of the first switch, wherein the voltage boost circuit is configured to boost a voltage at the first node on the clock path to generate a boosted control signal and output the boosted control signal to the control input of the first switch.

[0143] 16. The system of any one of clauses 10-15, wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input of the first switch.

[0144] 17. The system of any one of clauses 10-16, wherein a control input of the third switch is coupled to the output of the bootstrap circuit.

[0145] 18. The system of any one of clauses 1-17, further comprising:

[0146] a buffer; and

[0147] a sampling capacitor, wherein the switching transistor is coupled between an output of the buffer and the sampling capacitor.

[0148] 19. The system of clause 18, further comprising a receiver coupled to an input of the buffer.

[0149] 20. The system of clause 19, wherein the receiver comprises a mixer.

[0150] 21. A system, comprising:

[0151] bootstrap circuit having an input and an output, the bootstrap

[0152] circuit comprises:

[0153] a boost capacitor having a first terminal and a second terminal;

[0154] a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit;

[0155] a second transistor coupled between a gate of the first transistor and the second terminal of the boost capacitor;

[0156] a first switch coupled between the output of the bootstrap circuit and ground; and

[0157] a timing circuit comprising:

[0158] a logic gate having a first input, a second input, and an output, wherein the first input of the logic gate is coupled to an input of the timing circuit, and the output of the logic gate is coupled to a gate of the second transistor; and a clock path coupled between the input of the timing circuit and the second input of the logic gate, wherein a control input of the first switch is coupled to the clock path;

[0159] and

[0160] a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

[0161] 22. The system of clause 21, wherein:

[0162] the bootstrap circuit further comprises a third transistor coupled between the gate of the first transistor and a supply rail; and

[0163] a gate of the third transistor is coupled to the output of the logic gate.

[0164] 23. The system of clause 22, wherein:

[0165] the second transistor comprises an n-type field effect transistor (NFET); and

[0166] the third transistor comprises a p-type field effect transistor (PFET).

[0167] 24. The system of any of Clauses 21-23, wherein the logic gate comprises a NAND gate.

[0168] 25. The system of any of Clauses 21-24, wherein the clock path comprises a delay circuit and one or more drivers coupled in series, and the control input of the first switch is coupled to a node on the clock path before the delay circuit.

[0169] 26. The system of any of Clauses 21-25, wherein the bootstrap circuit further comprises:

[0170] a second switch coupled between the first terminal of the boost capacitor and a supply rail;

[0171] a third switch coupled between the second terminal of the boost capacitor and the ground; and

[0172] a fourth switch coupled between the second terminal of the boost capacitor and the input of the bootstrap circuit.

[0173] 27. The system of Clause 26, wherein the clock path comprises a delay circuit and one or more drivers coupled in series, the control input of the first switch and a control input of the third switch are coupled to a node on the clock path before the delay circuit.

[0174] 28. The system of Clause 27, wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input of the second switch, and wherein the voltage boost circuit is configured to boost a voltage at the node on the clock path to generate a boosted control signal, and output the boosted control signal to the control input of the second switch.

[0175] 29. The system of any of Clauses 26-28, wherein a control input of the fourth switch is coupled to the output of the bootstrap circuit.

[0176] 30. The system of any of Clauses 26-39, wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input of the second switch.

[0177] 31. The system of Clause 22 or 23, further comprising a fourth transistor coupled between the gate of the first transistor and the second terminal of the boost capacitor, wherein a gate of the fourth transistor is coupled to the output of the bootstrap circuit.

[0178] It should be appreciated that the present disclosure is not limited to the terminology used in the above description of aspects of the present disclosure. For example, a buffer can also be referred to as a driver, an amplifier, or another term. A switch transistor can also be referred to as a switch, a transistor, a bootstrapped switch, a switch that is bootstrapped, a sampling switch (e.g., in the context of analog-to-digital conversion), or another term. A bootstrap circuit can also be referred to as a bootstrap switch, a voltage boosting circuit, or another term. In general, a bootstrap circuit encompasses any circuit configured to drive a gate of a switch transistor with a boosted voltage that tracks a voltage of a signal in a signal path (e.g., a voltage at a terminal (e.g., a source) of the switch transistor). It should also be appreciated that a bootstrap circuit and a switch transistor can also be collectively referred to as a bootstrap switch.

[0179] It should be appreciated that a transistor can be physically implemented on a chip using two or more transistors arranged in parallel, with the gates of the two or more transistors coupled together.

[0180] Within the present disclosure, the word“exemplary” is used to mean“serving as an example, instance, or illustration.” Any implementation or aspect described herein as“exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term“aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term“coupled” is used herein to refer to the direct or indirect coupling between two structures.

[0181] Any reference to an element herein using a designation such as“first,”“second,” and so forth does not generally limit the quantity or order for or between elements. Rather, these designations are used herein as a convenient method of distinguishing between or among two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

[0182] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Modifications to various implementations of the disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A bootstrap circuit, having an input terminal and an output terminal, comprising: A boost capacitor having a first terminal and a second terminal; A first transistor is coupled between the first terminal of the boost capacitor and the output terminal of the bootstrap circuit; The second transistor; and A third transistor, wherein the second transistor and the third transistor are coupled in series between the gate of the first transistor and the second terminal of the boost capacitor; and A switching transistor, wherein the gate of the switching transistor is coupled to the output of the bootstrap circuit, and the terminal of the switching transistor is coupled to the input of the bootstrap circuit.

2. The system of claim 1, wherein the bootstrap circuit further includes a switch coupled between the output terminal of the bootstrap circuit and ground.

3. The system of claim 2, wherein the bootstrap circuit further comprises a clock path, the clock path comprising a series-coupled delay circuit and one or more drivers, wherein: The control input terminal of the switch is coupled to a first node on the clock path located before the delay circuit; and The gate of the third transistor is coupled to a second node on the clock path located after the delay circuit.

4. The system of claim 3, wherein the gate of the second transistor is coupled to a third node on the clock path preceding the delay circuit.

5. The system of claim 4, wherein one of the one or more drivers is located between the second node and the third node.

6. The system according to claim 4, wherein: The bootstrap circuit further includes a fourth transistor coupled between the gate of the first transistor and the power supply rail; and The gate of the fourth transistor is coupled to the third node on the clock path.

7. The system of claim 3, wherein the delay circuit has a programmable delay.

8. The system of claim 3, wherein each of the one or more drivers includes a corresponding inverter.

9. The system according to claim 1, wherein: The bootstrap circuit further includes a fourth transistor coupled between the gate of the first transistor and the power supply rail; The second transistor includes a first n-type field-effect transistor (NFET); The third transistor includes a second NFET; and The fourth transistor includes a p-type field-effect transistor (PFET).

10. The system of claim 1, wherein the bootstrap circuit further comprises: A first switch is coupled between the first terminal of the boost capacitor and the power supply rail. A second switch is coupled between the second terminal of the boost capacitor and ground; A third switch is coupled between the second terminal of the boost capacitor and the input terminal of the bootstrap circuit; and A fourth switch is coupled between the output terminal of the bootstrap circuit and the ground.

11. The system of claim 10, wherein the bootstrap circuit further comprises a clock path, the clock path comprising a series-coupled delay circuit and one or more drivers, wherein: The control input terminals of the second switch and the fourth switch are coupled to the first node on the clock path located before the delay circuit; and The gate of the third transistor is coupled to a second node on the clock path located after the delay circuit.

12. The system of claim 11, wherein the gate of the second transistor is coupled to a third node on the clock path preceding the delay circuit.

13. The system according to claim 12, wherein: The bootstrap circuit further includes a fourth transistor coupled between the gate of the first transistor and the power supply rail; and The gate of the fourth transistor is coupled to the third node on the clock path.

14. The system of claim 13, further comprising a fifth transistor coupled between the gate of the first transistor and the second terminal of the boost capacitor, wherein the gate of the fifth transistor is coupled to the output of the bootstrap circuit.

15. The system of claim 11, wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input terminal of the first switch, wherein the voltage boost circuit is configured to boost the voltage at the first node on the clock path to generate a boost control signal, and output the boost control signal to the control input terminal of the first switch.

16. The system of claim 10, wherein the bootstrap circuit further comprises a voltage boost circuit coupled to the control input terminal of the first switch.

17. The system of claim 10, wherein the control input terminal of the third switch is coupled to the output terminal of the bootstrap circuit.

18. The system according to claim 1, further comprising: buffer; and A sampling capacitor, wherein the switching transistor is coupled between the output of the buffer and the sampling capacitor.

19. The system of claim 18, further comprising a receiver coupled to an input of the buffer.

20. The system of claim 19, wherein the receiver includes a mixer.

21. A system comprising: A bootstrap circuit, having an input terminal and an output terminal, comprising: A boost capacitor having a first terminal and a second terminal; A first transistor is coupled between the first terminal of the boost capacitor and the output terminal of the bootstrap circuit; A second transistor is coupled between the gate of the first transistor and the second terminal of the boost capacitor; A first switch, coupled between the output terminal of the bootstrap circuit and ground; and A timing circuit, the timing circuit comprising: A logic gate having a first input, a second input, and an output, wherein the first input of the logic gate is coupled to the input of the timing circuit, and the output of the logic gate is coupled to the gate of the second transistor; and A clock path, coupled between the input terminal of the timing circuit and the second input terminal of the logic gate, wherein the control input terminal of the first switch is coupled to the clock path; and A switching transistor, wherein the gate of the switching transistor is coupled to the output of the bootstrap circuit, and the terminal of the switching transistor is coupled to the input of the bootstrap circuit.

22. The system according to claim 21, wherein: The bootstrap circuit further includes a third transistor coupled between the gate of the first transistor and the power supply rail; and The gate of the third transistor is coupled to the output of the logic gate.

23. The system according to claim 22, wherein: The second transistor includes an n-type field-effect transistor (NFET); and The third transistor includes a p-type field-effect transistor (PFET).

24. The system of claim 21, wherein the logic gates include NAND gates.

25. The system of claim 21, wherein the clock path includes a series-coupled delay circuit and one or more drivers, and the control input of the first switch is coupled to a node on the clock path preceding the delay circuit.

26. The system of claim 21, wherein the bootstrap circuit further comprises: A second switch is coupled between the first terminal of the boost capacitor and the power supply rail; A third switch is coupled between the second terminal of the boost capacitor and the ground. and A fourth switch is coupled between the second terminal of the boost capacitor and the input terminal of the bootstrap circuit.

27. The system of claim 26, wherein the clock path includes a series-coupled delay circuit and one or more drivers, and the control input of the first switch and the control input of the third switch are coupled to a node on the clock path preceding the delay circuit.

28. The system of claim 27, wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input terminal of the second switch, and wherein the voltage boost circuit is configured to boost the voltage at the node on the clock path to generate a boost control signal, and output the boost control signal to the control input terminal of the second switch.

29. The system of claim 26, wherein the control input of the fourth switch is coupled to the output of the bootstrap circuit.

30. The system of claim 26, wherein the bootstrap circuit further includes a voltage boost circuit coupled to a control input terminal of the second switch.

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