Circuits and methods for generating oscillator signals

Abstract

The invention relates to a circuit and a method for generating an oscillator signal. The present disclosure relates to an oscillator circuit comprising: a controller configured to generate a frequency control signal, the frequency control signal comprising a first frequency control value; a digitally controlled oscillator (DCO) configured to generate an oscillator output signal based on the frequency control signal, where the output signal is generated at a first frequency in response to a first frequency control value of the frequency control signal; and a digital feedback circuit configured to receive the output signal and output a first feedback signal, where the oscillator circuit is configured such that the first frequency depends on or is at least partially based on a value of the first feedback signal, and the controller is configured to provide a first control instruction to instruct the digital feedback circuit to update the first feedback signal, the digital feedback circuit is configured to, in response to the first control instruction: measure a first frequency of the output signal; and adjusting a value of the first feedback signal to reduce an error between the first frequency and the first target frequency.

Description

Technical Field

[0001] This disclosure relates to oscillator circuits for generating oscillator signals, and methods for generating oscillator signals. Specifically, this disclosure relates to circuits and methods for generating oscillator signals in conjunction with spread spectrum modulation (SSM) and on / off keying (OOK) modulation schemes. Background Technology

[0002] A digital frequency-locked loop (DFLL) can be used to maintain the output signal frequency of an oscillator at a predetermined target frequency. However, DFLLs are typically designed to operate continuously once the system is powered on.

[0003] In some scenarios, the output signal of an oscillator can have a discontinuous profile. For example, if the oscillator is controlled according to a spread spectrum modulation scheme, the output signal can have a discontinuous frequency distribution. However, a DFLL designed for continuous operation cannot be used with such an oscillator because the DFLL cannot interpret the constantly changing frequencies of the output signal.

[0004] In another example, if the oscillator is controlled according to an on-off keying (OOK) amplitude modulation scheme, the output signal can have a discontinuous amplitude profile. Specifically, the oscillator can switch between an on and off state. However, similarly, a typical DFLL may not be able to account for the constantly changing amplitude of the oscillator signal. Specifically, the DFLL may not be able to handle the oscillator being off. Furthermore, the behavior of turning the oscillator on and off according to OOK modulation results in a discontinuous oscillator phase trajectory, meaning that the phase-locked loop (PLL) method is not applicable. Summary of the Invention

[0005] According to a first aspect of this disclosure, an oscillator circuit is provided, comprising: a controller configured to generate a frequency control signal including a first frequency control value; a digitally controlled oscillator (DCO) configured to generate an oscillator output signal based on the frequency control signal, wherein the output signal is generated at a first frequency in response to the first frequency control value of the frequency control signal; and a digital feedback circuit configured to receive the output signal and output a first feedback signal, wherein the oscillator circuit is configured such that the first frequency depends on or at least partially based on the value of the first feedback signal, wherein the controller is configured to provide a first control command to instruct the digital feedback circuit to update the first feedback signal, wherein the digital feedback circuit is configured, in response to the first control command, to: measure a first frequency of the output signal; and adjust the value of the first feedback signal to reduce an error between the first frequency and a first target frequency.

[0006] In some examples, the controller is configured to provide first control commands to the digital feedback circuit intermittently or aperiodically.

[0007] In some examples, the digital feedback circuit is configured to adjust the value of the first feedback signal in response to an update control command. Optionally, the controller is configured to provide the update control command at a different time than when the first control command is provided.

[0008] In some examples, the frequency control signal includes a sequence of discrete frequency control values ​​ranging from a first frequency control value to a second frequency control value, wherein the DCO is configured to generate an output signal at an instantaneous frequency corresponding to the current value of the frequency control signal, and wherein the controller is configured to provide a first control command when the current value of the frequency control signal corresponds to the first frequency control value.

[0009] In some examples, the oscillator circuit further includes a second digital feedback circuit configured to receive an output signal and output a second feedback signal, wherein a controller is configured to receive a first feedback signal and a second feedback signal and generate a frequency control signal based on the first and second feedback signals, wherein a first frequency control value is proportional to the value of the first feedback signal and the second frequency control value is proportional to the value of the second feedback signal, wherein the output signal is generated at a second frequency in response to the second frequency control value of the frequency control signal, wherein the controller is further configured to provide a second control command to instruct the second digital feedback circuit to update the second feedback signal, wherein the controller is configured to provide the second control command when the current value of the frequency control signal corresponds to the second frequency control value, wherein the second digital feedback circuit is configured to, in response to the second control command, measure a second frequency of the output signal and adjust the value of the second feedback signal to reduce the error between the second frequency and the second target frequency.

[0010] In some examples, the digital feedback circuit is configured to respond to a first control command by: measuring a first frequency within a time window initiated by the first control command, determining the error between the first frequency and a first target frequency; and adjusting the value of the first feedback signal based on the determined error.

[0011] In some examples, adjusting the value of the first feedback signal includes: increasing the value of the first feedback signal if the error indicates that the first frequency is less than the first target frequency; and decreasing the value of the first feedback signal if the error indicates that the first frequency is greater than the first target frequency.

[0012] In some examples, adjusting the value of the first feedback signal includes: increasing the value of the first feedback signal if the error indicates that the first frequency is less than the first target frequency by a first threshold amount; and decreasing the value of the first feedback signal if the error indicates that the first frequency is greater than the first target frequency by a second threshold amount.

[0013] In some examples, adjusting the value of the first feedback signal includes:

[0014] If the error is greater than the previous error between the first frequency and the first target frequency, then: if the error indicates that the first frequency is less than the first target frequency, then the value of the first feedback signal is increased, and if the error indicates that the first frequency is greater than the first target frequency by a first threshold amount, then the value of the first feedback signal is decreased; and if the error is less than the previous error, then: if the error indicates that the first frequency is greater than the first target frequency by a second threshold amount, then the value of the first feedback signal is increased, and if the error indicates that the first frequency is greater than the first target frequency, then the value of the first feedback signal is decreased.

[0015] In some examples, the digital feedback circuit is configured to output a second feedback signal, wherein the controller is also configured to receive a first feedback signal and a second feedback signal, and generate a frequency control signal based on the first and second feedback signals, wherein the first frequency control value is proportional to the value of the first feedback signal, and the second frequency control value is proportional to the value of the second feedback signal, wherein the output signal is generated at a second frequency in response to the second frequency control value of the frequency control signal, wherein the controller is configured to provide a first control command when the current value of the frequency control signal corresponds to the first frequency control value, and to provide a second control command to instruct the digital feedback circuit to update the second feedback signal, wherein the controller provides the second control command when the current value of the frequency control signal corresponds to the second frequency control value, wherein the digital feedback circuit is configured to, in response to the second control command, measure a second frequency of the output signal; and adjust the value of the second feedback signal to reduce the error between the second frequency and the second target frequency.

[0016] In some examples, the digital feedback circuit is configured to: in response to a first control command, use a frequency estimation circuit to measure a first frequency within a time window initiated by the first control command, use a digital subtractor to determine the error between the first frequency and a first target frequency, and adjust the value of the first feedback signal based on the determined error; and in response to a second control command, use a frequency estimation circuit to measure a second frequency within a time window initiated by the second control command, use a digital subtractor to determine the error between the second frequency and a second target frequency, and adjust the value of the first feedback signal based on the determined error.

[0017] In some examples, the digital feedback circuit also includes a multiplexer configured to provide a first target frequency to the subtractor in response to a first control command and a second target frequency to the subtractor in response to a second control command.

[0018] In some examples, the digital feedback circuit is configured to: in response to a first control command, generate an adjustment value using an error processing circuit and based on the error between a first frequency and a first target frequency, the adjustment value indicating a desired adjustment to the value of a first feedback signal to reduce the error, and adjust the first feedback signal by adding the adjustment value to the first feedback signal using a digital adder; and in response to a second control command, generate an adjustment value using an error processing circuit and based on the error between a second frequency and a second target frequency, the adjustment value indicating a desired adjustment to the value of a second feedback signal to reduce the error, and adjust the second feedback signal by adding the adjustment value to the second feedback signal using a digital adder.

[0019] In some examples, the digital feedback circuit further includes: a first output configured to output a first feedback signal and a second output configured to output a second feedback signal; and a multiplexer configured to provide the first feedback signal from the first output to an adder in response to a first control command, and to provide the second feedback signal from the second output to the adder in response to a second control command.

[0020] In some examples, the controller is configured to provide a clock signal to the DCO, wherein the DCO is configured to switch between an on and off state in response to the clock signal; and wherein the controller is configured to provide a first control command when the DCO is in the on state.

[0021] In some examples, the clock signal is a pulse width modulation (PWM) clock signal, which has a duty cycle that defines the on-time of the PWM signal, wherein the DCO is configured to be on during the on-time of the PWM signal.

[0022] In some examples, the controller is configured to provide a first control command when the DCO is on and when the duty cycle of the PWM signal is higher than a threshold duty cycle.

[0023] In some examples, the DCO is configured to receive a first feedback signal and apply a frequency offset to the output signal based on the first feedback signal, wherein the frequency offset is proportional to the value of the first feedback signal.

[0024] According to a second aspect of this disclosure, an oscillator circuit is provided, comprising: a digitally controlled oscillator (DCO) configured to generate an oscillator output signal at a first frequency; and a digital feedback circuit configured to receive the output signal and output a feedback signal, wherein the DCO is configured to receive the feedback signal, and wherein the first frequency of the output signal is at least partially based on the value of the feedback signal; wherein the digital feedback circuit is configured to, in response to a control command, measure the first frequency of the output signal and adjust the value of the feedback signal to reduce the error between the first frequency and a target frequency.

[0025] In some examples, the oscillator circuit also includes a controller, which is configured to provide control commands to the digital feedback circuit discontinuously or aperiodically.

[0026] In some examples, the digital feedback circuit is configured to adjust the value of the feedback signal in response to an update control command. Optionally, the controller is configured to provide the update control command at a different time than when the control command is provided.

[0027] In some examples, the oscillator circuit also includes a controller configured to provide a clock signal to the DCO, wherein the DCO is configured to switch between an on and off state in response to the clock signal; and wherein the controller is configured to provide control commands to the digital feedback circuit when the DCO is in the on state.

[0028] In some examples, the clock signal is a pulse width modulation (PWM) clock signal, which has a duty cycle that defines the on-time of the PWM signal, wherein the DCO is configured to be on during the on-time of the PWM signal.

[0029] In some examples, the controller is configured to provide control commands when the DCO is on and when the duty cycle of the PWM signal is higher than a threshold duty cycle.

[0030] In some examples, the DCO is configured to: receive a frequency control signal including a first frequency control value, wherein the output signal is generated at a first frequency in response to the first frequency control value of the frequency control signal; and apply a frequency offset to the output signal based on a first feedback signal, wherein the frequency offset is proportional to the value of the first feedback signal.

[0031] In some examples, the frequency control signal includes a sequence of discrete frequency control values ​​ranging from a first frequency control value to a second frequency control value, wherein the DCO is configured to generate an output signal at an instantaneous frequency corresponding to the current value of the frequency control signal, and wherein the controller is configured to provide control commands to the digital feedback circuit when the current value of the frequency control signal corresponds to the first frequency control value.

[0032] In some examples, the DCO is configured to generate an output signal at a first frequency in response to the value of the feedback signal, wherein the first frequency is proportional to the value of the feedback signal.

[0033] In some examples, the digital frequency circuit is configured to respond to control commands by: measuring a first frequency within a time window initiated by the control command, determining the error between the first frequency and a target frequency, and adjusting the value of the feedback signal based on the determined error.

[0034] In some examples, adjusting the value of the feedback signal includes: increasing the value of the feedback signal if the error indication first frequency is less than the target frequency; and decreasing the value of the feedback signal if the error indication first frequency is greater than the target frequency.

[0035] In some examples, adjusting the value of the feedback signal includes: increasing the value of the feedback signal if the error-indicating first frequency is less than the target frequency by a first threshold amount; and decreasing the value of the feedback signal if the error-indicating first frequency is greater than the target frequency by a second threshold amount.

[0036] In some examples, adjusting the value of the feedback signal includes: if the error is greater than a previous error between the first frequency and the target frequency, then: if the error indicates that the first frequency is less than the target frequency, then increase the value of the feedback signal, and if the error indicates that the first frequency is greater than the target frequency by a first threshold amount, then decrease the value of the feedback signal; and if the error is less than a previous error, then: if the error indicates that the first frequency is less than the target frequency by a second threshold amount, then increase the value of the feedback signal, and if the error indicates that the first frequency is greater than the target frequency, then decrease the value of the feedback signal.

[0037] According to a third aspect of this disclosure, a method for generating an oscillator output signal is provided, the method comprising: generating the oscillator output signal based on a frequency control signal, the frequency control signal including a first frequency control value, wherein the output signal is generated at a first frequency in response to the first frequency control value of the frequency control signal, wherein the first frequency depends on or is at least partially based on a value of a first feedback signal; and, in response to a first control command: measuring the first frequency of the output signal; and adjusting the value of the first feedback signal to reduce an error between the first frequency and a first target frequency.

[0038] According to a fourth aspect of this disclosure, a method for generating an oscillator output signal is provided, the method comprising: generating the oscillator output signal at a first frequency based on a feedback signal, wherein the first frequency of the output signal is at least partially based on the value of the feedback signal; in response to a control command: measuring the first frequency of the output signal; and adjusting the value of the feedback signal to reduce an error between the first frequency and a target frequency.

[0039] According to another aspect, an electrically isolated power delivery circuit is provided, comprising: a first circuit region and a second circuit region separated by an electrically isolated barrier, the first circuit region including any of the aforementioned aspects of oscillator circuitry; a first transformer configured to transmit an oscillator output signal across the isolation barrier to the second circuit region; wherein the second circuit region includes a power-on circuit configured to receive a power supply voltage signal based on the transmitted oscillator output signal.

[0040] In some examples, the DCO is configured to receive a pulse-width modulation (PWM) clock signal having a duty cycle that defines the on-time of the PWM signal, wherein the DCO is configured to be on during the on-time of the PWM signal. The power delivery circuit also includes a feedback circuit configured to receive a voltage supply signal and adjust the duty cycle of the PWM signal to maintain the voltage supply signal at a reference voltage signal. Attached Figure Description

[0041] Figure 1 A digitally controlled oscillator (DCO) is shown as an example according to this disclosure;

[0042] Figure 2 It shows Figure 1 Frequency control mapping of the DCO;

[0043] Figure 3 An oscillator circuit according to an example of this disclosure is shown;

[0044] Figure 4 A digital feedback circuit according to an example of this disclosure is shown;

[0045] Figure 5 A frequency measurement circuit according to an example of this disclosure is shown;

[0046] Figure 6 An example is shown. Figure 5 The timing diagram of the operation of the frequency measurement circuit;

[0047] Figures 7A to 7B A feedback signal generator circuit according to an example of this disclosure is shown;

[0048] Figures 8A to 8C The transfer function of hysteresis detectors (bang-bang detectors) according to examples of this disclosure is shown;

[0049] Figures 9A to 9B An example emission spectrum of the output signal of the oscillator circuit is shown;

[0050] Figure 10 An oscillator circuit according to another example of this disclosure is shown;

[0051] Figure 11A An example frequency control signal is shown;

[0052] Figure 11B It shows Figure 10 Example spectrum of the output signal of the oscillator circuit;

[0053] Figures 12A to 12B An example emission spectrum of the output signal of the oscillator circuit is shown;

[0054] Figure 13 An oscillator circuit according to another example of this disclosure is shown;

[0055] Figure 14 An oscillator circuit according to another example of this disclosure is shown;

[0056] Figure 15 A digital feedback circuit according to another example of this disclosure is shown;

[0057] Figures 16A to 16C A feedback signal generator circuit according to another example of this disclosure is shown;

[0058] Figures 17A to 17B An example emission spectrum of the output signal of the oscillator circuit is shown;

[0059] Figure 18 An oscillator circuit according to another example of this disclosure is shown;

[0060] Figure 19 An example PWM signal for controlling the DCO according to an on / off keying (OOK) modulation scheme is shown;

[0061] Figure 20 An oscillator circuit according to another example of this disclosure is shown;

[0062] Figure 21 An oscillator circuit according to another example of this disclosure is shown;

[0063] Figure 22 An example emission spectrum of the output signal of the oscillator circuit is shown;

[0064] Figure 23 An oscillator circuit according to another example of this disclosure is shown;

[0065] Figure 24 An oscillator circuit according to another example of this disclosure is shown;

[0066] Figures 25 to 28 An example DCO circuit according to an example of this disclosure is shown; and

[0067] Figure 29 An electrically isolated power delivery circuit according to an example of this disclosure is shown. Detailed Implementation

[0068] Figure 1 A digitally controlled oscillator (DCO) 110 according to an example of this disclosure is shown. The DCO 110 has a frequency control input 102 and an analog output 104. The DCO 110 is configured to receive a digital frequency control signal D at input 102. The digital frequency control signal D can be a plurality of N discrete frequency control values ​​or codes d0 to d... N-1 Either of these. In other words, the DCO110 can receive any frequency control value d. n Where the index n is an integer in the range 0 < n < N-1. Each frequency control value d n Indicate the corresponding frequency f n .

[0069] DCO 110 is configured to generate an output signal v(t) at output terminal 104 based on the frequency control signal D. DCO 110 generates the output signal v(t) at an instantaneous frequency F corresponding to (or proportional to) the value of the frequency control signal D. Specifically, DCO 110 generates the output signal v(t) at a frequency d corresponding to the value of the frequency control signal D. n frequency f n The DCO 110 generates an output signal v(t). Therefore, the DCO 110 can output signals at multiple N unique frequencies f0 to f... N-1 Either of them generates the output signal v(t).

[0070] The output signal v(t) preferably has a sinusoidal waveform. However, it should be understood that the output signal v(t) can have any type of periodic waveform (e.g., square wave, triangle wave, sawtooth wave, etc.). The output signal v(t) can be adapted to supply power to a load.

[0071] refer to Figure 2 The possible frequency control values ​​d0 to d are further illustrated. N-1 With the corresponding frequencies f0 to f N-1 The mapping between them. The x-axis shows the possible values ​​d0 to d... N-1 The y-axis on the left shows the corresponding frequencies f0 to f1. N-1 As shown in the figure, each unique value d n This will cause DCO 110 to operate at the corresponding unique instantaneous frequency f. n Generate an output signal v(t). As the value d... n Increase, f n With unit frequency f unitThe increment increases. Therefore, increasing or incrementing the value of the frequency control signal D will cause the instantaneous frequency F of the output signal v(t) to increase. Decreasing or decrementing the frequency control signal D will cause the instantaneous frequency F to decrease. Therefore, DCO 110 has f0 to f N-1 The nominal output frequency range.

[0072] Optionally, the DCO 110 has an offset control input 106. The offset control input 106 is configured to receive an offset control signal G. The DCO 110 is also configured to generate an output signal v(t) based on the offset control signal G. Specifically, the DCO 110 applies a frequency offset to the output signal v(t) based on the offset control signal G.

[0073] The offset control signal G can have M discrete offset control values ​​g0 to g M-1 Either of the following. In other words, the offset control signal G can have a value g. m , where the exponent m is an integer in the range 0 < m < M-1. Each value g m Indicates the corresponding frequency offset δf m The DCO 110 applies a frequency offset δf to the output signal v(t). m This frequency offset corresponds to (or is proportional to) the value g of the offset control signal G. m Therefore, the DCO 110 can apply multiple M offsets δf0 to δf to the output signal v(t). M-1 Any one of them. Values ​​g0 to g M-1 It can indicate a combination of negative and positive offsets. For example, the value g0 can indicate the most negative offset δf0. The value g... M-1 It can indicate the maximum positive offset δf M-1 The intermediate value g |(M-1) / 2| An offset value of 0 can be indicated. The instantaneous frequency F at a given time will be F = f n + δf m , where f n It corresponds to the current value d of the frequency control signal D. n The frequency, and δf m It corresponds to the current value g of the offset control signal G. m Frequency offset.

[0074] Optionally, DCO 110 has an enable terminal 109. Enable terminal 109 is configured to receive an enable signal EN. The enable signal EN can be used to turn DCO 110 on and off. The enable signal EN can have a first state (e.g., "0" or "low") and a second state (e.g., "1" or "high"). When the enable signal EN is in the second state, DCO 110 operates in the on state. In the on state, DCO 110 generates and outputs an output signal v(t). When the enable signal EN is in the first state, DCO 110 operates in the off state. In the off state, DCO 110 does not output the output signal v(t).

[0075] Figure 3 An oscillator circuit 300 according to an example of this disclosure is shown. As described below, the oscillator circuit 300 is capable of maintaining the instantaneous frequency F of the output signal v(t) substantially at a target frequency F. target Or at least within the tolerance range of the target frequency.

[0076] The oscillator circuit 300 includes a digital control unit (DCO) 110, a digital feedback circuit 310, and a controller 330. The controller 330 has a digital input terminal 332, which receives a digital feedback signal P. The digital feedback signal P is received from the digital output terminal 318 of the digital feedback circuit 310. The digital feedback signal P indicates the desired frequency control value. Specifically, the feedback signal P can be a plurality of N discrete values ​​p0 to p100. N-1 Either of them. In other words, the feedback signal P can have a value p. n , where the index n is an integer in the range 0 < n < N-1. Each value p n Indicate the corresponding frequency control value d n .

[0077] The controller 330 is configured to generate a frequency control signal D based on the feedback signal P. Specifically, the controller 330 sets the value of the frequency control signal D to the desired frequency control value indicated by the feedback signal P. For example, if the current value of the feedback signal P is p... n Then the controller 330 sets the value of the frequency control signal D to the corresponding frequency control value d. n .

[0078] The controller 330 has a digital output terminal 334. The controller 330 is configured to output a digital frequency control signal D at the output terminal 334. The output terminal 334 is coupled to the frequency control input terminal 102 of the DCO 110. Therefore, the DCO 110 will generate an output signal v(t) at a frequency corresponding to the value of the frequency control signal D.

[0079] The digital feedback circuit 310 has an analog input terminal 312, where the output signal v(t) is received. The digital feedback circuit 310 is also configured to receive a target or reference frequency value F at a frequency reference input terminal 314. target It also receives command signal X at control input terminal 316. Target frequency value F target It can be represented by a digital code. The command signal X is received from the command output terminal 336 of the controller 330. For example, the command signal X can be a pulse. The command signal X can be considered as a control command from the controller 330. The controller 330 can provide the command signal X to the digital feedback circuit 310 discontinuously or aperiodically.

[0080] The digital feedback circuit 310 is configured to perform an update cycle in response to receiving a command signal X from the controller 336. During the update cycle, the digital feedback circuit 310 updates the value of the digital feedback signal P. Specifically, the digital feedback circuit 310 adjusts or updates the digital feedback signal P in such a way as to reduce or minimize the difference between the instantaneous frequency F of the output signal v(t) and the target frequency value F. target The error between the feedback signal P and the target frequency F is as follows: When the feedback signal P is adjusted, the controller 330 will adjust the frequency control signal D accordingly, which will cause the instantaneous frequency F of the output signal v(t) to be adjusted. For example, increasing the value of the feedback signal P will cause the instantaneous frequency F of the output signal v(t) to increase accordingly. Decreasing the value of the feedback signal P will cause the instantaneous frequency F of the output signal v(t) to decrease accordingly. Therefore, whenever the controller 330 outputs the command signal X, the instantaneous frequency of the output signal v(t) is different from the target frequency F. target The error between them will be reduced or minimized. The controller 330 can output the command signal X periodically (e.g., at regular intervals) or at irregular intervals. In either case, over time, the oscillator circuit 300 is able to maintain the instantaneous frequency F of the output signal v(t) substantially at the target frequency F. target Or, within the tolerance range of the target frequency.

[0081] Figure 4The digital feedback circuit 310 is shown in more detail. The feedback circuit 310 includes a frequency estimator 410 (also referred to as a frequency measurement circuit), a digital subtractor 420, and a feedback signal generator 430. The frequency estimator 410 receives the output signal v(t) of the oscillator at analog input 412. The frequency estimator 410 is also configured to receive a command signal X at control input 414. The frequency estimator 410 is configured to estimate or measure the instantaneous frequency of the output signal v(t) in response to receiving the command signal X. Specifically, the frequency estimator 410 can estimate the frequency within a time window initiated by receiving the command signal X. The frequency estimator 410 can estimate the frequency relative to a reference clock CLK received at reference clock input 418 of the frequency estimator. ref The instantaneous frequency. Frequency estimator 410 is configured to output frequency estimate F' at the output terminal 416 of frequency estimator 416. Frequency estimate F' can be represented by a digital signal.

[0082] The digital subtractor 420 receives the frequency estimate F' at its first input 422 and the target frequency value F at its second input 424. target The digital subtractor 420 is configured to determine the frequency estimate F' and the target frequency value F. target The error E between the frequency estimate F' and the target frequency F. Specifically, the digital subtractor 420 calculates the error as the frequency estimate F' versus the target frequency F. target The difference between them, where E = F' – F target Therefore, if the error value E is positive, it indicates that the instantaneous frequency F is greater than the target value F. target If the error value E is negative, it indicates that the instantaneous frequency F is less than the target value F. target If the absolute value of the error value E is lower than the (non-zero) threshold e T This can indicate that the instantaneous frequency F is essentially at the target frequency F. target Alternatively, it may operate within the tolerance range of the target frequency. The subtractor 420 outputs an error value E at its output terminal 426. The error value E can be represented by a digital signal.

[0083] Feedback signal generator 430 receives the error value E at input 432. Feedback signal generator 430 is configured to adjust or update the feedback signal P based on the error value E. Feedback signal generator 430 adjusts the feedback signal P in such a way that it reduces or minimizes the difference between the instantaneous frequency F and the target value F. target The error between the values. Specifically, the feedback signal generator 430 can adjust the feedback signal P based on the polarity of the error value E. For example, if the error E is positive, this can indicate that the frequency F of the output signal v(t) is higher than the target frequency F. target In this case, the feedback signal generator 430 can decrease or decrement the value of the feedback signal P (e.g., from p...).n Change to p n-1 This will result in a corresponding decrease in the value of the frequency control signal D output by the controller 330 (e.g., from d). n Change to d n-1 Accordingly, the frequency F of the output signal v(t) will therefore decrease accordingly (e.g., from f). n Change to f n-1 This reduces the error. If the error E is negative, this indicates that the frequency F of the output signal v(t) is lower than the target frequency F. target In this case, the feedback signal generator 430 can increase or increment the value of the feedback signal P (e.g., from p...). n Change to p n+1 This will result in a corresponding increase in the value of the frequency control signal D output by the controller 330 (e.g., from d). n Change to d n+1 Accordingly, the frequency F of the output signal v(t) will therefore increase accordingly (e.g., from f). n Change to f n+1 This reduces the error. In some examples, if the absolute value of the error E is below the error threshold e, the error will be reduced. T Therefore, the feedback signal generator 430 can keep the feedback signal P unchanged as the result of the update cycle. Thus, the error threshold e T It is possible to define the target frequency F target The tolerance range. Advantageously, this can improve the stability of the feedback signal P. Furthermore, this can also improve the stability of the frequency control signal D by eliminating limiting periodic behavior (i.e., by eliminating repetitive switching of the signal under steady-state conditions).

[0084] Whenever the digital feedback signal 310 receives the command signal X, the digital feedback circuit 310 updates the feedback signal P as described above. Therefore, over time, the feedback circuit 310 is able to maintain the frequency F of the output signal v(t) substantially at the target frequency F. target Or, within the tolerance range of the target frequency.

[0085] Figure 5 The frequency estimator 410 is shown in more detail. The frequency estimator 410 includes a counter 520, a switch 530, and a switch controller 510. The switch controller 510 is implemented as a D-type flip-flop (FF).

[0086] Counter 520 is configured to receive a signal v(t) at its input 522 via switch 530. Specifically, switch 530 has a first terminal 532 for receiving the signal v(t) and a second terminal 534 coupled to the input 522 of counter 520. When switch 530 is closed, counter 520 receives the signal v(t). FF 510 is configured to receive a command signal X at data input 512 and a reference clock CLK at clock input 418. ref FF 510 has a data output 514 coupled to a control terminal 536 of switch 530. Switch 530 is configured to open when data output 514 is in a first state (e.g., "0" or "low") and close when data output 514 is in a second state (e.g., "1" or "high"). In some examples, switch 530 may be implemented as a logic gate. For example, switch 530 may be an AND gate that performs an AND operation between data output 514 and signal 412 to produce signal 522.

[0087] refer to Figure 6 describe Figure 5 The frequency estimator 410 is shown to function. As shown, the command signal X can include a pulse. The data output 514 can initially be low, and therefore the switch 530 can initially be open. FF 510 at time t 13 The rising edge of the receive pulse. This causes the data output terminal 514 to be at time t. 13 At reference clock CLK ref The falling edge becomes high. Therefore, at time t 13 Switch 530 is closed. Then, at time t... 15 The data output terminal 514 is at the reference clock CLK. ref The subsequent falling edge returns to low. Therefore, at time t 15 Switch 530 is turned off again. Therefore, time t 13 To t 15 A frequency estimation window 610 is defined, which corresponds to the reference clock CLK. ref The period. During the frequency estimation window 610, when the switch is closed, the counter 520 counts the number of periods (or cycles) of the signal v(t). The number of cycles indicates the period of the signal v(t) relative to the reference clock CLK. ref The frequency F is then determined. The counter 520 outputs the final count value at its output terminal 524 as the frequency estimate F'. Therefore, the frequency estimate F' can correspond to the frequency at the reference clock CLK. ref The number of cycles of the signal v(t) occurring within a period (or any defined number of cycles). Therefore, to ensure that the frequency estimate F' is close to the target frequency value F targetA correct comparison between them, the target frequency value F target It can be determined by the signal v(t) at the reference clock CLK. ref It is expressed as the target number of cycles within a given period (or any defined number of cycles).

[0088] It should be understood that Figure 5 One possible implementation of the frequency estimator 410 is shown, and other alternative implementations are envisioned. For example, the frequency estimator 410 may employ various other frequency estimation techniques, including the use of phase interpolation, calibrated TDC, and / or calibrated ring oscillators.

[0089] Figure 7A The feedback signal generator 430 is shown in more detail. The feedback signal generator 430 includes an error processor 710, a digital adder 720, a limiter 730, and a register 740. The register 740 is shown as being implemented as a flip-flop (FF).

[0090] Error processor 710 receives an error value E at input 712. Error processor 710 is configured to generate an adjustment value α based on the error value E. The adjustment value α indicates the amount by which the feedback signal P will be adjusted. Error processor 710 can generate the adjustment value α based on the polarity of the error value E.

[0091] Figure 8A An example transfer function 800A of the error processor 710 is shown. The transfer function 800A shows the error value E on the x-axis and the resulting adjustment value α on the y-axis. As shown, if the error value E is positive (> 0), the error processor 710 can generate an adjustment value of α = -1. Accordingly, this will cause the value of the feedback signal P to decrease or diminish (e.g., from p...). n Change to p n-1 This reduces the frequency F of the frequency control signal D and the output signal v(t), as described above. If the error value E is negative (< 0), the error processor 710 can generate an adjustment value of α = +1. Accordingly, this will cause the value of the feedback signal P to increase or decrease (e.g., from p...). n Change to p n+1 The frequency control signal D and the frequency F of the output signal v(t) are increased, as described above. If the error value E is approximately 0, the error processor 710 can generate an adjustment value of α = 0, so that the feedback signal P remains unchanged due to the update cycle.

[0092] Figure 8B Another example transfer function 800B of the error processor 710 is shown. Transfer function 800B is similar to 800A. However, as shown, transfer function 800B includes a (non-zero) error threshold -e. T with +e TThe dead zone is 810. Therefore, if the absolute error value |E| is less than the error threshold e T Then, the error processor 710 can generate an adjustment value of α = 0, so that the feedback signal P remains unchanged as a result of the update cycle. In other words, if the error value E is within a lower error threshold -e... T With a higher error threshold +e T Between these values, the error processor 710 can generate an adjustment value of α = 0. Advantageously, the transfer function 800B can provide an adjustment value α that improves stability. T and +e T The absolute values ​​can be the same or different.

[0093] Figure 8C Another example transfer function 800C of the error processor 710 is shown. Transfer function 800C is similar to 800B. However, as shown, transfer function 800C exhibits hysteresis behavior in the dead zone 810. Specifically, the error processor 710 can further generate an adjustment value α based on a previous error value from a previous update cycle. If the previous error value is less than the current error value E, this can indicate that the error has changed in the positive direction. In this case, the error processor 710 can operate in a first mode. In the first mode, transfer function 800C only applies the upper limit error threshold + e. T Instead of applying the negative error threshold -e T Specifically, if the error value E is negative (< 0), the error processor 710 generates an adjustment value α = +1. If the error value E is between 0 and +1, the error processor 710 generates an adjustment value α = +1. T If the error value E is between +e and 0, the error processor 710 generates an adjustment value α = 0. T If α = -1, then the error processor 710 generates an adjustment value α = -1. Therefore, in the first mode, the error processor 710 uses 0 and e. T The positive dead zone between the two sides. If the previous error value is greater than the current error value E, this can indicate that the error has changed in the negative direction. In this case, the error processor 710 can operate in the second mode. In the second mode, the transfer function 800C applies the negative error threshold -e. T Instead of applying the positive error threshold + e T Specifically, if the error value E is positive (> 0), the error processor 710 generates an adjustment value α = -1. If the error value E is between 0 and -1... T If the error value E is between -e and -e, then the error processor 710 generates an adjustment value α = 0. T If α = +1, then the error processor 710 generates an adjustment value α = +1. Therefore, in the first mode, the error processor 710 uses 0 with -e TThe negative-side dead zone between. Advantageously, a hysteresis detector with hysteresis can generate an adjustment signal α with further improved stability. -e T and +e T The absolute values ​​can be the same or different.

[0094] Return to reference again Figure 7A Adder 720 receives an adjustment value α at its first input 722 and a current feedback signal P at its second input 724. The current feedback signal P can be represented as P(i). Adder 720 is configured to generate an updated or adjusted feedback signal by adding the adjustment value α to the current feedback signal P(i). The updated feedback signal can be represented as P(i+1). For example, if the current value of the feedback signal is P(i) = p... n Then the updated feedback signal can have the value P(i+1) = p n+α Adder 720 is configured to output an updated feedback signal P(i+1) at output 726.

[0095] Limiter 730 is configured to receive an updated feedback signal P(i+1) at input 732. Limiter 730 is configured to limit the value of feedback signal P(i+1) to a value between p0 and p1. N-1 Within the range. Specifically, the limiter 730 checks whether the value of the feedback signal P(i+1) is within the range. If the value of the feedback signal P(i+1) has increased to p... N-1 If the value is above or below p0, the value may be invalid. If the limiter 730 determines that the value of the feedback signal P(i+1) exceeds p... N-1 Then the limiter 730 will limit the feedback signal to a value p. N-1 If the limiter 730 determines that the value of the feedback signal P(i+1) is lower than p0, then the limiter 730 sets the feedback signal to the value p0. The limiter 730 then outputs the updated (and limited) feedback signal P(i+1) at the output terminal 734.

[0096] Register 740 receives the updated feedback signal P(i+1) at input 742. Register 740 includes a control input 746 configured to receive an update signal U. The update signal U can have a first state (e.g., "0" or "low") and a second state (e.g., "1" or "high"). When the update signal U is in the first state, register 740 stores the updated feedback signal P(i+1) at input 742 and stores the current feedback signal P(i) at output 744. Then, when the update signal is in the second state, register 740 provides the feedback signal P(i+1) to output 744, as shown below. Figure 7BAs shown. Then, the digital feedback circuit 310 outputs the updated feedback signal P(i+1). Once the updated feedback signal P(i+1) is ready at input 742, register 740 can receive the updated signal U, for example, from controller 330. Typically, controller 330 can provide the updated signal U at a different time than when the command signal X is provided. Specifically, controller 330 can provide the updated signal U at a predetermined or planned time after the command signal X, for example, to allow sufficient time to generate the updated feedback signal.

[0097] In some examples, limiter 730 may be optional, and register 740 may receive the updated feedback signal P(i+1) directly from adder 720. Alternatively, in some examples, register 740 may be optional. Instead, the updated feedback signal P(i+1) may be provided directly to the output of feedback circuit 310 after being output by limiter 734 (or adder 720).

[0098] refer to Figure 9A The figure shows the initial electromagnetic emission spectrum 900A of the oscillator output signal v(t) generated by circuit 300. As shown, the emission spectrum 900A includes emission peaks 910, 920, 930, and 940. Emission peak 910 is a result of the (fundamental) frequency F of the output signal v(t). Emission peaks 920, 930, and 940 are the results of the second, third, and fourth harmonics of the output signal v(t), respectively. Although not shown, the emission may include additional emission peaks caused by further harmonics of the output signal v(t). Even-order harmonics may cause larger or stronger emission peaks due to common-mode currents in circuit 300 (e.g., in DCO 110).

[0099] In some examples, the oscillator circuit 300 may include a radio frequency (RF) transceiver (or may otherwise be very close to an RF transceiver). The RF transceiver may be... Figure 9A The RF band shown operates at 990, which is at a lower RF frequency f. RF-L With higher RF frequencies f RF-U Between. Although the fundamental frequency range of the DCO 110 is much lower than the RF band 990, the harmonic emissions of the signal v(t) may still overlap with the RF band 990. For example, as Figure 9A As shown, the transmit peak 940 can enter the RF band 990. This may interfere with the wireless signals transmitted or received by the RF transceiver.

[0100] One option to reduce interference is to add shielding to circuit 300. However, this could significantly increase the cost of the circuit. Furthermore, if portions of circuit 300 are electrically isolated, shielding may reduce the effectiveness of that isolation.

[0101] Given the above, it may be desirable to maintain the frequency F of the signal v(t) at a target frequency F. target The target frequency F can be selected. target This ensures that the fourth harmonic emission 940 is outside the RF band 990. Specifically, the target frequency F target It can be determined that condition k*F is satisfied. target < f RF-L In this case, k = 4.

[0102] One option is to identify frequencies f0 to f N-1 The set that corresponds to (or is otherwise closest to) F target instantaneous frequency f n The controller 330 can then fix the digital control signal D at a value d. n However, this may only temporarily maintain the frequency F of the output signal v(t) at the target frequency. Specifically, the frequency control values ​​d0 to d N-1 With the result frequency f0 to f N-1 The mapping between them may change over time, for example due to PVT drift, load pulling, and / or aging effects within circuit 100. Therefore, the response of DCO 110 to the value d n The frequency f generated n It may eventually be from the target frequency F target Drift. Therefore, over time, the frequency of the signal v(t) may drift in such a way that the fourth harmonic transmission 940 re-enters the RF band 990.

[0103] Using circuit 300, the frequency F of signal v(t) can be maintained essentially at the target frequency F. target Or, within the tolerance range of the target frequency. Specifically, the controller 330 may periodically or irregularly provide a command signal X to the digital feedback circuit 310. Whenever the digital feedback circuit 310 receives the command signal X, the digital feedback circuit 310 will execute an update cycle as described above in order to reduce the frequency F of the output signal v(t) relative to the target frequency F. target The error between them. Over time, this will ensure that the frequency F of the signal v(t) remains at the target frequency F. target .

[0104] Figure 9B The emission spectrum 900B is shown after running one or more update cycles. As shown, the frequency F of the signal v(t) can be at the target frequency F. target Therefore, the fourth harmonic emission at 940° is at the target frequency 4F. targetThe fourth harmonic is located outside the RF band 990. The controller 330 can continue to output command signal X to run the update cycle in order to keep F at F. target .

[0105] Figure 10 An oscillator circuit 1000 according to another example of this disclosure is shown. As described below, oscillator circuit 1000 differs from oscillator circuit 300. It should be understood that circuit 1000 may otherwise resemble oscillator circuit 300, at least as can be seen from the same reference numerals.

[0106] As described below, in the oscillator circuit 1000, a signal v(t) is generated according to a spread spectrum frequency modulation scheme. Specifically, the instantaneous frequency of the signal v(t) is modulated over a discrete frequency range. The oscillator circuit 1000 is able to maintain the maximum instantaneous frequency of the signal v(t) substantially at the target frequency F. target Or, within the tolerance range of the target frequency.

[0107] The oscillator circuit 1000 includes a controller 1030. Controller 1030 is similar to controller 330, but with the following differences: Controller 1030 stores a parameter V corresponding to the maximum frequency control value. max The controller 1030 also stores the parameter V corresponding to the minimum frequency control value. min For example, V max It can be initialized to the highest possible value d N-1 , and V min It can be initialized to the lowest possible value d0.

[0108] Controller 1030 is based on the maximum frequency control value V max and minimum frequency control value V min Generate a frequency control signal D. (Reference) Figure 11A This shows the value of the frequency control signal D (left y-axis) changing with time (x-axis). As shown in the figure, the frequency control signal D corresponds to a pseudo-random sequence of frequency control values. The value sequence is modulated at a frequency rate F. mod Provided. In other words, the value of the frequency control signal D is determined according to the sequence every T. mod = 1 / F mod The frequency changes once per second. The sequence is controlled by a minimum frequency value V. min With the maximum frequency control value V max Each frequency control value is generated from the frequency control values ​​between (including endpoints). For example, initially, the sequence can be generated using the frequency control value V. min = d0 to V max = d N-1Each of these is used to generate the frequency control signal D. It should be understood that in some examples, the frequency control signal D is not a pseudo-random sequence, but rather a cyclic pattern of frequency control values ​​(e.g., repeatedly increasing the value to V in ascending order in a triangular pattern). max Then decrease the values ​​to V in descending order. min Or, for example, in the Hershey-kiss pattern.

[0109] As a result of the frequency control signal D, DCO 110 receives a sequence of frequency control values ​​at the frequency control input terminal 102. Therefore, the instantaneous frequency of the signal v(t) will be modulated at a rate F. mod Modulated. Specifically, in response to the frequency control value sequence received at input 102, the instantaneous frequency of v(t) will be modulated every T. mod It changes once per second. For example... Figure 11A As shown (right y-axis), the maximum instantaneous frequency F of signal v(t) max This will correspond to the maximum frequency control value V max The frequency of the signal v(t). The minimum instantaneous frequency F. min This will correspond to the minimum frequency control value V min The frequency of. Therefore, as Figure 11B As shown, the signal v(t) will have a value range V that depends on the frequency control signal D. min To V max Frequency range F min To F max The signal v(t) will have a center frequency f c The bandwidth ΔF = F centered on max – F min F max It can be considered as the upper edge of the bandwidth ΔF, while F min This can be considered as the lower edge of the bandwidth ΔF. Initially, when V... min = d0 to V max = d N-1 At that time, the maximum instantaneous frequency will be F. max = f N-1 And the minimum instantaneous frequency will be F. min = f0. Therefore, the initial frequency range of the signal v(t) is F. min = f0 to F max = f N-1 Advantageously, in F min To F max Modulating the frequency of the output signal v(t) across a wider range will result in a reduction in the average power / amplitude of the transmitted peak value corresponding to the fundamental frequency of v(t). This can make the circuit more compliant with industrial emission standards.

[0110] The controller 1030 interprets the value of the feedback signal P as an indication of the maximum frequency control value V. max Specifically, as described above, the value of the feedback signal P indicates the frequency control value. The controller 1030 sets the maximum frequency control value V. max Set to the frequency control value indicated in the value of the feedback signal P. For example, the feedback signal could have a value p. v , where p v The value is from p0 to p N-1 Any one of them. Value p v Indicates the corresponding frequency control value d v The controller 1030 then sets the frequency control value d. v This is interpreted as the maximum frequency control value. Specifically, the controller 1030 will set the maximum frequency control value V... max Set to d v Therefore, whenever the value of the feedback signal P is updated to a new value (e.g., p), v+1 When this happens, controller 1030 updates the maximum frequency control value V accordingly. max (For example, updated to d) v+1 ).

[0111] Controller 1030 is configured to operate when the current value of the frequency control signal D (i.e., the current frequency control value in the sequence) is the maximum frequency control value V. max The controller 1030 outputs a command signal X at the frequency control output terminal 334. In other words, when the controller 1030 outputs the maximum frequency control value V... max At that time, the controller can output a command signal X. For example, refer to Figure 11A The controller 1030 can be at time t 110 Output command signal X. This will cause the digital feedback circuit 310 to execute an update cycle, while the DCO 110 operates at its maximum instantaneous frequency F. max v(t) is generated. Therefore, the digital feedback circuit 310 will adjust or update the digital feedback signal P in such a way as to reduce or minimize the maximum instantaneous frequency F of the output signal v(t). max With the target frequency value F target The error between them. For example, as previously described, the feedback circuit 310 can measure the instantaneous frequency F. max Determine the measured frequency and the frequency target F. target The error between the two is calculated, and the feedback signal P is then adjusted or updated based on this error. The feedback circuit 310 can operate as described in conjunction with the previously described example, and therefore the detailed operation of the feedback circuit 310 will not be repeated here.

[0112] When the feedback signal P is adjusted, the controller 1030 will adjust the parameter V accordingly. max The value of V. As described above, only the frequency control value V is used.min To V max This generates the frequency control signal D. Therefore, correspondingly, the maximum frequency control value V... max The adjustment will result in a change in the maximum instantaneous frequency F of the output signal v(t). max The corresponding adjustments will result in changes to the bandwidth ΔF and center frequency f of the signal v(t). c Changes occur. For example, if the feedback signal P increases (e.g., from p...). v Change to p v+1 If the controller 1030 increases the maximum frequency control value V accordingly, then the controller 1030 will increase the maximum frequency control value V accordingly. max (e.g. from d) v Change to d v+1 The maximum frequency F of signal v(t). max Therefore it will increase (e.g., from f). v Change to f v+1 This effectively increases the bandwidth ΔF and center frequency f of the signal v(t). c If the feedback signal P decreases (e.g., from p...) v Change to p v-1 The controller 1030 will correspondingly decrease the maximum frequency control value V. max (e.g. from d) v Change to d v-1 The maximum frequency F of signal v(t). max Therefore, it will decrease (e.g., from f). v Change to f v-1 This effectively reduces the bandwidth ΔF and center frequency f of the signal v(t). c If the feedback signal P remains constant (e.g., because the error is within tolerance), the controller 1030 will maintain the maximum frequency control value V. max The bandwidth and center frequency of the signal v(t) remain unchanged.

[0113] Therefore, whenever the controller 1030 outputs a command signal X, the maximum instantaneous frequency F of the signal v(t) is... max With target frequency F target The error between them will be reduced or minimized. Whenever the frequency control signal D is at its maximum value V... max At any given time (or at least some of those times), the controller 1030 can output a command signal X. As time progresses, the oscillator circuit 1000 is able to increase the maximum instantaneous frequency F of the output signal v(t). max Basically maintain the target frequency F target Or, within the tolerance range of the target frequency.

[0114] refer to Figure 12AThe figure shows the initial electromagnetic emission spectrum 1200A of the oscillator output signal v(t) generated by circuit 1000. As shown, the emission spectrum 1200A includes transmission frequency bands 1210, 1220, 1230, and 1240. Transmission frequency band 1210 is the frequency (fundamental frequency) F of the output signal v(t) within the frequency range F. min To F max The modulation results are shown above. Transmission bands 1220, 1230, and 1240 are the results of the second, third, and fourth harmonics of the output signal v(t), respectively. Although not shown, the transmission may include additional transmission bands caused by further harmonics of the output signal v(t). Even-order harmonics may result in larger or stronger (i.e., higher amplitude) transmission bands due to the common-mode current in circuit 1000 (e.g., in DCO 110).

[0115] like Figure 12A As shown, the transmission frequency band 1240 overlaps with the RF frequency band 990. The transmission frequency band 1240 has a bandwidth of 4ΔF and a center frequency of 4f. c The higher frequency 4F centered on max and lower frequency 4F min The higher frequency of the RF band 990 is 4F. max Initially greater than the lower frequency f RF-L This means that over time, the signal v(t) will be modulated to an instantaneous frequency within the RF band 990. As previously described, this could interfere with the wireless signals transmitted or received by the RF transceiver.

[0116] Target frequency F target It can be selected as satisfying condition k*F target < f RF-L In this case, k = 4. Using circuit 1000, the maximum frequency F of signal v(t) is... max It can basically maintain the target frequency F target Or, within the tolerance range of the target frequency. Specifically, whenever DCO 110 at frequency F max During operation (or at least some of these times), the controller 1030 may provide a command signal X to the digital feedback circuit 310. Whenever the digital feedback circuit 310 receives the command signal X, it will execute an update cycle as described above to reduce the frequency F of the output signal v(t). max With target frequency F target The error between them. Over time, this will ensure that the frequency F of the signal v(t) remains constant. max Maintain at the target frequency F target .

[0117] Figure 12BThe emission spectrum 1200B is shown after running one or more update cycles. As shown, the maximum frequency F of the signal v(t) is... max It can be at the target frequency F target Therefore, the fundamental frequency range is adapted to F. min To F target The fourth harmonic emission frequency range of 1240' is now in the 4F range. min To 4F target Between, including 4F target < f RF-L When DCO 110 is in F max During operation, the controller 1030 can continue to output command signal X to run the update cycle, so as to set F max Keep at F target .

[0118] Figure 13 An oscillator circuit 1300 according to another example of this disclosure is shown. Oscillator circuit 1300 is similar to oscillator circuit 1000 (as can be seen at least by the same reference numerals), with the differences described below. Specifically, as described below, oscillator circuit 1300 is capable of simultaneously oscillating the maximum frequency F of signal v(t). max Maintain at the target frequency F target And the minimum frequency F min Maintain at the second target frequency F target2 .

[0119] The oscillator circuit 1300 includes a second digital feedback circuit 310-2. The digital feedback circuit 310-2 has an analog input terminal 312-2 for receiving the output signal v(t). The digital feedback circuit 310-2 is also configured to receive a second target or reference frequency value F at a frequency reference input terminal 314-2. target2 The second command signal X2 is received at control input 316-2. Digital feedback circuit 310-2 is also configured to output a second feedback signal P2 at output 318-2. The function of digital feedback circuit 310-2 is similar to that of digital feedback circuit 310, and therefore will not be described in detail. Furthermore, the characteristics of signals P2, X2, and Ftarget2 are similar to the corresponding signals received / output by digital feedback circuit 310, and therefore will not be described in detail. The first command signal X can be considered as a first control command from the controller, and the second command signal X2 can be considered as a second control command from the controller.

[0120] The oscillator circuit 1300 includes a controller 1330 similar to the controller 1030. However, the controller 1330 also includes a second digital feedback input 332-2 and a second command output 336-2. The controller 1030 receives a second digital feedback signal P2 at input 332-2. The controller 1030 is also configured to provide a second command signal X2 from the second command output 336-2 to the digital feedback circuit 310-2.

[0121] The controller 1330 interprets the value of the feedback signal P2 as an indication of the minimum frequency control value V. min Specifically, as described above, the value of feedback signal P2 indicates the frequency control value. Controller 1330 sets the minimum frequency control value V... min Set to the frequency control value indicated in the value of the feedback signal P2. For example, the feedback signal could have a value p w , where p w The value is from p0 to p N-1 Any one of them. Value p w Indicates the corresponding frequency control value d w The controller 1330 then sets the frequency control value d. w This is interpreted as the minimum frequency control value. Specifically, controller 1330 will set the minimum frequency control value V... min Set to d w Therefore, whenever the value of the feedback signal P2 is updated to a new value (e.g., p...), w+1 When this happens, controller 1030 updates the minimum frequency control value V accordingly. min (For example, updated to d) w+1 ).

[0122] Controller 1330 is configured to operate when the current value of the frequency control signal D (i.e., the current frequency control value in the sequence) is the minimum frequency control value V. min The controller 1330 outputs a command signal X2 at the frequency control output terminal 334. In other words, when the controller 1330 outputs the minimum frequency control value V... min At this time, the controller can output a command signal X2. This will cause the digital feedback circuit 310-2 to perform an update cycle, while DCO 110 operates at a minimum instantaneous frequency F. min This generates v(t). Therefore, the digital feedback circuit 310-2 will adjust or update the digital feedback signal P2 in such a way as to reduce or minimize the minimum instantaneous frequency F of the output signal v(t). min With the target frequency value F target2 The error between them. For example, as previously described, the feedback circuit 310-2 can measure the instantaneous frequency F. min Determine the measured frequency and the frequency target F. target2The error between the two is calculated, and the feedback signal P2 is then adjusted or updated based on this error. The feedback circuit 310-2 can operate as described in conjunction with the previously described example, and therefore the detailed operation of the feedback circuit 310-2 will not be repeated here.

[0123] When the feedback signal P2 is adjusted, the controller 1330 will adjust the parameter V accordingly. min The value of V. As described above, only the frequency control value V is used. min To V max This generates the frequency control signal D. Therefore, correspondingly, the minimum frequency control value V... min The adjustment will result in the minimum instantaneous frequency F of the output signal v(t). min The corresponding adjustments will result in changes to the bandwidth ΔF and center frequency f of the signal v(t). c Changes occur. For example, if the feedback signal P2 increases (e.g., from p...). w Change to p w+1 If the minimum frequency control value V is increased accordingly, then the controller 1330 will increase the minimum frequency control value V accordingly. min (e.g. from d) w Change to d w+1 The minimum frequency F of signal v(t). min Therefore it will increase (e.g., from f). w Change to f w+1 This effectively reduces the bandwidth ΔF and increases the center frequency f of the signal v(t). c If the feedback signal P2 decreases (e.g., from p...), w Change to p w-1 If the minimum frequency control value V is decreased accordingly, then the controller 1330 will decrease the minimum frequency control value V. min (e.g. from d) w Change to d w-1 The minimum frequency F of signal v(t). min Therefore, it will decrease (e.g., from f). w Change to f w-1 This effectively increases the bandwidth ΔF and decreases the center frequency f of the signal v(t). c If the feedback signal P2 remains unchanged (e.g., because the error is within tolerance), the controller 1330 will maintain the minimum frequency control value V. min The bandwidth and center frequency of the signal v(t) remain unchanged.

[0124] Therefore, whenever the controller 1330 outputs the command signal X2, the minimum instantaneous frequency F of the signal v(t) is... min With target frequency F target2 The error between them will be reduced or minimized. Whenever the frequency control signal D is at its minimum value V... minAt any given time (or at least some of these times), controller 1330 may output command signal X2. Over time, oscillator circuit 1000 is able to output the minimum instantaneous frequency F of the output signal v(t). min Basically maintain the target frequency F target2 Or, within the tolerance range of the target frequency.

[0125] refer to Figure 17A This shows the initial electromagnetic emission spectrum 1700A of the output signal v(t) generated by circuit 1300. If the RF transceiver is a multi-band transceiver operating in a second RF band 1790 in addition to RF band 990, as shown, the transmitting RF band 1240 can also overlap with RF band 1790. Specifically, the lower frequency 4F... min Initially, higher frequencies f less than 1790 MHz in the RF band RF-U2 This means that over time, the signal v(t) will be modulated to an instantaneous frequency within the RF band 1790. As previously described, this could interfere with the wireless signals transmitted or received by the RF transceiver.

[0126] Target frequency F target2 It can be selected as satisfying condition k*F target2 > f RF-U2 In this case, k = 4. Using circuit 1300, the minimum frequency F of signal v(t) is... min It can basically maintain the target frequency F target2 Or, within the tolerance range of the target frequency. Specifically, whenever DCO 110 at frequency F min During operation (or at least some of these times), the controller 1330 may provide a command signal X2 to the digital feedback circuit 310-2. Whenever the digital feedback circuit 310-2 receives the command signal X2, it will execute an update cycle as described above to reduce the frequency F of the output signal v(t). min With target frequency F target2 The error between them. Over time, this will ensure that the frequency F of the signal v(t) remains constant. min Maintain at the target frequency F target2 .

[0127] Figure 17B The emission spectrum 1700B is shown after one or more update cycles of the digital feedback circuits 310 and 310-2. As shown, the maximum frequency F of the signal v(t) is... max It can be at the target frequency F target Furthermore, the minimum frequency F of the signal v(t) min It can be at the target frequency F target2Therefore, the fundamental frequency range is adapted to F. target2 To F target The fourth harmonic emission frequency range of 1240' is now in the 4F range. target2 To 4F target Between, including 4F target < f RF-L And 4F target2 > f RF-U2 When DCO 110 is in F max During operation, controller 1330 can continue to output command signal X to run the update cycle, so as to set F max Keep at F target Furthermore, when DCO 110 is in F min During operation, controller 1330 can continue to output command signal X2 to run the update cycle, so as to set F min Keep at F target2 .

[0128] Figure 14 Another example of an oscillator circuit 1400 according to this disclosure is shown. Oscillator circuit 1400 is similar to oscillator circuit 1300, but provides F for simultaneously adjusting the output signal v(t). min and F max Alternative layout options.

[0129] The oscillator circuit 1400 includes a controller 1430 and a digital feedback circuit 1410. The controller 1430 is similar to the controller 1330, but with the following differences. The controller 1430 has a command output 336 for outputting a command signal X (i.e., the second command output 336-2 and the second command signal X2 are omitted). Instead, the controller 1430 has a selection output 1431 configured to output a selection signal S. The selection signal can have a first state (e.g., "0" or low) and a second state (e.g., "1" or high).

[0130] The oscillator circuit 1400 includes an interleaved digital feedback circuit 1410. The digital feedback circuit 1410 is configured to receive a signal v(t) and a target frequency F. target And the command signal X, and output feedback signal P, as described in conjunction with feedback circuit 310. As described in conjunction with feedback circuit 310-2, digital feedback circuit 1410 is also configured to receive a second target frequency F. target2 It also outputs a second feedback signal P2. However, the second command input 316-2 is omitted. Instead, the digital feedback circuit 1410 is configured to receive a selection signal S at the selection input 1417. The digital feedback circuit 1410 is configured to operate in a first mode when the selection signal S is in a first state, and in a second mode when the selection signal S is in a second state.

[0131] When the digital feedback circuit 1410 is in the first mode and receives a command signal X (e.g., a pulse), the digital feedback circuit 1410 will execute an update cycle in the first mode. The digital feedback circuit 1410 will base its update cycle on the signal v(t) and the target frequency F. target The feedback signal P is updated. Specifically, the digital feedback circuit 1410 adjusts or updates the digital feedback signal P in such a way as to reduce or minimize the difference between the current instantaneous frequency of the output signal v(t) and the target frequency value F. target The error between them. When the digital feedback circuit 1410 is in the second mode and receives a command signal X (e.g., a pulse), the digital feedback circuit 1410 performs an update cycle in the second mode. The digital feedback circuit 1410 will base the update cycle on the signal v(t) and the frequency target F. target2 Update the feedback signal P2. Specifically, the digital feedback circuit 1410 will adjust or update the digital feedback signal P2 in such a way as to reduce or minimize the difference between the current instantaneous frequency of the output signal v(t) and the target frequency value F. target2 The error between them.

[0132] The controller 1430 is configured to control the digital feedback circuit 1410 as follows: when the current value of the frequency control signal D (i.e., the current frequency control value in the sequence) is the maximum frequency control value V... max At this time, the controller 1410 sets the selection signal S to the first state and outputs a command signal X (e.g., a pulse). This causes the digital feedback circuit 1410 to perform an update cycle in the first mode, while the DCO 110 operates at the maximum instantaneous frequency F. max v(t) is generated. Therefore, the digital feedback circuit 1410 will adjust or update the digital feedback signal P in such a way as to reduce or minimize the minimum instantaneous frequency F of the output signal v(t). max With the target frequency value F target The error between them. Therefore, in the first mode, the digital feedback circuit 1410 performs the same function as the feedback circuit 310 described previously.

[0133] When the current value of the frequency control signal D (i.e., the current frequency control value in the sequence) is the minimum frequency control value V min At this time, controller 1410 sets the selection signal S to the second state and outputs a command signal X (e.g., a pulse). This causes digital feedback circuit 1410 to perform an update cycle in the second mode, while DCO 110 operates at a minimum instantaneous frequency F. min v(t) is generated. Therefore, the digital feedback circuit 1410 will adjust or update the digital feedback signal P2 in such a way as to reduce or minimize the minimum instantaneous frequency F of the output signal v(t). min With the target frequency value Ftarget2 The error between them. Therefore, in the second mode, the digital feedback circuit 1410 performs the same function as the feedback circuit 310 described previously.

[0134] Whenever DCO 110 reaches its maximum frequency F max During operation (or at least some of these times), controller 1430 can operate feedback circuit 1410 in a first mode. Furthermore, whenever DCO 110 operates at minimum frequency F... max During operation (or at least some of these times), the controller 1430 can operate the feedback circuit 1410 in a second mode.

[0135] In view of the above, the oscillator circuit 1400 can achieve a combination Figure 12A and Figure 12B The same results are described. Advantageously, by operating a single digital feedback circuit 1410 in both modes, hardware resources can be shared, thereby reducing hardware resources, while achieving similar functionality.

[0136] The controller 1430 can be viewed as providing a first control command to the feedback circuit 1410, wherein the controller 1430 sets the selection signal S to a first state and provides a command signal X to cause the feedback circuit 1410 to update the feedback signal p. The controller 1430 can also be viewed as providing a second control command to the feedback circuit 1410, wherein the controller 1430 sets the selection signal S to a second state and provides a command signal X to cause the feedback circuit 1410 to update the second feedback signal P2.

[0137] Figure 15 The digital feedback circuit 1410 is shown in more detail. The digital feedback circuit 1410 is similar to the digital feedback circuit 310, but with the following modifications.

[0138] The digital feedback circuit 1410 includes a multiplexer (MUX) 1520. The MUX 1520 receives the target frequency value F at its first input 1522-1. target And receive the second frequency target value F at the second input terminal 1522-2. target2The output 1526 of MUX 1520 is coupled to the second input 424 of digital subtractor 420. MUX 1520 receives a selection signal S at control input 1524. When selection signal S is in a first state, MUX 1520 provides the target frequency value Ftarget to output 1526 at first input 1522-1. When selection signal S is in a second state, MUX 1520 provides the target frequency value Ftarget2 to output 1526 at second input 1522-2. Therefore, in the first mode of digital feedback circuit 1410, subtractor 420 will determine the frequency estimate F' and the target frequency value F. target The error between them is E, where E = F' – F target In the second mode of the digital feedback circuit 1410, the subtractor 420 will determine the frequency estimate F' and the target frequency value F. target2 The error between them is E, where E = F' – F target2 .

[0139] The digital feedback circuit 1410 includes a feedback signal generator 1530. The feedback signal generator 1530 is similar to the feedback signal generator 430. However, the feedback signal generator 1530 receives a selection signal S at a control input 1531. The feedback signal generator 1530 is also configured to output a second feedback signal P2 at a second output 434-2. When the selection signal S is in a first state, the feedback signal generator 1530 operates in a first mode. When the selection signal S is in a second state, the feedback signal generator 1530 operates in a second mode. In the first mode, the feedback signal generator 1530 adjusts or updates the feedback signal P based on the received error value E, as previously described. For example, as previously described, the feedback signal generator 1530 can increase or decrease the value of the feedback signal P based on the error value E. Therefore, when the feedback circuit 1410 performs an update cycle in the first mode, the feedback signal generator 1530 adjusts the feedback signal P in such a way as to decrease or minimize the instantaneous frequency F. max With the target value F target The error between them. In the second mode, the feedback signal generator 1530 adjusts or updates the feedback signal P2 based on the received error value E, instead of updating the signal P. For example, the feedback signal generator 1530 can increase or decrease the value of the feedback signal P2 based on the error value E, as previously described. Therefore, when the feedback circuit 1410 performs an update cycle in the second mode, the feedback signal generator 1530 adjusts the feedback signal P2 in such a way as to reduce or minimize the instantaneous frequency F. min With the target value F target2 The error between them.

[0140] Advantageously, the feedback circuit 1410 reuses or shares the hardware of the frequency estimator 410 and the digital subtractor 420 between the two operating modes, which can reduce the size and cost of the circuit. The feedback circuit 1410 can also share the hardware of the feedback signal generator 1530 between the two modes.

[0141] Figure 16A The feedback signal generator 1530 is shown in more detail. As shown, the feedback signal generator 1530 is similar to the feedback signal generator 430, but with the following modifications.

[0142] Feedback signal generator 1530 includes a second register 740-2. Input 742-2 is coupled to output 734 of limiter 730. Output 744-2 of register 740-2 corresponds to output 434-2 of the feedback signal generator. Feedback signal generator 1530 also includes a digital AND gate 1610-2. Gate 1610-2 receives an update signal U at a first input and a selection signal S at a second input. Control input 746-2 of register 740-2 receives the output of gate 1610-2. When the output of gate 1610-2 is in a first state (low), register 740-2 stores the signal at its input 742-2. When the output of gate 1610-2 is in a second state (high), register 740-2 updates its output 744-2 (i.e., provides the signal at its input 742-2 to output 744-2). Therefore, when both U and S are in the second state (high), register 740-2 will update its output 744-2.

[0143] The feedback signal generator 1530 also includes a digital AND gate 1610-1. Gate 1610-1 receives an update signal U at its first input and a selection signal S at its second input via a digital inverter 1611. The control input 746 of register 740 receives the output of gate 1610. When the output of gate 1610-1 is in a first state (low), register 740 stores the signal at its input 742. When the output of gate 1610-1 is in a second state (high), register 740 updates its output 744 (i.e., provides the signal from its input 742 to output 744). Therefore, when U is high and S is low, register 740 updates its output 744-2.

[0144] The feedback signal generator 1530 also includes a MUX 1620. The MUX 1620 receives a first feedback signal P at a first input 1622-1 and a second feedback signal P2 at a second input 1622-2. The output 1626 of the MUX 1620 is coupled to the second input 724 of the digital adder 720. The MUX 1620 receives a selection signal S at the control input 1624.

[0145] Figure 16B The feedback signal generator 1530 is shown when in the first mode (i.e., when the digital feedback circuit 1410 performs an update cycle to update the feedback signal P in the first mode). In the first mode, the signal S is in the first state. When S is in the first state, the MUX 1620 provides the current feedback signal P(i) from the first input 1622-1 to the output 1626, and thus to the second input 724 of the adder 720. The adder 720 then generates the updated feedback signal P(i+1), which is then provided to the input 742 of the register 740, as previously described. Then, when the update signal U transitions to the second state (high), the updated feedback signal P(i+1) is provided to the outputs 744 / 434. Meanwhile, since the signal S is in the first state, the output of the gate 1610-2 remains low. Therefore, the register 740-2 is not updated, and thus the feedback signal P2(j) remains unchanged.

[0146] Figure 16C The feedback signal generator 1530 is shown when in the second mode (i.e., when the digital feedback circuit 1410 performs an update cycle to update the feedback signal P2 in the second mode). In the second mode, the signal S is in the second state. When S is in the second state, the MUX 1620 provides the current feedback signal P2(j) from the second input 1622-2 to the output 1626, and thus to the second input 724 of the adder 720. The adder 720 then generates the updated feedback signal P2(j+1) by adding an adjustment value α as previously described. As previously described, the limiter 730 limits the updated feedback signal P2(j+1). The updated feedback signal P2(j+1) is then provided to the input 742-2 of the register 740-2. Then, when the update signal U transitions to the second state (high), the updated feedback signal P2(j+1) will be provided to the outputs 744-2 / 434-2. Meanwhile, since signal S is in the second state, the output of gate 1610-1 remains low. Therefore, register 740 is not updated, and thus the feedback signal P(i) remains unchanged.

[0147] Advantageously, the feedback signal generator 1530 reuses or shares the hardware of the error processor 710, adder 720 and limiter 730 between the two operating modes, which can reduce the size and cost of the circuit.

[0148] Figure 18 An oscillator circuit 1800 according to another example of this disclosure is shown. The oscillator circuit 1800 corresponds to circuit 300 and has the following modifications.

[0149] Controller 1830 corresponds to controller 330. However, controller 1830 is also configured to generate a pulse width modulation (PWM) clock signal. The PWM signal is used to modulate the output v(t) of DCO 110 according to an on / off keying (OOK) modulation scheme. The PWM signal is as follows: Figure 19 As shown. The PWM signal has T en The period and frequency F en The PWM signal also has a variable duty cycle of x%. For each cycle of the PWM signal, the PWM signal will be in a first state (e.g., low) for (1-x)% of the cycle and in a second state (e.g., high) for x% of the cycle. For example, as... Figure 19 As shown, the duty cycle is x1% during the period from t1 to t3. This causes the PWM signal to be in the second state ("high") between times t1 and t2, and in the first state ("low") between times t2 and t3. During the period from t5 to t7, the duty cycle is x2%, where x2% < x1%. This causes the PWM signal to be in the second state within a relatively short time window t5 to t6. The PWM signal switches between the first and second states.

[0150] Controller 1830 is configured to output a PWM signal at output terminal 1839. DCO 110 is configured to receive the PWM signal at enable terminal 109. Therefore, the PWM signal controls the on / off state of DCO 110. Specifically, when the PWM signal is in the first state (low), DCO 110 will be in the off state. When the PWM signal is in the second state (high), DCO 110 will be in the on state. For example, as... Figure 19 As shown, DCO 110 is turned on, and therefore generates signal v(t) between times t1 and t2, while PWM is high. When the PWM signal is low, DCO 110 is turned off between times t2 and t3 and stops generating signal v(t). When the duty cycle decreases to x2%, the output signal v(t) will be at period T. en The output signal v(t) is generated within a shorter portion of the time interval. Therefore, the average power of the output signal v(t) is relatively low between time t5 and t7, and relatively high between time t1 and t3. Therefore, the average power of the output signal v(t) can be adjusted by controlling the duty cycle x%. Typically, the frequency f of the PWM signal... en The minimum possible frequency (i.e., f) below the output signal v(t) en < f0). The duty cycle x% can be considered as defining each cycle T of the PWM signal (and therefore the DCO). en The on-time, and the ratio (x-1)% can be considered as defining the PWM signal (and therefore the DCO) for each cycle T. enThe off time. The DCO responds to the PWM signal by switching between on and off states.

[0151] In some examples, the output signal v(t) can be used to power a load. The load can be timed by a clock signal CLK having the same frequency as the PWM signal. The load can perform operations in response to the falling edge of the clock signal CLK. As shown in Figure 9, as a result of the PWM signal, DCO 110 is turned off before each falling edge of the clock signal CLK. Advantageously, this prevents the output signal v(t) from interfering with the operation performed by the load on the falling edge of the clock signal CLK.

[0152] It should be understood that in some examples, the PWM signal is not pulse width modulated, but rather a clock signal that may have a fixed duty cycle (e.g., 50% or others).

[0153] The controller 1830 is configured to output a command signal X when the PWM signal is high (i.e., when DCO 110 is on). This ensures that the digital feedback circuit 310 performs the update cycle only when DCO 110 is on. Specifically, this ensures that the frequency estimator can correctly estimate the frequency of the oscillation signal v(t). Otherwise, if the digital feedback circuit 310 attempts to perform the update cycle when DCO 110 is off, the digital feedback circuit will attempt to adjust the feedback signal based on invalid frequency measurements of the signal v(t) (e.g., measurements based on the DC "off" value of the signal v(t)).

[0154] In some examples, controller 1830 is configured to operate when the current duty cycle x% is higher than a threshold ratio x. thresh The command signal is output under further conditions. This ensures that the DCO 110 is turned on for a sufficiently long time to allow the digital feedback circuit 310 to estimate the frequency of the signal v(t) during the estimation time window.

[0155] It should be understood that the previously described controllers 1030 / 1330 / 1430 can also be configured to provide a PWM signal to the enable input of DCO 110. Therefore, these controllers can output command signals X and X2 under the further condition that the PWM signal is high when command signals X and X2 are output (i.e., DCO 110 is on at that time). As described above, when the current duty cycle x% is higher than the threshold ratio x... thresh Under further conditions, the controller may optionally output command signals X and X2.

[0156] It should be understood that in some examples, the PWM signal is not received from the controller, but rather from other external circuitry.

[0157] Figure 20An oscillator circuit 2000 according to another example of this disclosure is shown. As described below, the oscillator circuit 300 is capable of maintaining the instantaneous frequency F of the output signal v(t) substantially at a target frequency F. target Or at least within the tolerance range of the target frequency.

[0158] In the oscillator circuit 2000, the feedback signal output by the digital feedback circuit 310 is the offset control signal G. Specifically, the digital feedback circuit 310 directly outputs the offset control signal G at its output terminal 318. The DCO 110 receives the offset control signal G at its offset control input terminal 106. When the feedback circuit 310 executes an update cycle, the digital feedback circuit 310 updates the value of the offset control signal G. Specifically, the digital feedback circuit 310 adjusts or updates the offset control signal G in such a way as to reduce or minimize the difference between the instantaneous frequency F of the output signal v(t) and the target frequency value F. target The error between them. When the offset control signal G is adjusted, DCO 110 will correspondingly adjust the frequency offset applied to the output v(t), which will cause the instantaneous frequency F of the output signal v(t) to be adjusted. For example, increasing the value of the offset control signal G (e.g., from g...) m Change to g m+1 This will result in a corresponding increase in the instantaneous frequency F of the output signal v(t) (e.g., from f). n + δf m Change to f n + δf m+1 Decrease the value of the offset control signal G (e.g., from g). m Change to g m-1 This will result in a corresponding decrease in the instantaneous frequency F of the output signal v(t) (e.g., from f). n + δf m Change to f n + δf m-1 Therefore, whenever the feedback circuit 310 receives a command signal X (e.g., from the controller), the instantaneous frequency of the output signal v(t) is different from the target frequency F. target The error between them will be reduced or minimized. Feedback circuit 310 can receive command signal X periodically (e.g., at regular intervals) or at irregular intervals. In either case, over time, oscillator circuit 2000 is able to maintain the instantaneous frequency F of the output signal v(t) substantially at the target frequency F. target Or, within the tolerance range of the target frequency. Therefore, the oscillator circuit 2000 can achieve a combination Figure 9A and Figure 9B The same result as described.

[0159] The digital feedback circuit 310 can operate as previously described, but updates the offset control signal G instead of the feedback signal P. Specifically, as previously described, the same components with equivalent functionality can be arranged. Therefore, the detailed function of the feedback circuit 310 in the oscillator circuit 2000 will not be repeated.

[0160] Figure 21 An oscillator circuit 2100 according to another example of this disclosure is shown. The oscillator circuit 2100 shows that the oscillator circuit 2000 can be used with a controller 2130, which controls the DCO 110 according to a spread spectrum modulation scheme. Specifically, the controller 2130 can generate a frequency control signal D, as V min With V max The sequence of values ​​between, as previously described. Therefore, controller 2130 will output command signal X under the conditions previously described. Specifically, if circuit 2100 wants to output the maximum frequency F of signal v(t), max Stay at target F target Then when the current value of signal D corresponds to V max At that time, the controller 2130 can output a command signal X. Over time, the maximum frequency Fmax will remain at the target F... target For example, refer to Figure 22 This shows the emission spectrum of signal v(t) after one or more update cycles. The update offset control signal G will effectively shift the center frequency f of the transmission frequency band 2210'-2240'. c Because the update cycle is performed only when the signal v(t) is at frequency Fmax, the center frequency will shift in such a way as to minimize Fmax. max With F target The error between them.

[0161] Circuit 2100 can also be used to convert the minimum frequency F of signal v(t) min Stay at target F target In this case, when the current value of signal D corresponds to V min At this time, the controller 2130 can output a command signal X.

[0162] Oscillator circuit 2100 also shows that oscillator circuit 2000 can be used with controller 2130, which uses a PWM signal (PWM) to perform OOK modulation of DCO 110. In this case, controller 2130 can output command signal X under the further condition that the PWM signal is currently high (i.e., during the on-time of the PWM signal, and DCO 110 is on). Optionally, controller 2130 can output command signal X when the duty cycle x% is higher than a threshold x. thresh Under further conditions, output command signal X.

[0163] Figure 23 Another example of an oscillator circuit 2300 according to this disclosure is shown. Oscillator circuit 2300 is similar to oscillator circuit 2000. However, digital feedback circuit 310 is used to directly update the frequency control signal D to minimize the frequency F of signal v(t) from the target F. target The error between them.

[0164] In the oscillator circuit 2300, the feedback signal output by the digital feedback circuit 310 is the frequency control signal D. Specifically, the digital feedback circuit 310 directly outputs the frequency control signal D at its output terminal 318. The DCO 110 receives the frequency control signal D at its frequency control input terminal 102. When the feedback circuit 310 executes an update cycle, it updates the value of the frequency control signal D. Specifically, the digital feedback circuit 310 adjusts or updates the frequency control signal D in such a way as to reduce or minimize the difference between the instantaneous frequency F of the output signal v(t) and the target frequency value F. target The error between them. When the frequency control signal D is adjusted, DCO 110 will adjust the frequency of the output v(t) accordingly, which will cause the instantaneous frequency F of the output signal v(t) to be adjusted. For example, increasing the value of the frequency control signal D (e.g., from d...) n Change to d n+1 This will result in a corresponding increase in the instantaneous frequency F of the output signal v(t) (e.g., from f). n Change to f n+1 Decrease the value of the frequency control signal D (e.g., from d). n Change to d n-1 This will result in a corresponding decrease in the instantaneous frequency F of the output signal v(t) (e.g., from f). n Change to f n-1 Therefore, whenever the feedback circuit 310 receives a command signal X (e.g., from the controller), the instantaneous frequency of the output signal v(t) is different from the target frequency F. target The error between them will be reduced or minimized. Feedback circuit 310 can receive command signal X periodically (e.g., at regular intervals) or at irregular intervals. In either case, over time, oscillator circuit 2300 is able to maintain the instantaneous frequency F of the output signal v(t) substantially at the target frequency F. target Or, within the tolerance range of the target frequency. Therefore, the oscillator circuit 2300 can achieve a combination Figure 9A and Figure 9B The same result as described.

[0165] The digital feedback circuit 310 can operate as previously described, but updates the frequency control signal D instead of the feedback signal P. Specifically, as previously described, the same components with equivalent functionality can be arranged. Therefore, the detailed function of the feedback circuit 310 in the oscillator circuit 2300 will not be repeated.

[0166] Figure 24 Another example of an oscillator circuit 2400 according to this disclosure is shown. Oscillator circuit 2400 is also shown to be used with controller 2430, which uses a PWM signal (PWM) to perform OOK modulation of DCO 110. In this case, controller 2430 can output a command signal X under the further condition that the PWM signal is currently high (i.e., during the on-time of the PWM signal, and DCO 110 is on). Optionally, controller 2430 can output a command signal X when the duty cycle x% is higher than a threshold x. thresh Under further conditions, output command signal X.

[0167] Figure 25 An example DCO 2500 according to this disclosure is shown. The DCO 2500 can be used to implement the DCO 110 as previously described. The output 104 of the DCO 2500 is formed by a first output node 2501 and a second output node 2502. The DCO 2500 includes an LC oscillator circuit 2505. The LC oscillator circuit 2505 is coupled between the output nodes 2501 and 2502 of the DCO 2500. The LC oscillator circuit 2505 is formed by an inductor L and a switchable capacitor bank 2510. In the case of the DCO used for an electrically isolated power transfer circuit as described herein, the inductor L may correspond to the primary winding of a converter used to transfer the oscillator signal across the isolation barrier. Each of the inductor L and the capacitor bank 2510 is connected in parallel between the output nodes 2501 and 2502, and thus in parallel with each other. The DCO 2500 also includes a first MOS transistor M1 and a second MOS transistor M2. In this example, transistors M1 and M2 are N-type MOS transistors; however, it should be understood that P-type MOS transistors may be used alternatively. It should be understood that complementary PMOS / NMOS structures and variations are well known in the literature. The gate of M1 is coupled to output node 2502. The drain of M1 is coupled to output node 2501. The gate of M2 is coupled to output node 2501. The drain of M2 is coupled to output node 2502. The sources of M1 and M2 are coupled to each other at a common node 2520. Switch S1 is coupled at the common node 2520 to the low supply voltage V. SS between.

[0168] The switchable capacitor bank 2510 is configured to provide multiple N capacitors C0 to C1 connected in parallel with the inductor 1.N-1 Any one of them. Specifically, capacitor bank 2510 is configured to receive multiple N digital frequency control values ​​or codes d0 to d0 via frequency control signal D. N-1 Either of them. Capacitor bank 2510 provides the current value d corresponding to the frequency control signal D. n Capacitor C n The instantaneous frequency F of the output signal v(t) is proportional to the capacitance of capacitor bank 2510. Therefore, DCO 2500 corresponds to the capacitance C of capacitor bank 2510. n instantaneous frequency f n Generate an output signal v(t), for example, as Figure 2 As shown. Capacitors C0 to C N-1 With unit capacitance C unit The increment increases. In another example, the capacitance C0 to C... N-1 It can be increased unevenly to produce frequency linear digital control.

[0169] Capacitor bank 2510 consists of N capacitor circuits 250 to 25 N-1 Formation. Capacitor circuit 250 to 25 N-1 They are connected in parallel between output nodes 2501 and 2502. Each capacitor circuit 25 n It can operate in the first switching state, wherein the capacitor circuit 25 n Contributes a unit capacitance C to the total capacitance of capacitor bank 2510 unit Each capacitor circuit is 25. n It can also operate in the second switching state, where capacitor circuit 25n does not contribute any capacitance to capacitor bank 2510. Frequency control value d n Control capacitor circuit 250 to 25 N-1 The state of each of the components causes the capacitor bank 2510 to have a corresponding capacitance C. n Specifically, the frequency control code d n Capacitor circuits can be 250 to 25 n It is in the first switching state, and the capacitor circuit 25 is in the first switching state. n+1 Up to 25 N-1 It is in the second switching state. Therefore, an appropriate number of unit capacitors C are provided between output nodes 2501 and 2502. unit The total generation frequency is f. n The required capacitance C for the output signal v(t) n .

[0170] 25 per capacitor circuit n From the first capacitor C a Second capacitor C bThis is formed with switch S2. Switch S2 is connected in series between the first capacitor Ca and the second capacitor Cb. When switch S2 is closed, capacitor circuit 25... n In the first switching state, the capacitor circuit 25 n Contributes a unit capacitance C to the total capacitance of capacitor bank 2510 unit Unit capacitance C unit It is formed by the series connection of the first capacitor Ca and the second capacitor Cb. When switch S2 is open, capacitor circuit 25 n It is in the second switching state. It should be understood that other switching capacitor arrangements are known and can be used to implement capacitor circuits 250-25. N-1 .

[0171] Switch S1 is configured to receive a PWM signal. When the PWM signal is high, switch S1 is closed. When the enable signal is low, switch S1 is open. When switch S1 is closed, the DCO 2500 will be in the ON state and will operate at a frequency controlled by the value d. n Determined instantaneous frequency f n Output signal v(t). When switch S1 is open, DCO 2500 will be in the off state and will not output signal v(t).

[0172] Figure 26 Another example of this disclosure, DCO 2600, is shown. Figure 26 This demonstrates how the DCO 2500 can be modified to apply a frequency offset to the output signal v(t) based on the frequency offset control signal G.

[0173] The DCO 2600 also includes M capacitor circuits 260 to 26 M-1 A capacitor bank 2610 is formed. The capacitor bank 2610 is connected in parallel with the capacitor bank 2510 and the inductor L. The capacitor bank 2610 provides additional M capacitors C0 to C10 connected in parallel with the capacitor bank 2510 and the inductor L. M-1 Specifically, capacitor bank 2610 is configured to receive multiple M digital offset control values ​​or codes g0 to g0 via offset control signal G. M-1 Either of them. Capacitor bank 2610 provides the current value g corresponding to the offset control signal D. m Capacitor C m The instantaneous frequency F of the output signal v(t) is proportional to the capacitance of capacitor bank 2510. Therefore, DCO2500 outputs a signal with an instantaneous frequency f. n + δf m Generate an output signal v(t), where δf m The capacitance C corresponding to capacitor bank 2610 mCapacitor bank 2610 is similar to capacitor bank 2510. Specifically, capacitor circuits 260 to 26... M-1 The capacitor circuit is similar to that of capacitor bank 2510, and therefore will not be described in detail.

[0174] Figure 27 Another example of this disclosure, DCO 2700, is shown. Figure 27 Another example is shown of how the DCO 2500 can be modified to apply a frequency offset to the output signal v(t) based on the frequency offset control signal G.

[0175] The DCO 2700 includes a first variable capacitor C series coupled between output nodes 2501 and 2502. v1 Second variable capacitor C v2 capacitor C v1 With C v2 They share a common node 2710. Capacitor C v1 and C v2 This can be a varactor diode tuned capacitor. The DCO 2700 also includes a digital-to-analog converter (DAC) 2720. DAC 2720 receives an offset control signal G at its input. DAC 2720 converts the offset control signal into an analog voltage signal g(t). The analog signal g(t) is provided to a common node 2720 so that the corresponding frequency offset is applied to the output signal v(t). DAC 2720 can be any type of DAC.

[0176] Figure 28 Another example DCO 2800 of this disclosure is shown. In the DCO 2800, a delta-sigma DAC 2820 is used in conjunction with a low-pass filter (LPF) 2825. Specifically, the DAC 2820 receives the offset control signal G and converts it into a delta-sigma output signal. The LPF 2825 low-pass filters the output of the DAC 2820. The low-pass filtered signal is then provided from the output of the LPF to node 2710. Here, the resolution of the offset adjustment is determined by the effective resolution of the delta-sigma DAC 2820, while quantization noise is filtered by the low-pass filter. Advantageously, very high offset resolution can be easily obtained using well-known delta-sigma techniques.

[0177] Figure 29An example of how the oscillator circuit of this disclosure can be used in an electrically isolated power delivery circuit 2900 is shown. The power delivery circuit 2900 includes a first circuit region or domain 2920A and a second circuit region 2920B. The first circuit region 2920A is electrically isolated from the second circuit region 2920B via an electrical isolation barrier 2903. The first circuit region 2920A includes an oscillator circuit 2930. The oscillator circuit 2930 can be any oscillator circuit described herein and outputs an oscillator output signal v(t). The circuit 2900 includes a transformer 2901. The transformer 2901 receives the signal v(t) at its primary winding and transmits it across the isolation barrier 2903 to its secondary winding. The transmitted signal is denoted as v'(t). The second circuit region 2920B of the circuit 2900 includes a rectifier 2905 that receives and rectifies the (AC) signal v'(t) to generate and output a DC voltage source V. DC The DC voltage VDC is then supplied to the energized circuit 2907, which is included in the second circuit region 2920B of circuit 2900. Therefore, the oscillator circuit 2930 is used to supply power to the energized circuit 2907 across the isolation barrier 2903.

[0178] In some examples, circuit 2900 also includes feedback circuit 2909. Feedback circuit 2909 implements a feedback loop to maintain the power level supplied to energizing circuit 2907 at a predetermined or target power level. Specifically, feedback circuit 2909 generates a PWM signal to maintain the power level at the target power level. The PWM signal is provided to oscillator circuit 2930 and controls the on / off keying (OOK) modulation of the DCO of oscillator circuit 2930, as described herein. Therefore, as previously described, the average power of signal v(t) will depend on the duty cycle of the PWM signal. Feedback circuit 2909 thus controls the duty cycle of the PWM signal to meet the target power level of energizing circuit 2907. Feedback circuit 2909 includes a first circuit 2911 in second circuit region 2920B, which determines the DC voltage V. DCThe error between the reference voltage indicating the target power level and the input voltage is determined using a comparator. Circuit 2911 then encodes the error into an AC signal e(t). Circuit 2909 includes a transformer 2913, whose primary winding in the second circuit region 2920B receives the signal e(t). Transformer 2913 transmits the signal e(t) across isolation barrier 2903, where the transmitted signal is represented as e'(t). Circuit 2909 includes a second circuit 2915 in the first circuit region 2920A, which receives the transmitted error signal e'(t). Circuit 2915 decodes the error from the signal e'(t) and adjusts the PWM signal based on the error to minimize it. Therefore, the average power of the signal v(t) is adjusted accordingly, resulting in the voltage V received at the energized circuit 2907 being adjusted in such a way that... DC Adjustments to reduce voltage V DC The error between the reference voltage and the reference voltage.

[0179] It should be understood that the circuits described herein can be implemented as integrated circuits in FPGAs and / or chip-scale packages.

Claims

1. An oscillator circuit, the oscillator circuit comprising: a controller configured to generate a frequency control signal, the frequency control signal comprising a first frequency control value; a digitally controlled oscillator (DCO) configured to generate an oscillator output signal based on the frequency control signal, wherein the output signal is generated at a first frequency in response to the first frequency control value of the frequency control signal; and a digital feedback circuit configured to receive the output signal and output a first feedback signal, wherein the oscillator circuit is configured such that the first frequency depends on or is at least partially based on a value of the first feedback signal, wherein the controller is configured to provide a first control instruction to instruct the digital feedback circuit to update the first feedback signal, wherein the digital feedback circuit is configured to respond to the first control instruction by: measuring the first frequency of the output signal; and adjusting the value of the first feedback signal to reduce an error between the first frequency and a first target frequency.

2. The oscillator circuit of claim 1, wherein the controller is configured to provide the first control instruction to the digital feedback circuit non-continuously or aperiodically.

3. The oscillator circuit of claim 1 or 2, wherein the digital feedback circuit is configured to adjust the value of the first feedback signal in response to an update control instruction, optionally wherein the controller is configured to provide the update control instruction at a different time than the first control instruction.

4. The oscillator circuit of any preceding claim, wherein the frequency control signal comprises a sequence of discrete frequency control values ranging from the first frequency control value to a second frequency control value, wherein the DCO is configured to generate the output signal at an instantaneous frequency corresponding to a current value of the frequency control signal, wherein the controller is configured to provide the first control instruction when the current value of the frequency control signal corresponds to the first frequency control value.

5. The oscillator circuit of claim 4, wherein the oscillator circuit further comprises a second digital feedback circuit configured to receive the output signal and output a second feedback signal, wherein the controller is configured to receive the first feedback signal and the second feedback signal and generate the frequency control signal based on the first feedback signal and the second feedback signal, wherein the first frequency control value is proportional to the value of the first feedback signal and the second frequency control value is proportional to a value of the second feedback signal, wherein the output signal is generated at a second frequency in response to the second frequency control value of the frequency control signal, ​ wherein the controller is further configured to provide a second control instruction to instruct the second digital feedback circuit to update the second feedback signal, wherein the controller is configured to provide the second control instruction when the current value of the frequency control signal corresponds to the second frequency control value, wherein the second digital feedback circuit is configured to update the second feedback signal in response to the second control instruction: measure the second frequency of the output signal; and adjust the value of the second feedback signal to reduce an error between the second frequency and a second target frequency.

6. The oscillator circuit of any preceding claim, wherein the digital feedback circuit is configured to respond to the first control instruction by: measuring the first frequency over a time window initiated by the first control instruction, determining an error between the first frequency and the first target frequency; and adjusting the value of the first feedback signal based on the determined error.

7. The oscillator circuit of claim 6, wherein adjusting the value of the first feedback signal comprises one of: increasing the value of the first feedback signal if the error indicates that the first frequency is less than the first target frequency, and decreasing the value of the first feedback signal if the error indicates that the first frequency is greater than the first target frequency; increasing the value of the first feedback signal if the error indicates that the first frequency is less than the first target frequency by a first threshold amount, and decreasing the value of the first feedback signal if the error indicates that the first frequency is greater than the first target frequency by a second threshold amount; or if the error is greater than a previous error between the first frequency and the first target frequency, then: increasing the value of the first feedback signal if the error indicates that the first frequency is less than the first target frequency, and decreasing the value of the first feedback signal if the error indicates that the first frequency is greater than the first target frequency by a first threshold amount; and if the error is less than the previous error, then: increasing the value of the first feedback signal if the error indicates that the first frequency is greater than the first target frequency by a second threshold amount, and decreasing the value of the first feedback signal if the error indicates that the first frequency is greater than the first target frequency.

8. The oscillator circuit of claim 4, wherein the digital feedback circuit is configured to output a second feedback signal, wherein the controller is further configured to receive the first feedback signal and the second feedback signal, and to generate the frequency control signal based on the first feedback signal and the second feedback signal, wherein the first frequency control value is proportional to the value of the first feedback signal and the second frequency control value is proportional to a value of the second feedback signal, wherein the output signal is generated at the second frequency in response to the second frequency control value of the frequency control signal, ​ wherein the controller is configured to provide the first control instruction when the current value of the frequency control signal corresponds to the first frequency control value, and to provide a second control instruction to instruct the digital feedback circuit to update the second feedback signal, wherein the controller provides the second control instruction when the current value of the frequency control signal corresponds to the second frequency control value, wherein the digital feedback circuit is configured to respond to the second control instruction by: measuring the second frequency of the output signal; and adjusting the value of the second feedback signal to reduce an error between the second frequency and a second target frequency.

9. The oscillator circuit of claim 8, wherein the digital feedback circuit is configured to: in response to the first control instruction: measure, using a frequency estimation circuit, the first frequency over a time window initiated by the first control instruction, determining an error between the first frequency and the first target frequency using a digital subtractor; and adjust the value of the first feedback signal based on the determined error; and in response to the second control instruction: measure, using the frequency estimation circuit, the second frequency over a time window initiated by the second control instruction, determine, using the digital subtractor, an error between the second frequency and a second target frequency; and adjust the value of the first feedback signal based on the determined error, optionally wherein the digital feedback circuit further comprises a multiplexer configured to provide the first target frequency to the subtractor in response to the first control instruction, and to provide the second target frequency to the subtractor in response to the second control instruction.

10. The oscillator circuit of claim 9, wherein the digital feedback circuit is configured to: in response to the first control instruction: generate, using an error processing circuit and based on the error between the first frequency and the first target frequency, an adjustment value indicative of a desired adjustment to the value of the first feedback signal to reduce the error, and adjust the first feedback signal by adding the adjustment value to the first feedback signal using a digital adder; and in response to the second control instruction: generate, using the error processing circuit and based on the error between the second frequency and the second target frequency, an adjustment value indicative of a desired adjustment to the value of the second feedback signal to reduce the error, and adjust the second feedback signal by adding the adjustment value to the second feedback signal using a digital adder, optionally wherein the digital feedback circuit further comprises: a first output configured to output the first feedback signal and a second output configured to output the second feedback signal; and a multiplexer configured to provide the first feedback signal from the first output to the adder in response to the first control instruction, and to provide the second feedback signal from the second output to the adder in response to the second control instruction.

11. The oscillator circuit of any preceding claim, wherein the controller is configured to provide a clock signal to the DCO, wherein the DCO is configured to switch between an on state and an off state in response to the clock signal; and wherein the controller is configured to provide the first control instruction when the DCO is in the on state.

12. The oscillator circuit of claim 11, wherein the clock signal is a pulse width modulated (PWM) clock signal, the PWM signal having a duty cycle defining an on time of the PWM signal, wherein the DCO is configured to be in the on state during the on time of the PWM signal, optionally wherein the controller is configured to provide the first control instruction when the DCO is in the on state and when the duty cycle of the PWM signal is above a threshold duty cycle.

13. The oscillator circuit of any preceding claim, wherein the DCO is configured to receive the first feedback signal and apply a frequency offset to the output signal based on the first feedback signal, wherein the frequency offset is proportional to the value of the first feedback signal.

14. An oscillator circuit, the oscillator circuit comprising: a digitally controlled oscillator (DCO) configured to generate an oscillator output signal at a first frequency; a digital feedback circuit configured to receive the output signal and output a feedback signal, wherein the DCO is configured to receive the feedback signal, and wherein the first frequency of the output signal is based at least in part on a value of the feedback signal; wherein the digital feedback circuit is configured to, in response to a control instruction: measure the first frequency of the output signal; and adjust the value of the feedback signal to reduce an error between the first frequency and a target frequency.

15. The oscillator circuit of claim 14, further comprising a controller, wherein the controller is configured to provide a clock signal to the DCO, wherein the DCO is configured to switch between an on state and an off state in response to the clock signal; and wherein the controller is configured to provide the control instruction to the digital feedback circuit when the DCO is in the on state.

16. The oscillator circuit of any of claims 14 or 15, wherein the DCO is configured to: receive a frequency control signal comprising a first frequency control value, wherein the output signal is generated at the first frequency in response to the first frequency control value of the frequency control signal; and apply a frequency offset to the output signal based on a first feedback signal, wherein the frequency offset is proportional to a value of the first feedback signal.

17. The oscillator of claim 16, wherein the frequency control signal comprises a sequence of discrete frequency control values ranging from the first frequency control value to a second frequency control value, wherein the DCO is configured to generate the output signal at an instantaneous frequency corresponding to a current value of the frequency control signal, wherein the controller is configured to provide the control instruction to the digital feedback circuit when the current value of the frequency control signal corresponds to the first frequency control value.

18. The oscillator of any one of claims 14 to 15, wherein the DCO is configured to generate the output signal at the first frequency in response to the value of the feedback signal, wherein the first frequency is proportional to the value of the feedback signal.

19. A method of generating an oscillator output signal, the method comprising: generating an oscillator output signal based on a frequency control signal, the frequency control signal comprising a first frequency control value, wherein the output signal is generated at a first frequency in response to the first frequency control value of the frequency control signal, wherein the first frequency depends on or is based at least in part on a value of a first feedback signal; and in response to a first control instruction: measuring the first frequency of the output signal; and adjusting the value of the first feedback signal to reduce an error between the first frequency and a first target frequency.

20. A method of generating an oscillator output signal, the method comprising: generating an oscillator output signal at a first frequency based on a feedback signal, wherein the first frequency of the output signal is based at least in part on a value of the feedback signal; in response to a control instruction: measuring the first frequency of the output signal; and adjusting the value of the feedback signal to reduce an error between the first frequency and a target frequency. ​

Images