Silicon carbide epitaxial wafer and preparation method thereof

Abstract

The invention provides a silicon carbide epitaxial wafer and a preparation method thereof. The preparation method of the silicon carbide epitaxial wafer comprises the following steps: providing a silicon carbide substrate, and placing the silicon carbide substrate in a reaction cavity; controlling the reaction cavity to perform first heating so as to relieve initial stress in the silicon carbide substrate; controlling the reaction cavity to cool for the first time so as to eliminate stress in the silicon carbide substrate; controlling the reaction cavity to perform second heating; and growing an epitaxial layer on the surface of the silicon carbide substrate. According to the preparation method provided by the invention, a heating-cooling-heating annealing mode is adopted before epitaxial growth, and the stress in the silicon carbide substrate can be eliminated, so that the warping degree of the silicon carbide substrate and the epitaxial layer is reduced, the thickness uniformity of the epitaxial layer is improved, and the overall quality of the epitaxial wafer is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and particularly relates to a silicon carbide epitaxial wafer and a preparation method thereof. BACKGROUND

[0002] As a key basic material for manufacturing silicon carbide devices, the quality of the silicon carbide epitaxial wafer directly affects the performance of the final device. The thickness uniformity and the doping concentration uniformity of the epitaxial film in the silicon carbide epitaxial wafer determine the performance of the power chip. For example, good thickness uniformity can ensure uniform and stable electric field distribution inside the device, so that the device exhibits excellent voltage resistance performance under high voltage working conditions, thereby ensuring safe and efficient operation of the device in high power applications. Uniform doping concentration can ensure consistent carrier concentration in the active region of the entire power device, which helps to reduce local current concentration and reduce the risk of device performance degradation and failure caused by local overheating.

[0003] However, during the preparation of the silicon carbide crystal, the crystal may grow unevenly, and the silicon carbide substrate may be warped, so that the thickness uniformity of the epitaxial layer cannot meet the increasingly high requirements of semiconductor devices.

[0004] Therefore, how to develop a silicon carbide epitaxial wafer and a preparation method thereof to obtain a silicon carbide epitaxial wafer with good thickness uniformity is a problem to be solved at present. SUMMARY

[0005] The present application provides a silicon carbide epitaxial wafer and a preparation method thereof, aiming to solve the problem of non-ideal thickness uniformity of the epitaxial layer of the existing silicon carbide epitaxial wafer finished product.

[0006] The first embodiment of the present application provides a silicon carbide epitaxial wafer, comprising a silicon carbide substrate and an epitaxial layer arranged on one side of the silicon carbide substrate.

[0007] In the present application, the warpage of the silicon carbide substrate is-30-30 μm, and the warpage of the epitaxial layer is-30-30 μm.

[0008] In some embodiments, the thickness of the epitaxial layer is 9-12 μm, and the thickness uniformity of the epitaxial layer is 0-2.0%.

[0009] In some embodiments, the epitaxial layer is doped with nitrogen elements, and the doping concentration of the nitrogen elements is 7.0 x 10 15 -1.2 x 10 16 cm -3 -3.1%.

[0010] The second embodiment of the present application provides a preparation method of a silicon carbide epitaxial wafer, comprising the following steps:

[0011] providing a silicon carbide substrate;

[0012] controlling the reaction chamber to perform a first temperature rise to relieve initial stress in the silicon carbide substrate;

[0013] controlling the reaction chamber to perform a first temperature drop to eliminate stress in the silicon carbide substrate;

[0014] controlling the reaction chamber to perform a second temperature rise;

[0015] growing an epitaxial layer on the surface of the silicon carbide substrate.

[0016] In some embodiments, the end temperature of the first temperature rise is T1, the end temperature of the first temperature drop is T2, and the end temperature of the second temperature rise is T3, satisfying:

[0017] 800℃≤T1-T2≤1000℃, and T1=T3.

[0018] In some embodiments, the first temperature rise has a first rate v1, the first temperature drop has a second rate v2, and the second temperature rise has a third rate v3, satisfying:

[0019] v2<v3<v1.

[0020] In some embodiments, the step of providing a silicon carbide substrate further comprises:

[0021] controlling the reaction chamber to have an initial temperature T0, satisfying:

[0022] T2

[0023] In some embodiments, 885℃≤T0≤915℃.

[0024] In some embodiments, 1550℃≤T1≤1650℃.

[0025] In some embodiments, 600℃≤T2≤700℃.

[0026] In some embodiments, 1550℃≤T3≤1650℃.

[0027] In some embodiments, 75℃ / min≤v1≤81.3℃ / min.

[0028] In some embodiments, 52.5℃ / min≤v2≤56.7℃ / min.

[0029] In some embodiments, 70℃ / min≤v3≤76℃ / min.

[0030] In some embodiments, the step of growing an epitaxial layer on the surface of the silicon carbide substrate comprises:

[0031] introducing a growth source and a doping source into the reaction chamber, and depositing at least one epitaxial layer on the surface of the silicon carbide substrate.

[0032] In some embodiments, the growth source comprises a carbon source and a silicon source, the doping source comprises a nitrogen source, and a carrier gas is used.

[0033] In some embodiments, the carbon source comprises at least one of ethylene, propane and methane.

[0034] In some embodiments, the silicon source comprises at least one of trichlorosilane and silane.

[0035] In some embodiments, the doping source comprises at least one of nitrogen and ammonia.

[0036] In some embodiments, the carrier gas comprises hydrogen.

[0037] In some embodiments, the flow rate of the carrier gas is 100-120 slm.

[0038] In some embodiments, the flow rate of the doping source is 135-270 sccm.

[0039] In some embodiments, the flow rate of the carbon source is 20-300 sccm.

[0040] In some embodiments, the flow rate of the silicon source is 100-750 sccm.

[0041] In some embodiments, the flow rate ratio of the carbon source to the silicon source is (0.4-1.0):1.

[0042] In some embodiments, the step of growing an epitaxial layer on the surface of the silicon carbide substrate further comprises:

[0043] controlling the pressure in the reaction chamber to be 80-120 mbar.

[0044] In some embodiments, after the step of growing an epitaxial layer on the surface of the silicon carbide substrate, the method further comprises:

[0045] controlling the reaction chamber to undergo a second temperature drop.

[0046] In some embodiments, the end temperature of the second temperature drop is 885-915℃.

[0047] In some embodiments, the second temperature drop has a fourth rate v4℃ / min, which satisfies: 40℃ / min≤v4≤45℃ / min.

[0048] The present application provides a silicon carbide epitaxial wafer, comprising a silicon carbide substrate and an epitaxial layer arranged on one side of the silicon carbide substrate; wherein the warpage of the silicon carbide substrate is -30-30 μm, and the warpage of the epitaxial layer is -30-30 μm. By controlling the warpage of the silicon carbide substrate and the epitaxial layer in the silicon carbide epitaxial wafer, the thickness uniformity of the epitaxial layer can be effectively coordinated, and thus the overall quality of the epitaxial wafer is improved. The present application provides a preparation method of a silicon carbide epitaxial wafer, comprising the following steps: providing a silicon carbide substrate, placing the silicon carbide substrate in a reaction cavity; controlling the reaction cavity to perform a first temperature rise to relieve the initial stress in the silicon carbide substrate; controlling the reaction cavity to perform a first temperature drop to eliminate the stress in the silicon carbide substrate; controlling the reaction cavity to perform a second temperature rise; and growing an epitaxial layer on the surface of the silicon carbide substrate. The preparation method provided by the present application adopts the annealing mode of temperature rise-temperature drop-temperature rise before epitaxial growth, which can eliminate the stress in the silicon carbide substrate, thereby reducing the warpage of the silicon carbide substrate and the epitaxial layer, and further improving the thickness uniformity of the epitaxial layer and the overall quality of the epitaxial wafer. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0050] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0051] Figure 1 The epitaxial layer test point map provided by the present application;

[0052] Figure 2 The thickness test trend graph of the epitaxial wafer provided by the present application Example 1 and Comparative Example 1;

[0053] Figure 3 The thickness test trend graph of the epitaxial wafer provided by the present application Example 2 and Comparative Example 2;

[0054] Figure 4 The thickness test trend graph of the epitaxial wafer provided by the present application Example 3 and Comparative Example 3;

[0055] Figure 5 The doping concentration test trend graph of the epitaxial wafer provided by the present application Example 1 and Comparative Example 1;

[0056] Figure 6A doping concentration test trend chart of the epitaxial wafer provided for the present application embodiment 2 and comparative example 2 is shown in the following table;

[0057] Figure 7 A doping concentration test trend chart of the epitaxial wafer provided for the present application embodiment 3 and comparative example 3 is shown in the following table. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0059] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or electrically connected, or it can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. In the description of the present application, the meaning of "multiple" is two or more than two, unless otherwise explicitly specified and limited. In addition, the terms "first", "second" are for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can be explicitly or implicitly included one or more features.

[0060] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application.

[0061] In the process of preparing silicon carbide crystal, due to the temperature gradient in the axial and radial directions of the crystal, the growth rate of each part of the crystal is inconsistent, and uneven growth will produce stress in the crystal; in addition, various defects in the crystal will also produce stress around the defects; and in the process of growing silicon carbide epitaxial layer, due to the high temperature environment, the stress existing in the silicon carbide substrate will cause the substrate to warp, and the contact with the heating base is uneven, so that the temperature distribution on the surface of the substrate is uneven, resulting in poor thickness uniformity and temperature distribution uniformity of the epitaxial layer, and further resulting in uneven doping concentration.

[0062] The first embodiment of the present application provides a silicon carbide epitaxial wafer, comprising a silicon carbide substrate and an epitaxial layer arranged on one side of the silicon carbide substrate;

[0063] The warping degree of the silicon carbide substrate is -30-30 μm, and the warping degree of the epitaxial layer is -30-30 μm.

[0064] It can be understood that the warping degree of the silicon carbide substrate (unit: μm) can be any one of -30, -20, -10, 0, 10, 20, 30 or a range between any two values. The warping degree of the epitaxial layer (unit: μm) can be any one of -30, -20, -10, 0, 10, 20, 30 or a range between any two values. When the warping degree of the silicon carbide substrate in the silicon carbide epitaxial wafer meets the above value range, it can be in uniform contact with the heating base in the epitaxial furnace, effectively coordinating the thickness uniformity of the epitaxial layer, and controlling the warping degree of the epitaxial layer in the ideal range, which can further control the thickness uniformity of the whole epitaxial wafer, and further improve the overall quality of the epitaxial wafer.

[0065] In some embodiments, the thickness of the epitaxial layer is 9-12 μm, and the thickness uniformity of the epitaxial layer is 0-2.0%.

[0066] It can be understood that the thickness of the epitaxial layer (unit: μm) can be any one of 9, 10, 11, 12 or a range between any two values. The thickness uniformity of the epitaxial layer can be any one of 0%, 0.4%, 0.8%, 1.2%, 1.6%, 2.0% or a range between any two values. When the thickness of the epitaxial layer meets the above value range, it can ensure that the epitaxial wafer has good voltage resistance and conductivity, while avoiding the process adaptability from being reduced due to the over-thickness of the epitaxial layer. On the one hand, the thickness uniformity of the epitaxial layer will affect the process compatibility of the epitaxial wafer, and on the other hand, it will also affect the uniformity of the doping element concentration. When the thickness uniformity of the epitaxial layer meets the above value range, it can ensure that the internal electric field distribution of the device is uniform and stable, so that the device exhibits excellent voltage resistance performance under high voltage working conditions, while ensuring that the concentration of the doping element in the epitaxial layer also has good uniformity, further improving the electrical performance of the epitaxial wafer.

[0067] In some embodiments, the epitaxial layer is doped with nitrogen element, the doping concentration of the nitrogen element is 7.0×10 15 -1.2×10 16 cm -3 , and the doping concentration uniformity of the nitrogen element is 0-3.1%.

[0068] It can be understood that the doping concentration of the nitrogen element (unit: cm -3 ) can be any one of 7.0×10 15 , 8.0×10 159.0×10 15 1.0×10 16 1.1×10 16 1.2×10 16 The uniformity of nitrogen doping concentration can be any value or any two values ​​within the range specified in the table. This means that the uniformity of nitrogen doping concentration can be any value or any two values ​​within the range specified in the table. When the nitrogen doping concentration meets the above range, it can effectively increase the carrier concentration in the epitaxial layer, thereby giving the epitaxial layer an ideal resistivity. Furthermore, when the uniformity of nitrogen doping concentration meets the above range, it can ensure a consistent carrier concentration throughout the active region of the power device, helping to reduce local current concentration and decrease the risk of device performance degradation and failure due to local overheating.

[0069] The second embodiment of this application provides a method for preparing a silicon carbide epitaxial wafer, comprising the following steps:

[0070] A silicon carbide substrate is provided, and the silicon carbide substrate is placed inside the reaction chamber;

[0071] The reaction chamber is heated for the first time to relieve the initial stress in the silicon carbide substrate;

[0072] The reaction chamber is cooled for the first time to eliminate stress in the silicon carbide substrate;

[0073] The reaction chamber is heated a second time.

[0074] An epitaxial layer is grown on the surface of a silicon carbide substrate.

[0075] Understandably, during the fabrication of silicon carbide substrates, residual mechanical stress and some lattice distortion regions exist within the substrate. The first heating process allows the atoms in these distorted regions to rearrange, activating lattice movement and initially relaxing the local stress in the substrate through dislocation slip or climb. Subsequently, the first cooling process allows the silicon carbide substrate lattice to re-achieve thermodynamic equilibrium under low stress, thus fixing this low-stress state. Finally, the second heating process brings the reaction chamber to the temperature required for epitaxial layer growth, providing a stable substrate platform and suppressing the chain reaction of uneven epitaxial layer growth caused by stress within the silicon carbide substrate. This improves the consistency of the electrical properties of the epitaxial wafer.

[0076] In some embodiments, the endpoint temperature of the first heating is T1, the endpoint temperature of the first cooling is T2, and the endpoint temperature of the second heating is T3, satisfying:

[0077] 800℃≤T1-T2≤1000℃, and T1=T3.

[0078] It can be understood that the end temperature T1 of the first temperature rise is also the start temperature of the first temperature drop, and the value (unit: ℃) of T1-T2 can be any one of 800, 850, 900, 950, 1000 or a range between any two values. By controlling the temperature difference of the first temperature drop stage to meet the above value range, it can be ensured that the thermal dynamics of the silicon carbide substrate overcome the lattice resistance, so that the stress is fully released, while avoiding the generation of secondary stress due to too fast thermal shrinkage, causing new defects. And controlling T1=T3 can make the starting interface of the epitaxial layer growth consistent with the surface structure after stress release, so as to control the warpage of the silicon carbide substrate within the ideal range.

[0079] In some embodiments, the first temperature rise has a first rate v1, the first temperature drop has a second rate v2, and the second temperature rise has a third rate v3, satisfying:

[0080] v2

[0081] It can be understood that by controlling v2

[0082] In some embodiments, the step of placing the silicon carbide substrate in the reaction chamber further comprises:

[0083] The reaction chamber is controlled to have an initial temperature T0, satisfying:

[0084] T2

[0085] It can be understood that controlling the value of the initial temperature T0 to be between T1 and T2 can further ensure that the first temperature drop effectively eliminates the stress in the silicon carbide substrate and reduces the warpage of the silicon carbide substrate.

[0086] In some embodiments, 885℃≤T0≤915℃.

[0087] It can be understood that the value (unit: ℃) of T0 can be any one of 885, 890, 895, 900, 905, 910, 915 or a range between any two values.

[0088] In some embodiments, 1550℃≤T1≤1650℃.

[0089] It can be understood that the value (unit: ℃) of T1 can be any one of 1550, 1570, 1590, 1610, 1630, 1650 or a range between any two values.

[0090] In some embodiments, 600℃≤T2≤700℃.

[0091] It can be understood that the value of T2 (unit: ℃) can be any one of 600, 620, 640, 660, 680, 700 or a range between any two values.

[0092] In some embodiments, 1550℃≤T3≤1650℃.

[0093] It can be understood that the value of T3 (unit: ℃) can be any one of 1550, 1570, 1590, 1610, 1630, 1650 or a range between any two values. When T0, T1, T2 and T3 meet the above value range, it can further ensure that the thermal dynamics of the silicon carbide substrate overcome the lattice resistance, so that the stress is fully released.

[0094] In some embodiments, 75℃ / min≤v1≤81.3℃ / min.

[0095] It can be understood that the value of the first rate v1 (unit: ℃ / min) can be any one of 75, 76, 77, 78, 79, 80, 71.3 or a range between any two values.

[0096] In some embodiments, 52.5℃ / min≤v2≤56.7℃ / min.

[0097] It can be understood that the value of the second rate v2 (unit: ℃ / min) can be any one of 52.5, 53.4, 54.3, 55.2, 56.0, 56.7 or a range between any two values.

[0098] In some embodiments, 70℃ / min≤v3≤76℃ / min.

[0099] It can be understood that the value of the third rate v3 (unit: ℃ / min) can be any one of 70, 71, 72, 73, 74, 75, 76 or a range between any two values. When the first rate v1, the second rate v2 and the third rate v3 meet the above value range, it can effectively eliminate the residual stress in the silicon carbide substrate, so that the silicon carbide substrate maintains the ideal flatness during the temperature change.

[0100] In some embodiments, the step of growing an epitaxial layer on the surface of the silicon carbide substrate comprises:

[0101] The growth source and the doping source are introduced into the reaction cavity to deposit at least one epitaxial layer on the surface of the silicon carbide substrate.

[0102] In some embodiments, the growth source includes a carbon source and a silicon source, the doping source includes a nitrogen source, and a carrier gas is used to carry the nitrogen source.

[0103] In some embodiments, the carbon source includes at least one of ethylene, propane, and methane.

[0104] In some embodiments, the silicon source includes at least one of trichlorosilane and silane.

[0105] In some embodiments, the doping source includes at least one of nitrogen and ammonia.

[0106] In some embodiments, the carrier gas includes hydrogen.

[0107] In some embodiments, the flow rate of the carrier gas is 100-120 slm.

[0108] It can be understood that the flow rate of the carrier gas (unit: slm) can be any one of 100, 105, 110, 115, 120 or a range between any two values.

[0109] In some embodiments, the flow rate of the doping source is 135-270 sccm.

[0110] It can be understood that the flow rate of the doping source (unit: slm) can be any one of 135, 150, 200, 250, 270 or a range between any two values.

[0111] In some embodiments, the flow rate of the carbon source is 20-300 sccm.

[0112] It can be understood that the flow rate of the carbon source (unit: sccm) can be any one of 20, 50, 100, 200, 300 or a range between any two values.

[0113] In some embodiments, the flow rate of the silicon source is 100-750 sccm.

[0114] It can be understood that the flow rate of the silicon source (unit: sccm) can be any one of 100, 250, 500, 750 or a range between any two values.

[0115] In some embodiments, the flow rate ratio of the carbon source and the silicon source is (0.4-1.0):1.

[0116] It can be understood that the flow rate ratio of the carbon source and the silicon source, i.e., the carbon-silicon ratio, can be any one of 0.4, 0.6, 0.8, 1.0 or a range between any two values. When the flow rate of the carrier gas, the flow rate of the doping source, the flow rate of the carbon source, the flow rate of the silicon source, and the flow rate ratio of the carbon source and the silicon source meet the above value ranges, the epitaxial layer can have an ideal thickness and doping concentration.

[0117] In some embodiments, the flow rate of the dopant source includes a first flow rate and a second flow rate, the flow rate of the carbon source includes a third flow rate and a fourth flow rate, and the flow rate of the silicon source includes a fifth flow rate and a sixth flow rate. Specifically, according to the required thickness and dopant concentration of the epitaxial layer, or according to the real-time growth of the epitaxial layer in the reaction cavity, the flow rate of the dopant source can be switched between the first flow rate and the second flow rate, the flow rate of the carbon source can be switched between the third flow rate and the fourth flow rate, and the flow rate of the silicon source can be switched between the fifth flow rate and the sixth flow rate, so as to make the epitaxial layer have a preset thickness and nitrogen doping concentration.

[0118] Further, the switching between the first flow rate and the second flow rate, the switching between the third flow rate and the fourth flow rate, and the switching between the fifth flow rate and the sixth flow rate can be completed by manual operation or automatically by a control system.

[0119] In some embodiments, the first flow rate is 210-270 sccm.

[0120] It can be understood that the value of the first flow rate (unit: sccm) can be any one of 210, 220, 230, 240, 250, 260, 270 or a range between any two values.

[0121] In some embodiments, the second flow rate is 135-195 sccm.

[0122] It can be understood that the value of the second flow rate (unit: sccm) can be any one of 135, 145, 155, 165, 175, 185, 195 or a range between any two values.

[0123] In some embodiments, the third flow rate is 200-300 sccm.

[0124] It can be understood that the value of the third flow rate (unit: sccm) can be any one of 200, 220, 240, 260, 280, 300 or a range between any two values.

[0125] In some embodiments, the fourth flow rate is 20-80 sccm.

[0126] It can be understood that the value of the fourth flow rate (unit: sccm) can be any one of 20, 30, 40, 50, 60, 70, 80 or a range between any two values.

[0127] In some embodiments, the fifth flow rate is 650-750 sccm.

[0128] It can be understood that the value of the fifth flow (unit: sccm) can be any one of 650, 670, 690, 710, 730, 750 or a range between any two values.

[0129] In some embodiments, the sixth flow is 100-200 sccm.

[0130] It can be understood that the value of the sixth flow (unit: sccm) can be any one of 100, 120, 140, 160, 200 or a range between any two values. When the first flow, the second flow, the third flow, the fourth flow, the fifth flow and the sixth flow meet the above value range, the thickness and the doping concentration of the epitaxial layer can be further ensured to have ideal uniformity, while cooperating with the warpage of the silicon carbide substrate.

[0131] In some embodiments, the carbon-to-silicon ratio includes a first carbon-to-silicon ratio M1 and a second carbon-to-silicon ratio M2. Specifically, according to the required doping type and electrical properties of the epitaxial layer, the carbon-to-silicon ratio can be switched between the first carbon-to-silicon ratio M1 and the second carbon-to-silicon ratio M2, so that the epitaxial layer has a preset doping type and resistivity.

[0132] In some embodiments, the first carbon-to-silicon ratio M1 satisfies: 0.8≤M1≤1.0.

[0133] It can be understood that the value of the first carbon-to-silicon ratio M1 can be any one of 0.9, 0.85, 0.9, 0.95, 1.0 or a range between any two values.

[0134] In some embodiments, the second carbon-to-silicon ratio M2 satisfies: 0.4≤M2≤0.6.

[0135] It can be understood that the value of the second carbon-to-silicon ratio M2 can be any one of 0.4, 0.45, 0.5, 0.55, 0.6 or a range between any two values. When the first carbon-to-silicon ratio M1 and the second carbon-to-silicon ratio M2 meet the above value range, the epitaxial wafer can be further ensured to have ideal electrical properties.

[0136] In some embodiments, the step of growing the epitaxial layer on the surface of the silicon carbide substrate further includes:

[0137] The pressure in the reaction chamber is controlled to be 80-120 mbar.

[0138] It can be understood that the value of the pressure in the reaction chamber (unit: mbar) can be any one of 80, 90, 100, 110, 120 or a range between any two values. When the pressure in the reaction chamber meets the above value range, the growth source can be uniformly deposited on the surface of the silicon carbide substrate, so that the obtained epitaxial layer has ideal subsequent uniformity.

[0139] In some embodiments, after the step of growing the epitaxial layer on the surface of the silicon carbide substrate, further comprising:

[0140] Controlling the reaction chamber to perform a second temperature reduction.

[0141] It can be understood that, by performing the second temperature reduction, space is provided for the atoms in the silicon carbide substrate and the epitaxial layer to relax, so as to return to stable lattice positions and reduce lattice defects caused by thermal excitation.

[0142] In some embodiments, the end temperature of the second temperature reduction is 885-915℃.

[0143] It can be understood that the end temperature of the second temperature reduction (unit: ℃) can be any one of 885, 890, 895, 900, 905, 910, 915 or a range between any two values. When the end temperature of the second temperature reduction satisfies the above value range, in combination with the growth temperature of the epitaxial layer (i.e. the end temperature T3 of the second temperature increase), the reaction chamber can have an ideal temperature reduction amplitude, thereby avoiding the case that the thermal stress in the material exceeds the critical value due to too large temperature reduction amplitude, resulting in warping of the epitaxial wafer, and the case that the stress release effect is not significant enough due to too small temperature reduction amplitude.

[0144] In some embodiments, the second temperature reduction has a fourth rate v4 ℃ / min, satisfying: 40℃ / min≤v4≤45℃ / min.

[0145] It can be understood that the value of the fourth rate v4 (unit: ℃ / min) can be any one of 40, 41, 42, 43, 44, 45 or a range between any two values. When the fourth rate v4 satisfies the above value range, the epitaxial layer can maintain lattice relaxation during the cooling process, reduce the occurrence of surface roughness or step accumulation of the epitaxial layer, and maintain the flatness of the epitaxial wafer surface.

[0146] The silicon-based gallium nitride epitaxial wafer and the preparation method thereof provided by the present application will be described below through specific embodiments.

[0147] Embodiment 1

[0148] The present application provides a silicon carbide epitaxial wafer, which is prepared by the following steps:

[0149] S1: providing a 6-inch silicon carbide substrate, the substrate thickness is 350μm;

[0150] S2: placing the silicon carbide substrate into a transfer chamber of an epitaxial furnace, and then transferring the silicon carbide substrate from the transfer chamber to a reaction chamber of the epitaxial furnace, the reaction chamber has an initial temperature T0 of 900℃; performing a first temperature increase on the reaction chamber, the end temperature T1 is 1550℃, and the temperature increase rate v1 is 81.25℃ / min;

[0151] S3: the reaction cavity is subjected to a first temperature decrease, the terminal temperature T2 is 700°C, and the temperature decrease rate v2 is 56.7°C / min;

[0152] S4: the reaction cavity is subjected to a second temperature increase, the terminal temperature T3 is 1550°C, and the temperature increase rate v3 is 70.8°C / min;

[0153] S5: a silicon carbide epitaxial film is grown on the silicon carbide substrate, the carbon source is ethylene, the silicon source is trichlorosilane, the carbon-silicon ratio is 1.1, the nitrogen element doping source is nitrogen, the carrier gas is hydrogen, the growth temperature is 1550°C, the reaction cavity pressure is 90 bar, the carrier gas flow rate is 110 slm, and the epitaxial film thickness is 10 μm;

[0154] S6: the reaction cavity is cooled to 900°C, and the epitaxial wafer is transferred to a transfer cavity; the thickness and doping concentration of the epitaxial film are tested.

[0155] Example 2 and Example 3 are consistent with the preparation steps of Example 1, and the only difference is the adjustment of the process conditions.

[0156] Comparative Examples 1-3

[0157] Comparative Examples 1-3 are similar to the preparation steps of Example 1, and the difference is that there is no step S3 and step S4, and after the first temperature increase is completed, the epitaxial layer is directly grown on the surface of the silicon carbide substrate.

[0158] The process parameters of Example 1-3 and Comparative Example 1-3 are shown in Table 1.

[0159] Table 1

[0160]

[0161] The epitaxial wafers in Example 1-3 and Comparative Example 1-3 are subjected to thickness measurement and doping concentration measurement, and the measurement method is as follows:

[0162] (1) Fourier transform infrared spectrometer is used to measure the film thickness, and mercury probe (mercury CV) tester is used to measure the doping concentration.

[0163] (2) Doping concentration uniformity: the standard deviation of the doping concentrations of 25 measurement points on the epitaxial layer / the arithmetic mean of the doping concentrations of 25 measurement points on the epitaxial layer x 100%, and the point map of 25 measurement points on the epitaxial layer is as shown in Figure 1 .

[0164] (3) Thickness uniformity: the standard deviation of the thicknesses of 25 measurement points on the epitaxial layer / the arithmetic mean of the thicknesses of 25 measurement points on the epitaxial layer x 100%.

[0165] The measurement results are shown in Table 2; a comparison chart of the thickness trend of the epitaxial wafer of Example 1 and Comparative Example 1 is shown in Figure 2 a comparison chart of the thickness trend of the epitaxial wafer of Example 2 and Comparative Example 2 is shown in Figure 3 a comparison chart of the thickness trend of the epitaxial wafer of Example 3 and Comparative Example 3 is shown in Figure 4 a comparison chart of the doping concentration trend of the epitaxial wafer of Example 1 and Comparative Example 1 is shown in Figure 5 a comparison chart of the doping concentration trend of the epitaxial wafer of Example 2 and Comparative Example 2 is shown in Figure 6 a comparison chart of the doping concentration trend of the epitaxial wafer of Example 3 and Comparative Example 3 is shown in Figure 7

[0166] Table 2

[0167]

[0168] According to Table 2 and Figures 2 to 7 It can be seen that, by using the preparation method provided in the present application, especially by performing the first cooling and second heating steps before growing the epitaxial layer, the warpage of the epitaxial layer can be effectively reduced, and an epitaxial wafer with both the thickness uniformity and the doping concentration uniformity of the epitaxial layer meeting the process requirements can be obtained; in addition, by comparing the substrate warpage and the epitaxial layer warpage in Comparative Examples 1-3 and Examples 1-3, it can be seen that, by using the preparation process provided in the present application to prepare the silicon carbide epitaxial wafer, even if the initial substrate warpage is slightly high, after the subsequent reaction, an epitaxial wafer with excellent epitaxial layer warpage can still be obtained, and the warpage of the epitaxial layer can be controlled within -3-3 μm.

[0169] The above has described in detail the epitaxial wafer and the preparation method thereof provided in the embodiments of the present application; the principles and implementation manners of the present application have been described by using specific examples; the above description of the embodiments is only for helping to understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that: the technical solutions recorded in the above embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.​

Claims

1. A silicon carbide epitaxial wafer, characterized in that, It includes a silicon carbide substrate and an epitaxial layer disposed on one side of the silicon carbide substrate; The warpage of the silicon carbide substrate is -30 to 30 μm, and the warpage of the epitaxial layer is -30 to 30 μm.

2. The silicon carbide epitaxial wafer according to claim 1, characterized in that, The thickness of the epitaxial layer is 9–12 μm, and the thickness uniformity of the epitaxial layer is 0–2.0%.

3. A silicon carbide epitaxial wafer according to claim 1, characterized in that, The epitaxial layer is doped with nitrogen, and the nitrogen doping concentration is 7.0 × 10⁻⁶. 15 ~1.2×10 16 cm -3 The uniformity of nitrogen doping concentration is 0–3.1%.

4. A method for preparing a silicon carbide epitaxial wafer, characterized in that, Includes the following steps: A silicon carbide substrate is provided, and the silicon carbide substrate is placed in a reaction chamber; The reaction chamber is heated for the first time to relieve the initial stress in the silicon carbide substrate; The reaction chamber is controlled to undergo a first cooling process to eliminate stress in the silicon carbide substrate; The reaction chamber is controlled to undergo a second heating process; An epitaxial layer is grown on the surface of the silicon carbide substrate.

5. The method for preparing a silicon carbide epitaxial wafer according to claim 4, characterized in that, The endpoint temperature of the first heating is T1, the endpoint temperature of the first cooling is T2, and the endpoint temperature of the second heating is T3, satisfying the following: 800℃≤T1-T2≤1000℃, and T1=T3.

6. The method for preparing a silicon carbide epitaxial wafer according to claim 4, characterized in that, The first heating has a first rate v1℃ / min, the first cooling has a second rate v2℃ / min, and the second heating has a third rate v3℃ / min, satisfying: v2 <v3<v1。 7. The method for preparing a silicon carbide epitaxial wafer according to claim 5, characterized in that, The step of placing the silicon carbide substrate in the reaction chamber further includes: The reaction chamber is controlled to have an initial temperature T0, satisfying: T2 < T0 < T1.

8. The method for preparing a silicon carbide epitaxial wafer according to claim 7, characterized in that, At least one of the following conditions must be met: a) 885℃≤T0≤915℃; b) 1550℃≤T1≤1650℃; c) 600℃≤T2≤700℃; d) 1550℃≤T3≤1650℃.

9. The method for preparing a silicon carbide epitaxial wafer according to claim 6, characterized in that, At least one of the following conditions must be met: e)75℃ / min≤v1≤81.3℃ / min; f)52.5℃ / min≤v2≤56.7℃ / min; g)70℃ / min≤v3≤76℃ / min.

10. The method for preparing a silicon carbide epitaxial wafer according to claim 4, characterized in that, The step of growing an epitaxial layer on the surface of the silicon carbide substrate includes: A growth source and a doping source are introduced into the reaction chamber to deposit at least one epitaxial layer on the surface of the silicon carbide substrate.

11. The method for preparing a silicon carbide epitaxial wafer according to claim 10, characterized in that, The growth source includes a carbon source and a silicon source, and the doping source includes a nitrogen source and a carrier gas.

12. The method for preparing a silicon carbide epitaxial wafer according to claim 11, characterized in that, The carbon source includes at least one of ethylene, propane, and methane; and / or, The silicon source includes at least one of trichlorosilane and silane; and / or, The doping source includes at least one of nitrogen and ammonia; and / or, The carrier gas includes hydrogen.

13. The method for preparing a silicon carbide epitaxial wafer according to claim 11, characterized in that, The flow rate of the carrier gas is 100–120 slm; and / or, The flux of the doped source is 135–270 sccm; and / or, The flow rate of the carbon source is 20–300 sccm; and / or, The flow rate of the silicon source is 100–750 sccm.

14. The method for preparing a silicon carbide epitaxial wafer according to claim 11, characterized in that, The flow rate ratio of the carbon source to the silicon source is (0.4 to 1.0):

1.

15. The method for preparing a silicon carbide epitaxial wafer according to claim 4, characterized in that, The step of growing an epitaxial layer on the surface of the silicon carbide substrate further includes: The pressure inside the reaction chamber is controlled to be 80–120 mbar.

16. The method for preparing a silicon carbide epitaxial wafer according to claim 4, characterized in that, After the step of growing an epitaxial layer on the surface of the silicon carbide substrate, the method further includes: The reaction chamber is then cooled a second time.

17. The method for preparing a silicon carbide epitaxial wafer according to claim 16, characterized in that, The endpoint temperature of the second cooling process is 885–915°C; and / or, The second cooling has a fourth rate v4℃ / min, satisfying: 40℃ / min≤v4≤45℃ / min.

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