Integrated circuit performance testing method based on multi-dimension parameter fusion

Abstract

The application provides an integrated circuit performance test method based on multi-dimensional parameter fusion, and belongs to the technical field of integrated circuit performance test, and the method comprises the following steps: S1, preparation before test; S2, multi-dimensional parameter acquisition; S3, data preprocessing; S4, multi-dimensional parameter fusion; and S5, performance test analysis. Through multi-parameter coverage, multi-algorithm cooperation and full-process closed loop, the application solves the problems of isolation, fragmentation and singleness of traditional tests, and provides systematic and refined technical support for integrated circuit performance test.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a method for testing the performance of integrated circuits based on the fusion of multi-dimensional parameters. Background Technology

[0002] As integrated circuit manufacturing processes continue to upgrade (from micrometer-level to nanometer-level) and functional complexity continues to increase (integrating billions of transistors on a single chip), the performance of integrated circuits is increasingly affected by the coupling of multiple parameters. Current traditional integrated circuit performance testing methods suffer from the following core challenges:

[0003] Parameter evaluation is isolated: Most test schemes only evaluate a single-dimensional parameter (such as only measuring power consumption or logic correctness), ignoring the correlation between parameters. For example, judging a chip as qualified based solely on "logic correctness" may mask the hidden danger of "excessive timing jitter causing functional failure under high load," resulting in test results that cannot reflect the actual working performance of the chip.

[0004] Data processing fragmentation: Raw data such as collected electrical parameters and time series parameters are often stored and processed independently, lacking unified preprocessing standards (such as outlier judgment rules and unit unification methods), which makes it impossible to directly integrate different parameter data and difficult to form quantitative comprehensive performance indicators.

[0005] Algorithm application is limited: Existing fusion algorithms mostly use a single linear weighting or a simple nonlinear model, which cannot take into account the linear correlation of parameters (such as current and power consumption), nonlinear coupling (such as temperature and timing delay), and uncertainty (such as interpolation data error in long-term testing). This results in insufficient robustness of the fusion results, which are easily affected by fluctuations in the test environment or equipment.

[0006] Lack of process closure: Test results are only used for performance level determination, and a closed-loop mechanism of "abnormal results - tracing previous links - process optimization" has not been established. For example, after abnormal parameters are found, it is not possible to quickly locate whether the cause is equipment calibration deviation, data acquisition process defect or improper preprocessing method, making it difficult to continuously improve test accuracy.

[0007] The aforementioned problems result in traditional testing solutions having drawbacks such as "high false positive rate, low reliability of results, and slow process iteration," which cannot meet the refined and comprehensive performance testing requirements of highly complex integrated circuits. Summary of the Invention

[0008] This invention provides an integrated circuit performance testing method based on multi-dimensional parameter fusion. By covering multiple parameters, coordinating multiple algorithms, and completing the entire process in a closed loop, it solves the problems of "isolation, fragmentation, and singularity" in traditional testing, and provides systematic and refined technical support for integrated circuit performance testing.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] Integrated circuit performance testing methods based on multi-dimensional parameter fusion include:

[0011] S1. Pre-test preparation: Determine the electrical parameters, timing parameters, reliability parameters and functional parameters to be tested, calibrate the test equipment and set up a standardized test environment, and output a list of calibrated test equipment, a multi-dimensional test parameter table and a standardized test environment parameter record;

[0012] S2. Multi-dimensional parameter acquisition: Based on the test equipment list and multi-dimensional test parameter table, the raw data of the electrical parameters, timing parameters, reliability parameters and functional parameters are collected synchronously, associated with standardized test environment parameter records, and output multi-dimensional raw test dataset;

[0013] S3. Data Preprocessing: Perform outlier removal, noise filtering, unit standardization, and timestamp alignment on the multi-dimensional original test dataset, fill in missing values, and output a standardized preprocessed dataset.

[0014] S4. Multi-dimensional parameter fusion: Based on the standardized preprocessed dataset, a three-level fusion algorithm is used to calculate the comprehensive performance index. The three-level fusion algorithm includes:

[0015] Weighted average method: The parameter weights determined by the statistical weighting method based on historical test data are linearly superimposed with the parameter values ​​in the standardized preprocessed dataset to output the first intermediate value;

[0016] BP neural network method: Taking the parameter values ​​in the standardized preprocessed dataset and the first intermediate value as input, the trained neural network model captures the nonlinear relationship between parameters and outputs the second intermediate value;

[0017] DS Evidence Theory Method: Using the first and second intermediate values ​​as evidence, the support for the performance level is formed by merging them, and a third intermediate value is output.

[0018] Integrate the first intermediate value, the second intermediate value, and the third intermediate value to output the comprehensive performance index value of the integrated circuit;

[0019] S5. Performance Test Analysis: Based on the comprehensive performance index value of the integrated circuit, the performance level is determined by comparing it with the preset performance level threshold. Abnormal parameters are located by combining the standardized preprocessed dataset, and the performance level determination result and abnormal parameter location report are output.

[0020] Integrated circuit performance testing methods based on multi-dimensional parameter fusion also include:

[0021] S6. Test Result Feedback and Iterative Optimization: Based on the abnormal parameter location report, optimize the equipment calibration, data acquisition, preprocessing methods or fusion algorithms in steps S1 to S4, repeat steps S2 to S5 to verify the optimization effect until the stability requirements are met, and output the optimized test process specification.

[0022] S7. Test Report Output: Integrate all the outputs from steps S1 to S6 to generate a test report that includes the test basis, process, conclusions, and optimization suggestions.

[0023] In this specification, in step S1, the electrical parameters include operating voltage, operating current, and power consumption; the timing parameters include signal transmission delay, clock jitter, setup time, and hold time; the reliability parameters include temperature stability, voltage stability, and operational stability; and the functional parameters include logical correctness and signal integrity.

[0024] In this specification, step S4, the process of determining parameter weights based on the statistical weighting method of historical test data includes: collecting historical test data of multi-dimensional parameters and actual application performance feedback data of at least 1,000 integrated circuits of the same model. The multi-dimensional parameters are consistent with the parameters determined in step S1. The performance feedback data includes fault frequency, mean time between failures, performance degradation rate and target scenario compatibility rate.

[0025] Historical data is preprocessed to remove outliers, performance feedback data is quantified into a unified performance label, and parameters are standardized from 0 to 1 to obtain a standardized parameter matrix.

[0026] Principal component analysis was performed on the standardized parameter matrix to calculate the covariance matrix and decompose it to obtain eigenvalues ​​and eigenvectors. Principal components with a cumulative variance contribution rate ≥ 85% were selected.

[0027] Calculate the contribution of each parameter to the total variance in the selected principal components, and obtain the parameter weights after normalization;

[0028] The validity of the weights was verified by a 7:3 cross-validation method, ensuring that the Pearson correlation coefficient between the weight calculation results and the performance labels was ≥0.85. The final weights were output after the verification was passed.

[0029] In this specification, step S4, the training process of the BP neural network method includes: taking the standardized parameter values ​​of multiple integrated circuit samples with known performance levels and the first intermediate value as input, taking the intermediate value of the corresponding level as the label value, training the neural network with the Adam optimizer and the mean squared error loss function, avoiding overfitting by the early stopping method, and saving the weights and bias parameters after training.

[0030] In this specification, step S4, the evidence body assignment rules of the DS evidence theory method include: if the first intermediate value or the second intermediate value belongs to the interval [0.9, 1], then the support for the excellent grade is 0.9, and the support for the qualified and unqualified grades is 0.05 each; if it belongs to the interval [0.6, 0.9), then the support for the qualified grade is 0.9, and the support for the excellent and unqualified grades is 0.05 each; if it belongs to the interval [0, 0.6), then the support for the unqualified grade is 0.9, and the support for the excellent and qualified grades is 0.05 each.

[0031] In this specification, step S4, the process of integrating the first intermediate value, the second intermediate value, and the third intermediate value includes: adopting a weighted integration strategy, wherein the weight of the weighted average method is 0.3, the weight of the BP neural network method is 0.4, and the weight of the DS evidence theory method is 0.3, and the weighted sum of the three is the integrated circuit comprehensive performance index value.

[0032] In this specification, in step S3, the outlier removal adopts the 3σ rule, calculates the mean and standard deviation for each parameter, and removes data that are less than the mean minus 3 times the standard deviation or greater than the mean plus 3 times the standard deviation; the noise filtering uses a moving average filter for the time series parameters and signal integrity parameters, with a window size of 5 consecutive data points.

[0033] In this specification, the stability requirements in step S6 include: the fluctuation of the integrated circuit comprehensive performance index value in three consecutive iterations of testing does not exceed ±2%, and the performance level is consistent, with the contribution of abnormal parameters to the improvement of comprehensive performance not less than 10%.

[0034] In this specification, step S4 uses a quantum surface fitting algorithm in conjunction with a weighted average method and a BP neural network method: the first intermediate value output by the weighted average method and the second intermediate value output by the BP neural network method are taken as inputs, and both are encoded into quantum state vectors. The quantized correlation features between parameters are extracted through a preset observation operator, and a fourth intermediate value is output. The encoding rule of the quantum state vector is based on the normalization of the first and second intermediate values. The structure of the observation operator is determined through optimization of training samples and is used to capture the nonlinear correlation of integrated circuit parameters under nanoscale processes caused by quantum effects. The fourth intermediate value participates in the integrated calculation of the final comprehensive performance index, improving the accuracy of performance evaluation of high-complexity chips.

[0035] In summary, the present invention has at least the following beneficial effects:

[0036] Enhancing the comprehensiveness and objectivity of performance evaluation: By integrating 11 core parameters across 4 categories—electrical, timing, reliability, and functionality—it breaks through the limitations of traditional single-parameter evaluation, achieving full-dimensional performance coverage of integrated circuits in terms of "power consumption, signal transmission, environmental adaptability, and functional implementation." Simultaneously, based on a statistical weighting method using historical test data and the collaborative fusion of multiple algorithms, it avoids biases caused by subjective human weighting, making comprehensive performance indicators more closely reflect the actual working performance of the chip and reducing misjudgments of "partially excellent parameters but overall unqualified results."

[0037] Enhance the robustness and traceability of test results: Through a three-level preprocessing process of "data cleaning (removing outliers) - standardization (unifying units) - time alignment (synchronizing data)," noise and interference in the original data are eliminated; combined with the ability of DS evidence theory to correct uncertain data, the resistance of the fused results to equipment fluctuations and environmental interference is improved; and the entire process retains "equipment calibration records, data acquisition logs, and anomaly traceability reports," so that each test result can be traced back to the specific equipment, operation steps, and data source, ensuring that the test process is reproducible and the results are verifiable.

[0038] Optimize the efficiency and iteration capability of the testing process: Establish a closed-loop process of "test-analysis-optimization" - through the abnormal parameter location of S5, accurately identify the root cause of problems in the preceding links (such as equipment calibration and data acquisition), and then through targeted optimization of S6 (such as shortening the calibration cycle and improving the interpolation method), avoid the recurrence of similar problems; at the same time, the optimized process can be directly reused for testing of the same type of chip, reducing the cost of repeated development and improving testing efficiency.

[0039] Supporting the entire lifecycle improvement of integrated circuits: The output of "comprehensive performance indicators + abnormal parameter reports" can not only be used for factory quality inspection (screening qualified chips), but also provide optimization directions for chip design (such as improving clock tree design for "excessive timing jitter") and provide process adjustment basis for production (such as optimizing packaging heat dissipation structure for "poor temperature stability"), thus achieving full lifecycle performance improvement support from design, production to application. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the integrated circuit performance testing method based on multi-dimensional parameter fusion involved in this invention.

[0041] Figure 2 This is a schematic diagram of the data preprocessing process involved in this invention.

[0042] Figure 3 This is a schematic diagram of the multi-dimensional parameter fusion flowchart (content subsurface fitting algorithm) involved in this invention.

[0043] Figure 4This is a schematic diagram of the test iteration optimization process involved in this invention. Detailed Implementation

[0044] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0045] like Figure 1 As shown, this embodiment provides an integrated circuit performance testing method based on multi-dimensional parameter fusion. This solution revolves around the core idea of ​​"multi-dimensional parameter collaborative fusion," constructing a seven-step closed-loop testing process of "preparation-acquisition-preprocessing-fusion-analysis-optimization-reporting" to achieve a comprehensive and accurate evaluation of integrated circuit performance.

[0046] Basic Preparation Phase (S1): Define 11 test parameters across 4 categories, calibrate test equipment, and establish a standardized test environment to provide a unified benchmark for subsequent testing; Parameter Acquisition Phase (S2): Based on qualified equipment and a standard environment, synchronously acquire multi-dimensional raw data to ensure data integrity and time consistency; Data Preprocessing Phase (S3): Transform the raw data into a high-quality standardized dataset through outlier removal, noise filtering, unit unification, and time alignment; Multi-Dimensional Fusion Phase (S4): Employ a weighted average method (linear benchmark) - BP neural network method (nonlinear deepening) - DS evidence theory method (uncertainty correction). "The three-level collaborative algorithm, combined with parameter weights determined by statistical weighting based on historical test data, calculates a quantitative comprehensive performance index; Performance analysis stage (S5): Determines the level threshold based on industry standards and manufacturer specifications, judges the chip performance level, and locates abnormal parameters and root causes affecting performance; Iterative optimization stage (S6): Feeds back the abnormal root causes to the preceding stages (such as equipment calibration and data acquisition process), implements targeted optimization and verifies the effect, forming a closed loop process; Report output stage (S7): Integrates the data and results of the entire process, generates a standardized report containing test basis, process, conclusions and optimization suggestions, supporting subsequent applications and improvements."

[0047] S1: Pre-test Preparation Phase – Determining Basic Conditions and Calibration Equipment

[0048] This stage forms the foundation of the entire test plan, providing a unified test benchmark, qualified hardware, and stable environmental conditions for subsequent parameter acquisition in S2, data preprocessing in S3, and multi-dimensional fusion in S4. Any equipment calibration deviations or incomplete parameter definitions in this stage will directly lead to data distortion in S2, thus affecting the reliability of the S4 fusion results. Therefore, this stage requires rigorous parameter definition, equipment calibration, and environmental control, outputting three core documents: a "List of Calibrated Test Equipment," a "Multi-Dimensional Test Parameter Table," and a "Standardized Test Environment Parameter Record." These documents provide a traceable basis for subsequent steps.

[0049] 1.1 Determination of multi-dimensional test parameters (connecting with S2 data collection requirements)

[0050] The selection of test parameters needs to cover the core dimensions of integrated circuit performance. Refer to the general rules of integrated circuit testing methods in the industry or relevant test technical materials and the specifications of the chip under test (such as the manufacturer's technical documents for CPU, MCU or application-specific integrated circuits). Finally, determine 11 key parameters in 4 categories (supplementing signal integrity parameters to ensure correspondence with the 11 parameters of S4):

[0051] Electrical parameters (reflecting the chip's power consumption and power supply stability): operating voltage (core voltage Vcore, IO voltage Vio, which must match the rated values ​​in the chip datasheet, such as Vcore=1.8V±5%), operating current (static current Iddq, dynamic current Idd, static current is the current when the chip has no input, dynamic current is the current when the chip is under full load), and power consumption (standby power consumption Pstandby, full load power consumption Pactive, power consumption = voltage × current, which needs to be distinguished between different operating modes).

[0052] Timing parameters (reflecting the time characteristics of signal transmission): signal transmission delay (input-to-output delay Tpd, clock-to-output delay Tco, where Tpd is the time from the change of the input signal to the response of the output signal, and Tco is the time from the clock edge to the change of the output signal), clock jitter (period jitter Tjitter_pp, phase jitter Tjitter_rms, where period jitter is the peak-to-peak deviation of the clock period, and phase jitter is the phase deviation accumulated over a long period), setup time Tsetup and hold time Thold (Tsetup is the minimum time before the data stabilizes earlier than the clock edge, and Thold is the minimum time after the data stabilizes later than the clock edge).

[0053] Reliability parameters (reflecting the chip's performance stability under different environments): Temperature stability (parameter drift rate at five temperature points: -40℃, 0℃, 25℃, 75℃, and 125℃, drift rate = (extreme temperature value - normal temperature value) / normal temperature value × 100%), Voltage stability (performance fluctuation under rated voltage ±10%, such as testing 1.62V, 1.8V, and 1.98V for a 1.8V chip), Long-term working stability (parameter decay rate after 1000 hours of continuous operation, decay rate = (initial value - value after 1000 hours) / initial value × 100%).

[0054] Functional parameters (reflecting the chip's logic implementation and signal quality): Logic correctness (verified through full input combination, such as 4 input pins needing to cover 16 combinations, and the output matching rate with the preset vector ≥ 99.9%), signal integrity (output signal rise time Tr, fall time Tf, overshoot, undershoot, where Tr is the time for the signal to rise from 10% to 90% of its amplitude, and overshoot is the percentage exceeding the rated amplitude).

[0055] The above parameters need to be compiled into a "multi-dimensional test parameter table", which clearly defines the definition, unit, test range and pass threshold of each parameter (refer to the chip datasheet) to provide a clear basis for S2 data acquisition.

[0056] 1.2 Preparation and calibration of test equipment (to ensure the accuracy of S2 data)

[0057] Based on the parameter types defined in 1.1, dedicated testing equipment is provided, and measurement accuracy is ensured through metrological calibration:

[0058] Electrical parameter testing equipment: high-precision digital multimeter (such as Keysight 34461A, voltage measurement accuracy ±0.01%, current measurement accuracy ±0.02%), power analyzer (such as Yokogawa WT3000, power consumption measurement accuracy ±0.1%).

[0059] Timing parameter testing equipment: high-bandwidth oscilloscope (such as Tektronix MDO3024, bandwidth 200MHz, time resolution 1ns, ensuring the capture of nanosecond-level delays), clock analyzer (such as Agilent 53132A, jitter measurement resolution 1ps).

[0060] Reliability parameter testing equipment: high and low temperature test chamber (such as Binder MK53, temperature range -40℃~125℃, control accuracy ±0.5℃), programmable DC power supply (such as Keithley 2231A, output voltage accuracy ±0.05%), long-term stability test bench (with constant temperature and humidity control, temperature 25℃±1℃, humidity 50%±5%).

[0061] Functional parameter testing equipment: logic analyzer (such as Rigol MSO5074, 32 channels, supporting parallel testing of 16 input combinations), signal integrity tester (such as LeCroy SDA 813Zi, 13GHz bandwidth, capable of measuring overshoot / undershoot percentage).

[0062] Data acquisition and storage equipment: multi-channel data acquisition card (such as NIPCIe-6363, sampling rate 2MS / s, to ensure synchronous acquisition of data from each device), data storage server (hard disk capacity ≥1TB, supporting real-time storage in CSV format).

[0063] Equipment calibration must be commissioned to a metrology institution with CNAS accreditation. Calibration items include: voltage / current range accuracy of multimeters, time base and voltage probe calibration of oscilloscopes, power factor correction of power analyzers, and temperature uniformity of high and low temperature chambers. After successful calibration, a "List of Calibrated Test Equipment" must be generated, indicating the equipment number, calibration validity period (usually 1 year), and maximum permissible error (e.g., oscilloscope time base error ≤ 0.01%). This list serves as the basis for the use of S2 equipment. If the equipment exceeds its calibration validity period, the data collected in S2 must be marked as "suspicious data" and subject to key verification in S3.

[0064] 1.3 Setting up a standardized testing environment (reducing the impact of environmental interference on S2 data)

[0065] The stability of the testing environment directly affects the repeatability of parameter measurements. The following factors need to be controlled in a shielded testing chamber:

[0066] Ambient temperature: 25℃±2℃ (controlled by precision air conditioning, temperature fluctuation ≤±0.5℃ / hour) to avoid chip parameter drift caused by temperature changes (e.g., power consumption may increase by 5%~10% for every 10℃ increase in temperature); Ambient humidity: 50%RH±10%RH (controlled by dehumidifier / humidifier) ​​to prevent short circuits on circuit boards due to high humidity or electrostatic interference caused by low humidity; Electromagnetic interference (EMI): The shielding effectiveness of the test chamber is ≥80dB (achieved through copper mesh shielding walls and grounding resistance ≤4Ω) to avoid interference from external electromagnetic signals (such as mobile phone signals and power supply noise) on the measurements of oscilloscopes and logic analyzers; Power supply stability: Isolation transformers and UPS power supplies are used to ensure that the power supply voltage fluctuation of the test equipment is ≤±1% and the frequency is 50Hz±0.5Hz to avoid power supply noise affecting current / power consumption measurements. Environmental parameters need to be monitored in real time using a temperature and humidity recorder (sampling rate 1 time / minute) and an electromagnetic interference tester (frequency range 30MHz~1GHz) to form a "standardized test environment parameter record", which is stored in association with the data collected by S2. If the environmental parameter at a certain timestamp exceeds the range, S3 needs to mark the corresponding data as "data affected by environmental interference" and assess the impact on the fusion results.

[0067] S2: Multi-dimensional parameter acquisition phase – synchronous acquisition of raw test data

[0068] This stage, based on the "List of Calibrated Test Equipment," "Multi-Dimensional Test Parameter Table," and "Standardized Test Environment Parameter Record" output by S1, obtains a "Multi-Dimensional Raw Test Dataset" through hardware connection, synchronous acquisition of sub-parameters, and data association storage. This provides raw material for the data preprocessing in S3. The core of the acquisition process is to ensure the synchronization (consistent timestamps) and integrity (covering all 11 parameters) of the data; otherwise, the preprocessing in S3 will not be able to align the data, thus affecting the fusion accuracy of S4. The data preprocessing flow is as follows: Figure 2 As shown.

[0069] 2.1 Fixing and wiring of integrated circuit samples (to ensure reliable signal transmission)

[0070] The integrated circuit sample to be tested (hereinafter referred to as "sample") must undergo visual inspection (no pin deformation, package damage) before being fixed on a dedicated test fixture (such as a ZIF socket or probe station). The wiring must strictly follow the sample pin definitions (refer to the datasheet): Power pin: Connect to the output terminal of the programmable DC power supply, connect in series with a high-precision multimeter (current range) to measure the operating current, and connect in parallel with a multimeter (voltage range) to measure the operating voltage; Input / output pin: Connect the input pin to the output channel of the logic analyzer (load test vector), and connect the output pin to both an oscilloscope (to measure delay / jitter) and the logic analyzer (to measure logic correctness); Temperature monitoring: Attach a thermocouple temperature sensor (accuracy ±0.1℃) to the sample surface and connect it to the temperature acquisition terminal of the high and low temperature test chamber to monitor the chip junction temperature in real time; Grounding treatment: Connect the grounding terminals of all devices to the same grounding busbar to avoid measurement errors caused by ground potential differences (grounding resistance ≤1Ω). After wiring is completed, three checks must be performed: use a multimeter in continuity mode to verify the correctness of the pin connections (avoid short circuits), use an oscilloscope to observe the ripple on the power supply pins (≤50mV peak-to-peak value), and apply the minimum test vector to verify whether the sample starts up normally (the output signal meets expectations). Only after passing these checks can the data acquisition phase begin.

[0071] 2.2 Synchronous acquisition of sub-parameters (ensuring data consistency over time)

[0072] A multi-channel data acquisition card is used to achieve synchronous acquisition of all parameters. The acquisition frequency is uniformly 1Hz (one set of data is recorded per second), and the timestamp is synchronized by the hardware clock of the acquisition card (error ≤1ms). The specific acquisition method is as follows:

[0073] Electrical parameter acquisition: Operating voltage: The multimeter records the power pin voltage (in V) once every 1 second, and the storage format is "timestamp, voltage value, multimeter number"; Operating current: The multimeter is connected in series in the power circuit and records the current (in A) once every 1 second, distinguishing between static (no input) and dynamic (full load) modes; Power consumption: The power analyzer calculates "voltage × current" in real time and outputs the power consumption value (in W) once every 1 second, and records the power factor (PF) simultaneously for auxiliary analysis.

[0074] Timing parameter acquisition: Signal transmission delay: The oscilloscope uses "input signal rising edge triggering" to measure the time difference between the input and output signals (in ns) once every 1 second, and the trigger threshold is set to 50% of the signal amplitude; Clock jitter: The clock analyzer continuously acquires a 10ms clock signal and outputs the period jitter (peak-to-peak value, in ps) and phase jitter (RMS, in ps) once every 1 second; Setup / hold time: The logic analyzer loads a test vector containing timing offset (step size 1ns) and records the minimum Tsetup and Thold (in ns) that the sample can correctly identify, and acquires it once every 10 seconds (because the test vector loading takes a long time).

[0075] Reliability Parameter Acquisition: Temperature Stability: The high and low temperature test chamber was switched in the order of "-40℃→0℃→25℃→75℃→125℃". After each temperature point was stabilized for 30 minutes (to ensure that the chip temperature was consistent with the environment), 10 sets of electrical parameters and timing parameters were continuously collected (1 set / second); Voltage Stability: The programmable power supply was switched in the order of "1.62V→1.8V→1.98V". After each voltage point was stabilized for 10 minutes, 5 sets of power consumption and logic correctness data were collected; Long-term Working Stability: The sample was continuously operated at 25℃ for 1000 hours. Full parameter data was collected every 100 hours (lasting 10 minutes, 1 set / second), and the cumulative working time was recorded.

[0076] Functional parameter acquisition: Logic correctness: The logic analyzer cyclically loads 16 input combinations (covering all states of the 4 input pins), records the "input combination-output result" lookup table once every 1 second, and calculates the output accuracy (number of correct inputs / total number of inputs × 100%); Signal integrity: The signal integrity tester measures the output signal's Tr (10%~90%), Tf (90%~10%), overshoot (percentage exceeding Vdd), and undershoot (percentage below GND) once every 10 seconds.

[0077] 2.3 Data Association and Storage (Providing Structured Data for S3 Preprocessing)

[0078] All collected data must be linked to the "Standardized Test Environment Parameter Records" in S1 to form a raw dataset containing nine fields: "Parameter Category, Parameter Name, Value, Unit, Timestamp, Ambient Temperature, Ambient Humidity, Test Equipment Number, and Calibration Error," stored in CSV format (for easy processing by S3's Excel or Python). For example, a record might be: "Electrical Parameters, Operating Voltage, 1.82V, 20XX-05-20 10:00:00, 25.1℃, 49%RH, Multimeter-001, ±0.01V." The data storage server must enable redundant backup (RAID5) to prevent data loss and generate a "Data Acquisition Log" to record events such as acquisition start / end time, equipment malfunctions (e.g., oscilloscope trigger failure), and sample status (e.g., overheat protection), for S3 to trace abnormal data.

[0079] S3: Data Preprocessing Stage – Optimizing Raw Data Quality

[0080] This stage, based on the "multi-dimensional original test dataset" output by S2, eliminates noise, outliers, and dimensional differences through data cleaning, standardization, and time alignment, outputting a "standardized preprocessed dataset" to provide high-quality input for the S4 fusion algorithm. Incomplete preprocessing (such as retaining outliers) can cause the S4 fusion results to deviate from the true performance; therefore, a rigorous processing procedure is necessary to ensure data quality.

[0081] 3.1 Data cleaning (removing outliers and noise)

[0082] The raw data may contain outliers caused by equipment fluctuations (such as sudden jumps in multimeter readings), environmental interference (such as electromagnetic pulses), or loose wiring. These outliers need to be processed using the following steps:

[0083] Outlier identification: using the 3σ rule (applicable to parameters that are approximately normally distributed, such as voltage and current):

[0084] 1. For each parameter (e.g., operating voltage), calculate the mean μ and standard deviation σ of all data (based on the original dataset of S2); 2. Define the outlier range: data less than μ-3σ or greater than μ+3σ (only 0.3% of the data in a normal distribution are outside this range); For example: if the original operating voltage data is μ=1.8V and σ=0.02V, then the outliers are data <1.74V or >1.86V.

[0085] Outlier verification and handling: For identified outliers, the cause needs to be investigated by combining the "data acquisition log" of S2 with the equipment calibration record: If the log shows "multimeter-001 triggered overload at 10:00:05", the voltage data at that timestamp is confirmed as outlier, removed, and marked "removed due to equipment overload"; if the cause cannot be found (e.g., no log record), the data is retained but marked as "suspicious data", and its weight is reduced in the fusion of S4 (e.g., reducing the support for the data in DS evidence theory).

[0086] Noise filtering: Timing parameters (such as delay and jitter) and signal integrity parameters (such as Tr and Tf) are susceptible to high-frequency noise interference. Moving average filtering is used.

[0087] Filter window size = 5 consecutive data points (balancing smoothing effect and response speed), calculated using the following formula: For j≥3, edge data are padded with values ​​before and after the edge data. , ;

[0088] Example: The original delay data of a certain signal is [10ns, 12ns, 11ns, 13ns, 12ns]. After filtering... .

[0089] 3.2 Data standardization (unified units of measurement to facilitate weighted fusion in S4)

[0090] The dimensions of different parameters differ significantly (e.g., voltage in V, delay in ns), so all parameters need to be normalized to the [0,1] interval using 0-1 normalization, as shown in the formula: ; The standardized value of the j-th timestamp of the i-th parameter; , The minimum and maximum values ​​of the i-th parameter (from the original dataset of S2, after removing outliers).

[0091] Special parameter handling: Logical correctness (output accuracy): Directly take the accuracy rate (e.g., 98% → 0.98); Overshoot / Undershoot (the smaller the better): Use inverse normalization. Ensure that the "excellent value" is mapped to 1;

[0092] For example: if the original overshoot range is 0% to 5%, and a certain data point is 2%, then... .

[0093] The standardized data needs to retain the correspondence between the original values ​​and the standardized values ​​to form a "standardized mapping table" for S5 to trace the original values ​​of abnormal parameters.

[0094] 3.3 Data alignment (timestamp synchronization to ensure consistent input dimensions for S4 algorithms)

[0095] The sampling frequencies for different parameters in S2 differ (e.g., long-term stability parameters are sampled once every 100 hours, and electrical parameters once every second), and they need to be aligned according to timestamps.

[0096] Unified timeline: Using "1 second" as the smallest unit, a timeline covering the entire collection period is generated (e.g., 1000 hours → 3,600,000 timestamps).

[0097] Missing value imputation: For low-frequency parameters (such as long-term stability), cubic spline interpolation is used to impute missing timestamps (smoother than linear interpolation).

[0098] Known Time value , Time value ,beg of :

[0099] ;

[0100] Example: Power consumption 0.5W over 100 hours, power consumption 0.52W over 200 hours, interpolated power consumption over 150 hours: .

[0101] Aligned data needs to be labeled as "original data" or "interpolated data". S4's DS evidence theory method will reduce the support of interpolated data (e.g., reduce the weight of high support levels when assigning values ​​to evidence).

[0102] 3.4 Generate a standardized preprocessed dataset

[0103] The cleaned, standardized, and aligned data are integrated to form a structured dataset containing "time stamps, standardized values ​​of 11 parameters (including labels: normal / suspicious / interpolated), and raw value index (related to the raw data of S2)". This dataset is stored in Excel format (including a data quality report: percentage of outliers and percentage of interpolated data) and serves as the direct input to the S4 fusion algorithm.

[0104] S4: Multi-dimensional parameter fusion stage – Calculating comprehensive performance indicators

[0105] This step is the core hub connecting data preprocessing (S3) and performance analysis (S5). Its aim is to transform the scattered electrical, timing, reliability, and functional parameters in the "standardized preprocessed dataset" output by S3 into a comprehensive index that can be directly used for performance assessment through a multi-algorithm collaborative fusion strategy. Compared to traditional single-parameter evaluation methods (such as judging performance solely by power consumption or logic correctness), multi-dimensional fusion can more comprehensively reflect the overall performance of the integrated circuit—for example, a chip may have excellent power consumption but excessive timing jitter; single-parameter evaluation is prone to misjudgment, while the fusion algorithm can comprehensively weigh the impact of various parameters. The output of this step, the "integrated circuit comprehensive performance index value," will directly serve as the quantitative basis for performance level classification in S5; therefore, rigorous algorithm design is necessary to ensure the accuracy and robustness of the results.

[0106] 4.1 Design of the fusion algorithm system and weight allocation (connecting with S3 standardized data)

[0107] 4.1.1 Underlying Logic and Collaborative Framework for Algorithm Selection

[0108] Integrated circuits have complex multi-dimensional parameters: some parameters are linearly related (such as operating current and power consumption, where power consumption increases approximately linearly as current increases); some parameters are nonlinearly related (such as the effect of temperature rise on clock jitter, which may increase exponentially with increasing temperature); and some parameters are uncertain due to measurement limitations (such as in long-term stability testing, discontinuous sampling data within 1000 hours needs to be interpolated, and the interpolation results contain errors). Based on these characteristics, this scheme designs a three-level fusion framework of "linear benchmark - nonlinear deepening - uncertainty correction," selecting three types of algorithms to complement each other: Weighted average method: as the first-level fusion (linear fusion), it utilizes the linear superposition of parameter weights and standardized values ​​to quickly extract explicit correlations between parameters (such as the voltage-current relationship within electrical parameters), outputting preliminary performance trends and providing benchmark input for subsequent algorithms; BP neural network method: as the second-level fusion (nonlinear fusion), it captures implicit nonlinear correlations between parameters through a multi-layered neuron structure (such as the coupling relationship between temperature stability and signal delay). Its input specifically incorporates the results of the weighted average method to reuse linear features and reduce network training complexity; DS evidence theory method: as the third-level fusion (uncertainty fusion), it corrects uncertainties in the data (such as interpolation data errors) by processing multi-source evidence (the outputs of the first two algorithms), improving the results' robustness against interference. The three types of algorithms do not operate independently but form a progressive interactive chain of "weighted average method → ​​BP neural network method → ​​DS evidence theory method": the output of the weighted average method is one of the inputs of the BP method, and the outputs of the first two together serve as the evidence body for DS.

[0109] 4.1.2 Statistical weighting method based on historical test data (determining parameter weights)

[0110] Core principle: By mining the statistical correlation between historical test data and actual application performance of a large amount of integrated circuits of the same model, and using the variance contribution measure of principal component analysis (PCA) to quantify the influence of each parameter on performance, objective weights are automatically generated. This scheme relies entirely on technical data, without any subjective human intervention. The weight results directly reflect the objective correlation between parameters and chip performance, and can seamlessly replace the expert scoring weight determination method based on the analytic hierarchy process.

[0111] 1. Historical data collection and standardization processing

[0112] Data Scope: Collect complete data from at least 1000 chips of the same model. Each chip must contain two types of core information: Multi-dimensional parameter raw data: Consistent with the 11 parameters collected by S2, including electrical parameters (operating voltage, operating current, power consumption), timing parameters (signal transmission delay, clock jitter, setup / hold time), reliability parameters (temperature stability, voltage stability, long-term operating stability), and functional parameters (logic correctness, signal integrity). Each parameter must record full lifecycle test data (such as values ​​under different timestamps and environmental conditions); Actual application performance feedback data: Quantified performance results indicators, including: 1. Failure frequency: The number of failures (0, 1, ≥2) of the chip during 1000 hours of continuous operation under rated conditions; 2. Lifespan: Mean time between failures (MTBF) in actual applications, in hours; 3. Performance degradation rate: The percentage degradation of key parameters (such as power consumption and delay) relative to their initial values ​​after 1000 hours; 4. Application adaptability: The pass / fail rate (%) in the target scenario (such as industrial control, automotive electronics). Data Preprocessing: 1. Outlier Removal: Box plot method is used (IQR = Q3 - Q1, removing data <Q1 - 1.5IQR or >Q3 + 1.5IQR) to avoid data distortion caused by faulty chips or testing errors; 2. Performance Feedback Quantification: Multi-dimensional performance feedback indicators are transformed into a unified comprehensive performance value Y (range 0~1). Entropy weight method is used to determine the weight of each feedback indicator (failure frequency 0.3, lifespan 0.3, performance degradation rate 0.2, application adaptability 0.2), and weighted summation is used to obtain the final performance label Y for each chip; 3. Parameter Standardization: 11 test parameters are standardized using 0-1 (consistent with S3) to obtain a standardized parameter matrix. (Rows represent chip samples, columns represent parameters).

[0113] 2. Principal Component Analysis (PCA) Modeling and Variance Contribution Calculation

[0114] Step 2.1: Calculate the covariance matrix

[0115] Based on the standardized parameter matrix X, the covariance matrix among the 11 parameters is calculated. The covariance formula is: ;in, Covariance matrix The element in the i-th row and j-th column represents the covariance between the i-th and j-th test parameters, reflecting the degree of linear correlation between the two parameters; n is the total number of historical test samples, and k is the sample index. Let be the standardized value of the i-th test parameter in the k-th sample. This is the standardized value of the j-th test parameter in the k-th sample; , These are the mean values ​​of the i-th and j-th parameters, respectively. This matrix is ​​used to reflect the degree of linear correlation between the parameters, laying the foundation for subsequent principal component extraction.

[0116] Step 2.2: Solve for eigenvalues ​​and eigenvectors

[0117] For covariance matrix Eigenvalue decomposition yields 11 eigenvalues. and the corresponding feature vectors Eigenvalues The eigenvectors represent the variance contribution of the corresponding principal components. The parameter composition direction represents the principal component.

[0118] Step 2.3: Determine the number of principal components and their contribution percentage to variance.

[0119] Principal components were selected using the criterion of "cumulative variance contribution rate ≥ 85%", i.e., the smallest m was chosen. , making This criterion ensures that the selected principal components retain most of the information from the original parameters, avoiding information loss. For example, if the sum of the first four eigenvalues ​​accounts for 86% of the total eigenvalues, then the first four principal components are selected. .

[0120] Step 2.4: Calculate the variance contribution of each parameter.

[0121] The total variance contribution of each parameter is the sum of its variance contributions across all selected principal components, calculated using the following formula: ;in It is the i-th element of the eigenvector corresponding to the j-th principal component. The larger the value, the greater the contribution of the parameter to the principal components, meaning a more significant impact on chip performance. For example, assuming the "clock jitter" timing parameter contributes 3.2%, 2.8%, 1.5%, and 0.5% to the variance of the four principal components, respectively, then its total variance contribution... =3.2%+2.8%+1.5%+0.5% = 8%.

[0122] 3. Weight Normalization and Validation

[0123] Weight generation: The variance contribution of the 11 parameters. Normalization is performed to obtain the final weights. The formula is: After normalization, it satisfies This can be directly used for the weighted average calculation of S4. For example: the sum of the total variance contributions of the 11 parameters is 100%, where "logical correctness" accounts for a significant portion. Then its weight .

[0124] Weight Validation: Cross-validation is used to test the effectiveness of the weights. The 1000 samples are divided into training and test sets in a 7:3 ratio. The first median value of the weighted average method is calculated using the weights determined in the training set. The weights are then correlated with the performance label Y of the test set. If the Pearson correlation coefficient is ≥0.85, it indicates that the weights effectively reflect the relationship between parameters and performance and can be used. If this is not met, more samples (e.g., increasing to 2000) need to be added and the weights recalculated to ensure the objectivity and reliability of the weights. The output weights are used as the first intermediate value of the S4 weighted average method. calculate.

[0125] 4.2 Weighted Average Fusion (Algorithm 1: Linear Fusion, Output) )

[0126] 4.2.1 Algorithm Principles and Core Functions

[0127] The weighted average method transforms multi-dimensional parameters into a single intermediate index through the linear superposition of parameter weights and standardized values. Its mathematical expression is as follows: ; : The median value of the overall performance output by the weighted average method (range 0~1, the higher the value, the better the performance). : The weight of the i-th parameter (see 4.1.2, e.g., i=1 corresponds to the working voltage, w1=0.1); : The standardized value of the i-th parameter at the j-th timestamp (from the "standardized preprocessing dataset" of S3, ranging from 0 to 1).

[0128] The core contributions of this algorithm are: 1. Fast benchmark evaluation: The linear calculation process is simple and efficient, outputting preliminary performance trends within milliseconds, providing a reference for subsequent complex algorithms; 2. Strong interpretability: The contribution of each parameter can be directly expressed through… Quantization (e.g., the contribution of power consumption) ), making it easy to trace the direct causes of performance differences; 3. Providing input for subsequent algorithms: its output These features will be used as input features to the BP neural network to enable information transfer between algorithms.

[0129] 4.2.2 Calculation process

[0130] Taking the standardized data of a certain timestamp in S3 as an example: Electrical parameters: x1=0.8 (operating voltage, standardized value), x2=0.8 (operating current), x3=0.8 (power consumption); Timing parameters: x4=0.7 (signal delay), x5=0.7 (clock jitter), x6=0.7 (setup / hold time); Reliability parameters: x7=0.9 (temperature stability), x8=0.9 (voltage stability), x9=0.9 (long-term stability); Functional parameters: x 10 =1.0 (logical correctness), x 11 =0.9 (signal integrity).

[0131] Substitute into the formula to calculate: =0.1×0.8+0.1×0.8+0.1×0.8+0.08×0.7+0.08×0.7+0.09×0.7+0.09×0.9+0.08×0.9+0.08×0.9+0.12×1.0+0.08×0.9=0.08+0.08+0.08+0.056+0.056+0.063+0.081+0.072+0.072+0.12+0.072=0.892;

[0132] Output =0.892, this value will be used as one of the inputs to the BP neural network.

[0133] 4.3 BP Neural Network Fusion Method (Algorithm 2: Nonlinear Fusion, Input includes...) Output )

[0134] 4.3.1 Model Building and Interaction Design

[0135] Backpropagation (BP) neural networks are multi-layer feedforward neural networks that adjust weights through backpropagation, effectively capturing nonlinear relationships between parameters (such as the nonlinear amplification effect of power consumption increases on clock jitter under high-temperature environments). To enhance the model's utilization of linear features, this scheme specifically incorporates a weighted average method at the input layer. This forms a composite input of "linear features + original parameters", with the following specific structure: Input layer: 12 nodes (11 standardized parameters) +1 weighted average result P1), input vector is Hidden layer: 25 nodes (calculation formula: 2 × number of input layer nodes + 1 = 2 × 12 + 1 = 25, ensuring sufficient non-linear fitting capability), activation function uses... The input is mapped to the range of 0 to 1 to avoid gradient explosion; the output layer has 1 node and outputs P2 (the median value of the overall performance, ranging from 0 to 1), with the activation function being Sigmoid to ensure that the output is consistent with the normalized range of the parameters.

[0136] Model parameter definition:

[0137] : Weight matrix from input layer to hidden layer (initialized using He normal distribution, mean 0, variance 2 / 12, to avoid excessively large initial weights); Hidden layer bias vector (zero initialization, reducing initial bias); : Weight vector from hidden layer to output layer (He normal initialization); Output layer bias (zero initialization).

[0138] 4.3.2 Model Training Process (Ensuring Generalization Ability)

[0139] 1. Training set construction: Select 120 integrated circuit samples of the same model (covering different performance levels: 40 excellent, 50 qualified, and 30 unqualified), and extract 3600 timestamps from each sample. As input (a total of 120 × 3600 = 432,000 samples); the labeled values ​​are the median values ​​of the grades (Excellent = 0.95, Pass = 0.75, Fail = 0.3) to ensure that the training objectives are clear.

[0140] 2. Training parameter settings: Loss function: Mean Squared Error (MSE), which measures the deviation between the predicted value P2 and the labeled value. Where N=120 (number of samples) and T=3600 (number of timestamps). This is the labeled value for the k-th sample.

[0141] Optimizer: Adam optimizer (adaptive learning rate, suitable for non-convex optimization), initial learning rate η=0.001, first moment estimation decay rate β1=0.9, second moment estimation decay rate β2=0.999, to prevent excessive learning rate from causing oscillations; Training strategy: Early stopping is used, training stops when the validation set loss does not decrease for 50 consecutive rounds to avoid overfitting; finally, training is performed until the validation set loss <0.001, and the optimal weights are saved. and bias .

[0142] 4.3.3 Model Application and Calculation Process (Input includes P1)

[0143] The calculation steps for a specific timestamp data of the current test sample are as follows:

[0144] 1. Hidden layer output calculation: The input to a hidden layer neuron is a linear combination of the input layer and weights plus a bias. After Sigmoid activation, the output is: For example: Suppose (25 elements), substituting them into the Sigmoid function, we get: ;

[0145] 2. Output layer calculation (P2): The output layer combines the hidden layer output with the weights, and after sigmoid activation, obtains P2. For example: Suppose ,but:

[0146] The output P2 = 0.891, which, together with P1, serves as the input to the DS evidence theory method, enabling interaction with the third algorithm.

[0147] 4.4DS Evidence Theory Fusion (Algorithm 3: Uncertainty Fusion, Input includes P1 and P2, Output P3)

[0148] 4.4.1 Model Building and Evidence Design

[0149] DS evidence theory addresses uncertainty by fusing multi-source evidence (information), making it particularly suitable for parameter uncertainties caused by measurement errors and interpolation data in integrated circuit testing. Its core idea is to treat the outputs of different algorithms as "evidence" of performance levels, and to obtain more reliable conclusions through evidence combination rules. Model definition: Recognition framework: Where H1 represents "Excellent" (overall performance index ≥ 0.9), H2 represents "Pass" (0.6 ≤ overall performance index < 0.9), and H3 represents "Unsatisfactory" (overall performance index < 0.6), covering all possible performance levels; Evidence bodies: Two evidence bodies m1 (based on P1) and m2 (based on P2), representing the support of the weighted average method and the BP neural network for each level, respectively, satisfying... and ( An empty set represents a set without any hierarchical support.

[0150] 4.4.2 Assignment of Evidence and Conflict Resolution

[0151] 1. Evidence body assignment rules (based on the intervals to which P1 and P2 belong):

[0152] Based on the numerical ranges of P1 and P2, the support levels for each level are defined as follows: If P∈[0.9,1] (Excellent): m(H1)=0.9 (High Support Excellent), m(H2)=0.05 (Low Support Satisfactory), m(H3)=0.05 (Low Support Unsatisfactory); If P∈[0.6,0.9) (Satisfactory): m(H1)=0.05 (Low Support Excellent), m(H2)=0.9 (High Support Satisfactory), m(H3)=0.05 (Low Support Unsatisfactory); If P∈[0,0.6) (Unsatisfactory): m(H1)=0.05 (Low Support Excellent), m(H2)=0.05 (Low Support Satisfactory), m(H3)=0.9 (High Support Unsatisfactory).

[0153] For example: P1=0.892∈[0.6,0.9), so m1(H1)=0.05, m1(H2)=0.9, m1(H3)=0.05; P2=0.891∈[0.6,0.9), so m2(H1)=0.05, m2(H2)=0.9, m2(H3)=0.05.

[0154] 2. Conflict Coefficient Calculation (Measures Evidence Consistency): The conflict coefficient K is used to quantify the degree of contradiction between two pieces of evidence. The calculation formula is as follows: ;in This indicates that the two levels are mutually exclusive (e.g., H1 and H2 cannot be true at the same time).

[0155] Substitute example data: =0.05×0.9+0.05×0.05+0.9×0.05+0.9×0.05+0.05×0.05+0.05×0.9=0.045+0.0025+0.045+0.0025+0.045=0.185;

[0156] If K = 0.185 < 0.5, it indicates that the two pieces of evidence have little conflict and can be directly merged. If K ≥ 0.5 (high conflict), the Yager rule (preserving conflict information and not normalizing) is used to avoid fusion distortion.

[0157] 3. Evidence Fusion (Dempster Rule): After fusion, the evidence is considered for level H. K The support level is: For example: For H2 (qualified), the intersection is H2 only if Hᵢ=H2 and Hⱼ=H2. Therefore: Similarly, m(H1) = m1(H1)·m2(H1) / (1-K) = 0.05×0.05 / 0.815≈0.003, m(H3) = 0.003.

[0158] 4. Output P3: Take the median value of the highest support level as P3: In this example, H2 has the highest support (0.994), so P3=0.75 (the median value of the qualified level).

[0159] 4.5 Integration of Three Algorithms (Output of Final Overall Performance Index P)

[0160] 4.5.1 Integration Strategy and Weight Determination

[0161] Each of the three algorithms has its advantages: the weighted average method is highly stable but ignores nonlinearity; the backpropagation neural network captures nonlinearity but is sensitive to noise; and the DS evidence theory is resistant to interference but depends on the quality of evidence. To combine these advantages, a weighted ensemble strategy is adopted, with the following formula: ;

[0162] Integration weight definition:

[0163] α1=0.3 (weight of weighted average method), α2=0.4 (weight of BP neural network), α3=0.3 (weight of DS evidence theory), determined based on historical test accuracy (BP neural network 95%> weighted average method 92%> DS evidence theory 90%, the higher the accuracy, the greater the weight), and α1+α2+α3=1.

[0164] 4.5.2 Final Calculation and Output

[0165] Substituting the results from the previous examples (P1=0.892, P2=0.891, P3=0.75):

[0166] ;

[0167] The output is "Integrated Circuit Comprehensive Performance Index Value P=0.849". This value integrates linear characteristics, nonlinear correlation and uncertainty correction, and comprehensively reflects the chip performance, providing a quantitative basis for the performance level determination of S5 (0.6≤0.849<0.9, judged as "qualified").

[0168] S5: Performance Testing and Analysis Phase – Determining Performance Level and Identifying Problems

[0169] This phase, based on the "Integrated Circuit Comprehensive Performance Index Values" output by S4 and the "Standardized Preprocessing Dataset" from S3, outputs "Performance Level Judgment Results" and "Abnormal Parameter Location Reports" through level threshold comparison and anomaly parameter tracing, providing specific directions for S6 optimization. The analysis process must be closely integrated with the fusion logic of S4 to ensure the objectivity of level judgment and the accuracy of problem location.

[0170] 5.1 Determination of performance level thresholds (a comprehensive indicator connecting to S4)

[0171] The grading thresholds must be determined by combining industry standards and chip manufacturer specifications: Excellent: Overall performance index value ≥ 0.9, corresponding to all parameters exceeding the "target value" in the specification (e.g., power consumption ≤ 90% of the target value, latency ≤ 90% of the target value); Acceptable: 0.6 ≤ Overall performance index value < 0.9, corresponding to all parameters meeting the "minimum value" in the specification (e.g., power consumption ≤ maximum value, latency ≤ maximum value), but some parameters not meeting the "target value"; Unacceptable: Overall performance index value < 0.6, corresponding to at least one parameter exceeding the "maximum value" in the specification (e.g., power consumption > maximum value, logic correctness < 99%). The thresholds must be recorded in the "Grading Standard Table," indicating the basis (e.g., "Refer to Section 5.2 of the manufacturer's specification") to ensure traceability of the determination.

[0172] 5.2 Performance Level Determination (Based on S4 Comprehensive Indicators)

[0173] The "Integrated Circuit Comprehensive Performance Index Value P" output by S4 is compared with the threshold of 5.1, and the judgment result is output: Example 1: P=0.849 (S4 calculation result) → 0.6≤0.849<0.9 → judged as "Pass Grade"; Example 2: If a sample P=0.92 → ≥0.9 → judged as "Excellent Grade"; Example 3: If a sample P=0.58 → <0.6 → judged as "Fail Grade". The judgment result needs to be associated with the S4 fusion process record (such as the intermediate values ​​P1, P2, P3 of each algorithm). If "algorithm result conflict" occurs (such as P1=0.95, P3=0.5), the reason for the conflict needs to be explained in the report (such as the sensitivity of DS evidence theory to interpolated data).

[0174] 5.3 Abnormal Parameter Location (for non-compliant / marginally compliant samples)

[0175] For samples judged as "unacceptable" (P<0.6) or "marginally acceptable" (0.6≤P<0.7), it is necessary to identify the key parameters affecting performance: Calculate the parameter contribution: Based on the parameter weights of S4, calculate the contribution of each parameter to the overall index: ; The contribution of the i-th parameter. For standardized values, As weights; for example: for clock jitter (i=5), x'=0.3, w=0.08 → C5=0.3×0.08=0.024, which is much lower than other parameters (such as logical correctness C). 10 =1.0×0.12=0.12), then clock jitter is a key abnormal parameter.

[0176] Tracing the cause of the anomaly: Analyze the "Standardized Mapping Table" (restoring the original value) from S3, the "Data Acquisition Log" from S2, and the "Device Calibration Record" from S1: If the original value shows clock jitter = 50ps (exceeding the 30ps specification), and the oscilloscope calibration record from S1 shows "Time base error = 5% (allowable ≤2%)", then the cause is determined to be "Oscilloscope calibration failure leading to excessively high measured values"; if the original value shows logic correctness = 95% (specification requires ≥99%), and the S2 log shows "Test vector loading error", then the cause is determined to be "Defect in the acquisition process leading to distorted functional verification". The location results need to form an "Anomaly Parameter Location Report", clearly specifying the anomaly parameter name, original value, allowable range, cause of the anomaly, and related preceding steps (such as S1 device, S2 acquisition), providing specific basis for S6 optimization.

[0177] S6: Test Result Feedback and Iterative Optimization Phase – Improving Test Accuracy

[0178] This phase, based on the "Abnormal Parameter Location Report" output by S5, feeds back the problem to the previous steps and implements targeted optimizations. Iterative testing verifies the optimization effect, and finally, an "Optimized Test Process Specification" is output to ensure the stability and reliability of subsequent test results. The optimization process must form a closed loop, meaning each problem has a corresponding solution and verification results. The test iterative optimization process is as follows: Figure 4 As shown.

[0179] 6.1 Scenario-specific optimization measures (related to the causes of S5 anomalies)

[0180] Based on the causes of S5 positioning anomalies, optimization measures were formulated for different scenarios:

[0181] Scenario 1: Equipment calibration issues (e.g., oscilloscope timing error exceeding limits)

[0182] Feedback to S1 regarding the "equipment calibration process" includes measures such as: replacing calibration standards with higher precision ones (e.g., using a reference oscilloscope from the National Institute of Metrology); and shortening the calibration cycle (from 1 year to 6 months).

[0183] Add calibration items (such as calibrating the probe delay of the oscilloscope separately); after optimization, you need to obtain the "calibration certificate" again and update the "list of calibrated equipment for S1".

[0184] Scenario 2: Defects in the data acquisition process (such as test vector loading errors)

[0185] Feedback to the "parameter acquisition stage" of S2 includes the following measures: developing an automatic test vector verification program (comparing vector MD5 values ​​before loading); adding a "no-load test" before acquisition (verifying whether the device output is normal when there is no sample); and adding a "function wake-up" step every 100 hours for long-term stability testing (to prevent the sample from entering a dormant state and affecting the data).

[0186] After optimization, the "S2 Data Acquisition Operation Manual" needs to be updated, and testers need to be trained.

[0187] Scenario 3: Preprocessing method deviation (e.g., excessive interpolation error)

[0188] Feedback to the "data alignment process" in S3 includes the following measures: for long-term stability parameters, increase the acquisition frequency (from once every 100 hours to once every 50 hours) to reduce interpolation requirements; switch to "Kalman filter interpolation method" (combining parameter change trends to reduce smoothing errors); after optimization, historical data needs to be reprocessed to verify whether the interpolation error has decreased from ±5% to within ±2%.

[0189] Scenario 4: Errors in fusion algorithms (such as overfitting in backpropagation neural networks)

[0190] Feedback to the "BP neural network training stage" in S4 includes the following measures: expanding the training set to 200 samples (adding samples from different batches and with different aging levels); adding L2 regularization (weight decay coefficient λ=0.001) to suppress overfitting; after optimization, the network needs to be retrained to verify whether the accuracy of the test set has improved from 92% to over 95%.

[0191] 6.2 Iterative Testing and Stability Verification

[0192] After implementing the optimization measures, three samples from the same batch need to be selected for iterative testing (repeating S2~S5) to verify the effect. Stability judgment criteria: 1. The fluctuation of the comprehensive performance index value over three consecutive iterations is ≤±2% (e.g., 0.849→0.852→0.847, fluctuation 0.6%<2%); 2. Consistent performance level (e.g., all three are "qualified"); 3. The contribution of abnormal parameters increases by ≥10% (e.g., clock jitter). (Increase from 0.024 to 0.027). If the above criteria are met, the optimization is deemed effective; otherwise, the cause of the S5 anomaly needs to be re-analyzed, and the optimization measures adjusted (e.g., if the equipment problem is not resolved, replace the equipment) until the verification is passed.

[0193] 6.3 Output Optimization Results

[0194] Integrate all optimization measures and verification data to form a "Test Process Optimization Report", which includes: a performance index comparison table before and after optimization; revised S1~S4 operating specifications (such as equipment calibration checklist, data acquisition process sequence diagram); and anomaly handling plans (such as emergency data acquisition plan in case of sudden equipment failure).

[0195] This report will serve as the standard for subsequent testing, ensuring the continued stability of test quality.

[0196] S7: Test Report Output Phase – Integrating Results from the Entire Process

[0197] This stage requires the system to integrate all outputs from S1 to S6 to generate a complete and standardized test report, providing authoritative evidence for integrated circuit design improvements, production quality control, and market access. The report must be both technically sound and readable, containing detailed test data as well as clear performance conclusions and recommendations.

[0198] 7.1 Report Structure and Content Integration

[0199] The report employs a modular structure to ensure clear logic and complete content.

[0200] Chapter 1: Test Overview: Includes sample information (model, batch, production number, number of tests), test basis (industry standard number, manufacturer's specification version), and test purpose (e.g., "to verify the performance stability of a certain MCU in an industrial environment").

[0201] Chapter 2: Test Preparation and Environment: Integrate the "Multi-dimensional Test Parameter Table", "List of Calibrated Test Equipment", and "Standardized Test Environment Parameter Record" from S1, with copies of equipment calibration certificates and environmental monitoring curves attached.

[0202] Chapter 3: Data Acquisition and Preprocessing: Overview of the S2 acquisition process (with wiring diagram), S3 preprocessing methods (including outlier handling examples and standardized mapping tables), and key data are presented in charts (such as 24-hour power consumption trend charts and temperature stability parameter drift curves).

[0203] Chapter 4: Multi-dimensional Parameter Fusion and Performance Analysis: This section details the fusion algorithm of S4 (with a weight calculation table, a schematic diagram of the BP neural network structure, and the DS evidence fusion process), the grade determination results of S5 (including the time-series change curve of the comprehensive index P), and focuses on analyzing abnormal parameters of unqualified samples (with a contribution ranking table).

[0204] Chapter 5: Optimization Measures and Final Conclusions: Summarize the optimization measures and verification results of S6, give the final performance conclusions (e.g., "80% of the samples in this batch are qualified, and 20% are unqualified due to excessive clock jitter"), and make suggestions (e.g., "It is recommended that the manufacturer optimize the clock tree design to reduce jitter").

[0205] Appendix: Electronic files (compressed package with verification code) containing all raw data, preprocessed data, and fusion calculation process, for easy traceability and verification.

[0206] 7.2 Report Review and Issuance

[0207] The report must undergo three levels of review to ensure accuracy and authority: 1. Test engineer self-review: verifying the correctness of data calculations (e.g., whether there are errors in substituting the S4 fusion formula) and the consistency between charts and data; 2. Test team leader review: assessing the compliance of the test methods (whether they meet industry standards) and the rationality of anomaly analysis; 3. Technical head of the testing organization signing off: confirming the overall logical integrity of the report and the objectivity of the conclusions, affixing the "CNAS Accredited Testing Laboratory" seal, and giving the report legal validity.

[0208] 7.3 Report Delivery and Archiving

[0209] The report must be provided in both hard copy (3 copies, including a seal across the binding) and electronic version (PDF format, with an electronic signature) to the client (such as a chip design company or quality inspection agency). Simultaneously, the testing organization must retain a copy of the report and all original data (retention period ≥ 3 years) for future traceability or review. Through the close integration of the above seven steps—S1 providing basic conditions, S2 collecting raw data, S3 optimizing data quality, S4 integrating multi-dimensional information, S5 determining performance levels, S6 iteratively optimizing the process, and S7 outputting a complete report—a comprehensive integrated circuit performance testing solution covering "preparation-collection-processing-integration-analysis-optimization-reporting" is formed, ensuring comprehensive, accurate, and reliable test results.

[0210] In some embodiments, based on the "weighted average method-BP neural network method-DS evidence theory method," a quantum surface fitting algorithm is added to construct a four-level fusion system of "linear benchmark-nonlinear deepening-quantized correlation-uncertainty correction." The quantum surface fitting algorithm outputs the first intermediate value from the weighted average method. The second intermediate value output by the BP neural network method As input, the quantum superposition property is used to capture the quantized correlation between parameters (such as the nonlinear correlation caused by the quantum tunneling effect of parameters in nanoscale processes), and the fourth intermediate value is output. Finally, by integrating the outputs of the four algorithms, a more accurate integrated circuit performance index value P is obtained, providing a more comprehensive quantitative basis for S5. The multi-dimensional parameter fusion flowchart (content subsurface fitting algorithm) is shown below. Figure 3 As shown.

[0211] 4.1 Definition of Symbol System

[0212] 1. Basic general symbols: n: Total number of multi-dimensional test parameters (n=11, 3 electrical parameters, 3 timing parameters, 3 reliability parameters, 2 functional parameters); j: Timestamp index (j=1,2,...,T, T is the total number of timestamps collected, such as T=3600 seconds); : The i-th standardized parameter value at the j-th timestamp (i=1,2,...,n, range[0,1], from S3 "Standardized Preprocessing Dataset"); The weight of the i-th parameter (determined using a statistical weighting method based on historical test data). ,like =0.1 (operating voltage) =0.08 (signal integrity)); : The first intermediate value of the overall performance output by the weighted average method ([0,1]); : The second comprehensive performance intermediate value ([0,1]) output by the BP neural network method; : The third comprehensive performance intermediate value of the DS evidence theory method output ([0,1]); : The fourth comprehensive performance intermediate value ([0,1]) output by the quantum surface fitting algorithm; : Ensemble weights of four types of algorithms ( Determined based on historical accuracy. P: The final integrated circuit performance index value ([0,1]).

[0213] 2. Backpropagation (BP) neural network: : BP input vector (including , ); Input layer - hidden layer weight matrix; Hidden layer bias; : Sigmoid activation function; Hidden layer output ; Hidden layer - Output layer weight vector; Output layer bias; :BP loss function (N=120 is the number of training samples, (The value is labeled).

[0214] 3. DS Evidence Theory: : Recognition framework ( :excellent, :qualified, (Unqualified) :based on Basic probability allocation of evidence ; :based on Basic probability allocation of evidence; : Conflict coefficient of evidence; : Probability allocation after fusion.

[0215] 4. Quantum surface fitting: Quantum state vector (dimension d=4, based on input) , Encoding that satisfies normalization ); : Observation operator (d×d Hermitian matrix, used to extract fitting results, (for positional operators) Quantum surface fitting coefficients (k,l=0,1,2, a total of 9 coefficients, which need to be optimized through training); Quantum expectation value (i.e.) (range [0,1])

[0216] Quantum state fidelity loss function ( For the target quantum state, (For predicting quantum states).

[0217] 4.2 Algorithm Flow Optimization (Interactive Interface Reserved for Quantum Surface Fitting)

[0218] 4.2.1 Weighted Average Method (Algorithm 1: Output) (For use with BP, quantum surface fitting, and DS)

[0219] Core function: Linearly fuses 11 standardized parameters and outputs basic intermediate values. It provides linear feature input for BP and low-dimensional benchmark input for quantum surface fitting. At the same time, it serves as the first evidence body for DS, reducing the input dimension of subsequent algorithms.

[0220] Calculation formula and examples: ; Take the standardized data (11 parameters) for the j=1 timestamp: Electrical parameters: =0.8 (operating voltage) =0.8 (operating current) =0.8 (power consumption); Timing parameters: =0.7 (signal delay) =0.7 (clock jitter) =0.7 (setup / hold time); Reliability parameters: =0.9 (temperature stability) =0.9 (voltage stability) =0.9 (long-term stability); Functional parameters: =1.0 (logical correctness) =0.9 (signal integrity).

[0221] Substitute weights : =0.1×0.8+0.1×0.8+0.1×0.8+0.08×0.7+0.08×0.7+0.09×0.7+0.09×0.9+0.08×0.9+0.08×0.9+0.12×1.0+0.08×0.9=0.08+0.08+0.08+0.056+0.056+0.063+0.081+0.072+0.072+0.12+0.072=0.892; Output: =0.892, which is used as the input for Algorithm 2 (BP), Algorithm 4 (Quantum Surface Fitting), and Algorithm 3 (DS).

[0222] 4.2.2 BP Neural Network Method (Algorithm 2: Input contains...) Output (For quantum surface fitting and DS use)

[0223] Core function: To capture the classic nonlinear relationship between parameters (such as the exponential relationship between temperature and power consumption), and to include inputs... By reusing linear features, output As a high-dimensional nonlinear input for quantum surface fitting, and also as a second body of evidence for DS, it enhances the richness of multi-source evidence.

[0224] Model Construction and Training: Input Layer: 12 nodes (11 of which are...) + Hidden layer: 25 nodes (2×12+1), activation function Output layer: 1 node ( ), activation function Training: using 120 samples and labeled values (Excellent = 0.95, Pass = 0.75, Fail = 0.3) Training, Adam optimizer until ,save .

[0225] Applications and Examples: 1. Hidden Layer Output: Substitute (25 elements) 2. Output layer: Substitute ,have to Output: , which serves as the input for Algorithm 4 (Quantum Surface Fitting) and Algorithm 3 (DS).

[0226] 4.3 Quantum Surface Fitting Algorithm (Algorithm 4: Input contains , Output (For final integration use)

[0227] 4.3.1 Core Function and Algorithm Principle

[0228] Traditional nonlinear fitting (such as backpropagation) struggles to handle the quantum correlations of integrated circuit parameters in nanoscale processes (such as power consumption-timing quantization fluctuations caused by transistor tunneling current). Quantum surface fitting utilizes the superposition property of quantum states. , (as the superposition coefficient), (Linear characteristics) (Classical nonlinear characteristics) are encoded as quantum states, and quantized correlation information is extracted through observation operators to output... This compensates for the accuracy deficiencies of classical algorithms in quantum effect scenarios.

[0229] 4.3.2 Model Building Process

[0230] 1. Input quantization encoding: ... , (All values ​​are [0,1]) Encoded as 4-dimensional quantum states The encoding rules are based on normalization: ;in To calculate the basis vectors in 4D, satisfying ( (for the Kronecker function), ensuring Normalization is required: ;

[0231] 2. Observation Operator Design: Constructing a second-order polynomial observation operator (capture) , (secondary association) ; It is a 2×2 identity matrix. (Pauli X operator) (Pauli Y operator); These are the fitting coefficients (6 in total, which need to be trained and optimized, and i is the imaginary unit).

[0232] 3. Output mapping: For quantum state in The expected value (real number, due to) (It is a Hermitian matrix) ;

[0233] 4.3.3 Model Training Process

[0234] 1. Training set construction: Take 120 samples , (k=1,...,120 are sample indices, j=1,...,T are timestamps) as input, corresponding performance label values. As the target output, construct training pairs 2. Loss function definition: Quantum state fidelity loss (measuring the similarity between the predicted quantum state and the target quantum state): Target quantum state :Depend on coding, Predicting quantum states :Depend on coding, Loss function: 3. Optimization process: Optimize the fitting coefficients using gradient descent. Learning rate Iterate 500 times until... Save the optimal coefficients .

[0235] 4.3.4 Model Application Process (Input) , Output )

[0236] by =0.892、 Taking 0.891 as an example, the steps are as follows: 1. Input encoding and normalization: After normalization: 2. Substitute the optimal observation operator: Assume that the training yields... ,but: 3. Calculate the expected value :use Calculate the matrix elements, then sum them: Interaction relationship: The input of Algorithm 4 is the input of Algorithm 1. Algorithm 2 This enables pairwise interactions between "weighted average method ↔ quantum surface fitting" and "BP neural network method ↔ quantum surface fitting"; output For final integration use.

[0237] 4.4DS Evidence Theory Method (Algorithm 3: Input contains...) , Output (For final integration use)

[0238] Core function: processing , Uncertainty in (e.g.) linear approximation error (overfitting risk), output As the intermediate value after uncertainty correction, and , , Collaborate on integration to enhance the robustness of results.

[0239] Examples of Evidence Body Assignment and Integration: Evidence Body (based on =0.892∈[0.6,0.9)): =0.05、 =0.9、 =0.05; Evidence (based on =0.891∈[0.6,0.9)): =0.05、 =0.9、 =0.05; Conflict coefficient K=0.185 (calculation see above); After fusion =0.994 (maximum support), therefore =0.75 (intermediate value for acceptable grades).

[0240] Interaction relationship: The input of Algorithm 3 is the input of Algorithm 1. Algorithm 2 This achieves pairwise interactions between "weighted average method ↔ DS" and "BP neural network method ↔ DS"; output For final integration use.

[0241] 4.5 Four-algorithm integration (outputting the final comprehensive performance index P)

[0242] 4.5.1 Integration Strategy and Weight Determination

[0243] The four algorithms complement each other: weighted average (stable linear), backpropagation (classical nonlinear), quantum surface fitting (quantum correlation), and DS (uncertainty correction). The ensemble weights are determined based on historical accuracy (weighted average 92%, backpropagation 95%, quantum surface fitting 94%, DS 90%). =0.25、 =0.3、 =0.25、 =0.2, which satisfies .

[0244] 4.5.2 Integrated Calculation Formulas and Examples

[0245] Substitute : ;

[0246] Output: The final integrated circuit comprehensive performance index value P=0.855 (rounded to three decimal places) integrates four types of information: linearity, classical nonlinearity, quantum correlation, and uncertainty correction, comprehensively reflecting the chip performance and providing a precise quantitative basis for the S5 grade determination (0.6≤0.855<0.9, judged as "qualified").

[0247] 1. Data flow to closed loop: S3's →Algorithm 1 ( Algorithm 2 Algorithm 4 Algorithm 3 );

[0248] 2. Pairwise interaction with full coverage: Algorithm 1 ↔ Algorithm 2 ( (Input for Algorithm 2); Algorithm 1 ↔ Algorithm 4 ( (Input for Algorithm 4); Algorithm 1 ↔ Algorithm 3 ( (Input for Algorithm 3); Algorithm 2 ↔ Algorithm 4 ( (Input for Algorithm 4); Algorithm 2 ↔ Algorithm 3 ( (Input for Algorithm 3); Algorithm 4 ↔ Integration ( For integrated input), Algorithm 3↔ Integration ( (For integrated input).

[0249] 3. Algorithm Value: Quantum surface fitting fills the gap in classical algorithms for handling quantum correlations, improving the accuracy of fusion results by 5% to 8% in nanometer process chip testing (based on historical data verification), and is especially suitable for testing scenarios of automotive-grade and aerospace-grade high-reliability chips.

Claims

1. A method for testing the performance of integrated circuits based on multi-dimensional parameter fusion, characterized in that, include: S1. Pre-test preparation: Determine the electrical parameters, timing parameters, reliability parameters and functional parameters to be tested, calibrate the test equipment and set up a standardized test environment, and output a list of calibrated test equipment, a multi-dimensional test parameter table and a standardized test environment parameter record; S2. Multi-dimensional parameter acquisition: Based on the test equipment list and multi-dimensional test parameter table, the raw data of the electrical parameters, timing parameters, reliability parameters and functional parameters are collected synchronously, associated with standardized test environment parameter records, and output multi-dimensional raw test dataset; S3. Data Preprocessing: Perform outlier removal, noise filtering, unit standardization, and timestamp alignment on the multi-dimensional original test dataset, fill in missing values, and output a standardized preprocessed dataset. S4. Multi-dimensional parameter fusion: Based on the standardized preprocessed dataset, a three-level fusion algorithm is used to calculate the comprehensive performance index. The three-level fusion algorithm includes: Weighted average method: The parameter weights determined by the statistical weighting method based on historical test data are linearly superimposed with the parameter values ​​in the standardized preprocessed dataset to output the first intermediate value; BP neural network method: Taking the parameter values ​​in the standardized preprocessed dataset and the first intermediate value as input, the trained neural network model captures the nonlinear relationship between parameters and outputs the second intermediate value; DS Evidence Theory Method: Using the first and second intermediate values ​​as evidence, the support for the performance level is formed by merging them, and a third intermediate value is output. Integrate the first intermediate value, the second intermediate value, and the third intermediate value to output the comprehensive performance index value of the integrated circuit; S5. Performance Test Analysis: Based on the comprehensive performance index value of the integrated circuit, the performance level is determined by comparing it with the preset performance level threshold. Abnormal parameters are located by combining the standardized preprocessed dataset, and the performance level determination result and abnormal parameter location report are output.

2. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, Also includes: S6. Test Result Feedback and Iterative Optimization: Based on the abnormal parameter location report, optimize the equipment calibration, data acquisition, preprocessing methods or fusion algorithms in steps S1 to S4, repeat steps S2 to S5 to verify the optimization effect until the stability requirements are met, and output the optimized test process specification. S7. Test Report Output: Integrate all the outputs from steps S1 to S6 to generate a test report that includes the test basis, process, conclusions, and optimization suggestions.

3. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, In step S1, the electrical parameters include operating voltage, operating current, and power consumption; the timing parameters include signal transmission delay, clock jitter, setup time, and hold time; the reliability parameters include temperature stability, voltage stability, and operational stability; and the functional parameters include logical correctness and signal integrity.

4. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, In step S4, the process of determining parameter weights based on the statistical weighting method of historical test data includes: collecting historical test data of multi-dimensional parameters and actual application performance feedback data of at least 1,000 integrated circuits of the same model. The multi-dimensional parameters are consistent with the parameters determined in step S1. The performance feedback data includes fault frequency, mean time between failures, performance degradation rate and target scenario compatibility rate. Historical data is preprocessed to remove outliers, performance feedback data is quantified into a unified performance label, and parameters are standardized from 0 to 1 to obtain a standardized parameter matrix. Principal component analysis was performed on the standardized parameter matrix to calculate the covariance matrix and decompose it to obtain eigenvalues ​​and eigenvectors. Principal components with a cumulative variance contribution rate ≥ 85% were selected. Calculate the contribution of each parameter to the total variance in the selected principal components, and obtain the parameter weights after normalization; The validity of the weights was verified by a 7:3 cross-validation method, ensuring that the Pearson correlation coefficient between the weight calculation results and the performance labels was ≥0.

85. The final weights were output after the verification was passed.

5. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, In step S4, the training process of the BP neural network method includes: taking the standardized parameter values ​​of multiple integrated circuit samples with known performance levels and the first intermediate value as input, taking the intermediate value of the corresponding level as the label value, training the neural network with the Adam optimizer and the mean square error loss function, avoiding overfitting by using the early stopping method, and saving the weights and bias parameters after training.

6. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, In step S4, the evidence body assignment rules of the DS evidence theory method include: if the first intermediate value or the second intermediate value belongs to the interval [0.9,1], then the support for the excellent grade is 0.9, and the support for the qualified and unqualified grades is 0.05 each; if it belongs to the interval [0.6,0.9), then the support for the qualified grade is 0.9, and the support for the excellent and unqualified grades is 0.05 each; if it belongs to the interval [0,0.6), then the support for the unqualified grade is 0.9, and the support for the excellent and qualified grades is 0.05 each.

7. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, In step S4, the process of integrating the first intermediate value, the second intermediate value, and the third intermediate value includes: adopting a weighted integration strategy, wherein the weight of the weighted average method is 0.3, the weight of the BP neural network method is 0.4, and the weight of the DS evidence theory method is 0.3, and the weighted sum of the three is the integrated circuit comprehensive performance index value.

8. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, In step S3, the outlier removal adopts the 3σ rule, calculates the mean and standard deviation for each parameter, and removes data that are less than the mean minus 3 times the standard deviation or greater than the mean plus 3 times the standard deviation; the noise filtering uses a moving average filter for the time series parameters and signal integrity parameters, with a window size of 5 consecutive data points.

9. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 2, characterized in that, In step S6, the stability requirements include: the fluctuation of the integrated circuit comprehensive performance index value in three consecutive iterations of testing does not exceed ±2%, and the performance level is consistent; the contribution of abnormal parameters to the improvement of comprehensive performance is not less than 10%.

10. The integrated circuit performance testing method based on multi-dimensional parameter fusion according to claim 1, characterized in that, Step S4 uses a quantum surface fitting algorithm and a three-level fusion algorithm: a weighted average method, a backpropagation (BP) neural network method, and a DS evidence theory method, which together constitute a four-level fusion system. The quantum surface fitting algorithm takes as input the first intermediate value output by the weighted average method and the second intermediate value output by the BP neural network method. These two inputs are encoded into quantum state vectors. Quantum correlation features between parameters are extracted using a preset observation operator, and a fourth intermediate value is output. The encoding rule for the quantum state vectors is based on the normalization of the first and second intermediate values, and the structure of the observation operator is determined through training sample optimization. The fourth intermediate value, along with the first, second, and third intermediate values, participates in the calculation of the final integrated circuit performance index. A weighted integration strategy is used to allocate weights to each intermediate value. The weight for the quantum surface fitting algorithm is 0.2, the weight for the weighted average method is 0.25, the weight for the BP neural network method is 0.3, and the weight for the DS evidence theory method is 0.25, with a total weight of 1. The final integrated circuit performance index value is obtained by weighting and summing the four intermediate values ​​according to the above weights.

Images